Dual 3 MHz, 1200 mA Buck Regulators with One 300 mA LDO ADP5024 Data Sheet FEATURES GENERAL DESCRIPTION Main input voltage range: 2.3 V to 5.5 V Two 1200 mA buck regulators and one 300 mA LDO 24-lead, 4 mm × 4 mm LFCSP package Regulator accuracy: ±3% Factory programmable or external adjustable VOUTx 3 MHz buck operation with forced PWM and automatic PWM/PSM modes BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V LDO: output voltage range from 0.8 V to 5.2 V LDO: input supply voltage from 1.7 V to 5.5 V LDO: high PSRR and low output noise The ADP5024 combines two high performance buck regulators and one low dropout (LDO) regulator in a small, 24-lead, 4 mm × 4 mm LFCSP to meet demanding performance and board space requirements. The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low, the buck regulators operate in PWM mode when the load current is above a predefined threshold. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM), improving the light load efficiency. APPLICATIONS The two bucks operate out of phase to reduce the input capacitor requirement. The low quiescent current, low dropout voltage, and wide input voltage range of the LDO extends the battery life of portable devices. The ADP5024 LDO maintains power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. Power for processors, ASICS, FPGAs, and RF chipsets Portable instrumentation and medical devices Space constrained devices Regulators in the ADP5024 are activated though dedicated enable pins. The default output voltages can be either externally set in the adjustable version or factory programmable to a wide range of preset values in the fixed voltage version. TYPICAL APPLICATION CIRCUIT AVIN CAVIN 0.1µF VOUT1 VIN1 SW1 C1 4.7µF ON OFF BUCK1 EN1 FB1 PGND1 EN1 L1 1µH C5 10µF R2 MODE PWM MODE VIN2 MODE SW2 BUCK2 EN2 OFF 1.7V TO 5.5V EN3 VIN3 C3 1µF PSM/PWM VOUT2 C2 4.7µF ON VOUT1 AT 1200mA R1 EN2 EN3 FB2 PGND2 L2 1µH VOUT2 AT 1200mA R3 R4 C6 10µF VOUT3 LDO (ANALOG) FB3 R5 R6 ADP5024 AGND VOUT3 AT 300mA C7 1µF 09888-001 2.3V TO 5.5V HOUSEKEEPING Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved. ADP5024 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications ....................................................................................... 1 Power Management Unit........................................................... 17 General Description ......................................................................... 1 BUCK1 and BUCK2 .................................................................. 19 Typical Application Circuit ............................................................. 1 LDO.............................................................................................. 20 Revision History ............................................................................... 2 Applications Information .............................................................. 21 Specifications..................................................................................... 3 Buck External Component Selection....................................... 21 General Specifications ................................................................. 3 LDO External Component Selection....................................... 23 BUCK1 and BUCK2 Specifications ........................................... 4 Power Dissipation and Thermal Considerations ....................... 24 LDO Specifications ...................................................................... 5 Buck Regulator Power Dissipation .......................................... 24 Input and Output Capacitor, Recommended Specifications .. 6 Junction Temperature ................................................................ 25 Absolute Maximum Ratings ............................................................ 7 PCB Layout Guidelines .................................................................. 26 Thermal Resistance ...................................................................... 7 Typical Application Schematics .................................................... 27 ESD Caution .................................................................................. 7 Bill of Materials ........................................................................... 27 Pin Configuration and Function Descriptions ............................. 8 Outline Dimensions ....................................................................... 28 Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 28 REVISION HISTORY 1/1—Rev. 0 to Rev. A Changes to Features Section and Figure 1..................................... 1 Changes to Table 2 ............................................................................ 4 Changes to Table 3 ............................................................................ 5 Changes to Table 4 ............................................................................ 6 Changes to Table 7 ............................................................................ 8 Changes to Figure 34 ...................................................................... 14 Changes to LDO Section and Figure 48 ...................................... 20 Changes to Table 9 and Figure 50 ................................................. 22 Changes to Buck Regulator Power Dissipation Section ............ 24 Changes to Figure 52 and Figure 53............................................. 27 Changes to Ordering Guide .......................................................... 28 8/11—Revision 0: Initial Version Rev. A | Page 2 of 28 Data Sheet ADP5024 SPECIFICATIONS GENERAL SPECIFICATIONS VAVIN = VIN1 = VIN2 = 2.3 V to 5.5 V; VIN3 = 1.7 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1. Parameter INPUT VOLTAGE RANGE THERMAL SHUTDOWN Threshold Hysteresis START-UP TIME 1 BUCK1, LDO BUCK2 EN1, EN2, EN3, MODE INPUTS Input Logic High Input Logic Low Input Leakage Current INPUT CURRENT All Channels Enabled All Channels Disabled VIN1 UNDERVOLTAGE LOCKOUT High UVLO Input Voltage Rising High UVLO Input Voltage Falling Low UVLO Input Voltage Rising Low UVLO Input Voltage Falling 1 Symbol VAVIN, VIN1, VIN2 Test Conditions/Comments TSSD TSSD-HYS TJ rising Min 2.3 tSTART1 tSTART2 VIH VIL VI-LEAKAGE ISTBY-NOSW ISHUTDOWN Typ Max 5.5 150 20 °C °C 250 300 µs µs 1.1 No load, no buck switching TJ = −40°C to +85°C UVLOVIN1RISE UVLOVIN1FALL UVLOVIN1RISE UVLOVIN1FALL 0.05 0.4 1 V V µA 108 0.3 175 1 µA µA 3.9 V V V V 3.1 2.275 1.95 Unit V Start-up time is defined as the time from EN1 = EN2 = EN3 from 0 V to VAVIN to VOUT1, VOUT2, and VOUT3 reaching 90% of their nominal levels. Start-up times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information. Rev. A | Page 3 of 28 ADP5024 Data Sheet BUCK1 AND BUCK2 SPECIFICATIONS VAVIN = VIN1 = VIN2 = 2.3 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. 1 Table 2. Parameter OUTPUT CHARACTERISTICS Output Voltage Accuracy Line Regulation Load Regulation VOLTAGE FEEDBACK OPERATING SUPPLY CURRENT BUCK1 Only Test Conditions/Comments Min ΔVOUT1/VOUT1, ΔVOUT2/VOUT2 (ΔVOUT1/VOUT1)/ΔVIN1, (ΔVOUT2/VOUT2)/ΔVIN2 (ΔVOUT1/VOUT1)/ΔIOUT1, (ΔVOUT2/VOUT2)/ΔIOUT2 VFB1, VFB2 ILOAD1 = ILOAD2 = 0 mA to 1200 mA, PWM mode −3 IIN BUCK2 Only IIN BUCK1 and BUCK2 IIN PSM CURRENT THRESHOLD SW CHARACTERISTICS SW On Resistance Current Limit ACTIVE PULL-DOWN OSCILLATOR FREQUENCY 1 Symbol IPSM RNFET RPFET RNFET RPFET ILIMIT1, ILIMIT2 RPDWN-B fSW Typ Max Unit +3 % PWM mode −0.05 %/V ILOAD = 0 mA to 1200 mA, PWM mode −0.1 %/A Models with adjustable outputs MODE = ground ILOAD1 = 0 mA, device not switching, all other channels disabled ILOAD2 = 0 mA, device not switching, all other channels disabled ILOAD1 = ILOAD2 = 0 mA, device not switching, LDO channels disabled PSM to PWM operation VIN1 = VIN2 = 3.6 V VIN1 = VIN2 = 3.6 V VIN1 = VIN2 = 5.5 V VIN1 = VIN2 = 5.5 V PFET switch peak current limit Channel disabled 0.485 1600 2.5 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Rev. A | Page 4 of 28 0.5 0.515 V 44 μA 55 μA 67 μA 100 mA 155 205 137 162 1950 75 3.0 240 310 204 243 2300 3.5 mΩ mΩ mΩ mΩ mA Ω MHz Data Sheet ADP5024 LDO SPECIFICATIONS VIN3 = (VOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; CIN = COUT = 1 µF; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. 1 Table 3. Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT Bias Current per LDO 2 Total System Input Current Symbol VIN3 Test Conditions/Comments IVIN3BIAS IOUT3 = 0 µA IOUT3 = 10 mA IOUT3 = 300 mA Includes all current into AVIN, VIN1, VIN2, and VIN3 IOUT3 = 0 µA, all other channels disabled IIN LDO Only OUTPUT CHARACTERISTICS Output Voltage Accuracy Line Regulation Load Regulation 3 VOLTAGE FEEDBACK DROPOUT VOLTAGE 4 CURRENT-LIMIT THRESHOLD 5 ACTIVE PULL-DOWN OUTPUT NOISE Regulator LDO POWER SUPPLY REJECTION RATIO Regulator LDO ΔVOUT3/VOUT3 (ΔVOUT3/VOUT3)/ΔVIN3 (ΔVOUT3/VOUT3)/ΔIOUT3 100 µA < IOUT3 < 300 mA IOUT3 = 1 mA IOUT3 = 1 mA to 300 mA ILIMIT3 RPDWN-L NOISELDO PSRR Typ Max 5.5 Unit V 10 60 165 30 100 245 µA µA µA 53 −3 −0.03 µA +3 +0.03 0.003 0.515 % %/V %/mA V mV Channel disabled 0.001 0.5 50 75 100 180 600 600 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V 100 µV rms 10 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 100 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 1 MHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 60 dB 62 dB 63 dB VFB3 VDROPOUT Min 1.7 0.485 VOUT3 = 5.2 V, IOUT3 = 300 mA VOUT3 = 3.3 V, IOUT3 = 300 mA VOUT3 = 2.5 V, IOUT3 = 300 mA VOUT3 = 1.8 V, IOUT3 = 300 mA 335 140 mV mV mA Ω All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). This is the input current into VIN3, which is not delivered to the output load. Based on an endpoint calculation using 1 mA and 300 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages above 1.7 V. 5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V. 1 2 3 Rev. A | Page 5 of 28 ADP5024 Data Sheet INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS TA = −40°C to +125°C, unless otherwise specified. Table 4. Parameter NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS BUCK1, BUCK2 Input Capacitor Ratings BUCK1, BUCK2 Output Capacitor Ratings LDO 1 Input and Output Capacitor Ratings CAPACITOR ESR 1 Symbol Min CMIN1, CMIN2 CMIN1, CMIN2 CMIN3, CMIN4 RESR 4.7 10 1.0 0.001 Typ Max Unit 40 40 µF µF µF Ω 1 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics. Rev. A | Page 6 of 28 Data Sheet ADP5024 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter AVIN to AGND VIN1, VIN2 to AVIN PGND1, PGND2 to AGND VIN3, VOUT1, VOUT2, FB1, FB2, FB3, EN1, EN2, EN3, MODE to AGND VOUT3 to AGND SW1 to PGND1 SW2 to PGND2 Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating −0.3 V to +6 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to (AVIN + 0.3 V) −0.3 V to (VIN3 + 0.3 V) −0.3 V to (VIN1 + 0.3 V) −0.3 V to (VIN2 + 0.3 V) −65°C to +150°C −40°C to +125°C θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance Package Type 24-Lead, 0.5 mm pitch LFCSP ESD CAUTION JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For detailed information on power dissipation, see the Power Dissipation and Thermal Considerations section. Rev. A | Page 7 of 28 θJA 35 θJC 3 Unit °C/W ADP5024 Data Sheet 20 VOUT3 19 FB3 22 EN3 21 VIN3 24 AGND 23 AGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND 1 18 AGND AGND 2 17 AVIN VIN2 3 ADP5024 16 VIN1 SW2 4 TOP VIEW 15 SW1 PGND2 5 14 PGND1 NC 6 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE GROUND PLANE. 09888-002 FB1 11 EN1 12 VOUT2 9 VOUT1 10 FB2 8 EN2 7 13 MODE Figure 2. Pin Configuration—View from Top of the Die Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic AGND AGND VIN2 SW2 PGND2 NC EN2 FB2 9 10 11 VOUT2 VOUT1 FB1 12 13 EN1 MODE 14 15 16 17 18 19 PGND1 SW1 VIN1 AVIN AGND FB3 20 21 22 23 24 VOUT3 VIN3 EN3 AGND AGND EPAD (EP) Description Analog Ground. Analog Ground. BUCK2 Input Supply (2.3 V to 5.5 V). Connect VIN2 to VIN1 and AVIN. BUCK2 Switching Node. Dedicated Power Ground for BUCK2. No Connect. Leave this pin unconnected. BUCK2 Enable Pin. High level turns on this regulator, and low level turns it off. BUCK2 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the BUCK2 resistor divider. For device models with a fixed output voltage, leave this pin unconnected. BUCK2 Output Voltage Sensing Input. Connect VOUT2 to the top of the capacitor on VOUT2. BUCK1 Output Voltage Sensing Input. Connect VOUT1 to the top of the capacitor on VOUT1. BUCK1 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the BUCK1 resistor divider. For device models with a fixed output voltage, leave this pin unconnected. BUCK1 Enable Pin. High level turns on this regulator, and low level turns it off. BUCK1/BUCK2 Operating Mode. MODE = high for forced PWM operation. MODE = low for automatic PWM/PSM operation. Dedicated Power Ground for BUCK1. BUCK1 Switching Node. BUCK1 Input Supply (2.3 V to 5.5 V). Connect VIN1 to VIN2 and AVIN. Analog Input Supply (2.3 V to 5.5 V). Connect AVIN to VIN1 and VIN2. Analog Ground. LDO Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the LDO resistor divider. For device models with a fixed output voltage, connect this pin to the top of the capacitor on VOUT3. LDO Output Voltage. LDO Input Supply (1.7 V to 5.5 V). LDO Enable Pin. High level turns on this regulator, and low level turns it off. Analog Ground. Analog Ground. Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane. Rev. A | Page 8 of 28 Data Sheet ADP5024 TYPICAL PERFORMANCE CHARACTERISTICS VIN1= VIN2 = VIN3= 3.6 V, TA = 25°C, unless otherwise noted. 3.35 120 3.33 VIN = 3.6V, +25°C 100 VOUT (V) QUIESCENT CURRENT (µA) 140 80 60 3.31 VIN = 3.6V, +85°C 3.29 VIN = 3.6V, –40°C 40 3.27 2.8 3.3 3.8 4.3 4.8 5.3 INPUT VOLTAGE (V) 3.25 0 0.2 0.4 0.6 0.8 1.0 1.2 IOUT (A) Figure 3. System Quiescent Current vs. Input Voltage, VOUT1 = 3.3 V, VOUT2 = 1.8 V, VOUT3 = 1.2 V, All Channels Unloaded 09888-006 0 2.3 09888-003 20 Figure 6. BUCK1 Load Regulation Across Temperature, VOUT1 = 3.3 V, Automatic Mode 1.864 T SW 1.844 4 VIN = 3.6V, +25°C VOUT (V) IOUT 2 VOUT 1 1.824 VIN = 3.6V, +85°C 1.804 VIN = 3.6V, –40°C EN 1.784 BW BW CH2 50.0mA Ω BW M 40.0µs BW CH4 5.00V T 11.20% A CH3 2.2V 1.764 09888-004 CH1 2.00V CH3 5.00V 0 0.2 0.6 0.8 1.0 1.2 IOUT (A) Figure 4. BUCK1 Startup, VOUT1 = 1.8 V, IOUT1 = 5 mA Figure 7. BUCK2 Load Regulation Across Temperature, VOUT2 = 1.8 V, Automatic Mode 0.799 T 0.798 SW 0.797 IOUT 0.796 VOUT (V) 4 VOUT VIN = 3.6V, +85°C VIN = 3.6V, +25°C 0.795 0.794 0.793 1 EN 0.792 0.791 VIN = 3.6V, –40°C 3 0.790 BW BW CH2 50.0mA Ω BW M 40.0µs BW CH4 5.00V T 11.20% A CH3 2.2V 0.789 09888-005 CH1 2.00V CH3 5.00V 0 0.2 0.4 0.6 IOUT (A) 0.8 1.0 1.2 09888-008 2 0.4 09888-007 3 Figure 8. BUCK1 Load Regulation Across Input Voltage, VOUT1 = 0.8 V, PWM Mode Figure 5. BUCK2 Startup, VOUT2 = 3.3 V, IOUT2 = 10 mA Rev. A | Page 9 of 28 ADP5024 Data Sheet 100 100 VIN = 3.9V 90 80 80 VIN = 4.2V VIN = 2.3V VIN = 5.5V 60 50 40 20 20 10 10 0.01 0.1 1 0 0.001 100 90 90 80 80 70 EFFICIENCY(%) VIN = 3.9V 50 40 30 60 50 VIN = 5.5V VIN = 2.3V VIN = 3.6V 40 20 VIN = 4.2V 1 0.1 IOUT (A) 0 0.001 0.01 Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, PWM Mode 100 90 90 80 VIN = 3.6V 80 VIN = 2.3V 70 VIN = 5.5V EFFICIENCY (%) VIN = 4.2V VIN = 3.6V 50 40 40 20 10 10 IOUT (A) 09888-011 20 1 Figure 11. BUCK2 Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V, Automatic Mode VIN = 5.5V 50 30 0.1 VIN = 2.3V 60 30 0.01 1 Figure 13. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 0.8 V, Automatic Mode 100 70 0.1 IOUT (A) 0 0.001 VIN = 4.2V 0.01 0.1 IOUT (A) 1 09888-014 0.01 09888-013 10 09888-010 0 0.001 0 0.001 VIN = 4.2V 30 20 60 1 VIN = 5.5V 60 10 0.1 Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V, PWM Mode 100 70 0.01 IOUT (A) Figure 9. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, Automatic Mode EFFICIENCY (%) 40 30 0.001 VIN = 4.2V 50 30 IOUT (A) EFFICIENCY (%) VIN = 5.5V 60 09888-012 EFFICIENCY (%) 70 09888-009 EFFICIENCY (%) 70 0 0.0001 VIN = 3.6V 90 Figure 14. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 0.8 V, PWM Mode Rev. A | Page 10 of 28 Data Sheet ADP5024 3.3 100 +25°C –40°C 90 3.2 +25°C +85°C SCOPE FREQUENCY (MHz) 80 –40°C EFFICIENCY (%) 70 60 50 40 30 3.1 3.0 +85°C 2.9 2.8 2.7 20 2.6 10 0.1 1 IOUT (A) 0 0.2 0.6 0.8 1.0 1.2 IOUT (A) Figure 18. BUCK2 Switching Frequency vs. Output Current, Across Temperature, VOUT2 = 1.8 V, PWM Mode Figure 15. BUCK1 Efficiency vs. Load Current, Across Temperature, VIN = 3.9 V, VOUT1 = 3.3 V, Automatic Mode 100 90 0.4 09888-018 0.01 09888-015 2.5 0 0.001 T +25°C VOUT +85°C 80 1 EFFICIENCY (%) 70 ISW –40°C 60 2 50 40 SW 30 20 10 0.01 0.1 1 IOUT (A) Figure 16. BUCK2 Efficiency vs. Load Current, Across Temperature, VOUT2 = 1.8 V, Automatic Mode CH2 500mA Ω CH4 2.00V CH1 50mV A CH2 240mA T 28.40% Figure 19. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Automatic Mode 100 T +25°C 90 VOUT 80 1 70 EFFICIENCY (%) M 4.00µs 09888-019 4 09888-016 0 0.001 +85°C –40°C 60 ISW 2 50 40 SW 30 20 10 0.01 0.1 1 IOUT (A) Figure 17. BUCK1 Efficiency vs. Load Current, Across Temperature, VOUT1 = 0.8 V, Automatic Mode CH1 50mV BW M 4.00µs A CH2 CH2 500mA Ω BW CH4 2.00V T 28.40% 220mA 09888-020 4 09888-017 0 0.001 Figure 20. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, Automatic Mode Rev. A | Page 11 of 28 ADP5024 Data Sheet T T VOUT 1 VIN ISW VOUT 2 1 SW SW 4 3 M 400ns A CH2 CH2 500mA Ω BW CH4 2.00V T 28.40% BW 220mA CH1 50.0mV CH3 1.00V M 1.00ms BW BW CH4 2.00V A CH3 4.80V BW T 30.40% Figure 21. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode 09888-024 CH1 50mV 09888-021 4 Figure 24. Buck2 Response to Line Transient, VIN = 4.5 V to 5.0 V, VOUT2 = 1.8 V, PWM Mode T T SW VOUT 1 4 ISW VOUT 2 1 SW IOUT 2 CH2 500mA Ω M 400ns A CH2 BW CH4 2.00V T 28.40% BW 220mA CH1 50.0mV Figure 22. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, PWM Mode BW CH2 50.0mA Ω BW M 20.0µs A CH2 BW T 60.000µs CH4 5.00V 356mA 09888-025 CH1 50mV 09888-022 4 Figure 25. BUCK1 Response to Load Transient, IOUT1 from 1 mA to 50 mA, VOUT1 = 3.3 V, Automatic Mode T T SW 4 VIN VOUT VOUT 1 1 SW IOUT 3 BW BW M 1.00ms CH4 2.00V BW T 30.40% A CH3 4.80V CH1 50.0mV Figure 23. BUCK1 Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 3.3 V, PWM Mode BW CH2 50.0mA Ω BW M 20.0µs A CH2 BW CH4 5.00V T 22.20% 379mA 09888-026 CH1 50.0mV CH3 1.00V 09888-023 2 Figure 26. BUCK2 Response to Load Transient, IOUT2 from 1 mA to 50 mA, VOUT2 = 1.8 V, Automatic Mode Rev. A | Page 12 of 28 Data Sheet ADP5024 T T SW 4 IIN 2 VOUT 1 VOUT 1 EN IOUT BW CH2 200mA Ω CH4 5.00V BW M 20.0µs A CH2 408mA BW T 20.40% 09888-027 CH1 50.0mV CH1 2.00V CH3 5.00V BW BW CH2 50.0mA Ω BW M 40.0µs A CH3 2.2V BW T 11.20% 09888-030 3 2 Figure 30. LDO Startup, VOUT3 = 3.0 V, IOUT3 = 5 mA Figure 27. BUCK1 Response to Load Transient, IOUT1 from 20 mA to 180 mA, VOUT1 = 3.3 V, Automatic Mode 2.820 T SW 2.815 4 2.810 VOUT3 (V) 2.805 VOUT 1 2.800 VIN = 4.5V VIN = 3.3V 2.795 IOUT 2.790 VIN = 5.5V 2.785 BW CH2 200mA Ω CH4 5.00V BW M 20.0µs A CH2 88.0mA BW T 19.20% 09888-028 CH1 100mV 2.780 0 0.05 0.10 0.15 0.20 0.25 0.30 IOUT (A) Figure 28. BUCK2 Response to Load Transient, IOUT2 from 20 mA to 180 mA, VOUT2 = 1.8 V, Automatic Mode Figure 31. LDO Load Regulation Across Input Voltage, VOUT3 = 2.8 V 400 T 350 VOUT2 2 300 SW1 RDSON (mΩ) +125°C 3 VOUT1 1 VIN = 5.0V 09888-031 2 250 +25°C 200 150 –40°C SW2 100 50 BW BW CH2 5.00V CH4 5.00V BW M 400ns BW T 50.00% A CH4 1.90V 0 2.3 09888-029 CH1 5.00V CH3 5.00V 2.8 3.3 3.8 4.3 4.8 5.3 INPUT VOLTAGE (V) Figure 29. VOUTx and SW Waveforms for BUCK1 and BUCK2 in PWM Mode Showing Out-of-Phase Operation Rev. A | Page 13 of 28 Figure 32. NMOS RDSON vs. Input Voltage Across Temperature 09888-032 4 ADP5024 Data Sheet 250 50 45 200 40 +125°C GROUND CURRENT (µA) RDSON (mΩ) +25°C 150 –40°C 100 35 30 25 20 15 50 10 2.8 3.3 3.8 4.3 4.8 0 09888-033 0 2.3 5.3 INPUT VOLTAGE (V) 0.05 0.10 0.15 0.20 0.25 LOAD CURRENT (A) Figure 33. PMOS RDSON vs. Input Voltage Across Temperature Figure 36. LDO Ground Current vs. Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V 3.45 T 3.40 IOUT 3.35 VOUT (V) 0 09888-036 5 2 VIN = 4.2V, +85°C 3.30 VIN = 4.2V, +25°C 1 VOUT 3.25 VIN = 4.2V, –40°C 0 0.05 0.10 0.15 0.20 0.25 0.30 IOUT (A) Figure 34. LDO Load Regulation Across Temperature, VIN3 = 4.2 V, VOUT3 = 3.3 V 3.0 2.5 VOUT (V) 2.0 IOUT = 10mA CH1 100mV 09888-034 3.15 BW CH2 100mA Ω BW M 40.0µs A CH2 52.0mA T 19.20% 09888-037 3.20 Figure 37. LDO Response to Load Transient, IOUT3 from 1 mA to 80 mA, VOUT3 = 2.8 V T IOUT = 100µA IOUT = 1mA IOUT = 100mA IOUT = 150mA IOUT = 300mA VIN 1.5 VOUT 1 2 1.0 0.5 VIN (V) Figure 35. LDO Line Regulation Across Output Load, VOUT3 = 2.8 V CH1 20.0mV CH3 1.00V 09888-035 0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 M 100µs T 28.40% A CH3 4.80V 09888-038 3 Figure 38. LDO Response to Line Transient, Input Voltage from 4.5 V to 5.5 V, VOUT3 = 2.8 V Rev. A | Page 14 of 28 Data Sheet ADP5024 0 60 VIN = 5V 55 –20 VIN = 3.3V –40 PSRR (dB) 45 40 –60 –80 35 –100 30 0.01 0.1 1 10 –120 10 09888-039 25 0.001 100 ILOAD (mA) Figure 39. LDO Output Noise vs. Load Current, Across Input Voltage, VOUT3 = 2.8 V 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 42. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 3.0 V 0 65 VIN = 5V 60 –20 VIN = 3.3V 55 100µA 1mA 10mA 50mA 100mA 150mA –40 50 PSRR (dB) RMS NOISE (µV) 100µA 1mA 10mA 50mA 100mA 150mA 09888-042 RMS NOISE (µV) 50 45 40 –60 –80 35 0.01 0.1 1 ILOAD (mA) 10 –120 10 09888-040 100 Figure 40. LDO Output Noise vs. Load Current, Across Input Voltage, VOUT3 = 3.0 V –20 –10 –20 –30 PSRR (dB) –40 –50 –60 1M 10M –50 –60 –70 –80 –80 –90 –90 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100µA 1mA 10mA 50mA 100mA 150mA –40 –70 –100 10 10k 100k FREQUENCY (Hz) 0 100µA 1mA 10mA 50mA 100mA 150mA 09888-041 PSRR (dB) –30 1k Figure 43. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 2.8 V 0 –10 100 –100 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 44. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 3.0 V Figure 41. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V Rev. A | Page 15 of 28 09888-044 25 0.001 09888-043 –100 30 ADP5024 Data Sheet THEORY OF OPERATION VOUT1 FB1 FB2 VOUT2 GM ERROR AMP AVIN ENBK1 75Ω 75Ω ENBK2 GM ERROR AMP PWM COMP PWM COMP VIN1 SOFT START SOFT START PSM COMP PSM COMP VIN2 ILIMIT ILIMIT LOW CURRENT PWM/ PSM CONTROL BUCK1 PWM/ PSM CONTROL BUCK2 LOW CURRENT SW2 SW1 OSCILLATOR DRIVER AND ANTISHOOT THROUGH DRIVER AND OP ANTISHOOT MODE THROUGH SYSTEM UNDERVOLTAGE LOCKOUT SEL THERMAL SHUTDOWN PGND1 B MODE2 PGND2 Y A MODE EN2 EN3 ENABLE AND MODE CONTROL ENBK1 ENBK2 LDO UNDERVOLTAGE LOCKOUT ENLDO R1 AVIN LDO CONTROL 600Ω R2 ADP5024 VIN3 AGND FB3 VOUT3 Figure 45. Functional Block Diagram Rev. A | Page 16 of 28 ENLDO 09888-045 EN1 Data Sheet ADP5024 POWER MANAGEMENT UNIT Thermal Protection The ADP5024 is a micropower management unit (microPMU) combing two step-down (buck) dc-to-dc convertors and one low dropout linear regulator (LDO). The high switching frequency and tiny 24-lead LFCSP package allow for a small power management solution. In the event that the junction temperature rises above 150°C, the thermal shutdown circuit turns off all of the regulators. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 20°C hysteresis is included so that when thermal shutdown To combine these high performance regulators into the microPMU, there is a system controller allowing them to operate together. occurs, the regulators do not return to operation until the on-chip temperature drops below 130°C. When emerging from thermal shutdown, all regulators restart with soft start control. The buck regulators can operate in forced PWM mode if the MODE pin is at a logic level high. In forced PWM mode, the buck switching frequency is always constant and does not change with the load current. If the MODE pin is at logic level low, the switching regulators operate in automatic PWM/PSM mode. In this mode, the regulators operate at a fixed PWM frequency when the load current is above the PSM current threshold. When the load current falls below the PSM current threshold, the regulator in question enters PSM, where the switching occurs in bursts. The burst repetition rate is a function of the current load and the output capacitor value. This operating mode reduces the switching and quiescent current losses. The automatic PWM/PSM mode transition is controlled independently for each buck regulator. The two bucks operate synchronized to each other. Undervoltage Lockout The ADP5024 has individual enable pins (EN1 to EN3) that control the activation of each regulator. The regulators are activated by a logic level high applied to the respective EN pin, wherein EN1 controls BUCK1, EN2 controls BUCK2, and EN3 controls the LDO. To protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated in the system. If the input voltage on VIN1 drops below a typical 2.15 V UVLO threshold, all channels shut down. In the buck channels, both the power switch and the synchronous rectifier turn off. When the voltage on VIN1 rises above the UVLO threshold, the part is enabled once more. Alternatively, the user can select device models with a UVLO set at a higher level, suitable for USB applications. For these models, the device reaches the turn off threshold when the input supply drops to 3.65 V typical. In case of a thermal or UVLO event, the active pull-downs (if factory enabled) are enabled to discharge the output capacitors quickly. The pull-down resistors remain engaged until the thermal fault event is no longer present or the input supply voltage falls below the VPOR voltage level. The typical value of VPOR is approximately 1 V. Enable/Shutdown Regulator output voltages are set through external resistor dividers or can be optionally factory programmed to default values (see the Ordering Guide section). The ADP5024 has an individual control pin for each regulator. A logic level high applied to the ENx pin activates a regulator whereas a logic level low turns off a regulator. When a regulator is turned on, the output voltage ramp rate is controlled though a soft start circuit to avoid a large inrush current due to the charging of the output capacitors. Figure 46 shows the regulator activation timings for the ADP5024 when all enable pins are connected to AVIN. Also shown is the active pull-down activation. Rev. A | Page 17 of 28 ADP5024 Data Sheet VUVLO AVIN VPOR VOUT1 VOUT3 VOUT2 30µs (MIN) 30µs (MIN) 50µs (MIN) 50µs (MIN) 09888-046 BUCK1, LDO PULL-DOWNS BUCK2 PULL-DOWN Figure 46. Regulator Sequencing (EN1 = EN2 = EN3 = VAVIN) Rev. A | Page 18 of 28 Data Sheet ADP5024 BUCK1 AND BUCK2 The buck uses a fixed frequency and high speed current mode architecture. The buck operates with an input voltage of 2.3 V to 5.5 V. The buck output voltage is set through external resistor dividers, shown in Figure 47 for BUCK1. The output voltage can optionally be factory programmed to default values, as indicated in the Ordering Guide section. In this event, R1 and R2 are not needed, and FB1 can remain unconnected. In all cases, VOUT1 must be connected to the output capacitor. FB1 is 0.5 V. SW1 L1 1µH VOUT1 BUCK AGND VOUT1 = VFB1 R1 C5 10µF R2 R1 +1 R2 PSM Current Threshold Oscillator/Phasing of Inductor Switching 09888-047 FB1 The ADP5024 has a dedicated MODE pin controlling the PSM and PWM operation. A logic level high applied to the MODE pin forces both bucks to operate in PWM mode. A logic level low sets the bucks to operate in automatic PSM/PWM. The PSM current threshold is set to100 mA. The bucks employ a scheme that enables this current to remain accurately controlled, independent of input and output voltage levels. This scheme also ensures that there is very little hysteresis between the PSM current threshold for entry to and exit from the PSM. The PSM current threshold is optimized for excellent efficiency over all load currents. VOUT1 VIN1 mode. The output capacitor discharges until the output voltage falls to the PWM regulation voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. This process is repeated while the load current is below the PSM current threshold. The ADP5024 ensures that both bucks operate at the same switching frequency when both bucks are in PWM mode. Figure 47. BUCK1 External Output Voltage Setting Control Scheme The bucks operate with a fixed frequency, current mode PWM control architecture at medium to high loads for high efficiency, but shift to a power save mode (PSM) control scheme at light loads to lower the regulation power losses. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. When operating in PSM at light loads, the output voltage is controlled in a hysteretic manner, with higher output voltage ripple. During part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. PWM Mode In PWM mode, the bucks operate at a fixed frequency of 3 MHz, set by an internal oscillator. At the start of each oscillator cycle, the PFET switch is turned on, sending a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current threshold, which turns off the PFET switch and turns on the nFET synchronous rectifier. This sends a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier stays on for the remainder of the cycle. The buck regulates the output voltage by adjusting the peak inductor current threshold. Power Save Mode (PSM) The bucks smoothly transition to PSM operation when the load current decreases below the PSM current threshold. When either of the bucks enters PSM, an offset is induced in the PWM regulation level, which makes the output voltage rise. When the output voltage reaches a level approximately 1.5% above the PWM regulation level, PWM operation is turned off. At this point, both power switches are off, and the buck enters an idle Additionally, the ADP5024 ensures that when both bucks are in PWM mode, they operate out of phase, whereby the Buck2 PFET starts conducting exactly half a clock period after the BUCK1 PFET starts conducting. Short-Circuit Protection The bucks include frequency foldback to prevent output current runaway on a hard short. When the voltage at the feedback pin falls below half the target output voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. The reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. Soft Start The bucks have an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. Current Limit Each buck has protection circuitry to limit the amount of positive current flowing through the PFET switch and the amount of negative current flowing through the synchronous rectifier. The positive current limit on the power switch limits the amount of current that can flow from the input to the output. The negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% Duty Operation With a drop in input voltage, or with an increase in load current, the buck may reach a limit where, even with the PFET switch on 100% of the time, the output voltage drops below the Rev. A | Page 19 of 28 ADP5024 Data Sheet desired output voltage. At this limit, the buck transitions to a mode where the PFET switch stays on 100% of the time. When the input conditions change again and the required duty cycle falls, the buck immediately restarts PWM regulation without allowing overshoot on the output voltage. Active Pull-Down Resistors All regulators have optional, factory programmable, active pulldown resistors discharging the respective output capacitors when the regulators are disabled. The pull-down resistors are connected between VOUTx and AGND. Active pull-downs are disabled when the regulators are turned on. The typical value of the pull-down resistor is 600 Ω for the LDO and 75 Ω for each buck. Figure 46 shows the activation timings for the active pulldowns during regulator activation and deactivation. configurations where the LDO supply voltage is provided from one of the buck regulators. The LDO output voltage is set through external resistor dividers, as shown in Figure 48. The output voltage can optionally be factory programmed to default values, as indicated in the Ordering Guide section. In this event, Ra and Rb are not needed, and FB3 must be connected to the top of the capacitor on VOUT3. FB3 is 0.5 V. VIN3 VOUT3 LDO FB3 VOUT3 Ra C7 1µF Rb The ADP5024 contains one LDO with low quiescent current and low dropout voltage and provides up to 300 mA of output current. Drawing a low 10 μA quiescent current (typical) at no load makes the LDO ideal for battery-operated portable equipment. The LDO operates with an input voltage of 1.7 V to 5.5 V. The wide operating range makes the LDO suitable for cascading Ra VOUT3 = VFB3 +1 Rb 09888-048 LDO Figure 48. LDO External Output Voltage Setting The LDO also provides high power supply rejection ratio (PSRR), low output noise, and excellent line and load transient response with only a small 1 µF ceramic input and output capacitor. Rev. A | Page 20 of 28 Data Sheet ADP5024 APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Trade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in Figure 1. Feedback Resistors For the adjustable model, shown in Figure 47, the total combined resistance for R1 and R2 is not to exceed 400 kΩ. Inductor The high switching frequency of the ADP5024 bucks allows for the selection of small chip inductors. For best performance, use inductor values between 0.7 μH and 3 μH. Suggested inductors are shown in Table 8. The peak-to-peak inductor current ripple is calculated using the following equation: I RIPPLE = VOUT × (VIN − VOUT ) VIN × f SW × L The worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calculated using the following equation: CEFF = COUT × (1 − TEMPCO) × (1 − TOL) where: CEFF is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over −40°C to +85°C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and COUT is 9.2 μF at 1.8 V, as shown in Figure 49. where: fSW is the switching frequency. L is the inductor value. The minimum dc current rating of the inductor must be greater than the inductor peak current. The inductor peak current is calculated using the following equation: I PEAK = I LOAD( MAX ) + Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric that is adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. I RIPPLE 2 Substituting these values in the equation yields CEFF = 9.2 μF × (1 − 0.15) × (1 − 0.1) ≈ 7.0 μF To guarantee the performance of the bucks, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 12 Inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (DCR). Larger sized inductors have smaller DCR, which may decrease inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the bucks are high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its low core losses and low EMI. CAPACITANCE (µF) 10 8 6 4 Output Capacitor 0 0 1 2 3 4 5 DC BIAS VOLTAGE (V) 6 09888-049 2 Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. Figure 49. Capacitance vs. Voltage Characteristic Table 8. Suggested 1.0 μH Inductors Vendor Murata Murata Taiyo Yuden Coilcraft Coilcraft Toko Model LQM2MPN1R0NG0B LQH32PN1R0NN0 CBC3225T1R0MR XFL4020-102ME XPL2010-102ML MDT2520-CN Dimensions (mm) 2.0 × 1.6 × 0.9 3.2 × 2.5 × 1.6 3.2 × 2.5 × 2.5 4.0 × 4.0 × 2.1 1.9 × 2.0 × 1.0 2.5 × 2.0 × 1.2 Rev. A | Page 21 of 28 ISAT (mA) 1400 2300 2000 5400 1800 1350 DCR (mΩ) 85 45 71 11 89 85 ADP5024 Data Sheet The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: I RIPPLE V IN ≈ 8 × f SW × C OUT (2π × f SW )2 × L × C OUT A 4.7 µF capacitor is recommended for a typical application; depending on the application, a smaller or larger output capacitor may be chosen. A list of suggested 4.7 µF capacitors is shown in Table 10. The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 µF and a maximum of 10 µF. Capacitors with lower equivalent series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in the following equation: ESRCOUT ≤ VRIPPLE I RIPPLE Table 9. Suggested 10 μF Capacitors The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 µF and a maximum of 40 µF. Vendor Murata TDK Panasonic The buck regulators require 10 µF output capacitors to guarantee stability and response to rapid load variations and to transition into and out of the PWM/PSM modes. A list of suggested capacitors is shown in Table 9. In certain applications where one or both buck regulator powers a processor, the operating state is known because it is controlled by software. In this condition, the processor can drive the MODE pin according to the operating state; consequently, it is possible to reduce the output capacitor from 10 µF to 4.7 µF because the regulator does not expect a large load variation when working in PSM mode (see Figure 50). Vendor Murata Taiyo Yuden Panasonic 2.3V TO 5.5V Type X5R X5R X5R X5R SW1 BUCK1 EN1 EN1 FB1 PGND1 L1 1µH MODE MODE SW2 C2 4.7µF BUCK2 EN2 1.7V TO 5.5V EN3 VIN3 C3 1µF C5 10µF R2 PWM PSM/PWM VOUT2 VIN2 ON VOUT1 AT 1200mA R1 MODE OFF Model GRM155B30J105K C1005JB0J105KT ECJ0EB0J105K LMK105BJ105MV-F VOUT1 C1 4.7µF ON Model GRM188R60J475ME19D JMK107BJ475 ECJ-0EB0J475M HOUSEKEEPING VIN1 OFF Type X5R X5R X5R Vendor Murata TDK Panasonic Taiyo Yuden VOUT (VIN − VOUT ) VIN AVIN EN2 EN3 Voltage Rating (V) 6.3 6.3 6.3 Case Size 0402 0402 0402 Voltage Rating (V) 6.3 6.3 6.3 Case Size 0402 0402 0402 0402 Voltage Rating (V) 6.3 6.3 6.3 10.0 Table 11. Suggested 1.0 μF Capacitors Higher value input capacitors help to reduce the input voltage ripple and improve transient response. Maximum input capacitor current is calculated using the following equation: CAVIN 0.1µF Model GRM188R60J106 C1608JB0J106K ECJ1VB0J106M Case Size 0603 0603 0603 Table 10. Suggested 4.7 μF Capacitors Input Capacitor I CIN ≥ I LOAD( MAX ) Type X5R X5R X5R FB2 PGND2 L2 1µH R3 R4 VOUT2 AT 1200mA C6 10µF VOUT3 LDO (ANALOG) FB3 R5 R6 VOUT3 AT 300mA C7 1µF ADP5024 AGND Figure 50. Processor System Power Management with PSM/PWM Control Rev. A | Page 22 of 28 09888-050 V RIPPLE = To minimize supply noise, place the input capacitor as close as possible to the VINx pin of the buck. As with the output capacitor, a low ESR capacitor is recommended. Data Sheet ADP5024 1.2 LDO EXTERNAL COMPONENT SELECTION Feedback Resistors 1.0 CAPACITANCE (µF) For the adjustable model, the maximum value of Rb must not exceed 200 kΩ (see Figure 48). Output Capacitor Input Bypass Capacitor Connecting a 1 µF capacitor from VIN3 to ground reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when encountering long input traces or high source impedance. If greater than 1 µF of output capacitance is required, increase the input capacitor to match it. Input and Output Capacitor Properties Use any good quality ceramic capacitors with the ADP5024 as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric that is adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any LDO because of their poor temperature and dc bias characteristics. Figure 51 depicts the capacitance vs. voltage bias characteristic of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about ±15% over the −40°C to +85°C temperature range and is not a function of package or voltage rating. 0.6 0.4 0.2 0 0 1 2 3 4 DC BIAS VOLTAGE (V) 5 6 09888-051 The ADP5024 LDO is designed for operation with small, spacesaving ceramic capacitors, but functions with most commonly used capacitors as long as care is taken with the ESR value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or less is recommended to ensure stability of the ADP5024. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP5024 to large changes in load current. 0.8 Figure 51. Capacitance vs. Voltage Characteristic Use the following equation to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over −40°C to +85°C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 0.85 μF at 1.8 V, as shown in Figure 51. Substituting these values into the following equation yields: CEFF = 0.85 μF × (1 − 0.15) × (1 − 0.1) = 0.65 μF Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP5024, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. Rev. A | Page 23 of 28 ADP5024 Data Sheet POWER DISSIPATION AND THERMAL CONSIDERATIONS The ADP5024 is a highly efficient micropower management unit (microPMU), and, in most cases, the power dissipated in the device is not a concern. However, if the device operates at high ambient temperatures and maximum loading condition, the junction temperature can reach the maximum allowable operating limit (125°C). When the temperature exceeds 150°C, the ADP5024 turns off all of the regulators allowing the device to cool down. When the die temperature falls below 130°C, the ADP5024 resumes normal operation. This section provides guidelines to calculate the power dissipated in the device and ensure that the ADP5024 operates below the maximum allowable junction temperature. POUT × 100% PIN The power loss of the buck regulator is approximated by PLOSS = PDBUCK + PL (3) where: PDBUCK is the power dissipation on one of the ADP5024 buck regulators. PL is the inductor power loss. The inductor losses are external to the device and they do not have any effect on the die temperature. The inductor losses are estimated (without core losses) by PL ≈ IOUT1(RMS)2 × DCRL The efficiency for each regulator on the ADP5024 is given by η= BUCK REGULATOR POWER DISSIPATION (1) where: DCRL is the inductor series resistance. IOUT1(RMS) is the rms load current of the buck regulator. I OUT1( RMS ) = I OUT1 × 1 + where: η is the efficiency. PIN is the input power. POUT is the output power. (4) r 12 (5) where r is the normalized inductor ripple current. r = VOUT1 × (1 − D)/(IOUT1 × L × fSW) Power loss is given by PLOSS = PIN − POUT (2a) PLOSS = POUT (1− η)/η (2b) or Power dissipation can be calculated in several ways. The most intuitive and practical is to measure the power dissipated at the input and at all of the outputs. Perform the measurements at the worst-case conditions (voltages, currents, and temperature). The difference between input and output power is dissipated in the device and the inductor. Use Equation 4 to derive the power lost in the inductor, and from this result use Equation 3 to calculate the power dissipation in the ADP5024 buck converter. A second method to estimate the power dissipation uses the efficiency curves provided for the buck regulator, and the power lost on the LDO can be calculated using Equation 12. When the buck efficiency is known, use Equation 2b to derive the total power lost in the buck regulator and inductor, use Equation 4 to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using Equation 3. Add the power dissipated in the buck and in the LDO to find the total dissipated power. Note that the buck efficiency curves are typical values and may not be provided for all possible combinations of VIN, VOUT, and IOUT. To account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. A third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by Equation 8 to Equation 11 and calculating the losses in the LDO provided by Equation 12. (6) where: L is the inductance. fSW is the switching frequency. D is the duty cycle. D = VOUT1/VIN1 (7) The buck regulator power dissipation, PDBUCK, of the ADP5024 includes the power switch conductive losses, the switch losses, and the transition losses of each channel. There are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application is located. Equation 8 captures the calculation that must be made to estimate the power dissipation in the buck regulator. PDBUCK = PCOND + PSW + PTRAN (8) The power switch conductive losses are due to the output current, IOUT1, flowing through the P-MOSFET and the N-MOSFET power switches that have internal resistance, RDSON-P and RDSON-N. The amount of conductive power loss is found by PCOND = [RDSON-P × D + RDSON-N × (1 − D)] × IOUT12 (9) where RDSON-P is approximately 0.2 Ω, and RDSON-N is approximately 0.16 Ω at a junction temperature of 125°C and VIN1 = VIN2 = 3.6 V. At VIN1 = VIN2 = 2.3 V, these values change to 0.31 Ω and 0.21 Ω, respectively, and at VIN1 = VIN2 = 5.5 V, the values are 0.16 Ω and 0.14 Ω, respectively. Rev. A | Page 24 of 28 Data Sheet ADP5024 Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. The amount of switching power loss is given by PSW = (CGATE-P + CGATE-N) × VIN12 × fSW (10) where: CGATE-P is the P-MOSFET gate capacitance. CGATE-N is the N-MOSFET gate capacitance. The transition losses occur because the P-channel power MOSFET cannot be turned on or off instantaneously, and the SW node takes some time to slew from near ground to near VOUT1 (and from VOUT1 to ground). The amount of transition loss is calculated by (11) where tRISE and tFALL are the rise time and the fall time of the switching node, SW. For the ADP5024, the rise and fall times of SW are in the order of 5 ns. If the preceding equations and parameters are used for estimating the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. The converter performance also depends on the choice of passive components and board layout; therefore, include a sufficient safety margin in the estimate. LDO Regulator Power Dissipation The power loss of the LDO regulator is given by PDLDO = [(VIN − VOUT) × ILOAD] + (VIN × IGND) In cases where the board temperature, TA, is known, the thermal resistance parameter, θJA, can be used to estimate the junction temperature rise. TJ is calculated from TA and PD using the formula TJ = TA + (PD × θJA) For the ADP5024, the total of (CGATE-P + CGATE-N) is approximately 150 pF. PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW JUNCTION TEMPERATURE (12) where: ILOAD is the load current of the LDO regulator. VIN and VOUT are input and output voltages of the LDO, respectively. IGND is the ground current of the LDO regulator. The typical θJA value for the 24-lead, 4 mm × 4 mm LFCSP is 35°C/W (see Table 6). A very important factor to consider is that θJA is based on a 4-layer, 4 in × 3 in, 2.5 oz copper, as per JEDEC standard, and real applications may use different sizes and layers. To remove heat from the device, it is important to maximize the use of copper. Copper exposed to air dissipates heat better than copper used in the inner layers. Connect the exposed pad to the ground plane with several vias. If the case temperature can be measured, the junction temperature is calculated by TJ = TC + (PD × θJC) (15) where TC is the case temperature and θJC is the junction-to-case thermal resistance provided in Table 6. When designing an application for a particular ambient temperature range, calculate the expected ADP5024 power dissipation (PD) due to the losses of all channels by using Equation 8 to Equation 13. From this power calculation, the junction temperature, TJ, can be estimated using Equation 14. The reliable operation of the converter and the LDO regulator can be achieved only if the estimated die junction temperature of the ADP5024 (see Equation 14) is less than 125°C. Reliability and mean time between failures (MTBF) is highly affected by increasing the junction temperature. Additional information about product reliability can be found from the ADI Reliability Handbook, which is available at the following URL: www.analog.com/reliability_handbook. Power dissipation due to the ground current is small, and it can be ignored. The total power dissipation in the ADP5024 simplifies to PD = PDBUCK1 + PDBUCK2 + PDLDO (14) (13) Rev. A | Page 25 of 28 ADP5024 Data Sheet PCB LAYOUT GUIDELINES Poor layout can affect ADP5024 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines. Also, refer to User Guide UG-271. • • • • • Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas. Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference. Rev. A | Page 26 of 28 Maximize the size of ground metal on the component side to help with thermal dissipation. Use a ground plane with several vias connected to the component side ground to further reduce noise interference on sensitive circuit nodes. Connect VIN1, VIN2, and AVIN together close to the IC using short tracks. Data Sheet ADP5024 TYPICAL APPLICATION SCHEMATICS AVIN CAVIN 0.1µF 2.3V TO 5.5V HOUSEKEEPING VOUT1 VIN1 SW1 C1 4.7µF BUCK1 ON EN1 OFF EN1 L1 1µH PGND1 MODE PWM MODE MODE SW2 C2 4.7µF BUCK2 EN3 EN2 C3 1µF VOUT2 AT 1200mA FB2 C6 10µF PGND2 VOUT3 EN3 VIN3 1.7V TO 5.5V L2 1µH LDO (ANALOG) VOUT3 AT C7 300mA 1µF FB3 09888-052 EN2 ON PSM/PWM VOUT2 VIN2 OFF VOUT1 AT 1200mA C5 10µF FB1 ADP5024 AGND Figure 52. Fixed Output Voltages with Enable Pins AVIN CAVIN 0.1µF VOUT1 VIN1 SW1 C1 4.7µF BUCK1 ON EN1 OFF EN1 FB1 PGND1 L1 1µH PWM MODE SW2 C2 4.7µF OFF BUCK2 EN3 VIN3 1.7V TO 5.5V C3 1µF PSM/PWM VOUT2 VIN2 EN2 C5 10µF R2 MODE MODE ON VOUT1 AT 1200mA R1 EN2 EN3 FB2 PGND2 L2 1µH VOUT2 AT 1200mA R3 R4 C6 10µF VOUT3 LDO (ANALOG) FB3 R5 R6 VOUT3 AT 300mA C7 1µF ADP5024 AGND 09888-053 2.3V TO 5.5V HOUSEKEEPING Figure 53. Adjustable Output Voltages with Enable Pins BILL OF MATERIALS Table 12. Reference CAVIN C3, C7 C1, C2 C5, C6 L1, L2 IC1 Value 0.1 µF, X5R, 6.3 V 1 µF, X5R, 6.3 V 4.7 µF, X5R, 6.3 V 10 µF, X5R, 6.3 V 1 µH, 0.18 Ω, 850 mA 1 µH, 0.085 Ω, 1400 mA 1 µH, 0.059 Ω, 900 mA 1 µH, 0.086 Ω, 1350 mA Three-regulator microPMU Part Number JMK105BJ104MV-F LMK105BJ105MV-F ECJ-0EB0J475M JMK107BJ106MA-T BRC1608T1R0M LQM2MPN1R0NG0B EPL2014-102ML MDT2520-CN ADP5024 Rev. A | Page 27 of 28 Vendor Taiyo-Yuden Taiyo-Yuden Panasonic-ECG Taiyo-Yuden Taiyo-Yuden Murata Coilcraft Toko Analog Devices Package or Dimension (mm) 0402 0402 0402 0603 0603 2.0 × 1.6 × 0.9 2.0 × 2.0 × 1.4 2.5 × 2.0 × 1.2 24-lead LFCSP ADP5024 Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.30 0.25 0.20 0.50 BSC PIN 1 INDICATOR 24 19 18 1 EXPOSED PAD 0.50 0.40 0.30 TOP VIEW 0.80 0.75 0.70 13 12 6 7 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 SEATING PLANE 2.20 2.10 SQ 2.00 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 072809A 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8. Figure 54. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-24-10) Dimensions shown in millimeters ORDERING GUIDE Model1 ADP5024ACPZ-R7 Temperature Range −40°C to +125°C Output Voltage2 Adjustable ADP5024ACPZ-1-R7 −40°C to +125°C VOUT1 = 1.2 V VOUT2 = 3.3 V VOUT3 = 2.8 V UVLO3 Low Low Active Pull-Down4 Enabled on buck channels Enabled on buck channels ADP5024CP-EVALZ Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board for ADP5024ACPZ-R7 1 Z = RoHS Compliant Part. 2 For additional options, contact a local sales or distribution representative. Additional options available are: BUCK1 and BUCK2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.3 V, 2.0 V, 1.8 V, 1.6 V, 1.5 V, 1.4 V, 1.3 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V or adjustable. LDO: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.25 V, 2 V, 1.8 V, 1.7 V, 1.6 V, 1.5 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V, 0.8 V or adjustable. 3 UVLO: Low or High. 4 BUCK1, BUCK2, LDO: active pull-down resistor is programmable to be either enabled or disabled. ©2011-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09888-0-1/12(A) Rev. A | Page 28 of 28 Package Option CP-24-10 CP-24-10