IRLR120NPbF
IRLU120NPbF
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Surface Mount (IRLR120N)
Straight Lead (IRLU120N)
Advanced Process Technology
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Fast Switching
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HEXFET® Power MOSFET
D
Fully Avalanche Rated
Lead-Free
VDSS = 100V
RDS(on) = 0.185Ω
G
Description
Fifth Generation HEXFETs from International Rectifier utilize
advanced processing techniques to achieve the lowest possible
on-resistance per silicon area. This benefit, combined with the
fast switching speed and ruggedized device design that HEXFET
Power MOSFETs are well known for, provides the designer with
an extremely efficient device for use in a wide variety of
applications.
The D-PAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight lead
version (IRFU series) is for through-hole mounting applications.
Power dissipation levels up to 1.5 watts are possible in typical
surface mount applications.
Base Part Number
IRLR120NPbF
Package Type
D-Pak
IRLU120NPbF
ID = 10A
S
D
S
G
D-Pak
IRLR120NPbF
Standard Pack
Form
Quantity
Tube
75
Tape and Reel
2000
Tape and Reel Left
3000
S
D
I-Pak
IRLU120NPbF
Note
Orderable Part Number
IRLR120NPbF
IRLR120NTRPbF
IRLR120NTRLPbF
Tape and Reel Right
3000
IRLR120NTRRPbF
Tube
75
IRLU120NPbF
IPak
G
EOL notice # 289
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
Units
10
7.0
35
48
0.32
± 16
85
6.0
4.8
5.0
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
1
Junction-to-Case
Junction-to-Ambient (PCB mount) **
Junction-to-Ambient
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Typ.
Max.
Units
–––
–––
–––
3.1
50
110
°C/W
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IRLR/U120NPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
ΔV(BR)DSS/ΔTJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
V(BR)DSS
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
LD
Internal Drain Inductance
LS
Internal Source Inductance
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
IGSS
Min. Typ. Max. Units
Conditions
100 ––– –––
V
VGS = 0V, ID = 250μA
––– 0.12 ––– V/°C Reference to 25°C, I D = 1mA
––– ––– 0.185
VGS = 10V, ID = 6.0A
–––
––– 0.225
Ω
VGS = 5.0V, ID = 6.0A
––– ––– 0.265
VGS = 4.0V, ID = 5.0A
1.0
––– 2.0
V
VDS = VGS, ID = 250μA
3.1
––– –––
S
VDS = 25V, ID = 6.0A
––– ––– 25
VDS = 100V, VGS = 0V
μA
––– ––– 250
VDS = 80V, VGS = 0V, TJ = 150°C
––– ––– 100
VGS = 16V
nA
––– ––– -100
VGS = -16V
––– ––– 20
ID = 6.0A
––– ––– 4.6
nC
VDS = 80V
––– ––– 10
VGS = 5.0V, See Fig. 6 and 13
–––
4.0 –––
VDD = 50V
–––
35 –––
ID = 6.0A
ns
–––
23 –––
RG = 11Ω, VGS = 5.0V
–––
22 –––
RD = 8.2Ω, See Fig. 10
Between lead,
4.5
nH
6mm (0.25in.)
G
from package
––– 7.5 –––
and center of die contact
––– 440 –––
VGS = 0V
–––
97 –––
pF
VDS = 25V
–––
50 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
IS
ISM
VSD
trr
Qrr
ton
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
10
––– –––
showing the
A
G
integral reverse
––– –––
35
p-n junction diode.
S
––– ––– 1.3
V
TJ = 25°C, IS = 6.0A, VGS = 0V
––– 110 160
ns
TJ = 25°C, IF =6.0A
––– 410 620
nC di/dt = 100A/μs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 4.7mH
RG = 25Ω, IAS = 6.0A. (See Figure 12)
Pulse width ≤ 300μs; duty cycle ≤ 2%.
This is applied for I-PAK, LS of D-PAK is measured between lead and
center of die contact
ISD ≤ 6.0A, di/dt ≤ 340A/μs, VDD ≤ V(BR)DSS, Uses IRL520N data and test conditions.
TJ ≤ 175°C
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
2
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D
S
IRLR/U120NPbF
100
100
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
10
1
2.5V
20μs PULSE WIDTH
T J = 25°C
0.1
0.1
1
10
A
10
2.5V
1
3.0
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
1
VDS = 50V
20μs PULSE WIDTH
4
6
8
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
3
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10
A
100
Fig 2. Typical Output Characteristics
100
0.1
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
10
20μs PULSE WIDTH
T J = 175°C
0.1
0.1
100
VDS , Drain-to-Source Voltage (V)
2
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
ID , Drain-to-Source Current (A)
ID , Drain-to-Source Current (A)
TOP
10
A
I D = 10A
2.5
2.0
1.5
1.0
0.5
VGS = 10V
0.0
-60 -40 -20
0
20
40
60
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
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A
80 100 120 140 160 180
July 9, 2014
IRLR/U120NPbF
Ciss
C, Capacitance (pF)
600
15
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
C oss = C ds + C gd
V GS , Gate-to-Source Voltage (V)
800
Coss
Crss
0
1
10
V DS = 80V
V DS = 50V
V DS = 20V
12
400
200
I D = 6.0A
100
A
9
6
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
VDS , Drain-to-Source Voltage (V)
15
20
A
25
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
100
OPERATION IN THIS AREA LIMITED
BY R DS(on)
10μs
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
10
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
TJ = 175°C
10
TJ = 25°C
1
VGS = 0V
0.1
0.4
0.6
0.8
1.0
1.2
VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
5
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A
1.4
10
100μs
1ms
1
10ms
TC = 25°C
TJ = 175°C
Single Pulse
0.1
1
10
A
100
1000
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRLR/U120NPbF
10
V DS
VGS
ID, Drain Current (Amps)
8
D.U.T.
RG
6
RD
+
-VDD
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
4
Fig 10a. Switching Time Test Circuit
2
VDS
90%
A
0
25
50
75
100
125
150
175
TC , Case Temperature (°C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
0.01
0.00001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
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15V
L
VDS
D.U.T
RG
IAS
10V
tp
DRIVER
+
V
- DD
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
EAS , Single Pulse Avalanche Energy (mJ)
IRLR/U120NPbF
200
TOP
BOTTOM
160
ID
2.4A
4.2A
6.0A
120
80
40
0
25
V(BR)DSS
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
tp
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2μF
.3μF
5.0 V
QGS
+
V
- DS
D.U.T.
QGD
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
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IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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July 9, 2014
A
175
IRLR/U120NPbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
•
•
•
•
Driver Gate Drive
Period
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D=
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
7
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IRLR/U120NPbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120
WIT H AS SEMBLY
LOT CODE 1234
AS SEMBLED ON WW 16, 2001
IN T HE AS SEMBLY LINE "A"
PART NUMBER
INTERNAT IONAL
RECT IF IER
LOGO
Note: "P" in ass embly line pos ition
indicates "Lead-F ree"
IRFR120
12
116A
34
ASS EMBLY
LOT CODE
DATE CODE
YEAR 1 = 2001
WEEK 16
LINE A
"P" in as sembly line pos ition indicates
"Lead-F ree" qualification to the cons umer-level
OR
INTERNATIONAL
RECT IF IER
LOGO
PART NUMBER
IRFR120
12
AS SEMBLY
LOT CODE
34
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPTIONAL)
P = DES IGNAT ES LEAD-FREE
PRODUCT QUALIF IED T O T HE
CONS UMER LEVEL (OPT IONAL)
YEAR 1 = 2001
WEEK 16
A = AS SEMBLY SIT E CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
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IRLR/U120NPbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
E XAMP L E : T H IS IS AN IR F U 120
WIT H AS S E MB L Y
L OT CODE 5678
AS S E MB L E D ON WW 19, 2001
IN T H E AS S E MB LY L INE "A"
IN T E R NAT IONAL
R E CT IF IE R
L OGO
P AR T NU MB E R
IR F U 120
119A
56
78
AS S E MB LY
L OT CODE
Note: "P " in as s embly line pos ition
indicates L ead-F ree"
DAT E CODE
YE AR 1 = 2001
WE E K 19
LINE A
OR
INT E R NAT IONAL
R E CT IF IE R
L OGO
P AR T N U MB E R
IR F U 120
56
AS S E MB L Y
L OT CODE
78
DAT E CODE
P = DE S IGN AT E S LE AD-F R E E
P R ODU CT (OP T IONAL )
YE AR 1 = 2001
WE E K 19
A = AS S E MB L Y S IT E CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
9
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IRLR/U120NPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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July 9, 2014
IRLR/U120NPbF
†
Qualification information
Industrial
Qualification level
(per JEDE C JE S D47F
Moisture Sensitivity Level
guidelines)
MS L1
D-Pak
I-Pak
RoHS compliant
††
Yes
† Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability
†† Applicable version of JEDEC standard at the time of product release
Revision History
Date
7/9/2014
Comment
• Updated Electrical parameter table typo on Rdson units from "W" to "Ω" on page2.
• Updated Package outline on page 8 & page 9.
• Added Orderable table on page1.
• Updated datasheet with IR corporate template.
• Updated ordering information to reflect the End-Of-life (EOL notice #289)
• Added Qualification table on page10.
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
11
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July 9, 2014