AD7112–SPECIFICATIONS (VDD = +5 V 6 5%; OUT A = OUT B = AGND = DGND = 0 V; VIN A = VIN B = 10 V. Output amplifier AD712 except where noted. All specifications TMIN to TMAX unless otherwise noted.) Parameter ACCURACY Resolution Accuracy Relative to 0 dB Attenuation 0.375 dB Steps: Accuracy ≤ ± 0.17 dB Monotonic 0.75 dB Steps: Accuracy ≤ ± 0.35 dB Monotonic 1.5 dB Steps: Accuracy ≤ ± 0.7 dB Monotonic 3.0 dB Steps: Accuracy ≤ ± 1.4 dB Monotonic 6.0 dB Steps: Accuracy ≤ ± 2.7 dB Monotonic Gain Error Output Leakage Current OUT A, OUT B Input Resistance, VIN A, VIN B Input Resistance Match Feedback Resistance, RFB A, RFB B LOGIC INPUTS CS, WR, DAC A/DAC B, DB0–DB7 Input Low Voltage, VINL Input High Voltage, VINH Input Leakage Current Input Capacitance2 POWER REQUIREMENTS VDD, Range3 C Version1 TA = TA = +258C TMIN, TMAX B Version TA = TA = +258C TMIN, TMAX Units 0.375 0.375 dB 0.375 0.375 Conditions/Comments Guaranteed Attenuation Ranges for Specified Step Sizes. 0 to 36 0 to 54 0 to 36 0 to 54 0 to 30 0 to 48 0 to 30 0 to 48 dB min dB min 0 to 48 0 to 72 0 to 42 0 to 66 0 to 42 0 to 72 0 to 36 0 to 60 dB min dB min 0 to 54 0 to 48 Full Range 0 to 78 0 to 48 0 to 85.5 0 to 42 0 to 72 dB min dB min 0 to 66 0 to 54 Full Range Full Range 0 to 60 0 to 48 Full Range Full Range dB min dB min 0 to 72 0 to 60 Full Range Full Range ± 0.1 ± 0.15 0 to 60 0 to 60 Full Range Full Range ± 0.15 ± 0.2 dB min dB min dB max ± 50 ± 400 ± 50 ± 400 nA max 9/15 ±1 9/15 ±1 9/15 ±2 9/15 ±2 kΩ min/max Typically 12 kΩ. % max 9.3/15.7 9.3/15.7 9.3/15.7 9.3/15.7 kΩ min/max 0.8 2.4 ±1 10 0.8 2.4 ± 10 10 0.8 2.4 ±1 10 0.8 2.4 ± 10 10 V max V min µA max pF max 4.75/5.25 2 2 4.75/5.25 2 2 4.75/5.25 2 2 4.75/5.25 2 2 V min/max mA max mA max Full Range Is 0 dB to 88.5 dB. Measured Using RFB A, RFB B. Both DAC Registers Loaded With All 0s. For Specified Performance. Logic Inputs = VIL or VIH Logic Inputs = 0 V or VDD NOTES l Temperature range as follows: B, C Versions: –40°C to +85°C. 2 Guaranteed by design, not production tested. 3 The part will function with V DD = 5 V ± 10% with degraded performance. Specifications subject to change without notice. –2– REV. 0 AD7112 TIMING SPECIFICATIONS1 (V DD = +5 V 6 5%; 0UT A = OUT B = AGND = DGND = O V; VIN A = VIN B = 10 V) Parameter CS to WR Setup Time CS to WR Hold Time DAC Select to WR Setup Time DAC Select to WR Hold Time Data Valid to WR Setup Time Data Valid to WR Hold Time WR Pulse Width tCS tCH tAS tAH tDS tDH tWR TA = +258C TA = –408C to +858C Units Conditions/Comments 0 0 4 0 55 10 53 0 0 4 0 55 10 53 ns min ns min ns min ns min ns min ns min ns min See Figure 3. NOTES 1 Timing specifications guaranteed by design not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. AC PERFORMANCE CHARACTERISTICS1 (VDD = +5 V 6 5%; 0UT A = OUT B = AGND = DGND = 0 V; VIN A = VIN B = 10 V. Output amplifier AD712 except where noted.) Parameter TA = +258C TA = –408C to +858C Units Conditions/Comments DC Supply Rejection ∆ Gain/∆ VDD Digital-to-Analog Glitch Impulse 0.001 10 0.005 10 dB/% max nV s typ ∆ VDD = ± 5%. Input Code = 00000000 Measured with AD843 as output amplifier for input code transition 10000000 to 00000000. Output Capacitance, COUT A, COUT B AC Feedthrough VIN A to OUT A 50 50 pF max –94 –90 dB max VIN B to OUT B Channel-to-Channel Isolation VIN A to OUT B –94 –90 dB max –87 –87 dB typ –87 –87 dB typ Digital Feedthrough Output Noise Voltage Density (30 Hz to 50 kHz) 1 1 nV s typ 15 15 nV/√Hz typ Total Harmonic Distortion –91 –91 dB typ VIN B to OUT A NOTES 1 Guaranteed by design, not production tested. Specifications subject to change without notice. REV. 0 –3– VIN A, VIN B = 6 V rms at 1 kHz. DAC Registers loaded with all 1s. VIN A = 6 V rms at 10 kHz sine wave, VIN B = 0 V. DAC Registers loaded with all 0s. VIN B = 6 V rms at 10 kHz sine wave, VIN A = 0 V. DAC Registers loaded with all 0s. Measured with input code transitions of all 0s to all 1s. Measured between RFB A and OUT A or between RFB B and OUT B. VIN A = VIN B = 6 V rms at 1 kHz. DAC Registers loaded with all 0s. AD7112 ABSOLUTE MAXIMUM RATINGS* Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C Power Dissipation, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 1 W θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature (Soldering) Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C VDD to AGND or DGND . . . . . . . . . . . . . . . . . . –0.3 V, +7 V AGND to DGND . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V Digital Inputs to DGND . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V OUT A, OUT B to AGND . . . . . . . . . . . –0.3 V, VDD + 0.3 V VIN A, VIN B to AGND . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V VRFB A, VRFB B to AGND . . . . . . . . . . . . . . . . . . . . . . . ± 25 V Operating Temperature Range All Versions . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C Power Dissipation, DIP . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 102°C/W *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one Absolute Maximum Rating may be applied at any one time. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7112 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. TERMINOLOGY Pin MONOTONICITY: The device is monotonic if the analog output decreases or remains constant as the wdigital code increases. 1 2 3 4 5 6 OUTPUT CAPACITANCE: Capacitance from OUT A or OUT B to ground. GAIN ERROR: Gain error results from a mismatch between RFB (the feedback resistance) and the R-2R ladder resistance. Its effect in a LOGDAC is to produce a constant additive attenuation error in dB over the whole range of the DAC. ACCURACY: The difference (measured in dB) between the ideal transfer function as listed in Table I and the actual transfer function as measured with the device. DIGITAL-TO-ANALOG GLITCH IMPULSE: The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-s or nV-s depending on whether the glitch is measured as a current or voltage signal. Glitch impulse is measured with VIN = AGND. AD7112BN AD7112CN AD7112BR AD7112CR –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 0 dB to 60 dB 0 dB to 72 dB 0 dB to 60 dB 0 dB to 72 dB Description Analog Ground. Current Output Terminal of DAC A. Feedback Resistor for DAC A. Reference Input to DAC A Digital Ground. Selects Which DAC Can Accept Data from Input Port. 8 Data Inputs. Chip Select Input, Active Low. Write Input, Active Low. Power Supply Input 5 V ± 5%. Reference Input to DAC B. Feedback Resistor for DAC B. Current Output Terminal of DAC B. PIN CONFIGURATION DIP/SOIC ORDERING INFORMATION Specified Accuracy Range Mnemonic AGND OUT A RFB A VIN A DGND DAC A/ DAC B 7–14 DB7–DB0 15 CS 16 WR 17 VDD 18 VIN B 19 RFB B 20 OUT B FEEDTHROUGH ERROR: That portion of the input signal which reaches the output when all digital inputs are high. Model ESD SENSITIVE DEVICE PIN FUNCTION DESCRIPTION RESOLUTION: Nominal change in attenuation when moving between two adjacent codes. Temperature Range WARNING! Package Option* N-20 N-20 R-20 R-20 AGND 1 20 OUT B OUT A 2 19 RFB B RFB A 3 18 VIN B VIN A 4 17 AD7112 VDD DGND 5 DAC A/DAC B 6 (MSB) DB7 7 14 DB0 (LSB) DB6 8 13 DB1 DB5 9 DB4 10 TOP VIEW (Not to Scale) 16 WR 15 CS 12 DB2 11 DB3 *N = Plastic DIP; R = SOIC. –4– REV. 0 AD7112 CIRCUIT DESCRIPTION Figures 16 and 17 give a pictorial representation of the specified accuracy and monotonic ranges for all grades of the AD7112. High attenuation levels are specified with less accuracy than low attenuation levels. The range of monotonic behavior depends upon the attenuation step size used. To achieve monotonic operation over the entire 88.5 dB range, it is necessary to select input codes so that the attenuation step size at any point is consistent with the step size guaranteed for monotonic operation at that point. GENERAL CIRCUIT INFORMATION The AD7112 consists of a dual 17-bit R-2R CMOS multiplying D/A converter with extensive digital logic. Figure 1 shows a simplified circuit of the D/A converter section of the AD7112. The logic translates the 8-bit binary input into a 17-bit word which is used to drive the D/A converter. Figure 2 shows a typical circuit configuration for the AD7112. The transfer function for the circuit of Figure 2 is given by: VO = –V IN VDD 0.375 N × 10 exp – 20 RFB A C1 3 17 or 2 DAC A VO dB = – 0.375 N V IN where 0.375 is the step size (resolution ) in dB and N is the input code in decimal for values 0 to 239. For 240 ≤ N ≤ 255 the output is zero. Table I gives the output attenuation relative to 0 dB for all possible input codes. R R VIN A 4 CS 15 WR 16 DAC A/DAC B 6 R 2R 2R S2 S3 SIGNAL GROUND AD7112 A1 VOUT A1: 1/2 AD712 1/2 OP-275 DGND 5 2R 2R Figure 2. Typical Circuit Configuration R S1 AGND NOTES 1. ONLY ONE DAC IS SHOWN FOR CLARITY. 2. DATA INPUT CONNECTIONS ARE OMITTED. 3. C1 PHASE COMPENSATION (5–15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIER. VINA 2R 1 OUT A RFB A S17 OUT A AGND Figure 1. Simplified D/A Circuit of 1/2 AD7112 D 3– Table I. Ideal Attenuation in dB vs. Input Code D 0 D7–D4 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0.000 6.000 12.000 18.000 0.375 6.375 12.375 18.375 0.750 6.750 12.750 18.750 1.125 7.125 13.125 19.125 1.500 7.500 13.500 19.500 1.875 7.875 13.875 19.875 2.250 8.250 14.250 20.250 2.625 8.625 14.625 20.625 3.000 9.000 15.000 21.000 3.375 9.375 15.375 21.375 3.750 9.750 15.750 21.750 4.125 10.125 16.125 22.125 4.500 10.500 16.500 22.500 4.875 10.875 16.875 22.875 5.250 11.250 17.250 23.250 5.625 11.625 17.625 23.625 0100 0101 0110 0111 24.000 30.000 36.000 42.000 24.375 30.375 36.375 42.375 24.750 30.750 36.750 42.750 25.125 31.125 37.125 43.125 25.500 31.500 37.500 43.500 25.875 31.875 37.875 43.875 26.250 32.250 38.250 44.250 26.625 32.625 38.625 44.625 27.000 33.000 39.000 45.000 27.375 33.375 39.375 45.375 27.750 33.750 39.750 45.750 28.125 34.125 40.125 46.125 28.500 34.500 40.500 46.500 28.875 34.875 40.875 46.875 29.250 35.250 41.250 47.250 29.625 35.625 41.625 47.625 1000 1001 1010 1011 48.000 54.000 60.000 66.000 48.375 54.375 60.375 66.375 48.750 54.750 60.750 66.750 49.125 55.125 61.125 67.125 49.500 55.500 61.500 67.500 49.875 55.875 61.875 67.875 50.250 56.250 62.250 68.250 50.625 56.625 62.625 68.625 51.000 57.000 63.000 69.000 51.375 57.375 63.375 69.375 51.750 57.750 63.750 69.750 52.125 58.125 64.125 70.125 52.500 58.500 64.500 70.500 52.875 58.875 64.875 70.875 53.250 59.250 65.250 71.250 53.625 59.625 65.625 71.625 1100 1101 1110 1111 72.000 78.000 84.000 MUTE 72.375 78.375 84.375 MUTE 72.750 78.750 84.750 MUTE 73.125 79.125 85.125 MUTE 73.500 79.500 85.500 MUTE 73.875 79.875 85.875 MUTE 74.250 80.250 86.250 MUTE 74.625 80.625 86.625 MUTE 75.000 81.000 87.000 MUTE 75.375 81.375 87.375 MUTE 75.750 81.750 87.750 MUTE 76.125 82.125 88.125 MUTE 76.500 82.500 88.500 MUTE 76.875 82.875 88.875 MUTE 77.250 83.250 89.250 MUTE 77.625 83.625 89.625 MUTE REV. 0 –5– AD7112 DYNAMIC PERFORMANCE INTERFACE LOGIC INFORMATION DAC Selection Both DAC latches share a common 8-bit port. The control input DAC A/DAC B selects which DAC can accept data from the input port. Mode Selection Inputs CS and WR control the operating mode of the selected DAC. See the Mode Selection Table below. Write Mode When CS and WR are both low the DAC is in the write mode. The input data latches of the selected DAC are transparent and its analog output responds to activity on DB0–DB7. Hold Mode The selected DAC latch retains the data which was present on DB0–DB7 just prior to CS and WR assuming a high state. Both analog outputs remain at the values corresponding to the data in their respective latches. Mode Selection Table DACA/ DAC B CS WR DAC A DAC B L H X X L L H X L L X H WRITE HOLD HOLD HOLD HOLD WRITE HOLD HOLD It is recommended that when using the AD7112 with a high speed amplifier, a capacitor (C1) be connected in the feedback path as shown in Figure 2. This capacitor which should be between 5 pF and 15 pF, compensates for the phase lag introduced by the output capacitance of the D/A converter. Figures 4 and 5 show the performance of the AD7112 using the AD712, a high speed, low cost BiFET amplifier, and the OP275, a dual bipolar/JFET amplifier suitable for audio applications. The performance with and without the compensation capacitor is shown in both cases. For operation beyond 250 kHz, capacitor C1 may be reduced in value. This gives an increase in bandwidth at the expense of a poorer transient response as shown in Figure 7. In circuits where C1 is not included, the high frequency roll-off point is primarily determined by the characteristics of the output amplifier and not the AD7112. L = Low State, V IL; H = High State, V IH; X = Don’t Care. tCH tCS CS tAH Feedthrough and accuracy are sensitive to output leakage currents effects. For this reason it is recommended that the operating temperature of the AD7112 be kept as close to +25°C as is practically possible, particularly where the devices performance at high attenuation levels is important. A typical plot of leakage current vs. temperature is shown in Figure 11. DAC A/DAC B tAS tWR WR tDS The dynamic performance of the AD7112 will depend on the gain and phase characteristics of the output amplifier, together with the optimum choice of PC board layout and decoupling components. Circuit layout is most important if the optimum performance of the AD7112 is to be achieved. Most application problems stem from either poor layout, grounding errors, or inappropriate choice of amplifier. Ensure that the layout of the printed circuit board has the digital and analog lines separated as much as possible. Take care not to run any digital track alongside an analog signal track. Establish a single point analog ground (star ground) separate from the logic system ground. Place this ground as close as possible to the AD7112. Connect all analog grounds to this star ground, and also connect the AD7112 DGND to this ground. Do not connect any other digital grounds to this analog ground point. Low impedance analog and digital power supply common returns are essential for low noise and high performance of these converters, therefore the foil width of these tracks should be as wide as possible. The use of ground planes is recommended as this minimizes impedance paths and also guards the analog circuitry from digital noise. Some solder fluxes and cleaning materials can form slightly conductive films which cause leakage effects between analog input and output. The user is cautioned to ensure that the manufacturing process for circuits using the AD7112 does not allow such films to form. Otherwise the feedthrough, accuracy and maximum usable range will be affected. tDH VIH DB0–DB7 VIL NOTES 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF VDD. tR = tF = 20ns. STATIC ACCURACY PERFORMANCE The D/A converter section of the AD7112 consists of a 17-bit R–2R type converter. To obtain optimum static performance at this level of resolution it is necessary to pay great attention to amplifier selection, circuit grounding, etc. 2. CONTROL TIMING MEASUREMENT REFERENCE LEVEL = (VIH + VIL) / 2 Figure 3. Write Cycle Timing Diagram Amplifier input bias current results in a dc offset at the output of the amplifier due to current flowing in the feedback resistor RFB. It is recommended that amplifiers with input bias currents of less than 10 nA be used (e.g., AD712) to minimize this offset. –6– REV. 0 AD7112 AD7112 accuracy is specified and tested using only the internal feedback resistor. Any gain error (i.e., mismatch of RFB to the R–2R ladder) that may exist in the AD7112 D/A converter circuit results in a constant attenuation error over the whole range. The AD7112 accuracy is specified relative to 0 dB attenuation, hence gain trim resistors can be used to adjust VOUT = VIN precisely (i.e., 0 dB attenuation) with input code 00000000. For further information on gain error refer to the “CMOS DAC Application Guide” which is available from Analog Devices, Publication Number G872b-8-1/89. Another error arises from the output amplifier’s input offset voltage. The amplifier is operated with a fixed feedback resistance, but the equivalent source impedance (the AD7112 output impedance) varies as a function of the attenuation level. This has the effect of varying the noise gain of the amplifier thus creating a varying error due to amplifier offset voltage. It is recommended that an amplifier with less than 50 µV of input offset be used (such as the AD712 or ADOP07) in dc applications. Amplifiers with a large input offset voltage may cause audible thumps in audio applications due to dc output changes. The TYPICAL PERFORMANCE CHARACTERISTICS 6 TA = +25°C ALL DIGITAL INPUTS TIED TOGETHER 5 4 0.8V I DD – mA A1 DATA CHANGE FROM 00H TO 80H 100 90 3 2 C1 = 0pF 1 10 0% 0 C1 = 15pF 5V 5V 0 200ns 1 2 3 4 5 VIN – Volts Figure 6. Supply Current vs. Logic Input Level Figure 4. Response of AD7112 with AD712 A1 NORMALIZED GAIN WITH RESPECT TO 1kHz 10 0.8V DATA CHANGE FROM 00H TO 80H 100 90 C1 = 0pF 10 0% C1 = 15pF 5V 5V 0 OP275 C1 = 15pF –10 –20 –30 104 200ns Figure 5. Response of AD7112 with OP275 REV. 0 OP275 C1 = 0pF AD712 C1 = 0pF VDD = +5V TA = +25°C DATA INPUT CODE = 0000 0000 VIN = 1V rms AD712 C1 = 15pF 105 106 FREQUENCY – Hz 107 Figure 7. Frequency Response with AD712 and OP275 –7– AD7112 –60 2 T = +25°C C1 = 15pF –70 OUTPUT LEAKAGE CURRENT IOUT – nA TOTAL HARMONIC DISTORTION – dB VIN = 6V rms INPUT CODE = 0000 0000 OP275 –80 AD712 –90 –100 1 10 10 2 3 10 FREQUENCY – Hz 4 10 10 VDD = +5V VIN = –10V DATA INPUT = 1111 XXXX 1 0 –40 5 –15 10 35 60 85 TEMPERATURE – °C Figure 8. Distortion vs. Frequency Figure 11. Output Leakage Current vs. Temperature –40 VDD = +5V FEEDTHROUGH – dB –50 T = +25°C VINA, VINB = 20V p–p SINE WAVE A1 –60 2.0V DATA INPUTS FROM 00H TO 80H 100 90 –70 –80 AD712 OUTPUT 10 VDD = +5V TA = +25°C VIN = AGND 0% –90 10mV 5V –100 103 104 105 FREQUENCY – Hz 200ns 106 Figure 12. Digital-to-Analog Glitch Impulse Figure 9. Feedthrough vs. Frequency 50 –40 –50 NOISE SPECTRAL DENSITY – nV/ Hz CHANNEL-CHANNEL ISOLATION – dB VDD = +5V TA = +25°C VINA = 20V p–p SINE WAVE VINB = 0V –60 BOTH DAC LATCHES LOADED WITH 0000 0000 –70 –80 –90 –100 103 104 105 FREQUENCY – Hz 40 30 20 10 102 106 Figure 10. Channel-to-Channel Isolation vs. Frequency VDD = +5V VIN = 0V DAC CODE = 0000 0000 INCLUDES OP275 AMPLIFIER NOISE 103 104 FREQUENCY – Hz 105 Figure 13. Noise Spectral Density vs. Frequency –8– REV. 0 AAAAAAA AAAAAAA AAAAA AD7112 0.4 MONOTONICITY FOR 1.5 dB ATTENUATION STEPS 0.75 dB ATTENUATION STEPS VDD = +5V * ** ** * * * * ** * ** * ** ** ** * * * * ** ** * * ** * * ** 1 * ** * ERROR – dB ERROR – dB 0.0 2 TA = +25°C 0.2 –0.2 +0.17 0 –0.17 –1 –0.4 –0.6 3 0 6 9 12 15 18 21 ATTENUATION – dB 24 27 –2 30 0 Figure 14. Typical Attenuation Error for 0.75 dB Steps 6 12 18 24 30 36 42 48 54 60 66 72 78 84 90 ATTENUATION – dB Figure 16. Accuracy Specification for B Grade Devices at TA = +25°C AAAAAAA AAAAAAA AAAAAA 1.0 MONOTONICITY FOR 1.5 dB ATTENUATION STEPS VDD = +5V 0.75 dB ATTENUATION STEPS 0.375 dB ATTENUATION STEPS 2 0.5 TA = +85°C 1 0.0 ERROR – dB ERROR – dB 85.5 0.375 dB ATTENUATION STEPS TA = +25°C –0.5 +0.17 0 –0.17 –1 –1.0 0 6 12 18 24 30 36 42 48 54 60 66 72 78 –2 84 ATTENUATION – dB Figure 15. Typical Attenuation Error for 3 dB Steps vs. Temperature REV. 0 0 6 12 18 24 30 36 42 48 54 60 66 72 78 84 90 ATTENUATION – dB Figure 17. Accuracy Specification for C Grade Devices at TA = +25°C –9– AD7112 MICROPROCESSOR INTERFACING AD7112–8051 INTERFACE Figures 18 to 20 show interfaces between the AD7112 and three popular 8-bit microprocessor systems, the MC68008, 8085A/8088 and the 8051. In the MC68008 and 8085/8088 interfaces, the AD7112 is memory mapped with separate addresses for each DAC. Figure 20 shows a connection diagram between the AD7112 and the 8051 microprocessor. The AD7112 is port mapped in this interface. The loading structure is as follows: Data to be loaded to the DAC is output to Port 1: P3.0, P3.1 and P3.2 are bit addressable port lines and are used to control the DAC select, CS and WR inputs. A sample routine for writing to DAC A is shown below. AD7112-8085A/8088 INTERFACE Figure 18 shows a connection diagram for interfacing the AD7112 to both the 8085A and the 8088 microprocessors. This scheme is also suited to the Z80 microprocessor, but the Z80 address/data bus does not have to be demultiplexed. The AD7112 is memory mapped with separate memory addresses for DAC A and DAC B. A15 – A8 MOV A,DATA; CLR 3.2; CLR 3.0; CLR 3.1; MOV A,P1; SET B 3.1; SET B 3.0; Data to be written is loaded to the accumulator. Select DAC A. Bring CS low. Bring WR low. Write data to DAC. Deactivate WR. Deactivate CS ADDRESS BUS P3.0 ADDRESS DECODE LOGIC A+1** A** DEN 8085A / 8088 ALE DAC A / DAC B WR AD7 – AD0 8-BIT LATCH P3.2 DAC A / DAC B P1.0 DB0 P1.1 P1.2 DB1 DB2 DB3 DB4 AD7112* P1.3 AD7112* DATA BUS CS WR 8051 CS WR P3.1 P1.4 P1.5 P1.6 P1.7 DB7 – DB0 * ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY. DB5 DB6 DB7 * ANALOG CIRCUITRY OMITTED FOR CLARITY ** A = DECODED ADDRESS FOR AD7112 DAC A A+1 = DECODED ADDRESS FOR AD7112 DAC B Figure 20. AD7112–8051 Interface Circuit Figure 18. AD7112–8085A/8088 Interface Circuit APPLICATIONS Automatic Gain Control AD7112–68008 INTERFACE Figure 19 shows a connection diagram for interfacing the AD7112 to the 68008 microprocessor. The AD7112 is again memory mapped with separate memory addresses for DAC A and DAC B. A23 – A1 AS ADDRESS BUS ADDRESS DECODE LOGIC A+1** A ** 68008 DAC A / DAC B CS DTACK WR AD7112* R /W D7 – D0 DATA BUS DB7 – DB0 In an automatic gain control system an input signal is attenuated or amplified so that its average output level remains constant. The AD7112 D/A converter is used here as a variable gain or attenuation element that adjusts the output signal relative to the input level. A feedback loop consisting of a detector, comparator, and up/ down counter continuously adjusts the contents of the counter and hence the gain or attenuation of the circuit so that the signal level at the output remains constant and equal to the reference input signal. The negative feedback action of the loop ensures that the average output voltage of the automatic gain control system remains constant. Figure 21 shows a block diagram of a typical AGC control loop using 1/2 AD7112 as the gain/ attenuation element. Whenever the input signal is outside the dynamic range of the programmable gain element in the AGC loop, there should be a stable, well defined input output relationship. * ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY. ** A = DECODED ADDRESS FOR AD7112 DAC A A+1 = DECODED ADDRESS FOR AD7112 DAC B Figure 19. AD7112–68008 Interface Circuit –10– REV. 0 AD7112 INPUT DAC Equivalent Resistance, VARIABLE GAIN ELEMENT 1/2 AD7112 OUTPUT REQ = DETECTOR UP/DOWN COUNTER where: D U RDAC 10 × EXP (–0.375 × N / 20) RDAC is the DAC ladder resistance. VREF COMPARATOR N is the DAC code in Decimal (0≤N≤240). END STOP AND CONTROL LOGIC DACs A1 and B1 control the gain and Q of the filter characteristic while DACs A2 and B2 control the cutoff frequency. Figure 21. Automatic Gain Control System Circuit equations: Programmable State Variable Filter The AD7112 with its multiplying capability and fast settling time is ideal for many types of signal conditioning applications. The circuit of Figure 22 shows its use in a state variable filter design. This type of filter has three outputs: low pass, bandpass and high pass. The particular version shown in Figure 22 uses two AD7112 to control the critical parameters f0, Q and A0. Instead of several fixed resistors, the circuit uses the DAC equivalent resistances as circuit elements. Thus, R1 in Figure 22 is controlled by the 8-bit word loaded to DAC A1 of the AD7112. This is also the case with R2, R3 and R4. C1 = C2, R3 = R4, R7 = R8. Resonant frequency, f0 = 1/(2 π R3C1). Quality factor, Q = (R6/R8) × (R2/RFBB1). RFBB1 is the feedback resistance of DAC B1 in Figure 22 Bandpass Gain, A0 = –R2/R1. Programmable range for component values shown is f0 = 0 kHz to 15 kHz and Q = 0.3 to 4.5. C3 10pF R8 30kΩ R7 30kΩ A2 HIGH PASS OUTPUT R6 10kΩ C1 1000pF C2 1000pF A3 A4 LOW-PASS OUTPUT A1 OUT A RFB B OUT B VIN B OUT A VIN B OUT B R5 VIN VIN A DAC A1 (R1) DAC B1 (R2) VIN A AD7112 DAC A2 (R3) DAC B2 (R4) AD7112 DB0–DB7 DATA 1 DB0–DB7 CS WR DATA 2 DAC A/ DAC B CS WR DAC A/ DAC B NOTES 1. A1, A2, A3, A4 : 1/4 x AD713 2. C3 IS A COMPENSATION CAPACITOR TO ELIMINATE Q AND GAIN VARIATIONS CAUSED BY AMPLIFIER GAIN BANDWIDTH LIMITATIONS Figure 22. Programmable State Variable Filter REV. 0 –11– BANDPASS OUTPUT AD7112 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20 C1692–10–7/92 20-Pin Plastic DIP (N-20) 11 0.280 (7.11) 0.240 (6.10) PIN 1 1 10 0.325 (8.25) 0.300 (7.62) 1.060 (26.90) 0.925 (23.50) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.015 (0.381) 0.008 (0.204) SEATING PLANE 20-Pin SOIC (R-20) 0.5118 (13.00) 0.4961 (12.60) 20 11 0.2992 (7.60) 0.2914 (7.40) PIN 1 0.4193 (10.65) 0.3937 (10.00) 10 1 0.0500 (1.27) BSC 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) X 45° 0.0098 (0.25) 0°- 8° 0.0192 (0.49) 0.0138 (0.35) 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) PRINTED IN U.S.A. 0.0118 (0.30) 0.0040 (0.10) –12– REV. 0