DATASHEET ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C FN6665 Rev 6.00 October 23, 2015 High-Efficiency, Quad or Triple-Output System Power Supply Controller for Notebook Computers The ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C and ISL62383C family of controllers generate supply voltages for battery-powered systems. These controllers include two pulse-width modulation (PWM) controllers, adjustable from 0.6V to 5.5V, and two linear regulators, LDO5 and LDO3, that generate a fixed 5V and an adjustable output respectively, and each can deliver up to 100mA. The ISL62383 and ISL62383C have the same outputs as the ISL62381, ISL62382, ISL62381C and ISL62382C but without LDO3 linear regulator. The channel 2 switching regulator will automatically take over the LDO5 load when programmed to 5V output. This provides a large power savings and boosts efficiency. These controllers include onboard power-up sequencing, two power-good (PGOOD) outputs, digital soft-start, and internal soft-stop output discharge that prevent negative voltages on shutdown. Features The patented R3 PWM control scheme provides a low jitter • Power-Good Indicator system with fast response to load transients. Light-load efficiency is improved with period-stretching discontinuous conduction mode (DCM) operation. To eliminate noise in audio frequency applications, an ultrasonic DCM mode is included, which limits the minimum switching frequency to approximately 28kHz. • Overvoltage, Undervoltage and Overcurrent Protection The ISL62381, ISL62382, ISL62381C and ISL62382C are available in a 32 Ld 5x5 TQFN package, and the ISL62383 and ISL62383C are available in a 28 Ld 4x4 TQFN package. This family of controllers can operate over the extended temperature range (-10°C to +100°C). FN6665 Rev 6.00 October 23, 2015 • High Performance R3 Technology • Fast Transient Response • ±1% Output Voltage Accuracy: -10°C to +100°C • Two Fully Programmable Switch-Mode Power Supplies with Independent Operation • Programmable Switching Frequency • Integrated MOSFET Drivers and Bootstrap Diode • Adjustable (+1.2V to +5V) LDO Output • Fixed +5V LDO Output with Automatic Switchover to SMPS2 • Internal Soft-Start and Soft-Stop Output Discharge • Wide Input Voltage Range: +5.5V to +25V • Full and Ultrasonic Pulse-Skipping Mode • Fault Identification by PGOOD Pull-Down Resistance • Thermal Monitor and Protection • Pb-Free (RoHS Compliant) Applications • Notebook and Sub-Notebook Computers • PDAs and Mobile Communication Devices • 3-Cell and 4-Cell Li+ Battery-Powered Devices • General Purpose Switching Buck Regulators Page 1 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING ISL62381HRTZ 62381 HRTZ PACKAGE (RoHS Compliant) TEMP RANGE (°C) -10 to +100 32 Ld 5x5 TQFN PKG. DWG. # L32.5x5A ISL62382HRTZ 62382 HRTZ -10 to +100 32 Ld 5x5 TQFN L32.5x5A ISL62383HRTZ 623 83HRTZ -10 to +100 28 Ld 4x4 TQFN L28.4x4 ISL62381CHRTZ (No longer available or supported) 62381 CHRTZ -10 to +100 32 Ld 5x5 TQFN L32.5x5A ISL62382CHRTZ (No longer available or supported) 62382 CHRTZ -10 to +100 32 Ld 5x5 TQFN L32.5x5A ISL62383CHRTZ 62383 CHRTZ -10 to +100 28 Ld 4x4 TQFN L28.4x4 NOTES: 1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C. For more information on MSL please see techbrief TB363. Pinouts ISL62383, ISL62383C (28 LD TQFN) TOP VIEW FB2 VOUT2 ISEN2 OCSET2 EN2 PHASE2 UGATE2 BOOT2 FB2 VOUT2 ISEN2 OSCET2 EN2 PHASE2 UGATE2 ISL62381, ISL62382, ISL62381C, ISL62382C (32 LD TQFN) TOP VIEW 32 31 30 29 28 27 26 25 28 27 26 25 24 23 22 PGOOD2 1 21 BOOT2 PGND FSET2 2 20 LGATE2 22 LDO5 FCCM 3 19 PGND 21 VIN VCC2 4 18 LDO5 VCC1 5 17 VIN FSET1 6 16 LGATE1 PGOOD1 7 15 BOOT1 FCCM 3 VCC2 4 GND FSET1 7 18 LDO3FB PGOOD1 8 17 LGATE1 9 10 11 12 13 14 15 16 BOOT1 LDO3 UGATE1 19 PHASE1 6 EN1 LDO3EN OSCET1 LDO3IN ISEN1 20 VOUT1 5 FB1 VCC1 FN6665 Rev 6.00 October 23, 2015 GND 8 9 10 11 12 13 14 UGATE1 23 PHASE1 2 EN1 FSET2 OCSET1 LGATE2 ISEN1 24 VOUT1 1 FB1 PGOOD2 Page 2 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Absolute Maximum Ratings Thermal Information VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V VCC1,2, PGOOD1,2, LDO5 to GND. . . . . . . . . . . . . . -0.3V to +7.0V EN1,2, LDO3EN . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC1 + 0.3V VOUT1,2, FB1,2, LDO3FB, FSET1,2 . . -0.3V to GND, VCC1 + 0.3V PHASE1,2 to GND . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V (<100ns Pulse Width, 10µJ) . . . . . . . . . . . . . . . . . . . . . . . . . -5.0V BOOT1,2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V BOOT1,2 to PHASE1,2 . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V UGATE1,2 . . . . . . . . . . . (DC) -0.3V to PHASE1,2, BOOT1,2 + 0.3V (<200ns Pulse Width, 20µJ) . . . . . . . . . . . . . . . . . . . . . . . . -4.0V LGATE1,2 . . . . . . . . . . . . . . . . . . . (DC) -0.3V to GND, VCC1 + 0.3V (<100ns Pulse Width, 4µJ) . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V LDO3, LDO5 Output Continuous Current . . . . . . . . . . . . . . +100mA Thermal Resistance (Typical, Notes 4, 5) JA (°C/W) JC (°C/W) 32 Ld TQFN Package . . . . . . . . . . . . . 30 1.75 28 Ld TQFN Package . . . . . . . . . . . . . 37 3 Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150C Operating Temperature Range . . . . . . . . . . . . . . . .-10C to +100C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +100°C Supply Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . 5.5V to 25V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications These specifications apply for TA = -10°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C, VIN = 12V. Boldface limits apply over the operating temperature range, -10°C to +100°C. MIN (Note 8) TYP MAX (Note 8) UNITS Rising Threshold 5.3 5.4 5.5 V Hysteresis 20 80 150 mV PARAMETER CONDITIONS VIN VIN Power-on Reset (POR) VIN Shutdown Supply Current EN1 = EN2 = GND or Floating, LDO3EN = GND - 6 15 µA VIN Standby Supply Current EN1 = EN2 = GND or Floating, LDO3EN = VCC1 - 150 250 µA I_LDO5 = 0 4.9 5.0 5.1 V I_LDO5 = 100mA (Note 6) 4.9 5.0 5.1 V LINEAR REGULATOR LDO5 Output Voltage LDO5 Short-Circuit Current (Note 6) LDO5 = GND - 190 - mA LDO5 UVLO Threshold Voltage (Note 6) Rising edge of LDO5 - 4.35 - V Falling edge of LDO5 - 4.15 - V 4.63 4.80 4.93 V SMPS2 to LDO5 Switchover Resistance (Note 6) VOUT2 to LDO5, VOUT2 = 5V - 2.5 3.2 LDO3 Reference Voltage (Note 6) - 1.2 - V 1.2 - 5 V - 180 - mA SMPS2 to LDO5 Switchover Threshold LDO3 Voltage Regulation Range LDO3IN > VLDO3+dropout LDO3 Short-Circuit Current (Note 6) LDO3 = GND LDO3EN Input Voltage Rising edge 1.1 - 2.5 V Falling edge 0.94 - 1.06 V 1 µA LDO3EN Input Leakage Current LDO3EN = GND or VCC1 -1 LDO3 Discharge ON-Resistance LDO3EN = GND - 36 60 VCC Input Bias Current (Note 6) EN1 = EN2 = VCC1, FB1 = FB2 = 0.65V - 2 - mA VCC1 Start-up Voltage EN1 = EN2 = LDO3EN = GND 3.45 3.6 3.75 V VCC FN6665 Rev 6.00 October 23, 2015 Page 3 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Electrical Specifications These specifications apply for TA = -10°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C, VIN = 12V. Boldface limits apply over the operating temperature range, -10°C to +100°C. (Continued) MIN (Note 8) TYP MAX (Note 8) UNITS Rising edge 4.35 4.45 4.55 V Falling edge 4.10 4.20 4.30 V - 0.6 - V PARAMETER VCC2 POR Threshold CONDITIONS PWM Reference Voltage (Note 6) Regulation Accuracy VOUT regulated to 0.6V -1 - 1 % FB Input Bias Current FB = 0.6V -10 - 30 nA 200 - 600 kHz Frequency Range Frequency Set Accuracy (Note 7) FSW = 300kHz -12 - 12 % VOUT Voltage Regulation Range VIN > 6V for VOUT = 5.5V 0.6 - 5.5 V - 14 50 Soft-start, I_PGOOD = 5mA sinking - 32 100 UVP, I_PGOOD = 5mA sinking - 95 200 OVP, I_PGOOD = 5mA sinking - 63 150 OCP, I_PGOOD = 5mA sinking - 32 100 PGOOD = VCC1 - 0 1 µA - 5 - mA From EN high to PGOOD high (for one SMPS channel) 2.20 2.75 3.70 ms EN2(1) = Floating, from EN1(2) high to PGOOD2(1) high 4.50 5.60 7.50 ms VOUT Soft-Discharge Resistance POWER-GOOD PGOOD Pull-Down Impedance PGOOD Leakage Current Maximum PGOOD Sink Current (Note 6) PGOOD Soft-start Delay GATE DRIVER UGATE Pull-Up ON-Resistance (Note 6) 200mA source current - 1.0 1.5 UGATE Source Current (Note 6) UGATE-PHASE = 2.5V - 2.0 - A UGATE Pull-Down ON-Resistance (Note 6) 250mA source current - 1.0 1.5 UGATE Sink Current (Note 6) UGATE-PHASE = 2.5V - 2.0 - A LGATE Pull-Up ON-Resistance (Note6) 250mA source current - 1.0 1.5 LGATE Source Current (Note 6) LGATE-PGND = 2.5V - 2.0 - A LGATE Pull-Down ON-Resistance (Note 6) 250mA source current - 0.5 0.9 LGATE Sink Current (Note 6) LGATE-PGND = 2.5V - 4.0 - A UGATE to LGATE Deadtime (Note 6) UG falling to LG rising, no load - 21 - ns LGATE to UGATE Deadtime (Note 6) LG falling to UG rising, no load - 21 - ns Bootstrap Diode Forward Voltage (Note 6) 2mA forward diode current - 0.58 - V Bootstrap Diode Reverse Leakage Current VR = 25V - 0.2 1 µA Low level (DCM enabled) - - 0.8 V Float level (DCM with audio filter) 1.9 - 2.1 V High level (Forced CCM) 2.4 - - V FCCM = GND or VCC1 -2 - 2 µA CONTROL FCCM Input Voltage FCCM Input Leakage Current FN6665 Rev 6.00 October 23, 2015 Page 4 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Electrical Specifications These specifications apply for TA = -10°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C, VIN = 12V. Boldface limits apply over the operating temperature range, -10°C to +100°C. (Continued) PARAMETER CONDITIONS MIN (Note 8) TYP MAX (Note 8) UNITS Audio Filter Switching Frequency (Note 6) FCCM floating - 28 - kHz EN Input Voltage Clear fault level/SMPS OFF level - - 0.8 V Delay start level 1.9 - 2.1 V SMPS ON level 2.4 - - V EN Input Leakage Current EN = GND or VCC1 -3.5 - 3.5 µA ISEN Input Impedance (Note 6) EN = VCC1 - 600 - k ISEN Input Leakage Current (Note 6) EN = GND - 0.1 - µA OCSET Input Impedance (Note 6) EN = VCC1 - 600 - k OCSET Input Leakage Current (Note 6) EN = GND - 0.1 - µA OCSET Current Source EN = VCC1 9 10.0 10.5 µA -1.75 0.0 1.75 mV PROTECTION OCP (VOCSET-VISEN) Threshold UVP Threshold Falling edge, referenced to FB 81 84 87 % OVP Threshold Rising edge, referenced to FB 113 116 120 % Falling edge, referenced to FB 99.5 103 106 % Rising edge - 150 - °C Falling edge - 135 - °C OTP Threshold (Note 6) NOTES: 6. Limits established by characterization and are not production tested. 7. FSW accuracy reflects IC tolerance only; it does not include frequency variation due to VIN, VOUT, LOUT, ESRCOUT, or other application specific parameters. 8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN6665 Rev 6.00 October 23, 2015 Page 5 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Typical Application Circuits The below typical application circuits generate the 5V/8A and 3.3V/8A main supplies in a notebook computer. The input supply (VBAT) range is 5.5V to 25V VBAT 4x10µF 4.7µH 3 .3 V 330µF V IN BO O T1 0.22µF IRF7821 BO O T2 UGATE1 UGATE2 PHASE1 PHASE2 LG ATE1 LGATE2 0.22µF IRF7821 0.022µF 14k IRF7832 ISL62381 ISL62382 ISL62383 ISL62381C ISL62382C ISL62383C OCSET1 45.3k IS E N 1 1200pF VOUT1 10k FB1 3 .3 V LDO 3* 17.4k 4.7µF 0.022µF 330µF LDO5 68.1k IS E N 2 1200pF FB2 9.09k 100k LDO5 100k EN1 EN2 LDO 3EN * FCCM FSET1 FSET2 VCC1 VCC2 1µF 750 VOUT2 PGOOD1 10 1µF 14k OCSET2 PGOOD2 10k 4.7µF IRF7832 L D O 3 IN * LDO 3FB* 5V 5V 14k 14k 750 4.7µH PGND 19.6k *ISL62381, ISL62382, ISL62381C, AND ISL62382C ONLY 0.01µF 24.3k GND 0.01µF FIGURE 1. TYPICAL APPLICATION CIRCUIT WITH INDUCTOR DCR CURRENT SENSE VBAT BOOT1 4x10µF 0.22µF 4.7µH 3 .3 V 0.001 330µF 1k 750 IRF7821 UGATE1 UGATE2 PHASE1 PHASE2 LG ATE1 LG ATE2 IS E N 1 45.3k VOUT1 FB1 3 .3 V 4.7µF 5V L D O 3 IN * PGOOD1 PGOOD2 10k LDO 5 EN1 EN2 10 *ISL62381, ISL62382, ISL62381C, AND ISL62382C ONLY 1µF 5V 330µF 1k 1k 750 68.1k 1200pF 9.09K 100k LDO5 100k LD O 3EN* FCCM FSET1 FSET2 VCC1 1µF 0.001 FB2 LDO 3FB* 4.7µF 4.7µH ISL62381 ISL62382 O C S E T 2 ISL62383 IS E N 2 ISL62381C VOUT2 ISL62382C ISL62383C LDO 3* 17.4k 0.22µF IRF7832 OCSET1 10k BOOT2 IRF7832 1k 1200pF V IN IRF7821 VCC2 PGND GND 24.3k 19.6k 0.01µF 0.01µF FIGURE 2. TYPICAL APPLICATION CIRCUIT WITH RESISTOR CURRENT SENSE FN6665 Rev 6.00 October 23, 2015 Page 6 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Typical Application Circuits The below typical application circuits generate the 1.05V/15A and 1.5V/15A main supplies in a notebook computer. The input supply (VBAT) range is 5.5V to 25V VBAT 6x10µF IRF7821x2 2.2µH 1 .0 5 V 330µFx2 V IN BO O T1 0.22µF BO O T2 UGATE1 UGATE2 PHASE1 PHASE2 LG ATE1 LGATE2 0.22µF IRF7821x2 IRF7832x2 16.2k 1800pF FB1 36.5k PGOOD1 LDO5 LDO 3EN * FCCM FSET1 FSET2 VCC1 1µF VCC2 1µF LDO5 100k EN1 EN2 10 24.3k 100k PGOOD2 10k 4.7µF VBAT L D O 3 IN * LDO 3FB* 5V 1800pF FB2 LDO 3* 17.4k 590 16.2k 3 .3 V 4.7µF 330µFx2 IRF7832x2 ISL62381 OCSET2 O C S E T 1 ISL62382 ISL62383 IS E N 2 IS E N 1 ISL62381C VOUT1 VOUT2 ISL62382C ISL62383C 36.5k 48.7k 1 .5 V 16.2k 0.022µF 0.022µF 16.2k 590 2.2µH PGND 14k *ISL62381, ISL62382, ISL62381C, AND ISL62382C ONLY 0.01µF 17.4k GND 0.01µF FIGURE 3. TYPICAL APPLICATION CIRCUIT WITH INDUCTOR DCR CURRENT SENSE VBAT IRF7821x2 BO O T1 6x10µF V IN IRF7821x2 BOOT2 0.22µF 0.22µF 2.2µH 1 .0 5 V 0.001 330µFx2 UGATE1 UG ATE2 PHASE1 PHASE2 LG ATE1 LG ATE2 2.2µH IRF7832x2 2k 0.001 330µFx2 IRF7832x2 2k 1 .5 V 2k 2k ISL62381 590 1800pF O C S E T 1 ISL62382 IS E N 1 36.5k VOUT1 FB1 ISL62383 ISL62381C ISL62382C ISL62383C 590 OCSET2 36.5k IS E N 2 FB2 3 .3 V 48.7k 4.7µF 5V LDO 3* 17.4k PGOOD1 LDO5 LDO 3EN * FCCM FSET1 FSET2 VCC1 1µF 1µF VCC2 PGND GND 14k *ISL62381, ISL62382, ISL62381C AND ISL62382C ONLY LDO5 100k EN1 EN2 10 24.3k 100k PGOOD2 10k 4.7µF VBAT L D O 3 IN * LDO 3FB* 1800pF VOUT2 17.4k 0.01µF 0.01µF FIGURE 4. TYPICAL APPLICATION CIRCUIT WITH RESISTOR CURRENT SENSE FN6665 Rev 6.00 October 23, 2015 Page 7 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Pin Descriptions PIN NUMBER 28 LD 32 LD NAME FUNCTION 1 1 2 2 FSET2 Frequency control input for SMPS2. Connect a resistor to ground to program the switching frequency. A small ceramic capacitor such as 10nF is necessary to parallel with this resistor to smooth the voltage. 3 3 FCCM Logic input to control efficiency mode. Logic high forces continuous conduction mode (CCM). Logic low allows full discontinuous conduction mode (DCM). Float this pin for ultrasonic DCM operation. 4 4 VCC2 SMPS2 analog power supply input for reference voltages and currents. Connect to VCC1 with a 10 resistor. Bypass to ground with a 1µF ceramic capacitor near the IC. 5 5 VCC1 SMPS1 analog power supply input for reference voltages and currents. It is internally connected to the LDO5 output. Bypass to ground with a 1µF ceramic capacitor near the IC. - 6 6 7 7 8 8 9 FB1 9 10 VOUT1 SMPS1 output voltage sense input. Used for soft-discharge. 10 11 ISEN1 SMPS1 current sense input. Used for overcurrent protection and R3 regulation. 11 12 12 13 13 14 PHASE1 SMPS1 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS source, the synchronous NMOS drain, and the output inductor for SMPS1. 14 15 UGATE1 High-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 switching FET. 15 16 BOOT1 SMPS1 bootstrap input for the switching NMOS gate drivers. Connect to PHASE1 with a 0.22µF ceramic capacitor. 16 17 LGATE1 Low-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 synchronous FET. - 18 LDO3FB LDO3 linear regulator feedback input used for output voltage programming and regulation. - 19 LDO3 - 20 LDO3IN 17 21 VIN 18 22 LDO5 5V linear regulator output, providing up to 100mA before switchover to SMPS2. Bypass to ground with a 4.7µF ceramic capacitor. 19 23 PGND Power ground for SMPS1 and SMPS2. This provides a return path for synchronous FET switching currents. 20 24 LGATE2 Low-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 synchronous FET. 21 25 BOOT2 SMPS2 bootstrap input for the switching NMOS gate drivers. Connect to PHASE2 with a 0.22µF ceramic capacitor. 22 26 UGATE2 High-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 switching FET. 23 27 PHASE2 SMPS2 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS source, the synchronous NMOS drain, and the output inductor for SMPS2. 24 28 25 29 26 30 ISEN2 SMPS2 current sense input. Used for overcurrent protection and R3 regulation. 27 31 VOUT2 SMPS2 output voltage sense input. Used for soft-discharge and switchover to LDO5 output. PGOOD2 SMPS2 open-drain power-good status output. Connect to LDO5 through a 100kΩ resistor. Output will be high when the SMPS2 output is within the regulation window with no faults detected. LDO3EN Logic input for enabling and disabling the LDO3 linear regulator. Positive logic input. FSET1 Frequency control input for SMPS1. Connect a resistor to ground to program the switching frequency. A small ceramic capacitor such as 10nF is necessary to parallel with this resistor to smooth the voltage. PGOOD1 SMPS1 open-drain power-good status output. Connect to LDO5 through a 100kΩ resistor. Output will be high when the SMPS1 output is within the regulation window with no faults detected. SMPS1 feedback input used for output voltage programming and regulation. OCSET1 Input from current-sensing network used to program the overcurrent shutdown threshold for SMPS1. EN1 EN2 Logic input to enable and disable SMPS1. A logic high will enable SMPS1 immediately. A logic low will disable SMPS1. Floating this input will delay SMPS1 start-up until after SMPS2 achieves regulation. LDO3 linear regulator output, providing up to 100mA. Bypass to ground with a 4.7µF ceramic capacitor. Power input for LDO3. Must be connected to a voltage greater than the LDO3 set point plus the dropout voltage. Feed-forward input for line voltage transient compensation. Connect to the power train input voltage. Logic input to enable and disable SMPS2. A logic high will enable SMPS2 immediately. A logic low will disable SMPS2. Floating this input will delay SMPS2 start-up until after SMPS1 achieves regulation. OCSET2 Input from current-sensing network used to program the over-current shutdown threshold for SMPS2. FN6665 Rev 6.00 October 23, 2015 Page 8 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Pin Descriptions (Continued) PIN NUMBER 28 LD 32 LD NAME FUNCTION 28 32 FB2 SMPS2 feedback input used for output voltage programming and regulation. Bottom Pad Bottom Pad GND Analog ground of the IC. Unless otherwise stated, signals are reference to this GND. Typical Performance 100 95 100 VIN = 7V 95 VIN = 12V 85 EFFICIENCY (%) EFFICIENCY (%) VIN = 7V 90 90 VIN = 19V 80 75 70 65 80 70 65 60 55 55 1.00 10.00 IOUT (A) FIGURE 5. CHANNEL 1 EFFICIENCY AT VO = 3.3V, DEM OPERATION. HIGH-SIDE 1xIRF7821, rDS(ON) = 9.1m; LOW-SIDE 1xIRF7832, rDS(ON) = 4m; L = 4.7µH, DCR = 14.3m; CCM FSW = 270kHz VIN = 19V 75 60 50 0.10 VIN = 12V 85 50 0.01 0.10 1.00 10.00 IOUT (A) FIGURE 6. CHANNEL 2 EFFICIENCY AT VO = 5V, DEM OPERATION. HIGH-SIDE 1xIRF7821, rDS(ON) = 9.1m; LOW-SIDE 1xIRF7832, rDS(ON) = 4m; L = 4.7µH, DCR = 14.3m; CCM FSW = 330kHz VO1 VO1 FB1 FB1 PGOOD1 PGOOD1 PHASE1 FIGURE 7. POWER-ON, VIN = 12V, LOAD = 5A, VO = 3.3V FN6665 Rev 6.00 October 23, 2015 PHASE1 FIGURE 8. POWER-OFF, VIN = 12V, IO = 5A, VO = 3.3V Page 9 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Typical Performance (Continued) VO1 VO1 FB1 FB1 PGOOD1 PGOOD1 EN1 EN1 FIGURE 9. ENABLE CONTROL, EN1 = HIGH, VIN = 12V, VO = 3.3V, IO = 5A FIGURE 10. ENABLE CONTROL, EN1 = LOW, VIN = 12V, VO = 3.3V, IO = 5A VO1 VO1 PHASE1 VO2 PHASE2 FIGURE 11. CCM STEADY-STATE OPERATION,VIN = 12V, VO1 = 3.3V, IO1 = 5A, VO2 = 5V, IO2 = 5A VO1 PHASE1 VO2 PHASE2 FIGURE 12. DCM STEADY-STATE OPERATION,VIN = 12V, VO1 = 3.3V, IO1 = 0. 2A, VO2 = 5V, IO2 = 0. 2A VO1 PHASE1 PHASE1 VO2 PHASE2 FIGURE 13. AUDIO FILTER OPERATION, VIN = 12V, VO1 = 3.3V, VO2 = 5V, NO LOAD FN6665 Rev 6.00 October 23, 2015 IO1 FIGURE 14. TRANSIENT RESPONSE, VIN = 12V, VO = 3.3V, IO = 0.1A/8.1A @ 2.5A/µs Page 10 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Typical Performance (Continued) VO1 VO1 PHASE1 IO1 FIGURE 15. LOAD INSERTION RESPONSE, VIN = 12V, VO = 3.3V, IO = 0.1A/8.1A @ 2.5A/µs PHASE1 IO1 FIGURE 16. LOAD RELEASE RESPONSE, VIN = 12V, VO = 3.3V, IO = 0.1A/8.1A @ 2.5A/µs EN1 EN2 VO1 VO1 VO2 FIGURE 17. DELAYED START, VIN = 12V, VO1 = 3.3V, VO2 = 5V, EN2 = FLOAT, NO LOAD VO1 PGOOD1 VO2 VO2 FIGURE 18. DELAYED START, VIN = 12V, VO1 = 3.3V, VO2 = 5V, EN1 = FLOAT, NO LOAD VO1 PGOOD1 IO1 PGOOD2 FIGURE 19. DELAYED START, VIN = 12V, VO1 = 3.3V, VO2 = 5V, EN1 = 1, EN2 = FLOAT, NO LOAD FN6665 Rev 6.00 October 23, 2015 FIGURE 20. OVERCURRENT PROTECTION, VIN = 12V, VO = 3.3V Page 11 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Typical Performance (Continued) VO1 UGATE1-PHASE1 UGATE1-PHASE1 LGATE1 LGATE1 PGOOD1 PGOOD1 FIGURE 21. CROWBAR OVERVOLTAGE PROTECTION, VIN = 12V, VO = 3.3V, NO LOAD FN6665 Rev 6.00 October 23, 2015 VO1 FIGURE 22. TRI-STATE OVERVOLTAGE PROTECTION, VIN = 12V, VO = 3.3V, NO LOAD Page 12 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Block Diagram VIN VOUT2 FSET1/2 4.8V 5V LDO FB1/2 R3 MODULATOR VREF LDO5 0.6V BOOT1/2 FCCM PWM VOUT1/2 UGATE DRIVER UGATE1/2 PHASE1/2 SOFT DISCHARGE LGATE DRIVER LGATE1/2 PGND EN1 PGOOD1/2 START-UP AND SHUTDOWN LOGIC LDO3EN* VCC1/2 BIAS AND REFERENCE 10µA OCSET1/2 OCP T-PAD PROTECTION LOGIC OVP/UVP/OCP/OTP ISEN1/2 LDO3IN* VREF + 16% LDO3FB* UVP 3.3V LDO FB1/2 LDO3* OVP VREF - 16% THERMAL MONITOR SOFT DISCHARGE * ISL62381, ISL2382, ISL62381C AND ISL62382C ONLY FN6665 Rev 6.00 October 23, 2015 Page 13 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Theory of Operation Four Output Controller The ISL62381, ISL62382, ISL62381C and ISL62382C generate four regulated output voltages, including two PWM controllers and two LDOs. The two PWM channels are identical and almost entirely independent, with the exception of sharing the GND pin. Unless otherwise stated, only one individual channel is discussed, and the conclusion applies to both channels. PWM Modulator The ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C and ISL62383C modulator features Intersil’s R3 technology, a hybrid of fixed frequency PWM control and variable frequency hysteretic control. Intersil’s R3 technology can simultaneously affect the PWM switching frequency and PWM duty cycle in response to input voltage and output load transients. The R3 modulator synthesizes an AC signal VR, which is an analog representation of the output inductor ripple current. The dutycycle of VR is the result of charge and discharge current through a ripple capacitor CR. The current through CR is provided by a transconductance amplifier gm that measures the VIN and VO pin voltages. The positive slope of VR can be written as Equation 1: (EQ. 1) V RPOS = g m V IN – V OUT C R The negative slope of VR can be written as Equation 2: V RNEG = g m V OUT C R (EQ. 2) Where gm is the gain of the transconductance amplifier. RIPPLE CAPACITOR VOLTAGE VR WINDOW VOLTAGE VW (WRT VCOMP) ERROR AMPLIFIER VOLTAGE VCOMP PWM FIGURE 23. MODULATOR WAVEFORMS DURING LOAD TRANSIENT A window voltage VW is referenced with respect to the error amplifier output voltage VCOMP, creating an envelope into which the ripple voltage VR is compared. The amplitude of VW is set by a resistor connected across the FSET and GND pins. The VR, VCOMP, and VW signals feed into a window comparator in which VCOMP is the lower threshold voltage and VCOMP + VW is the higher threshold voltage. Figure 23 shows FN6665 Rev 6.00 October 23, 2015 PWM pulses being generated as VR traverses the VCOMP and VCOMP + VW thresholds. The PWM switching frequency is proportional to the slew rates of the positive and negative slopes of VR; it is inversely proportional to the voltage between VW and VCOMP. Equation 3 illustrates how to calculate the window size based on output voltage and frequency set resistor RW. (EQ. 3) V W = g m V OUT 1 – D R W Programming the PWM Switching Frequency These controllers do not use a clock signal to produce PWMs. The PWM switching frequency FSW is programmed by the resistor RW that is connected from the FSET pin to the GND pin. The approximate PWM switching frequency can be expressed as written in Equation 4: 1 F SW = --------------------------------10 C R R W (EQ. 4) For a desired FSW, the RW can be selected by Equation 5. 1 R W = -----------------------------------10 C R F SW (EQ. 5) where CR = 17pF with ±20% error range. To smooth the FSET pin voltage, a ceramic capacitor such as 10nF is necessary to parallel with RW. It is recommended that whenever the control loop compensation network is modified, FSW should be checked for the correct frequency and if necessary, adjust RW. Power-On Reset These controllers are disabled until the voltage at the VIN pin has increased above the rising power-on reset (POR) threshold voltage. The controller will be disabled when the voltage at the VIN pin decreases below the falling POR threshold. In addition to VIN POR, the LDO5 pin is also monitored. If its voltage falls below 4.2V, the SMPS outputs will be shut down. This ensures that there is sufficient BOOT voltage to enhance the upper MOSFET. EN, Soft-Start and PGOOD These controllers use a digital soft-start circuit to ramp the output voltage of each SMPS to the programmed regulation setpoint at a predictable slew rate. The slew rate of the soft-start sequence has been selected to limit the in-rush current through the output capacitors as they charge to the desired regulation voltage. When the EN pins are pulled above their rising thresholds, the PGOOD Soft-Start Delay, tSS, starts and the output voltage begins to rise. The FB pin ramps to 0.6V in approximately 1.5ms and the PGOOD pin goes to high impedance approximately 1.25ms after the FB pin voltage reaches 0.6V. Page 14 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C 1.5ms VOUT tSOFTSTART VCC and LDO5 EN FB PGOOD 2.75ms PGOOD Delay FIGURE 24. SOFT-START SEQUENCE FOR ONE SMPS The PGOOD pin indicates when the converter is capable of supplying regulated voltage. It is an undefined impedance if VIN is not above the rising POR threshold or below the POR falling threshold. When a fault is detected, these controllers will turn on the open-drain NMOS, which will pull PGOOD low with a nominal impedance of 63 or 95 This will flag the system that one of the output voltages is out of regulation. Separate enable pins allow for full soft-start sequencing. Because low shutdown quiescent current is necessary to prolong battery life in notebook applications, the LDO5 5V LDO is held off until any of the three enable signals (EN1, EN2 or LDO3EN) is pulled high. Soft-start of all outputs will only start until after LDO5 is above the 4.2V POR threshold. In addition to user-programmable sequencing, these controllers include a pre-programmed sequential SMPS soft-start feature. Table 1 shows the SMPS enable truth table. After VIN is applied, the VCC1 start-up 3.6V voltage can be used as the logic high signal of any of EN1, EN2 and LDO3EN to enable PVCC if there is no other power supply on the board. MOSFET Gate-Drive Outputs LGATE and UGATE These controllers have internal gate-drivers for the high-side and low-side N-Channel MOSFETs. The low-side gate-drivers are optimized for low duty-cycle applications where the low-side MOSFET conduction losses are dominant, requiring a low r DS(ON) MOSFET. The LGATE pull-down resistance is small in order to clamp the gate of the MOSFET below the VGS(th) at turnoff. The current transient through the gate at turn-off can be considerable because the gate charge of a low r DS(ON) MOSFET can be large. Adaptive shoot-through protection prevents a gatedriver output from turning on until the opposite gate-driver output has fallen below approximately 1V. The dead-time shown in Figure 25 is extended by the additional period that the falling gate voltage stays above the 1V threshold. The typical dead-time is 21ns. The high-side gate-driver output voltage is measured across the UGATE and PHASE pins while the low-side gatedriver output voltage is measured across the LGATE and PGND pins. The power for the LGATE gate-driver is sourced directly from the LDO5 pin. The power for the UGATE gate-driver is sourced from a “boot” capacitor connected across the BOOT and PHASE pins. The boot capacitor is charged from the 5V LDO5 supply through a “boot diode” each time the low-side MOSFET turns on, pulling the PHASE pin low. These controllers have integrated boot diodes connected from the LDO5 pins to BOOT pins. TABLE 1. SMPS ENABLE SEQUENCE LOGIC tLGFUGR EN1 EN2 START-UP SEQUENCE 0 0 Both SMPS outputs OFF simultaneously 0 Float Both SMPS outputs OFF simultaneously Float 0 Both SMPS outputs OFF simultaneously UGATE Float Float Both SMPS outputs OFF simultaneously LGATE 0 1 SMPS1 OFF, SMPS2 ON 1 0 SMPS1 ON, SMPS2 OFF 1 1 Both SMPS outputs ON simultaneously Float 1 SMPS1 enables after SMPS2 is in regulation 1 Float SMPS2 enables after SMPS1 is in regulation tUGFLGR 50% 50% FIGURE 25. LGATE AND UGATE DEAD-TIME VCC1 The VCC1 nominal operation voltage is 5V. If EN1, EN2 and LDO3EN are all logic low, the VCC1 start-up voltage is 3.6V when VIN is applied on these controllers. LDO5 is held off until any of the three enable signals (EN1, EN2 or LDO3EN) is pulled high. When LDO5 is above the 4.2V VCC1 POR threshold, VCC1 will switchover to LDO5 internally. FN6665 Rev 6.00 October 23, 2015 Diode Emulation FCCM is a logic input that controls the power state of these controllers. If forced high, these controllers will operate in forced continuous-conduction-mode (CCM) over the entire load range. This will produce the best transient response to all load conditions, but will have increased light-load power loss. If FCCM is forced low, these controllers will automatically operate in diode-emulation-mode (DEM) at light load to optimize efficiency in the entire load range. The transition is Page 15 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C automatically achieved by detecting the load current and turning off LGATE when the inductor current reaches 0A. Positive-going inductor current flows from either the source of the high-side MOSFET, or the drain of the low-side MOSFET. Negative-going inductor current flows into the drain of the lowside MOSFET. When the low-side MOSFET conducts positive inductor current, the phase voltage will be negative with respect to the GND and PGND pins. Conversely, when the low-side MOSFET conducts negative inductor current, the phase voltage will be positive with respect to the GND and PGND pins. These controllers monitor the phase voltage when the low-side MOSFET is conducting inductor current to determine its direction. When the output load current is greater than or equal to ½ the inductor ripple current, the inductor current is always positive, and the converter is always in CCM. These controllers minimize the conduction loss in this condition by forcing the low-side MOSFET to operate as a synchronous rectifier. When the output load current is less than ½ the inductor ripple current, negative inductor current occurs. Sinking negative inductor current through the low-side MOSFET lowers efficiency through unnecessary conduction losses. These controllers automatically enter DEM after the PHASE pin has detected positive voltage and LGATE was allowed to go high for eight consecutive PWM switching cycles. These controllers will turn off the low-side MOSFET once the phase voltage turns positive, indicating negative inductor current. These controllers will return to CCM on the following cycle after the PHASE pin detects negative voltage, indicating that the body diode of the low-side MOSFET is conducting positive inductor current. Efficiency can be further improved with a reduction of unnecessary switching losses by reducing the PWM frequency. It is characteristic of the R3 architecture for the PWM frequency to decrease while in diode emulation. The extent of the frequency reduction is proportional to the reduction of load current. Upon entering DEM, the PWM frequency makes an initial step-reduction because of a 33% step-increase of the window voltage V W. Because the switching frequency in DEM is a function of load current, very light load conditions can produce frequencies well into the audio band. This can be problematic if audible noise is coupled into audio amplifier circuits. To prevent this from occurring, these controllers allow the user to float the FCCM input. This will allow DEM at light loads, but will prevent the switching frequency from going below ~28kHz to prevent noise injection into the audio band. A timer is reset each PWM pulse. If the timer exceeds 30µs, LGATE is turned on, causing the ramp voltage to reduce until another UGATE is commanded by the voltage loop. Overcurrent Protection The overcurrent protection (OCP) setpoint is programmed with resistor, ROCSET, that is connected across the OCSET and PHASE pins. L DCR IL PHASE1 + ROCSET ISL62381 10µA OCSET1 + VROCSET VDCR CSEN VO _ CO _ RO ISEN1 FIGURE 26. OVERCURRENT-SET CIRCUIT Figure 26 shows the overcurrent-set circuit for SMPS1. The inductor consists of inductance L and the DC resistance (DCR). The inductor DC current IL creates a voltage drop across DCR, given by Equation 6: (EQ. 6) V DCR = I L DCR Theses controllers sink a 10µA current into the OCSET1 pin, creating a DC voltage drop across the resistor ROCSET, given by Equation 7: (EQ. 7) V ROCSET = 10A R OCSET Resistor RO is connected between the ISEN1 pin and the actual output of the converter. During normal operation, the ISEN1 pin is a high impedance path, therefore there is no voltage drop across RO. The DC voltage difference between the OCSET1 pin and the ISEN1 pin can be established using Equation 8: V OCSET1 – V ISEN1 = I L DCR – 10A R OCSET (EQ. 8) These controllers monitor the OCSET1 pin and the ISEN1 pin voltages. Once the OCSET1 pin voltage is higher than the ISEN1 pin voltage for more than 10µs, these controllers declare an OCP fault. The value of ROCSET is then written as Equation 9: I OC DCR R OCSET = --------------------------10A (EQ. 9) Where: - ROCSET () is the resistor used to program the overcurrent setpoint - IOC is the output current threshold that will activate the OCP circuit - DCR is the inductor DC resistance For example, if IOC is 20A and DCR is 4.5m, the choice of ROCSET is ROCSET = 20A x 4.5m/10µA = 9k FN6665 Rev 6.00 October 23, 2015 Page 16 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Resistor ROCSET and capacitor CSEN form an RC network to sense the inductor current. To sense the inductor current correctly, not only in DC operation but also during dynamic operation, the RC network time constant ROCSETCSEN needs to match the inductor time constant L/DCR. The value of CSEN is then written as Equation 10: L C SEN = ----------------------------------------R OCSET DCR (EQ. 10) For example, if L is 1.5µH, DCR is 4.5m, and ROCSET is 9k the choice of CSEN = 1.5µH/(9kx 4.5m) = 0.037µF Upon converter start-up, the CSEN capacitor bias is 0V. To prevent false OCP during this time, a 10µA current source flows out of the ISEN1 pin, generating a voltage drop on the RO resistor, which should be chosen to have the same resistance as ROCSET. When PGOOD pin goes high, the ISEN1 pin current source will be removed. When an OCP fault is declared, the PGOOD pin will pull-down to 32and latch off the converter. The fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage, or until VIN has decayed below the falling POR threshold. When using a discrete current sense resistor, inductor time-constant matching is not required. Equation 7 remains unchanged, but Equation 8 is modified in Equation 11: V OCSET1 – V ISEN1 = I L R SENSE – 10A R OCSET (EQ. 11) Furthermore, Equation 9 is changed in Equation 12: I OC R SENSE R OCSET = ------------------------------------10A (EQ. 12) Where RSENSE is the series power resistor for sensing inductor current. For example, with an RSENSE = 1m and an OCP target of 10A, ROCSET = 1k Overvoltage Protection The OVP fault detection circuit triggers after the FB pin voltage is above the rising overvoltage threshold for more than 2µs. The FB pin voltage is 0.6V in normal operation. The rising over voltage threshold is typically 116% of that value, or 1.16*0.6V = 0.696V. When an OVP fault is declared, the PGOOD pin will pull down with 65and latch-off the converter. The OVP fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage, or until VIN has decayed below the falling POR threshold. For ISL62381, ISL62381C, ISL62383 and ISL62383C, although the converter has latched-off in response to an OVP fault, the LGATE gate-driver output will retain the ability to toggle the low-side MOSFET on and off in response to the output voltage transversing the OVP rising and falling thresholds. The LGATE gate-driver will turn on the low-side MOSFET to discharge the output voltage, thus protecting the FN6665 Rev 6.00 October 23, 2015 load from potentially damaging voltage levels. The LGATE gate-driver will turn off the low-side MOSFET once the FB pin voltage is lower than the falling overvoltage threshold for more than 2µs. The falling overvoltage threshold is typically 106% of the reference voltage, or 1.06*0.6V = 0.636V. This process repeats as long as the output voltage fault is present, allowing the ISL62381, ISL62381C, ISL62383 and ISL62383C to protect against persistent overvoltage conditions. For ISL62382 and ISL62382C, if OVP is detected, it simply tristates the PHASE node by turning UGATE and LGATE off. Undervoltage Protection The UVP fault detection circuit triggers after the FB pin voltage is below the undervoltage threshold for more than 2µs. The undervoltage threshold is typically 86% of the reference voltage, or 0.86*0.6V = 0.516V. If a UVP fault is declared, and the PGOOD pin will pull-down with 93and latch-off the converter. The fault will remain latched until the EN pin has been pulled below the falling enable threshold, or if VIN has decayed below the falling POR threshold. Programming the Output Voltage When the converter is in regulation, there will be 0.6V between the FB and GND pins. Connect a two-resistor voltage divider across the OUT and GND pins with the output node connected to the FB pin, as shown in Figure 27. Scale the voltage-divider network such that the FB pin is 0.6V with respect to the GND pin when the converter is regulating at the desired output voltage. The output voltage can be programmed from 0.6V to 5.5V. Programming the output voltage is written as Equation 13: R TOP V OUT = V REF 1 + ----------------------------- R BOTTOM (EQ. 13) Where: - VOUT is the desired output voltage of the converter - The voltage to which the converter regulates the FB pin is the VREF (0.6V) - RTOP is the voltage-programming resistor that connects from the FB pin to the converter output. In addition to setting the output voltage, this resistor is part of the loop compensation network - RBOTTOM is the voltage-programming resistor that connects from the FB pin to the GND pin Choose RTOP first when compensating the control loop, and then calculate RBOTTOM according to Equation 14: V REF R TOP R BOTTOM = ------------------------------------V OUT – V REF (EQ. 14) Compensation Design Figure 27 shows the recommended Type-II compensation circuit. The FB pin is the inverting input of the error amplifier. The COMP signal, the output of the error amplifier, is inside the chip and unavailable to users. CINT is a 100pF capacitor integrated inside the IC that connects across the FB pin and the COMP signal. Page 17 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C RTOP, RFB, CFB and CINT form the Type-II compensator. The frequency domain transfer function is given by Equation 15: 1 + s R TOP + R FB C FB G COMP s = ------------------------------------------------------------------------------------------s R TOP C INT 1 + s R FB C (EQ. 15) FB CINT = 100pF CFB RFB RTOP - VO FB EA RBOTTOM COMP + REF ISL6238 Thermal Monitor and Protection LDO3 and LDO5 can dissipate non-trivial power inside these controllers at high input-to-output voltage ratios and full load conditions. To protect the silicon, these controllers continually monitor the die temperature. If the temperature exceeds +150°C, all outputs will be turned off to sharply curtail power dissipation. The outputs will remain off until the junction temperature has fallen below +135°C. General Application Design Guide This design guide is intended to provide a high-level explanation of the steps necessary to design a single-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following section. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts. FIGURE 27. COMPENSATION REFERENCE CIRCUIT The LC output filter has a double pole at its resonant frequency that causes rapid phase change. The R3 modulator used in these controllers make the LC output filter resemble a first order system in which the closed loop stability can be achieved with the recommended Type-II compensation network. Intersil provides a PC-based tool (example page is shown later) that can be used to calculate compensation network component values and help simulate the loop frequency response. LDO5 Linear Regulator In addition to the two SMPS outputs, these controllers also provide two linear regulator outputs. LDO5 is fixed 5V LDO output capable of sourcing 100mA continuous current. When the output of SMPS2 is programmed to 5V, SMPS2 will automatically take over the load of LDO5. This provides a large power savings and boosts the efficiency. After switchover to SMPS2, the LDO5 output current plus the MOSFET drive current should not exceed 100mA in order to guarantee the LDO5 output voltage in the range of 5V ±5%. The total MOSFET drive current can be estimated by Equation 16. I DRIVE = Q g F SW (EQ. 16) where Qg is the total gate charge of all the power MOSFET in two SMPS regulators. Then the LDO5 output load current should be less than 100mA-IDRIVE. LDO3 Linear Regulator ISL62381, ISL62381C, ISL62382 and ISL62382C include LDO3 linear regulator whose output is adjustable from 1.2V to 5V through LDO3FB pin with a 1.2V reference voltage. It can be independently enabled from both SMPS channels. Logic high of LDO3EN will enable LDO3. LDO3 is capable of sourcing 100mA continuous current and draws its power from LDO3IN pin, which must be connected to a voltage greater than the LDO3 output voltage plus the dropout voltage. Currents in excess of the limit will cause the LDO3 voltage to drop dramatically, limiting the power dissipation. FN6665 Rev 6.00 October 23, 2015 Selecting the LC Output Filter The duty cycle of an ideal buck converter is a function of the input and the output voltage. This relationship is written as Equation 17: V OUT D = --------------V IN (EQ. 17) The output inductor peak-to-peak ripple current is written as Equation 18: V OUT 1 – D I PP = -------------------------------------F SW L (EQ. 18) A typical step-down DC/DC converter will have an IP-P of 20% to 40% of the maximum DC output load current. The value of IP-P is selected based upon several criteria such as MOSFET switching loss, inductor core loss, and the resistive loss of the inductor winding. The DC copper loss of the inductor can be estimated by Equation 19: P COPPER = I LOAD 2 (EQ. 19) DCR Where ILOAD is the converter output DC current. The copper loss can be significant so attention has to be given to the DCR selection. Another factor to consider when choosing the inductor is its saturation characteristics at elevated temperatures. A saturated inductor could cause destruction of circuit components, as well as nuisance OCP faults. A DC/DC buck regulator must have output capacitance CO into which ripple current IP-P can flow. Current IP-P develops out of the capacitor. These two voltages are written as Equation 20: V ESR = I PP E SR (EQ. 20) and Equation 21: I PP V C = ------------------------------8 CO F (EQ. 21) SW If the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total ESR until the required VP-P is achieved. The Page 18 of 24 inductance of the capacitor can cause a brief voltage dip if the load transient has an extremely high slew rate. Low inductance capacitors should be considered in this scenario. A capacitor dissipates heat as a function of RMS current and frequency. Be sure that IP-P is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated RMS current at FSW. Take into account that the rated value of a capacitor can fade as much as 50% as the DC voltage across it increases. Selection of the Input Capacitor The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the RMS current required by the switching circuit. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a preferred rating. Figure 28 is a graph of the input capacitor RMS ripple current, normalized relative to output load current, as a function of duty cycle and is adjusted for converter efficiency. The normalized RMS ripple current calculation is written as Equation 22: 2 Dk I MAX D 1 – D + -------------12 I C RMS ,NORMALIZED = ----------------------------------------------------------------------I MAX IN (EQ. 22) Where: - IMAX is the maximum continuous ILOAD of the converter - k is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of IMAX (0% to 100%) - D is the duty cycle that is adjusted to take into account the efficiency of the converter which is written as: V OUT D = -------------------------V IN EFF (EQ. 23) In addition to the bulk capacitance, some low ESL ceramic capacitance is recommended to decouple between the drain of the high-side MOSFET and the source of the low-side MOSFET. NORMALIZED INPUT RMS RIPPLE CURRENT ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C 0.6 0.48 k=1 k = 0.75 k = 0.5 k = 0.25 k=0 0.36 0.24 0.12 0 0 0.1 0.3 0.2 0.4 0.5 0.6 0.7 0.8 0.9 1.0 DUTY CYCLE FIGURE 28. NORMALIZED RMS INPUT CURRENT @ EFF = 1 MOSFET Selection and Considerations Typically, a MOSFET cannot tolerate even brief excursions beyond their maximum drain to source voltage rating. The MOSFETs used in the power stage of the converter should have a maximum VDS rating that exceeds the sum of the upper voltage tolerance of the input power source and the voltage spike that occurs when the MOSFET switches off. There are several power MOSFETs readily available that are optimized for DC/DC converter applications. The preferred high-side MOSFET emphasizes low gate charge so that the device spends the least amount of time dissipating power in the linear region. Unlike the low-side MOSFET which has the drain-source voltage clamped by its body diode during turn off, the high-side MOSFET turns off with a VDS of approximately VIN - VOUT, plus the spike across it. The preferred low-side MOSFET emphasizes low r DS(ON) when fully saturated to minimize conduction loss. It should be noted that this is an optimal configuration of MOSFET selection for low duty cycle applications (D < 50%). For higher output, low input voltage solutions, a more balanced MOSFET selection for high- and low-side devices may be warranted. For the low-side (LS) MOSFET, the power loss can be assumed to be conductive only and is written as Equation 24: 2 P CON_LS I LOAD r DS ON _LS 1 – D (EQ. 24) For the high-side (HS) MOSFET, the its conduction loss is written as Equation 25: P CON_HS = I LOAD 2 r DS ON _HS D (EQ. 25) For the high-side MOSFET, the switching loss is written as Equation 26: V IN I PEAK t OFF f V IN I VALLEY t ON f SW SW P SW_HS = ----------------------------------------------------------------- + ------------------------------------------------------------2 2 (EQ. 26) FN6665 Rev 6.00 October 23, 2015 Page 19 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Where: - IVALLEY is the difference of the DC component of the inductor current minus 1/2 of the inductor ripple current - IPEAK is the sum of the DC component of the inductor current plus 1/2 of the inductor ripple current - tON is the time required to drive the device into saturation - tOFF is the time required to drive the device into cut-off Co PIN 4 (VCC2) L2 PIN 21 (VIN) L2 ISL62381 AND ISL62382 Ci LINE OF SYMMETRY Selecting The Bootstrap Capacitor The selection of the bootstrap capacitor is written as Equation 27: Qg C BOOT = -----------------------V BOOT U2 (EQ. 27) Where: - Qg is the total gate charge required to turn on the high-side MOSFET - VBOOT, is the maximum allowed voltage decay across the boot capacitor each time the high-side MOSFET is switched on Ci L1 PGND PLANE PHASE PLANES VOUT PLANES VIN PLANE U1 L1 Co FIGURE 30. SYMMETRIC LAYOUT GUIDE Signal Ground and Power Ground As an example, suppose the high-side MOSFET has a total gate charge Qg, of 25nC at VGS = 5V, and a VBOOT of 200mV. The calculated bootstrap capacitance is 0.125µF; for a comfortable margin, select a capacitor that is double the calculated capacitance. In this example, 0.22µF will suffice. Use an X7R or X5R ceramic capacitor. The bottom of these controllers TQFN package is the signal ground (GND) terminal for analog and logic signals of the IC. Connect the GND pad of these controllers to the island of ground plane under the top layer using several vias for a robust thermal and electrical conduction path. Connect the input capacitors, the output capacitors, and the source of the lower MOSFETs to the power ground (PGND) plane. Layout Considerations The following pin descriptions use ISL62381 as an example. As a general rule, power should be on the bottom layer of the PCB and weak analog or logic signals are on the top layer of the PCB. The ground-plane layer should be adjacent to the top layer to provide shielding. The ground plane layer should have an island located under the IC, the compensation components, and the FSET components. The island should be connected to the rest of the ground plane layer at one point. VIAS TO VIAS TO GROUND GROUND PLANE PLANE GND VOUT INDUCTOR INDUCTOR HIGH-SIDE HIGH-SIDE MOSFETS MOSFETS PHASE NODE VIN OUTPUT OUTPUT CAPACITORS CAPACITORS SCHOTTKY SCHOTTKY DIODE DIODE LOW-SIDE LOW-SIDE MOSFETS MOSFETS INPUT INPUT CAPACITORS CAPACITORS FIGURE 29. TYPICAL POWER COMPONENT PLACEMENT Because there are two SMPS outputs and only one PGND pin, the power train of both channels should be laid out symmetrically. The line of bilateral symmetry should be drawn through pins 4 and 21 (pins 4 and 18 for ISL62383). This layout approach ensures that the controller does not favor one channel over another during critical switching decisions. Figure 30 illustrates one example of how to achieve proper bilateral symmetry. FN6665 Rev 6.00 October 23, 2015 PGND (Pin 23) This is the return path for the pull-down of the LGATE low-side MOSFET gate driver. Ideally, PGND should be connected to the source of the low-side MOSFET with a low-resistance, lowinductance path. VIN (Pin 21) The VIN pin should be connected close to the drain of the highside MOSFET, using a low resistance and low inductance path. VCC (Pins 4 and 5) For best performance, place the decoupling capacitor very close to the VCC and GND pins. LDO5 (Pin 22) For best performance, place the decoupling capacitor very close to the LDO5 and respective PGND pin, preferably on the same side of the PCB as the ISL62381 IC. EN (Pins 13 and 28) and PGOOD (Pins 1 and 8) These are logic signals that are referenced to the GND pin. Treat as a typical logic signal. OCSET (Pins 12 and 29) and ISEN (Pins 11 and 30) For DCR current sensing, current-sense network, consisting of ROCSET and CSEN, needs to be connected to the inductor pads for accurate measurement. Connect ROCSET to the phase-node side pad of the inductor, and connect CSEN to the output side pad of the inductor. The ISEN resistor should also Page 20 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C be connected to the output pad of the inductor with a separate trace. Connect the OCSET pin to the common node of node of ROCSET and CSEN. For resistive current sensing, connect ROCSET from the OCSET pin to the inductor side of the resistor pad. The ISEN resistor should be connected to the VOUT side of the resistor pad. In both current-sense configurations, the resistor and capacitor sensing elements, with the exclusion of the current sense power resistor, should be placed near the corresponding IC pin. The trace connections to the inductor or sensing resistor should be treated as Kelvin connections. FB (Pins 9 and 32), and VOUT (Pins 10 and 31) The VOUT pin is used to generate the R3 synthetic ramp voltage and for soft-discharge of the output voltage during shutdown events. This signal should be routed as close to the regulation point as possible. The input impedance of the FB pin is high, so place the voltage programming and loop compensation components close to the VOUT, FB, and GND pins keeping the high impedance trace short. FSET (Pins 2 and 7) These pins require a quiet environment. The resistor RFSET and capacitor CFSET should be placed directly adjacent to these pins. Keep fast moving nodes away from these pins. FN6665 Rev 6.00 October 23, 2015 LGATE (Pins 17 and 24) The signal going through these traces are both high dv/dt and high di/dt, with high peak charging and discharging current. Route these traces in parallel with the trace from the PGND pin. These two traces should be short, wide, and away from other traces. There should be no other weak signal traces in proximity with these traces on any layer. BOOT (Pins 16 and 25), UGATE (Pins 15 and 26), and PHASE (Pins 14 and 27) The signals going through these traces are both high dv/dt and high di/dt, with high peak charging and discharging current. Route the UGATE and PHASE pins in parallel with short and wide traces. There should be no other weak signal traces in proximity with these traces on any layer. Copper Size for the Phase Node The parasitic capacitance and parasitic inductance of the phase node should be kept very low to minimize ringing. It is best to limit the size of the PHASE node copper in strict accordance with the current and thermal management of the application. An MLCC should be connected directly across the drain of the upper MOSFET and the source of the lower MOSFET to suppress the turn-off voltage spike. Page 21 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION October 23, 2015 FN6665.6 CHANGE Updated Ordering Information table on page 2. Added Revision History and About Intersil sections. Updated Package Outline Drawing L28.4x4 to the latest revision. Changes are as follows: -Added +/- 0.05 tolerances to each dimension in Top View and Bottom View per Samsung request. -Added 2 degrees to Bottom view pin 1 index area dimension About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2008-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6665 Rev 6.00 October 23, 2015 Page 22 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Package Outline Drawing L28.4x4 28 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 6/15 A 2.50 ±0.05 PIN #1 INDEX AREA CHAMFER 0.400 ±0.05 x 45° ±2° 0.40 ±0.05 22 28 1 2.50 ±0.05 4.00 ±0.05 21 0.40 ±0.05 15 3.20 ±0.05 B PIN 1 INDEX AREA 0.4 x 6 = 2.40 REF 4.00 ±0.05 7 0.10 2x 14 8 0.4 x 6 = 2.40 REF 3.20 ±0.05 TOP VIEW 0.20 ±0.05 0.10 M C A B BOTTOM VIEW SEE DETAIL X'' 0.10 C (3.20) PACKAGE OUTLINE C MAX. 0.80 (28x 0.20) 0.00 - 0.05 0.20 REF SEATING PLANE 0.08 C (3.20) (2.50) SIDE VIEW (0.40) (0.40) C 0.20 REF 5 0 ~ 0.05 (2.50) (28x 0.60) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Controlling dimensions are in mm. Dimensions in ( ) are for reference only. 2. Unless otherwise specified, tolerance : Decimal ±0.05 Angular ±2° 3. Dimensioning and tolerancing conform to AMSE Y14.5M-1994. 4. Bottom side Pin#1 ID is diepad chamfer as shown. 5. Tiebar shown (if present) is a non-functional feature. FN6665 Rev 6.00 October 23, 2015 Page 23 of 24 ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP) L32.5x5A 2X 0.15 C A D A 32 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220WJJD-1 ISSUE C) D/2 MILLIMETERS 2X 6 INDEX AREA N 0.15 C B 1 2 3 SYMBOL MIN NOMINAL MAX NOTES A 0.70 0.75 0.80 - A1 - - 0.05 - 0.30 5, 8 3.55 7, 8 A3 E/2 b E D D2 B TOP VIEW 0.20 REF 0.18 5.00 BSC 3.30 C 0.08 C SEATING PLANE A3 SIDE VIEW A1 3.45 - E 5.00 BSC - 5.75 BSC 9 3.30 e / / 0.10 C - E1 E2 A 0.25 3.45 3.55 0.50 BSC 7, 8 - k 0.20 - - - L 0.30 0.40 0.50 8 N 32 2 Nd 8 3 Ne 8 3 Rev. 2 05/06 NX b 5 0.10 M C A B D2 NX k D2 2 (DATUM B) 8 7 N (DATUM A) 6 INDEX AREA E2 E2/2 3 2 1 NX L N 7 (Ne-1)Xe REF. 8 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. e 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 SECTION "C-C" FN6665 Rev 6.00 October 23, 2015 Page 24 of 24