IRF3808SPbF
IRF3808LPbF
HEXFET® Power MOSFET
Typical Applications
l Industrial Motor Drive
D
Benefits
l
l
l
l
l
l
l
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
VDSS = 75V
RDS(on) = 0.007Ω
G
ID = 106A
S
Description
This Advanced Planar Stripe HEXFET ® Power MOSFET
utilizes the latest processing techniques to achieve
extremely low on-resistance per silicon area. Additional
features of this HEXFET power MOSFET are a 175°C
junction operating temperature, low RθJC, fast switching
speed and improved repetitive avalanche rating. This
combination makes the design an extremely efficient and
reliable choice for use in a wide variety of applications.
Base Part Number
Package Type
IRF3808LPbF
TO-262
IRF3808SPbF
D Pak
2
Standard Pack
Form
Tube
Tube
Tape and Reel Left
Tape and Reel Right
D2Pak
IRF3808SPbF
Quantity
50
50
800
800
TO-262
IRF3808LPbF
Orderable Part Number
IRF3808LPbF
IRF3808SPbF
IRF3808STRLPbF
IRF3808STRRPbF
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
Units
106
75
550
200
1.3
± 20
430
82
See Fig.12a, 12b, 15, 16
5.5
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
1
Junction-to-Case
Junction-to-Ambient (PCB Mounted, Steady State)
Typ.
Max.
Units
–––
–––
0.75
40
°C/W
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IRF3808S/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
75
–––
–––
2.0
100
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.086
5.9
–––
–––
–––
–––
–––
–––
150
31
50
16
140
68
120
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
4.5
LS
Internal Source Inductance
–––
7.5
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
5310
890
130
6010
570
1140
V(BR)DSS
ΔV(BR)DSS/ΔTJ
IGSS
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250μA
––– V/°C Reference to 25°C, ID = 1mA
7.0
mΩ VGS = 10V, ID = 82A
4.0
V
VDS = 10V, ID = 250μA
–––
S
VDS = 25V, ID = 82A
20
VDS = 75V, VGS = 0V
μA
250
VDS = 60V, VGS = 0V, TJ = 150°C
200
VGS = 20V
nA
-200
VGS = -20V
220
ID = 82A
47
nC
VDS = 60V
76
VGS = 10V
–––
VDD = 38V
–––
ID = 82A
ns
–––
RG = 2.5Ω
–––
VGS = 10V
D
Between lead,
–––
6mm (0.25in.)
nH
G
from package
–––
and center of die contact
S
–––
VGS = 0V
–––
pF
VDS = 25V
–––
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 60V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 60V
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
IS
ISM
VSD
trr
Qrr
ton
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Starting TJ = 25°C, L = 0.130mH
RG = 25Ω, IAS = 82A. (See Figure 12).
ISD ≤ 82A, di/dt ≤ 310A/μs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Pulse width ≤ 400μs; duty cycle ≤ 2%.
2
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 106
showing the
A
G
integral reverse
––– ––– 550
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 82A, VGS = 0V
––– 93 140
ns
TJ = 25°C, IF = 82A
––– 340 510
nC di/dt = 100A/μs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to
application note #AN-994.
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IRF3808S/LPbF
I D, Drain-to-Source Current (A)
TOP
BOTTOM
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
I D, Drain-to-Source Current (A)
1000
100
4.5V
10
20μs PULSE WIDTH
T J= 25 ° C
1
0.1
1
10
BOTTOM
100
4.5V
10
20μs PULSE WIDTH
T J= 175 ° C
1
100
0.1
1
V DS, Drain-to-Source Voltage (V)
10
100
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.00
3.0
I D = 137A
RDS(on) , Drain-to-Source On Resistance
100.00
T J = 25°C
VDS = 15V
20μs PULSE WIDTH
10.00
1.0
3.0
5.0
7.0
9.0
11.0
13.0
15.0
2.0
(Normalized)
ID, Drain-to-Source Current (Α)
2.5
TJ = 175°C
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
80
TJ , Junction Temperature
100 120 140 160 180
( °C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
3
Fig 4. Normalized On-Resistance
Vs. Temperature
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IRF3808S/LPbF
100000
12
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
I D = 82A
VDS = 60V
VDS = 37V
VDS = 15V
10
VGS , Gate-to-Source Voltage (V)
C, Capacitance(pF)
Coss = Cds + Cgd
10000
Ciss
Coss
1000
8
6
4
2
Crss
0
100
1
10
0
100
40
VDS , Drain-to-Source Voltage (V)
1000.00
160
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
120
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
T J = 175°C
100.00
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
10.00
100
T J = 25°C
1.00
100μsec
1msec
10
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
10msec
1
0.10
0.0
0.5
1.0
1.5
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
80
QG, Total Gate Charge (nC)
2.0
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF3808S/LPbF
120
RD
VDS
ID, Drain Current (A)
100
VGS
D.U.T.
RG
80
+
-VDD
10V
60
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
40
Fig 10a. Switching Time Test Circuit
20
VDS
90%
0
25
50
75
100
125
150
175
TC , Case Temperature (°C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
(Z thJC )
1
D = 0.50
Thermal Response
0.20
0.1
0.10
P DM
0.05
t1
0.02
0.01
t2
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
t1/ t 2
J = P DM x Z thJC
0.1
+TC
1
10
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
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November 01, 2013
IRF3808S/LPbF
800
15V
TOP
+
V
- DD
IAS
20V
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
A
EAS , Single Pulse Avalanche Energy (mJ)
D.U.T
RG
640
DRIVER
L
VDS
BOTTOM
480
320
160
0
25
50
75
100
Starting Tj, Junction Temperature
I AS
ID
34A
58A
82A
125
150
( ° C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
QGS
QGD
3.5
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2μF
.3μF
D.U.T.
+
V
- DS
VGS(th) Gate threshold Voltage (V)
10 V
3.0
ID = 250μA
2.5
2.0
1.5
1.0
-75 -50 -25
VGS
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage Vs. Temperature
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IRF3808S/LPbF
10000
Avalanche Current (A)
1000
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming Δ Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
Duty Cycle = Single Pulse
100
0.01
0.05
0.10
10
1
0.1
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
EAR , Avalanche Energy (mJ)
500
TOP
Single Pulse
BOTTOM 10% Duty Cycle
ID = 140A
400
300
200
100
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
7
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
175
D = Duty cycle in avalanche = t av ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
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IRF3808S/LPbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VGS
*
+
-
VDD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 17. For N-channel HEXFET® power MOSFETs
8
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IRF3808S/LPbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
T HIS IS AN IRF530S WITH
LOT CODE 8024
ASSEMBLED ON WW 02, 2000
IN THE ASS EMBLY LINE "L"
INT ERNAT IONAL
RECT IF IER
LOGO
ASSE MBLY
LOT CODE
PART NUMBER
F 530S
DAT E CODE
YE AR 0 = 2000
WEE K 02
LINE L
OR
INT ERNAT IONAL
RECT IF IER
LOGO
ASSE MBLY
LOT CODE
PART NUMBER
F 530S
DAT E CODE
P = DESIGNATES LEAD - F REE
PRODUCT (OPT IONAL)
YE AR 0 = 2000
WEEK 02
A = ASS EMBLY SITE CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
9
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November 01, 2013
IRF3808S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE : T HIS IS AN IRL3103L
LOT CODE 1789
AS SEMBLED ON WW 19, 1997
IN T HE ASSEMBLY LINE "C"
Note: "P" in assembly line
position indicates "Lead-F ree"
INT E RNAT IONAL
RECT IFIER
LOGO
ASSE MBLY
LOT CODE
PART NUMBER
DAT E CODE
YE AR 7 = 1997
WEEK 19
LINE C
OR
INTE RNAT IONAL
RECT IFIER
LOGO
ASSE MBLY
LOT CODE
PART NUMBE R
DAT E CODE
P = DE SIGNAT ES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = ASSEMBLY SITE CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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November 01, 2013
IRF3808S/LPbF
D2Pak Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
60.00 (2.362)
MIN.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
11
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IRF3808S/LPbF
†
Qualification information
Industrial
Qualification level
(per JE DE C JE S D47F
RoHS compliant
D2-PAK
guidelines)
N/A
TO-262 PAK
Moisture Sensitivity Level
††
MS L1
††
(per JE DEC J-S T D-020D )
Yes
† Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability
†† Applicable version of JEDEC standard at the time of product release
Revision History
Date
11/1/2013
Comments
• Updated datasheet with New IR corporate template
• Removed note6 because update package ID from "75A" to "106A"-page 1 & 2
• Added Odering information table-page 1
• Corrected fig9-page 5
• Added Qualification information table-page 12
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
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