CY7C1061DV33 16-Mbit (1M x 16) Static RAM Features Functional Description ■ High speed ❐ tAA = 10 ns The CY7C1061DV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power ❐ ICC = 175 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 25 mA ■ Operating voltages of 3.3 ± 0.3V To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A19). ■ 2.0V data retention ■ Automatic power down when deselected ■ TTL compatible inputs and outputs ■ Easy memory expansion with CE1 and CE2 features ■ Available in Pb-free 54-Pin TSOP II and 48-Ball VFBGA packages To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the Truth Table on page 9 for a complete description of Read and Write modes. The input or output pins (IO0 through IO15) are placed in a high impedance state when the device is deselected (CE1 HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C1061DV33 is available in a 54-Pin TSOP II package with center power and ground (revolutionary) pinout, and a 48-Ball VFBGA package. Logic Block Diagram 1M x 16 ARRAY SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER IO0 – IO7 IO8 – IO15 A10 A11 A 12 A 13 A 14 A 15 A 16 A 17 A18 A19 COLUMN DECODER BHE WE OE BLE Cypress Semiconductor Corporation Document Number: 38-05476 Rev. *D • 198 Champion Court • CE2 CE1 San Jose, CA 95134-1709 • 408-943-2600 Revised September 06, 2007 CY7C1061DV33 Selection Guide –10 Unit Maximum Access Time 10 ns Maximum Operating Current 175 mA Maximum CMOS Standby Current 25 mA Pin Configuration Figure 1. 54-Pin TSOP II (Top View) [1] IO12 VCC IO13 IO14 VSS IO15 A4 A3 A2 A1 A0 BHE CE1 VCC WE CE2 A19 A18 A17 A16 A15 IO0 VCC IO1 IO2 VSS IO3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 45 44 IO11 VSS IO10 IO9 VCC IO8 A5 A6 A7 A8 A9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 NC OE VSS NC BLE A10 A11 A12 A13 A14 IO7 VSS IO6 IO5 VCC IO4 54 53 52 51 50 49 48 47 46 Figure 2. 48-Ball VFBGA (Top View) [1] 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A IO8 BHE A3 A4 CE1 IO0 B IO9 IO10 A5 A6 IO1 IO2 C VSS IO11 A17 A7 IO3 VCC D VCC IO12 NC A16 IO4 VSS E IO14 IO13 A14 A15 IO5 IO6 F IO15 NC A12 A13 WE IO7 G A18 A8 A9 A10 A11 A19 H Note 1. NC pins are not connected on the die. Document Number: 38-05476 Rev. *D Page 2 of 11 CY7C1061DV33 Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Static Discharge Voltage............. ...............................>2001V (MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch Up Current ..................................................... >200 mA Ambient Temperature with Power Applied ............................................ –55°C to +125°C Operating Range Supply Voltage on VCC Relative to GND [2] ....–0.5V to +4.6V Range VCC DC Voltage Applied to Outputs in High Z State [2] ................................... –0.5V to VCC + 0.5V Ambient Temperature Industrial –40°C to +85°C 3.3V ± 0.3V DC Input Voltage [2] ............................... –0.5V to VCC + 0.5V DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH Voltage [2] –10 Min Unit Max 2.4 V 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V VIL Input LOW Voltage IIX Input Leakage Current GND < VI < VCC –1 +1 µA IOZ Output Leakage Current GND < VOUT < VCC, Output disabled –1 +1 µA ICC VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA CMOS levels 175 mA ISB1 Automatic CE Power Down Max VCC, CE1 > VIH, CE2 < VIL, Current — TTL Inputs VIN > VIH or VIN < VIL, f = fMAX 30 mA ISB2 Automatic CE Power Down Max VCC, CE1 > VCC – 0.3V, CE2 < 0.3V, Current —CMOS Inputs VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 25 mA Note 2. VIL (min) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. Document Number: 38-05476 Rev. *D Page 3 of 11 CY7C1061DV33 Capacitance Tested initially and after any design or process changes that may affect these parameters. Description Test Conditions CIN Parameter Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V COUT IO Capacitance TSOP II VFBGA Unit 6 8 pF 8 10 pF TSOP II VFBGA Unit 24.18 28.37 °C/W 5.40 5.79 °C/W Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board AC Test Loads and Waveforms The AC test loads and waveform diagram follows. [3] HIGH-Z CHARACTERISTICS: R1 317Ω 3.3V 50Ω VTH = 1.5V OUTPUT Z0 = 50Ω OUTPUT 30 pF* 5 pF* INCLUDING JIG AND SCOPE (b) (a) * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT R2 351Ω ALL INPUT PULSES 3.0V GND 90% 90% 10% RISE TIME: > 1 V/ns 10% (c) FALL TIME: > 1 V/ns Note 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100 µs (tpower) after reaching the minimum operating VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document Number: 38-05476 Rev. *D Page 4 of 11 CY7C1061DV33 AC Switching Characteristics Over the Operating Range [4] Parameter –10 Description Min Max Unit Read Cycle tpower VCC(Typical) to the First Access [5] 100 µs tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW/CE2 HIGH to Data Valid 10 ns tDOE OE LOW to Data Valid 5 ns tLZOE OE LOW to Low Z 10 tHZOE OE HIGH to High Z CE1 LOW/CE2 HIGH to Low Z [6] tHZCE [6] CE1 HIGH/CE2 LOW to High Z 3 tPD CE1 HIGH/CE2 LOW to Power Down Byte Enable to Data Valid tLZBE Byte Enable to Low Z 0 [7] ns ns 10 ns 5 ns 1 Byte Disable to High Z ns ns 5 [7] tDBE Write Cycle ns 5 CE1 LOW/CE2 HIGH to Power Up tHZBE ns 1 [6] tLZCE tPU 3 ns ns 5 ns [8, 9] tWC Write Cycle Time 10 ns tSCE CE1 LOW/CE2 HIGH to Write End 7 ns tAW Address Setup to Write End 7 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 7 ns tSD Data Setup to Write End 5.5 ns tHD Data Hold from Write End 0 ns tLZWE WE HIGH to Low Z [6] 3 ns tHZWE WE LOW to High Z [6] tBW Byte Enable to End of Write 5 7 ns ns Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading shown in part a) of AC Test Loads and Waveforms, unless specified otherwise. 5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 6. tHZOE, tHZCE, tHZWE, tHZBE , tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ±200 mV from steady state voltage. 7. These parameters are guaranteed by design and are not tested. 8. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. Chip enables must be active and WE and byte enables must be LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05476 Rev. *D Page 5 of 11 CY7C1061DV33 Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR [10] Chip Deselect to Data Retention Time tR [ 11] Min Typ Max 2 V 25 VCC = 2V , CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V Operation Recovery Time Unit mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V VDR > 2V 3.0V tR tCDR CE Switching Waveforms Figure 3. Read Cycle No. 1 [12, 13] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Notes 10. Tested initially and after any design or process changes that may affect these parameters. 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs. 12. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. 13. WE is HIGH for read cycle. Document Number: 38-05476 Rev. *D Page 6 of 11 CY7C1061DV33 Switching Waveforms (continued) Figure 4. Read Cycle No. 2 (OE Controlled) [13, 14] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT tHZBE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% 50% ICC ISB Figure 5. Write Cycle No. 1 (CE Controlled) [15, 16, 17] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE t BW BHE, BLE tSD tHD DATA IO Notes 14. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. 15. CE is a shorthand combination of both CE1 and CE2 combined. It is active LOW. 16. Data IO is high impedance if OE, BHE, and/or BLE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05476 Rev. *D Page 7 of 11 CY7C1061DV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (WE Controlled, OE LOW) [15, 16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA IO tLZWE Figure 7. Write Cycle No. 3 (BLE or BHE Controlled) [15] tWC ADDRESS tSA tBW BHE, BLE tAW tHA tPWE WE tSCE CE tSD tHD DATA IO Document Number: 38-05476 Rev. *D Page 8 of 11 CY7C1061DV33 Truth Table CE1 CE2 OE WE BLE BHE IO0 – IO7 IO8 – IO15 Mode Power H X X X X X High Z High Z Power Down Standby (ISB) X L X X X X High Z High Z Power Down Standby (ISB) L H L H L L Data Out Data Out Read All Bits Active (ICC) L H L H L H Data Out High Z Read Lower Bits Only Active (ICC) L H L H H L High Z Data Out Read Upper Bits Only Active (ICC) L H X L L L Data In Data In Write All Bits Active (ICC) L H X L L H Data In High Z Write Lower Bits Only Active (ICC) L H X L H L High Z Data In Write Upper Bits Only Active (ICC) L H H H X X High Z High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) Ordering Code 10 CY7C1061DV33-10ZSXI Package Diagram Package Type 51-85160 54-Pin TSOP II (Pb-Free) Operating Range Industrial CY7C1061DV33-10BVXI 51-85178 48-Ball VFBGA (8 × 9.5 × 1 mm) (Pb-Free) Package Diagrams Figure 8. 54-Pin TSOP Type II 51-85160-** Document Number: 38-05476 Rev. *D Page 9 of 11 CY7C1061DV33 Package Diagrams (continued) Figure 9. 48-Ball VFBGA (8 x 9.5 x 1 mm) BOTTOM VIEW TOP VIEW A1 CORNER C Ø0.05 M Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 3 4 5 6 6 5 4 3 2 1 A B C B F G D E 2.625 E C 0.75 D 5.25 A 9.50±0.10 9.50±0.10 1 2 F G H H A 1.875 A B 8.00±0.10 0.75 B 0.10 C 0.21±0.05 0.25 C 0.55 MAX. 3.75 8.00±0.10 0.15(4X) Document Number: 38-05476 Rev. *D 1.00 MAX 0.26 MAX. SEATING PLANE C 51-85178. ** Page 10 of 11 CY7C1061DV33 Document History Page Document Title: CY7C1061DV33 16-Mbit (1M x 16) Static RAM Document Number: 38-05476 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance datasheet for C9 IPP *A 233748 See ECN RKF AC, DC parameters are modified as per EROS (Specification number 01-2165) Added Pb-free devices in the Ordering Information *B 469420 See ECN NXR Converted from Advance Information to Preliminary Corrected typo in the Document Title Removed –8 and –12 speed bins from product offering Removed Commercial Operating Range Changed 2G-Ball of FBGA and pin 40 of TSOPII from DNU to NC Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on page 3 Changed ICC(Max) from 220 mA to 125 mA Changed ISB1(Max) from 70 mA to 30 mA Changed ISB2(Max) from 40 mA to 25 mA Specified the Overshoot specification in footnote 1. Updated the Ordering Information Table *C 499604 See ECN NXR Added note 1 for NC pins Updated Test Condition for ICC in DC Electrical Characteristics table Updated the 48-Ball FBGA Package *D 1462583 See ECN VKN/AESA Converted from preliminary to final Changed ICC specification from 125 mA to 175 mA Updated thermal specs © Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05476 Rev. *D Revised September 06, 2007 All product and company names mentioned in this document are the trademarks of their respective holders. Page 11 of 11