MOTOROLA MC44827 Lowâ power pll tuning circuit Datasheet

Order this document by MC44827/D
The MC44827/27B are tuning circuits for TV and VCR tuner applications.
They contain on one chip all the functions required for PLL control of a VCO.
The integrated circuits also contain a high frequency prescaler and thus can
handle frequencies up to 1.3 GHz.
The MC44827 has programmable 512/1024 reference divider while the
MC44827B has a fixed reference divider of 1024.
The MC44827/27B offer the same features as MC44817/17B but has
improved sensitivity performance and reduced power dissipation. The low
frequency preamplifier has been removed and the operational amplifier
pull–up resistor has been increased to 60 kΩ.
The MC44827/27B are controlled via a 3–wire bus. The MC44827/27B
have the same functions as the MC44828 which is I2C bus controlled. The
MC44827/27B and the MC44828 can be exchanged to allow conversion
between 3–wire bus and I2C bus control.
The MC44827/27B are manufactured on a single silicon chip using
Motorola’s high density bipolar process, MOSAIC (Motorola Oxide Self
Aligned Implanted Circuits).
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LOW–POWER
PLL TUNING CIRCUIT
FOR 3–WIRE BUS WITH
1.3 GHz PRESCALER
SEMICONDUCTOR
TECHNICAL DATA
Complete Single Chip System for MPU Control (3–Wire Bus). Data and
Clock Inputs are I2C Bus Compatible
Divide–by–8 Prescaler Accepts Frequencies up to 1.3 GHz
16
1
15 Bit Programmable Divider Accepts Input Frequencies up to 165 MHz
3–State Phase/Frequency Comparator
DTB SUFFIX
PLASTIC PACKAGE
CASE 948F
(TSSOP–16)
Operational Amplifier for Direct Tuning Voltage Output (30 V)
Four Integrated PNP Band Buffers can drive up to 40 mA
(VCC1 to 14.4 V)
Output Options for the Reference Frequency and the
Programmable Divider
Bus Protocol for 18 or 19 Bit Transmission
PIN CONNECTIONS
Extra 34–Bit Protocol for Test and Further Features
High Sensitivity Preamplifier
Lower Power Consumption, 200 mW Typical
DA
1
16
EN
Improved Prescaler with Higher Margins for Sensitivity and
Temperature Range
Lock Detector with Push–Pull Output
CL
2
15
Lock
XTAL
3
14
VCC3 12 V
Amp In
4
13
B3
VTUN
5
12
B2
VCC2 33 V
6
11
B1
VCC1 5.0 V
7
10
B0
HF In
8
9
Gnd
Space–Saving TSSOP Package
ESD Protected to MIL–STD–883C, Method 3015.7 (1.5 kΩ,100 pF)
MOSAIC is a trademark of Motorola, Inc.
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
TA = – 20° to + 80°C
TSSOP–16
MC44827DTB
MC44827BDTB
(Top View)
 Motorola, Inc. 1998
MOTOROLA ANALOG IC DEVICE DATA
Rev 1
1
MC44827/27B
Figure 1. Representative Block Diagram
VTUN
VCC1
5.0 V 7
13
12
VCC3 12 V
10
14
11
5
VCC2 33 V
6
12 V
60 k (1)
Fout
B3
Test
Logic
Fref
B2 B1
9
Operational
Amplifier
Latches
T4
Gnd
T0 … T2
Phase
Comp
T5
DTB2
Latches
Fout
POR
16
CL
3–Wire Bus
Receiver
DA
2
15
Lock
P–On
Reset
EN
1
Amp In
Vref
Buffers
DTB1
4
B0
Data
RL
CL
DTF
4
Fref
512/1024
B = 1024 Only
6
Shift Register
15 Bit
Ref
Divider
15
Latches A
3
Osc
XTAL
Latches B
TDI
Preamp 1
÷8
Prescaler
8
HF In
Program Divider
15 Bit
Latch Control
Fout
DTS, EN
This device contains 3,204 active transistors.
NOTE:
1. This part may be used with an external pull–up resistor of 20 kΩ to remain compatible with MC44817/17B
designed tuners. Pin 6 is left open. The internal pull–up can also be used with an external resistor in parallel.
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Power Supply Voltage (VCC1)
Pin
Value
Unit
V
7
6.0
Band Buffer “Off” Voltage
10–13
14.4
V
Band Buffer “On” Current
10–13
50
mA
Band Buffer Pin Shorted to Ground or VCC3 (Short Circuit Duration) (Note 1)
10–13
Continuous
–
6
40
V
Operational Amplifier Pin Shorted to Ground or VCC2 (Short Circuit Duration)
5
Continuous
–
Power Supply Voltage (VCC3)
14
14.4
V
Storage Temperature
–
– 65 to +150
°C
Operational Amplifier Power Supply Voltage (VCC2)
–
– 20 to +80
°C
10–13
10
s
Operational Amplifier Output Voltage
5
RF Input Level (80 MHz to 1.3 GHz)
8
VCC2
1.5
Vrms
Operating Temperature Range
Band Buffer Operation (Note 2) at 50 mA each Buffer All Buffers “On” Simultaneously
V
NOTES: 1. At VCC3 = VCC1 to 14.4 V and TA = – 20° to + 80°C one buffer “On” only.
2. At VCC3 = VCC1 to 14.4 V and TA = – 20° to + 80°C.
3. ESD data available upon request.
2
MOTOROLA ANALOG IC DEVICE DATA
MC44827/27B
ELECTRICAL CHARACTERISTICS (Parameter Type: A–100% Tested, B–100% Correlation Tested, C–Characterized on Samples,
D–Design Parameter. VCC1 = 5.0 V; VCC2 = 33 V; VCC3 = 12 V; TA = 25°C, unless otherwise noted.)
Characteristic
Pin
Min
Typ
Max
Unit
Type
VCC1 Supply Voltage Range
7
4.5
5.0
5.5
V
A
VCC2 Supply Voltage Range
6
25
32
37
V
A
VCC3 Supply Voltage Range
14
VCC1
12
14.4
V
A
VCC1 Supply Current (VCC1 = 5.0 V; VCC3 = 12 V) One Buffer “On”
7
–
23
30
mA
A
VCC2 Supply Current (Output Open) VTUN = 15 V
6
–
0.3
1.0
mA
A
VCC3 Supply Current
All Buffers “Off”
One Buffer “On” when Open
One Buffer “On” at 40 mA
14
mA
A
–
–
–
0.15
6.5
46.5
0.3
8.0
50
Band Buffer Leakage Current when “Off” at 12 V
10–13
–
0.01
1.0
µA
A
Band Buffer Saturation Voltage when “On” at 30 mA
10–13
–
0.15
0.3
V
B
Band Buffer Saturation Voltage when “On” at 40 mA
10–13
–
0.2
0.5
V
A
Data/Clock/Enable Current at 0 V
1, 2, 16
–10
–
0
µA
A
Data/Clock/Enable Current at 5.0 V
1, 2, 16
0
–
1.0
µA
A
Data/Clock/Enable Input Voltage Low
1, 2, 16
–
–
1.5
V
A
Data/Clock/Enable Input Voltage High
1, 2, 16
3.0
–
–
V
A
Clock Frequency Range
2
–
–
100
kHz
D
Oscillator Frequency Range
3
3.15
3.2
4.05
MHz
D
Operational Amplifier Internal Reference Voltage
–
1.8
2.75
3.5
V
A
Operational Amplifier Input Current
4
–15
0
15
nA
A
DC Open Loop Gain
–
100
250
–
–
B
Gain Bandwidth Product (CL = 1.0 nF)
–
0.3
–
–
MHz
C
Vout Low, Sinking 50 µA (Note 1)
5
–
80
200
mV
A
Vout High, Sourcing 3.0 µA, VCC2 – Vout
5
–
0.2
0.5
V
B
Phase Comparator 3–State Current
4
–15
0
15
nA
A
Charge Pump High Current of Phase Comparator
4
30
50
85
µA
A
Charge Pump Low Current of Phase Comparator
4
10
15
30
µA
A
NOTE:
1. Using the internal 60 kΩ pull–up resistor only.
Figure 3. Typical Prescaler Input Sensitivity
Figure 2. HF (Prescaler Input) Sensitivity Test Circuit
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
40
Bus
VCC3
16
VCC1
1
2
20
RF Level (dBm)
Bus Controller
14
MC44827/27B
7
HF
8
Gnd
9
B0
10
B1
11
B2
12
B3
13
HF Generator
0
Guaranteed Operating Area
–20
–40
1.0 nF
HF Out Gnd
3.9 k
50 Ω Cable
3.9 k
3.9 k
50 Ω
3.9 k
Counter
–60
In
0
200
400
600
800
1000
1200
1400
RF In (MHz)
NOTES: 1. Device is in test mode. B2, B3 are “On” and B0, B1 are “Off”.
2. Sensitivity is level of HF generator on 50 Ω load.
MOTOROLA ANALOG IC DEVICE DATA
3
MC44827/27B
HF INPUT SENSITIVITY AND OVERLOAD CHARACTERISTICS (VCC1 = 5.0 V, TA = 25°C.) (See Figure 2.)
Frequency Range
Pin
Min
Typ
Max
Unit
Type
8
–
1.6
–
V
A
80–150 MHz
8
10
–
315
mVrms
C
150–600 MHz
8
5.0
–
315
mVrms
C
600–950 MHz
8
10
–
315
mVrms
C
950–1300 MHz
8
50
–
315
mVrms
C
DC Bias
Figure 4. Pin Circuit Schematic
VCC1
DA 1
Data input
(3–wire bus)
96 k
96 k
132 k
500
1/2 VCC1
20 V
VCC1
96 k
132 k
500
1/2 VCC1
20 V
96 k
VCC1
132 k
500
CL 2
Clock input (supplied
by a microprocessor
via 3–wire bus)
XTAL 3
Crystal oscillator
(3.2 MHz or 4.0 MHz)
VCC1
96 k
2.0 k
1/2 VCC1
20 V
15 Lock
Lock detector output
96 k
5.0 k
20 V
100 k
20 V
100
14 VCC3
Positive supply for integrated
band buffers (12 V)
5.0 V
20 V
13 B3
“On”/“Off”
AMP In 4
Negative input of
operation amplifier and
phase comparator output
16 EN
Enable input
(3–wire bus)
2.0 k
10 k
20 V
20 V
20 V
“On”/“Off”
12 B2
60 k
VTUN 5
Operational amplifier
output which provides
the tuning voltage
Band buffer outputs
can drive up to 30 mA
(40 mA at 0° to 80°C)
100
20 V
20 V
20 V
“On”/“Off”
VCC2 6
Operational amplifier
positive supply (33 V)
20 V
VCC1 7
Positive supply of
the circuit (5.0 V)
5.0 V
20 V
5.0 V
“On”/“Off”
20 V
10 B0
18 k
2.0 k
HF In 8
Input to
prescaler
11 B1
1.2 … 1.8 V
2.0 k
9 Gnd
Circuit Ground
4
MOTOROLA ANALOG IC DEVICE DATA
MC44827/27B
PIN FUNCTION DESCRIPTION
Pin
Symbol
Description
1
DA
3–wire bus data input
2
CL
3–wire bus clock input
3
XTAL
4
Amp In
Crystal oscillator (3.2 MHz or 4 MHz)
Negative operational amplifier input and phase comparator output
5
VTUN
Operational amplifier output which provides the tuning voltage
6
VCC2
Operational amplifier positive supply (33 V)
7
VCC1
Positive supply of the circuit (5 V)
8
HF In
Asymmetrical HF input
Ground
9
Gnd
10,11,12,13
B0 to B3
14
VCC3
Positive supply for integrated band buffers (12 V)
15
Lock
Lock detector output
16
EN
PNP Band buffer outputs
3–wire bus enable input
Data Format and Bus Receiver
The circuit is controlled by a 3–wire bus via Data (DA),
Clock (CL), and Enable (EN) inputs. The Data and Clock
inputs may be shared with other inputs on the I2C–Bus while
the Enable is a separate signal. The circuit is compatible with
18 and 19 bit data transmission and also has a mode for
34 bit transmission for test and additional features.
The 3–wire bus receiver receives data for the internal shift
register after the positive going edge of the EN–signal. The
data is transmitted to the band buffers on the negative going
edge of the clock pulse 4 (signal DTB1).
18 and 19 Bit Data Transmission
The programmable divider may receive a division ratio
coded by a 14 bit (18 bit transmission) or 15 bit (19 bit
transmission). The data is transmitted to the programmable
divider (latches A) on the negative going edge of clock pulse
19 or on the negative edge of the EN–signal if EN goes down
after the 18th clock pulse (signal DTF). If the programmable
divider receives a 14 bit byte, its MSB (bit N14) is internally
reset. The reset pulse is generated only if EN goes negative
after the 18th clock pulse (signal RL).
34 Bit Data Transmission
(For Test and Additional Features)
In the test mode, the programmable divider receives a 15
bit byte and the data is transferred to latches A on the
negative edge of clock pulse 19 (signal DTF). The
information for test is received on clock pulses 20 to 26 and
transmitted to the latches on the negative edge of pulse 34
(signal DTB2). These latches have a power–on reset. The
power–on reset sets the programmable divider to a counting
ratio of 256 or higher and resets the corresponding latches to
the test bits T0 to T6 (signal POR). The bus receiver is not
disturbed if the data format is wrong. Unused bits are
ignored. If for example the Enable signal goes low after clock
pulse 9, bits one to four are accepted as valid buffer
information and the other bits are ignored. If more than 34
bits are received, bit 35 and the following are ignored.
Figure 5. Bus Timing Diagram
Standard Bus Protocol 18 or 19 Bit
Data
1
4
5
18 19
Clock
Buffers
Counting Ratio
Enable
1
B3
4
Bus Protocol for Test and Features
19 20
5
B2 B1 B0 N14 N13 N12 N11 N10 N9 N8 N7
Buffers
N6 N5 N4 N3 N2
Counting Ratio
MOTOROLA ANALOG IC DEVICE DATA
N1 N0 T6 T5
26 27
T4
T3 T2
T1
Test & Features
T0 X7
33 34
X6 X5 X4
X3
X2 X1
X0
Not Used
5
MC44827/27B
Definition of Permissible Bus Protocols
1. Bus Protocol for 18 Bit
B3 B2 B1 B0 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3
N2 N1 N0
Max Counting Ratio 16363
N14 is Reset Internally
2. Bus Protocol for 19 Bit
B3 B2 B1 B0 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4
N3 N2 N1 N0
Max Counting Ratio 32767
B0 to B3: Control of Band Buffers
N0 to N14: Programmable Divider Counting Ratio
N14 = MSB; N0 = LSB
Minimum Counting Ratio Always 17
B3 = First Shifted Bit
N0 = Last Shifted Bit
3. Bus Protocol for Test and Further Features (34 Bit)
B3 B2 B1 B0 N14…N0 Y6 T5 T4 Y3 T2 T1 T0 X7
X6…X1 X0
T0 to T2: Control the Phase Comparator (Note 1)
T4: Switches Test Signals to the Buffer Outputs
T5: Division Ratio of the Reference Divider
B Version T5 = “X”
– X0 to X7: Are Random
– Y3 and Y6: Are Not Used
B3 = First Shifted Bit
X0 = Last Shifted Bit
Definition of the Bits for Test and Features
Bit T0: Defines the Charge Pump Current of the
Bit T0: Phase Comparator
Pump Current 50 µA Typical
Pump Current 15 µA Typical
T0 = 0
T0 = 1
Bits T1 and T2: Define the Digital Function of the Phase
Bits T1 and T2: Comparator
T2
T1
State
0
0
1
Normal Operation
Output Function of Phase Comparator
0
1
2
High Impedance (3–State)
1
0
3
Upper Source “On”, Lower Source “Off”
1
1
4
Lower Source “On”, Upper Source “Off”
NOTE: 1. The phase comparator pulls high if the input frequency is too
high and it pulls low when the input frequency is too low.
(Inversion by Operational Amplifier) The phase comparator
generates a fixed duration offset pulse for each comparison
pulse. This guarantees operation in the linear region.
The offset pulse is a positive current pulse (upper source).
Bit T4: Switches the Internal Frequencies Fref and
Bit T4: FBY2 to the Buffer Outputs (B2, B3)
T4 = 0
T4 = 1
NOTE:
6
Normal Operation
Fref Switched to Buffer Output B2
FBY2 Switched to Buffer Output B3
Bits B2 and B3 have to be one in this case.
Fref is the reference frequency.
FBY2 is the output frequency of the programmable divider,
divided by two.
Figure 6. Equivalent Circuit of the Integrated
Band Buffers
VCC3 12 V
20 …25 V
Protection
Gnd
Saturation Voltage
0.15 V Typical
0.3 V Max
IB
ISUB
“On”/“Off”
NOTES: IB + ISUB = 5.5 mA Typical
Out
B0…B3
30 mA (40 mA
at 0 to 80°C)
IB = Base Current
ISUB = Substrate Current of PNP
Bit T5: Defines the Division Ratio of the Reference
Bit T5: Divider
T5 = 0
T5 = 1
Division Ratio 512
Division Ratio 1024
NOTE: The division ratio of the reference divider can only be
programmed in the 34 bit bus protocol.
In the standard bus protocol the division ratio is 512.
(The power–up reset POR sets the division ratio to 512).
On “B–version”, T5 = “X”. Division ratio 1024 is fixed.
OPERATING DESCRIPTION
Introduction
A representative block diagram and typical system
application are shown in Figures 1 and 8. A discussion of the
features and function of each of the internal blocks is given.
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider; this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
N = 16384 x N14 + 8132 x N13 + … + 4 x N2 + 2 x N1 + N0
Maximum Ratio 32767
(16363 in case of 18 bit bus protocol)
Minimum Ratio 17
N0 … N14 are the different bits for frequency information.
At power–on the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N = 256 or
higher.
The Prescaler
The divide by 8 prescaler has a preamplifier which
guarantees high input sensitivity.
The Phase Comparator
The phase comparator is both phase and frequency
sensitive and has very low output leakage current in the high
impedance state.
Lock Detector
The lock–detector output is low in lock. The output goes
immediately high when an unlock condition is detected. The
output goes low again when the loop is in lock during a
complete period of the reference frequency.
MOTOROLA ANALOG IC DEVICE DATA
MC44827/27B
Figure 7. Equivalent Circuit of the Lock Output
The Oscillator
The oscillator uses a 3.2 or a 4.0 MHz crystal tied to ground
in series with a capacitor. The crystal operates in the series
resonance mode.
The voltage at Pin 3 has low amplitude and low harmonic
distortion.
VCC1 5.0 V
200 µA Typical
2.0 k
Lock
100 k
“On”/“Off”
Power Dissipation
The typical power dissipation of the circuit is about
200 mW (VTUN = 15 V with internal pull–up of 60 kΩ, one
buffer “On” at 30 mA). It is calculated with the following
formula:
25 V Protection
5.0 k
“Off”/“On”
PD
The Operational Amplifier
The operational amplifier is designed for very low noise,
low input bias current and high power supply rejection. The
positive input is biased internally. The operational amplifier
needs 28.5 V supply (VCC2) as minimum voltage for a
guaranteed maximum tuning voltage of 28 V.
Figure 8 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
)
+
ǒ
V
ǒ
V
x I
CC1
CC3
x I
Ǔ)
Ǔ)ǒ
V
CC1
CC3
V
– V
TUN x V
CC2
CC2
60 kΩ
sat(buffer)
x I
out(buffer)
Ǔ
) 32 60– 15 x 32 ) (12 x 6.5)
) (0.15 x 30) + 206.5
Example: (5 x 23)
Figure 8. Typical Tuner Application
IF
External Switching
UHF
VHF
B III
13
5.0 V 7
Antenna
Filter
12
B3
B2
11
10
B1
B0
14 12 V
VCC3
Mixer
B. P. Filter
MC44827/27B
1.0 nF
÷8
Pres
8
Program
Divider
Fosc
Oscillator
Gnd
9
Vref
6
5
4
VTUN
AGC
NOTE: 1. 330 pF minimum is required for stability.
MOTOROLA ANALOG IC DEVICE DATA
2
1
16
Bus
Rec
Osc & 3
Ref Div
CL
DA
EN
12 pF
3.2/4.0 MHz
Phase
Comp
15
Lock
120 k
18 nF
330 p
(Note 1)
33 V
8.2 nF
7
MC44827/27B
OUTLINE DIMENSIONS
DTB SUFFIX
PLASTIC PACKAGE
CASE 948F–01
(TSSOP–16)
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
–V–
M
N
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4 DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7 DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
H
D
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
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or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447
JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141,
4–32–1 Nishi–Gotanda, Shagawa–ku, Tokyo, Japan. 03–5487–8488
Customer Focus Center: 1–800–521–6274
Mfax: [email protected] – TOUCHTONE 1–602–244–6609
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
Motorola Fax Back System
– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
– http://sps.motorola.com/mfax/
HOME PAGE: http://motorola.com/sps/
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