Intersil ISL70003ASEHEV2Z Radiation and see tolerant 3v to 13.2v, 9a buck regulator Datasheet

DATASHEET
Radiation and SEE Tolerant 3V to 13.2V, 9A Buck
Regulator
ISL70003ASEH
Features
The ISL70003ASEH is an improved version of the ISL70003SEH
regulator with both tighter load regulation (<0.3% typical) and a
higher output current rating of 9A. Operating over an input voltage
range of 3.0V to 13.2V, with integrated low rDS(ON) MOSFETs
makes this monolithic solution highly efficient. Also, a tightly
regulated output voltage is possible, which is externally
adjustable from 0.6V to ~90% of the input voltage. Continuous
output load current capability is 9A for TJ ≤+125°C and 6A for
TJ ≤+150°C.
• Acceptance tested to 50krad(Si) (LDR) wafer-by-wafer
The ISL70003ASEH uses voltage mode control architecture
with feed-forward and switches at a selectable frequency of
500kHz or 300kHz. Loop compensation is externally
adjustable to allow for an optimum balance between stability
and output dynamic performance.
The device features two logic-level disable inputs that can be
used to inhibit pulses on the phase (LXx) pins in order to
maximize efficiency based on the load current. The
ISL70003ASEH also supports DDR applications and contains a
buffer amplifier for generating the VREF voltage.
High integration, best in class radiation performance and a
feature filled design make the ISL70003ASEH an ideal choice
to power many of todays small form factor applications.
All existing ISL70003SEH supporting collateral is relevant to
the ISL70003ASEH and can be used as such.
Applications
• ±1% reference voltage over line, temperature and radiation
• Integrated MOSFETs 31mΩPFET/21mΩ NFET
- 95% peak efficiency
• Externally adjustable loop compensation
• Supports DDR applications (VTT tracks VDDQ/2)
- Buffer amplifier for generating VREF voltage
- 3A current sinking capability
• Grounded lid eliminates charge build up
• IMON pin for output current monitoring
• Adjustable analog soft-start
• Diode emulation for increased efficiency at light loads
• 500kHz or 300kHz operating frequency
• Monotonic start-up into prebiased load
• Full military temperature range operation
- TA = -55°C to +125°C
- TJ = -55°C to +150°C
• Radiation tolerance
- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)*
* Limit established by characterization.
• SEE hardness
- SEB and SEL LETTH . . . . . . . . . . . . . . . . 86.4MeV•cm2/mg
- SET at LET 86.4MeV•cm2/mg . . . . . . . . . . . < ±3% ΔVOUT
- SEFI LETTH . . . . . . . . . . . . . . . . . . . . . . . . . 60MeV•cm2/mg
• Electrically screened to DLA SMD 5962-14203
• FPGA, CPLD, DSP, CPU core and I/O supply voltages
• DDR memory supply voltages
• Low-voltage, high-density distributed power systems
Related Literature
0.3
• AN1897, “ISL70003SEHEV1Z Evaluation Board”
• TR009, “Single Event Effects (SEE) Testing of the
ISL70003ASEH POL BUCK Regulator”
• AN1924, “Total Dose Testing of the ISL70003SEH Radiation
Hardened Point Of Load Regulator”
• TB502, “High Power ISL70003ASEH High Temperature
Operating Life (HTOL) and Overcurrent Abuse“
• UG046, “ISL70003ASEHEV2Z Evaluation Board User Guide”
LOAD REGULATION (%)
• AN1915, “ISL70003SEH iSim:PE Model”
0.2
-55°C
+25°C
0.1
+125°C
0.0
-0.1
+85°C
-0.2
-0.3
0
1
2
3
4
5
6
LOAD CURRENT (A)
7
8
9
FIGURE 1. TYPICAL LOAD REGULATION, VIN = 12V, VOUT = 3.3V,
fSW = 500kHz
August 5, 2015
FN8746.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL70003ASEH
12V INTERMEDIATE BUS
ISL70003ASEH
5V BUS
ISL70003ASEH
1.5V CORE
ISL75051SEH
1.8V AUX
ISL75051SEH
3.3V I/O
FIGURE 2. POWER DISTRIBUTION SOLUTION FOR RAD HARD LOW POWER FPGA’s
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ISL70003ASEH
Table of Contents
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
22
22
23
Fault Monitoring and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage and Overvoltage Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
23
23
24
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Voltage Feed-forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Switching Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Setting the Overcurrent Protection Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disabling the Power Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
IMON Current Sense Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DDR Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DDR Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operational Envelope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
High Current Protection Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Derating Current Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
General Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feedback Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modulator Break Frequency Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compensation Break Frequency Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
28
28
29
29
30
30
PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Plane Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Component Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LX Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead Strain Relief . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Heatsink Mounting Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Heatsink Electrical Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Heatsink Mounting Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
31
31
31
31
31
31
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Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Weight of Packaged Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Lid Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Die Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Interface Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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VREF_OUTS
VREFD
VREFA
EN
Functional Block Diagram
POR AND ON/OFF
POR_VIN
AVDD
LINEAR
REGULATORS
CONTROL
DVDD
SEL1
SEL2
RAMP
RT/CT
IMON
CURRENT
SENSE
PVINx
SOFTSTART
SS_CAP
NI
COMP
EA
FB
PWM
CONTROL
LOGIC
GATE
DRIVE
LXx
VERR
SGND
VOUT
MONITOR
PGOOD
PGNDx
PWM
REFERENCE
0.6V
REF
OCSETA
OVERCURRENT
ADJUST
OCSETB
BUFINBUFIN+
BUFOUT
DDR VREF
BUFFER AMP
BUF
DGND
PGNDx
SYNC
FSEL
AGND
DE
FIGURE 3. BLOCK DIAGRAM
Ordering Information
ORDERING SMD
NUMBER (Note 1)
PART NUMBER
(Note 2)
TEMPERATURE
RANGE (°C)
PACKAGE
(RoHS Compliant)
5962R1420302VYC
ISL70003ASEHVFE
-55 to +125
64 Ld CQFP with Heatsink
5962R1420302V9A
ISL70003ASEHVX
-55 to +125
Die
ISL70003ASEHFE/PROTO
ISL70003ASEHFE/PROTO
-55 to +125
64 Ld CQFP with Heatsink
ISL70003ASEHX/SAMPLE
ISL70003ASEHX/SAMPLE
-55 to +125
Die
ISL70003ASEHEV1Z
ISL70003ASEHEV1Z Full Featured Evaluation Board
ISL70003ASEHEV2Z
ISL70003ASEHEV2Z Small Form Factor Evaluation Board
PACKAGE
DRAWING
R64.C
R64.C
NOTES:
1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information must be used when ordering.
2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
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ISL70003ASEH
Pin Configuration
PVIN3
NC/HS*
IMON
SGND
PVIN2
LX2
PGND2
PGND1
LX1
PVIN1
OCSETA
OCSETB
BUFIN+
FOR PIN 1 LOCATION
BUFIN-
REF
BOTTOM SIDE DETAIL
BUFOUT
ISL70003ASEH
(64 LD CQFP)
TOP VIEW
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
FB
2
47
PGND3
VERR
3
46
PGND4
POR_VIN
4
45
LX4
VREFA
5
44
PVIN4
AVDD
6
AGND
7
DGND
8
VREF_OUTS
9
PRODUCT BRAND
NAME AREA
NI
1 (NI)
(Note 3)
LX3
43
PVIN5
42
LX5
41
PGND5
40
PGND6
39
LX6
38
PVIN6
DVDD
10
VREFD
11
ENABLE
12
37
PVIN7
RT/CT
13
36
LX7
FSEL
14
35
PGND7
SYNC
15
34
PGND8
LX8
PVIN8
DE
SEL2
SEL1
PVIN9
LX9
PGND9
PGND10
LX10
PVIN10
PGOOD
GND
GND
GND
GND
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND
SS_CAP
HEATSINK OUTLINE *
NOTE:
3. The ESD triangular mark is indicative of pin #1 location. It is part of the device marking and is
placed on the lid in the quadrant where pin #1 is located.
* Indicates heatsink package R64.C
Pin Descriptions
PIN NUMBER
PIN NAME
ESD CIRCUIT
1
NI
1
This pin is the noninverting input to the internal error amplifier. Connect this pin to the REF pin for
typical applications or the BUFOUT pin for DDR memory power applications.
2
FB
1
This pin is the inverting input to the internal error amplifier. An external type III compensation network
should be connected between this pin and the VERR pin. The connection between the FB resistor divider
and the output inductor should be a Kelvin connection to optimize performance.
3
VERR
1
This pin is the output of the internal error amplifier. An external compensation network should be
connected between this pin and the FB pin.
4
POR_VIN
1
This pin is the power-on reset input to the IC. This is a comparator-type input with a rising threshold of
0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND
with a 10nF ceramic capacitor to mitigate SEE.
5
VREFA
3
This pin is the output of the internal linear regulator and the bias supply input to the internal analog
control circuitry. Locally filter this pin to AGND using a 0.47µF ceramic capacitor as close as possible to
the IC.
6
AVDD
5
This pin provides the supply for the internal linear regulator of the ISL70003ASEH. The supply to AVDD
should be locally bypassed using a ceramic capacitor. Tie AVDD to the PVINx pins.
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6
DESCRIPTION
FN8746.0
August 5, 2015
ISL70003ASEH
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
ESD CIRCUIT
DESCRIPTION
7
AGND
1, 3
This pin is the analog ground associated with the internal analog control circuitry. Connect this pin
directly to the PCB ground plane.
8
DGND
2, 4
This pin is the ground associated with the internal digital control circuitry. Connect this pin directly to
the PCB ground plane.
9
VREF_OUTS
4
This pin is the output of the internal linear regulator and the supply input to the internal reference
circuit. Locally filter this pin to AGND using a 0.47µF ceramic capacitor as close as possible to the IC.
10
DVDD
6
This pin provides the supply for the internal linear regulator of the ISL70003ASEH. The supply to DVDD
should be locally bypassed using a ceramic capacitor. Tie DVDD to the PVINx pin.
11
VREFD
4
This pin is the output of the internal linear regulator and the bias supply input to the internal digital
control circuitry. Locally filter this pin to DGND using a 0.47µF ceramic capacitor as close as possible
to the IC.
12
ENABLE
6
This pin is a logic-level enable input. Pulling this pin low powers down the device by placing it into a very
low power sleep mode.
13
RT/CT
6
A resistor to VIN and a capacitor to GND provide feed-forward to keep a constant modulator gain of 4.8
as VIN varies.
14
FSEL
2
This pin is the oscillator frequency select input. Tie this pin to 5V to select a 300kHz nominal oscillator
frequency. Tie this pin to the PCB ground plane to select a 500kHz nominal oscillator frequency.
15
SYNC
2
This pin is the frequency synchronization input to the IC. This pin should be tied to GND to free-run from
the internal oscillator or connected to an external clock for external frequency synchronization.
16
SS_CAP
2
This pin is the soft-start input. Connect a ceramic capacitor from this pin to the PCB ground plane to set
the soft-start output ramp time in accordance with Equation 1:
t SS = C SS  V REF  I SS
(EQ. 1)
Where:
tSS = soft-start output ramp time
CSS = soft-start capacitance
VREF = reference voltage (0.6V typical)
ISS = soft-start charging current (23µA typical)
Soft-start time is adjustable from approximately 2ms to 200ms. The range of the soft-start capacitor
should be 82nF to 8.2µF, inclusive.
17, 18, 19, 20, 21
GND
2
Connect these pin to the PCB ground plane.
22
PGOOD
6
This pin is the power-good output. This pin is an open-drain logic output that is pulled to DGND when
the output voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage
from 0V to 13.2V, independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is
recommended. Bypass this pin to the PCB ground plane with a 10nF ceramic capacitor to mitigate SEE.
23, 28, 32, 37,
38, 43, 44, 49,
53, 58
PVINx
7
These pins are the power supply inputs to the corresponding internal power blocks. These pins must be
connected to a common power supply rail, which should fall in the range of 3V to 13.2V. Bypass these
pins directly to PGNDx with ceramic capacitors located as close as possible to the IC. When sinking
current or at a no load condition, the inductor valley current will be negative. During any time when the
inductor valley current is negative and the ISL70003A is exposed to a heavy ion environment, the abs
max PVIN voltage must be ≤13.7V.
29
SEL1
2
This pin is a logic-level disable (high) input working in conjunction with SEL2. These pins form a 2-bit
logic input that set the number of active power blocks. This allows the ISL70003ASEH current
capability to be tailored to the load current level the application requires and achieve the highest
possible efficiency.
30
SEL2
2
This pin is a logic-level disable input. Pulling this pin high inhibits pulses on the LXx outputs. See
description of Pin 29, SEL1, for more information.
31
DE
2
The DE pin enables or disables Diode Emulation. When it is HIGH, diode emulation is allowed.
Otherwise, continuous conduction mode is forced.
24, 27, 33, 36,
39, 42, 45, 48,
54, 57
LXx
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These pins are the switch node connections to the internal power blocks and should be connected to
the output filter inductor. Internally, these pins are connected to the synchronous MOSFET power
switches.
7
FN8746.0
August 5, 2015
ISL70003ASEH
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
ESD CIRCUIT
50
HS
N/A
51
IMON
1
IMON is a current source output that is proportional to the sensed current through the regulator. If not
used it is recommended to tie IMON to VREFA. It is also acceptable to tie IMON to GND through a
resistor.
52
SGND
1
This pin is connected to an internal metal trace that serves as a noise shield. Connect this pin to the
PCB ground plane.
25, 26, 34, 35,
40, 41, 46, 47,
55, 56
PGNDx
7
These pins are the power grounds associated with the corresponding internal power blocks. Connect
these pins directly to the PCB ground plane. These pins should also connect to the negative terminals
of the input and output capacitors. The package lid is internally connected to PGNDx.
59
OCSETA
3
This pin is the redundant output overcurrent set input. Connect a resistor from this pin to the PCB
ground plane to set the output overcurrent threshold.
60
OCSETB
3
This pin is the primary output overcurrent set input. Connect a resistor from this pin to the PCB ground
plane to set the output overcurrent threshold.
61
BUFIN+
1
This pin is the input to the internal unity gain buffer amplifier. For DDR memory power applications,
connect the VTT voltage to this pin.
62
BUFIN-
1
This pin is the inverting input to the buffer amplifier. For DDR memory power applications, connect
BUFOUT to this pin. Bypass this pin to the PCB ground plane with a 0.1µF ceramic capacitor.
63
BUFOUT
3
This pin is the output of the buffer amplifier. In DDR power applications, connect this pin to the
reference input of the DDR memory. The buffer needs a minimum of 1.0µF load capacitor for stability.
64
REF
1
This pin is the output of the internal reference voltage. Bypass this pin to the PCB ground plane with a
220nF ceramic capacitor located as close as possible to the IC. The bypass capacitor is needed to
mitigate SEE.
VREFA
On the R64.C package (heatsink option) this pin is electrically connected to the heatsink on the
underside of the package. Connect this pin and/or the heatsink to a thermal plane.
VREFD
PIN #
PIN #
GNDA
GNDD
CIRCUIT 2
CIRCUIT 1
7V
CLAMP
GNDA
CIRCUIT 3
PIN #
7V
CLAMP
GNDD
CIRCUIT 4
PGNDx
CIRCUIT 7
8
15V
CLAMP
GNDA
CIRCUIT 5
VDDD
15V
CLAMP
15V
CLAMP
GNDD
VDDA
GNDA
PVINx
15V
CLAMP
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PIN #
PGND
PIN #
CIRCUIT 6
DESCRIPTION
GNDD
CIRCUIT 8
GNDD
CIRCUIT 9
GNDA
CIRCUIT 10
FN8746.0
August 5, 2015
ISL70003ASEH
Typical Application Schematics
VIN = 12V
+
100k
5 x 1µF
4x100µF
P
22k
51k
P
51
D
D
15
16
357
1nF
SYNC
PGOOD
P
PORVIN
P
10nF
P
22
24
27
33
36
39
42
45
48
54
57
3.3µH
VOUT = 3.3V
+
10
P
1nF
150µF
x3
1µF
P
P
P
OCA 59
6.8nF
4.02k
D
2 FB
3
VERR
1
NI
64
REF
OCB
0.22µF
17
18
19
20
21
A
P
D
AGND
DGND
S
PGND10
PGND9
PGND8
PGND7
PGND6
PGND5
PGND4
PGND3
PGND2
PGND1
4.02k
SGND
D
2.7nF
60
A
A
A
6.8nF
A
8
52
7
528
25
26
34
35
40
41
46
47
55
56
51.1k
FSEL
SEL1
SEL2
DE
NC
12pF
3k
10nF
4
23
28
32
37
38
43
44
49
53
58
6
10
12
EN
SS
TDI
PGND
TPGM
PGND
PGND
TDO
TSTRIM
PGND
TCLK
PGND
A
ISL70003ASEH
ISL70003SEH
0.1µF
25k
5.49k
LX10
LX9
LX8
LX7
LX6
LX5
LX4
LX3
LX2
LX1
5
VREFA
9
11 VREFOUTS
VREFD
14
29
30
31
50
A
PGOOD
IMON
10k
0.47µF
0.47µF
7.15k
PVIN10
PVIN9
PVIN8
PVIN7
PVIN6
PVIN5
PVIN4
PVIN3
PVIN2
PVIN1
AVDD
DVDD
VIMON
0.47µF
BUFIN+
BUFINBUFOUT
13
RT/CT
D
A
61
62
63
A
370pF
A
P
FIGURE 4. ISL70003ASEH SINGLE UNIT OPERATION
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9
FN8746.0
August 5, 2015
ISL70003ASEH
Typical Application Schematics (Continued)
VIN = 5V
25k
5 x 1µF
4x100µF
22k
P
A
51
0.47µF
D
D
15
16
715
25k
1nF
68pF
A
SYNC
4
23
28
32
37
38
43
44
49
53
58
6
10
12
SS
1.5µH
VDDQ = 2.5V
+
10
P
1nF
31.2k
P
P
6.8nF
4.02k
2
3
1
64
1µF
3 x 150µF
OCA 59
0.1µF
FB
VERR
NI
REF
OCB
4nF
0.33µF
17
18
19
20
21
A
60
A
A
4.02k
PGND
TDI
PGND
TPGM
PGND
TDO
PGND
TSTRIM
PGND
TCLK
7.87k
D
ISL70003ASEH
ISL70003SEH
24
27
33
36
39
42
45
48
54
57
D
SGND
A
AGND
S
DGND
PGND10
PGND9
PGND8
PGND7
PGND6
PGND5
PGND4
PGND3
PGND2
PGND1
A
10nF
P
A
D
P
6.8nF
A
A
528
7
8
52
25
26
34
35
40
41
46
47
55
56
0.47µF
LX10
LX9
LX8
LX7
LX6
LX5
LX4
LX3
LX2
LX1
5
VREFA
9
11 VREFOUTS
VREFD
FSEL
SEL1
SEL2
DE
NC
0.47µF
PGOOD
IMON
PGOOD
P
22
10k
A
3k
10nF
P
PORVIN
VIMON
4k
PVIN10
PVIN9
PVIN8
PVIN7
PVIN6
PVIN5
PVIN4
PVIN3
PVIN2
PVIN1
AVDD
DVDD
D
EN
RT/CT 13
370pF
14
29
30
31
50
P
BUFIN+ 61
62
BUFIN63
BUFOUT
+
P
VREF = 1.25V
1µF
A
+
25k
5 x 1µF
4x100µF
P
22k
51
0.22µF
A
0.47µF
A
IMON
D
D
15
16
400
25k
LX10
LX9
LX8
LX7
LX6
LX5
LX4
LX3
LX2
LX1
5
9 VREFA
11 VREFOUTS
VREFD
ISL70003ASEH
ISL70003SEH
SYNC
SS
2.2µH
VTT = 1.25V
OCB
3 x 150µF
1µF
P
6.8nF
60
A
A
8.2k
SGND
D
A
AGND
DGND
S
PGND10
PGND9
PGND8
PGND7
PGND6
PGND5
PGND4
PGND3
PGND2
PGND1
A
6.8nF
A
528
7
528
25
26
34
35
40
41
46
47
55
56
FSEL
SEL1
SEL2
DE
NC
15nF
P
1nF
NI
PGND
TDI
PGND
TPGM
TDO
PGND
TSTRIM
PGND
PGND
TCLK
1
14
29
30
31
50
22.9k
25k
+
10
8.2k
17
18
19
20
21
A
24
27
33
36
39
42
45
48
54
57
OCA 59
0.1µF
82pF
10nF
P
22
P
2 FB
3
VERR
22.9k
PGOOD
P
P
A
1.6nF
3k
10nF
4
23
28
32
37
38
43
44
49
53
58
6
10
12
PGOOD
10k
0.47µF
0.47µF
REF
PORVIN
64
4k
PVIN10
PVIN9
PVIN8
PVIN7
PVIN6
PVIN5
PVIN4
PVIN3
PVIN2
PVIN1
AVDD
DVDD
P
EN
RT/CT 13
370pF
61
BUFIN+
62
BUFIN63
BUFOUT
P
7.87k
P
D
A
P
A
FIGURE 5. ISL70003ASEH DDR MEMORY POWER SOLUTION
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10
FN8746.0
August 5, 2015
ISL70003ASEH
Absolute Maximum Ratings
Thermal Information
LXx, PVINx . . . . . . . . . . . . . . . . . . . . . . . . . . . .PGNDx - 0.3V to PGNDx + 16V
LXx, PVINx (Note 4). . . . . . . . . . . . . . . . . . . PGNDx - 0.3V to PGNDx + 14.7V
LXx, PVINx (Note 5). . . . . . . . . . . . . . . . . . . PGNDx - 0.3V to PGNDx + 13.7V
AVDD - AGND, DVDD - DGND . . . . . . . . . . . . . . . . . . . . . . . . . . PVINx to -0.3V
VREFA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GNDA - 0.3V to GNDA + 5.5V
VREFD, VREF_OUTS . . . . . . . . . . . . . . . . . . . . .GNDD - 0.3V to GNDD + 5.5V
Signal Pins (Note 8) . . . . . . . . . . . . . . . . . . . . GNDA - 0.3V to VREFA + 0.3V
Digital Control Pins (Note 9) . . . . . . . . . . . . . .GNDD - 0.3V to VREFD+ 0.3V
SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND - 0.3V to DGND + 2.5V
PGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GNDD - 0.3V to DVDD
RTCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GNDD - 0.3V to DVDD
Sourcing Output D.C. Current TJ ≤+125°C (All Power Blocks) . . . . . . . 11A
Sourcing Output D.C. Current TJ ≤+150°C (All Power Blocks) . . . . . . . . 7A
Sinking Output D.C. Current TJ ≤+125°C (All Power Blocks) . . . . . . . . . -4A
ESD Rating
Human Body Model (Tested per MIL-STD-883 TM3015.7) . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Charge Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
CQFP Package R64.C (Notes 6, 7) . . . . . . .
17
0.7
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
PVINx, AVDD, DVDD . . . . . . . . . . . . . . . . . . . . . . . . 3.3V ±10% to 12V ±10%
Output D.C. Current TJ ≤+125°C (All Power Blocks) . . . . . . . . . . . . . . . ≤ 9A
Output D.C. Current TJ ≤+150°C (All Power Blocks) . . . . . . . . . . . . . . . ≤ 6A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. For operation in a heavy ion environment at LET = 86.4MeV•cm2/mg at +125°C (TC) and sourcing 11A load current.
5. For operation in a heavy ion environment at LET = 86.4MeV•cm2/mg at +125°C (TC) with any negative inductor current to sinking -4A load current.
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. For JC, the “case temp” location is the center of the exposed metal heatsink on the package underside.
8. POR_VIN, FB, NI, VERR, OCSETA, OCSETB, BUFOUT, BUFIN-, BUFIN+, IMON and REF pins.
9. FSEL, EN, SYNC, SEL1, SEL2, and DE pins.
Electrical Specifications
\
Unless otherwise noted, PVINx = AVDD = DVDD = 3V - 13.2V; GND = AGND = DGND = PGNDx = SGND = 0V;
POR_VIN = 0.65V; SYNC = LXx = Open Circuit; PGOOD is pulled up to VREFD with a 3k resistor; REF is bypassed to GND with a 220nF capacitor; SS is
bypassed to GND with a 100nF capacitor; IOUT = 0A; TA = TJ = +25°C. (Note 4). Boldface limits apply across the operating temperature range, -55°C to
+125°C; over a total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s; or over a total ionizing dose of 50krad(Si) with
exposure at a low dose rate of <10mrad(Si)/s.
PARAMETER
MIN
(Note 13)
TYP
MAX
(Note 13)
UNIT
PVINx = 13.2V, FSEL = 1 (1MHz)
80
125
mA
PVINx = 13.2V, FSEL = 0 (500kHz)
80
125
mA
PVINx = 3.0V, FSEL = 1 (1MHz)
30
60
mA
PVINx = 3.0V, FSEL = 0 (500kHz)
30
60
mA
PVINx = 13.2V, SEL1 = SEL2 = 5V, FSEL = 1
20
30
mA
PVINx = 13.2V, SEL1 = SEL2 = 5V, FSEL = 0
20
30
mA
PVINx = 3.0V, SEL1 = SEL2 = 5V, FSEL = 1
10
15
mA
PVINx = 3.0V, SEL1 = SEL2 = 5V, FSEL = 0
10
15
mA
PVINx = 13.2V, EN = GND
1.5
3.0
mA
PVINx = 3.0V, EN = GND
0.4
1.0
mA
5.0
5.5
V
190
mA
TEST CONDITIONS
POWER SUPPLY
Operating Supply Current
Standby Supply Current
Shutdown Supply Current
LINEAR REGULATORS
Output Voltage
AVDD, DVDD = 13.2V
4.5
Current Limit
AVDD, DVDD = 13.2V
50
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11
FN8746.0
August 5, 2015
ISL70003ASEH
Electrical Specifications
Unless otherwise noted, PVINx = AVDD = DVDD = 3V - 13.2V; GND = AGND = DGND = PGNDx = SGND = 0V;
POR_VIN = 0.65V; SYNC = LXx = Open Circuit; PGOOD is pulled up to VREFD with a 3k resistor; REF is bypassed to GND with a 220nF capacitor; SS is
bypassed to GND with a 100nF capacitor; IOUT = 0A; TA = TJ = +25°C. (Note 4). Boldface limits apply across the operating temperature range, -55°C to
+125°C; over a total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s; or over a total ionizing dose of 50krad(Si) with
exposure at a low dose rate of <10mrad(Si)/s. (Continued)
MIN
(Note 13)
TYP
MAX
(Note 13)
UNIT
POR Pin Input Voltage
0.56
0.6
0.64
V
POR Sink Current
9.6
12
14.4
µA
PARAMETER
TEST CONDITIONS
POWER-ON RESET
ENABLE
Enable VIH Voltage
2
V
Enable VIL Voltage
Enable (EN) Leakage
EN = 4.5V
1.0
0.8
V
10
µA
SELECT PHASE
SEL 1, 2 VIH Voltage
2
V
SEL 1, 2 VIL Voltage
SEL 1, 2 Leakage Current
SEL1, 2 = VREFD
0.8
V
1.0
10
µA
PWM CONTROL LOGIC
Switching Frequency
FSEL = 1
255
300
345
kHz
FSEL = 0
425
500
575
kHz
Minimum On Time
SS = GND (Note 12)
250
320
ns
Minimum On Time
(Note 12)
160
220
ns
Minimum Off Time
(Note 12)
200
270
ns
Modulator Gain (VIN /ΔVOSC)
RT = 22kΩ, CT = 370pF, FSEL = 0
5
V/V
RT = 36kΩ, CT = 370pF, FSEL = 1
4.8
V/V
External Synchronization Frequency Range FSEL = 1, PVINx = 3.0V
255
300
345
kHz
FSEL = 0, PVINx = 3.0V
425
500
575
kHz
SYNC VIH Voltage
2
V
SYNC VIL Voltage
Synchronization Input Leakage Current
SYNC = VREFD
0.8
V
1.0
4
µA
23
27
µA
3.0
6.0
Ω
SOFT-START
Soft-start Source Current
SS = GND
20
Soft-start Discharge ON-Resistance
Soft-start Discharge Time
(Note 12)
256
Clock Cycles
REFERENCE VOLTAGE
Reference Voltage Tolerance
VREF including Error Amplifier VIO
0.594
0.6
0.606
V
PVIN = 3V - 13.2V, to 9A
(Notes 11, 12)
-0.45
-0.05
0.25
%
LOAD REGULATION
Output Voltage Tolerance over Output
Current Range
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12
FN8746.0
August 5, 2015
ISL70003ASEH
Electrical Specifications
Unless otherwise noted, PVINx = AVDD = DVDD = 3V - 13.2V; GND = AGND = DGND = PGNDx = SGND = 0V;
POR_VIN = 0.65V; SYNC = LXx = Open Circuit; PGOOD is pulled up to VREFD with a 3k resistor; REF is bypassed to GND with a 220nF capacitor; SS is
bypassed to GND with a 100nF capacitor; IOUT = 0A; TA = TJ = +25°C. (Note 4). Boldface limits apply across the operating temperature range, -55°C to
+125°C; over a total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s; or over a total ionizing dose of 50krad(Si) with
exposure at a low dose rate of <10mrad(Si)/s. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
TYP
MAX
(Note 13)
UNIT
ERROR AMPLIFIER
DC Gain
(Note 12)
80
dB
Gain-bandwidth Product
(Note 12)
7
MHz
Maximum Output Voltage
VIN = 5.5V
4.2
V
Slew Rate
(Note 12)
8.5
V/µs
Feedback (FB) Input Leakage Current
VFB = 0.6V, PVINx = 13.2V
Offset Voltage (VIO)
3.5
250
nA
-3
0
3
mV
PVINx = 3.0V, PVIN to LX
170
420
700
mΩ
PVINx = 5.5V, PVIN to LX
120
310
600
mΩ
PVINx = 3.0V, LX to GND
90
240
455
mΩ
PVINx = 5.5V, LX to GND
60
210
425
mΩ
EN = LXx = GND, single LXx output
1
3
µA
EN = GND, LXx = PVINx, Single LXx Output
1
3
µA
POWER BLOCKS
CQFP Individual Upper FET rDS(ON)
CQFP Individual Lower FET rDS(ON)
LXx Output Leakage
Dead Time
Within a single power block or between power
blocks (Note 12)
4
ns
POWER-GOOD SIGNAL
Rising Threshold
VFB as a % of VREF
107
111
115
%
Rising Hysteresis
VFB as a % of VREF
2
3.5
5
%
Falling Threshold
VFB as a % of VREF
85
89
93
%
Falling Hysteresis
VFB as a % of VREF
2
3.5
5
%
Power-good Drive
PVIN = 3V, PGOOD = 0.4V, EN = GND
Power-good Leakage
PVIN = PGOOD = 13.2V
7.2
mA
1
µA
PROTECTION FEATURES
Undervoltage Protection
Undervoltage Trip Threshold
VFB as a % of VREF, test mode
71
75
79
%
Undervoltage Recovery Threshold
VFB as a % of VREF, test mode
86
90
94
%
0.43
0.6
0.77
A/LX
Overcurrent Protection
Overcurrent Accuracy
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ROCSETA, B = 6kΩ (IOC = 0.6A/LX) VIN = 12V
13
FN8746.0
August 5, 2015
ISL70003ASEH
Electrical Specifications
Unless otherwise noted, PVINx = AVDD = DVDD = 3V - 13.2V; GND = AGND = DGND = PGNDx = SGND = 0V;
POR_VIN = 0.65V; SYNC = LXx = Open Circuit; PGOOD is pulled up to VREFD with a 3k resistor; REF is bypassed to GND with a 220nF capacitor; SS is
bypassed to GND with a 100nF capacitor; IOUT = 0A; TA = TJ = +25°C. (Note 4). Boldface limits apply across the operating temperature range, -55°C to
+125°C; over a total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s; or over a total ionizing dose of 50krad(Si) with
exposure at a low dose rate of <10mrad(Si)/s. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
TYP
MAX
(Note 13)
UNIT
BUFFER AMPLIFIER
Gain Bandwidth Product
CL = 1µF, ISOURCE = 1mA, AV = 1, VOUT = 1.25V
(Note 12)
200
kHz
Source Current Capability
Sink Current Capability
Offset Voltage
20
mA
mV
250
400
-4
0
4
µA
225
300
IMON CURRENT MONITOR
IMON Sense Time
145
IMON Output Current Gain
ILOAD = 1A/power stage, LXx off time >300ns
IMON Gain Accuracy
ILOAD = 1A/power stage, LXx off time >300ns
100
-14
ns
µA/A
14
µA
NOTES:
10. Typical values shown are not guaranteed.
11. The 0A to 9A output current range may be reduced by Minimum LXx On Time and Minimum LXx Off Time specifications.
12. Limits established by characterization or analysis and are not production tested.
13. Parameters with MIN and/or MAX limits are 100% tested at -55°C, +25°C and +125°C, unless otherwise specified.
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FN8746.0
August 5, 2015
ISL70003ASEH
Typical Performance Curves
Unless otherwise noted, Test platform is the ISL70003ASEHEV1Z where VIN = 12V,
VOUT = 3.3V, IOUT = 3A, fSW = 500kHz, CIN = 4x 100µF + 5x1µF, LOUT = 3.3µH, COUT = 1x 150µF + 1µF, TCASE = +25°C, All outputs active.
100
100
5VOUT
3.3VOUT
1.8VOUT
5VOUT
2.5VOUT
EFFICIENCY (%)
EFFICIENCY (%)
80
70
1.5VOUT
60
50
3.3VOUT
90
90
1
2
3
4
5
70
1.5VOUT
60
1.2VOUT
0
80
1.2VOUT
0.9VOUT
6
7
8
50
0
9
1
2
3
LOAD CURRENT (A)
85
EFFICIENCY (%)
EFFICIENCY (%)
85
80
75
1.5VOUT
70
1.2VOUT
65
60
1.8VOUT
2.5VOUT
3.3VOUT
0.9VOUT
2
3
4
5
1.5VOUT
70
6
7
3.3VOUT
2.5VOUT
8
50
9
0.9VOUT
0
1
2
95
90
90
85
85
EFFICIENCY (%)
EFFICIENCY (%)
100
95
80
1.5VOUT
1.8VOUT 2.5V
OUT
3.3VOUT
60
5
6
7
1
2
3
4
5
6
LOAD CURRENT (A)
7
8
FIGURE 10. EFFICIENCY vs LOAD, VIN = 5V, 300kHz
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15
9
75
1.2VOUT
70
1.5VOUT 1.8V
OUT
2.5VOUT
0.9VOUT
65
3.3VOUT
55
0
8
80
60
55
50
4
FIGURE 9. EFFICIENCY vs LOAD, VIN = 8V, 500kHz
100
0.9VOUT
3
LOAD CURRENT (A)
FIGURE 8. EFFICIENCY vs LOAD, VIN = 8V, 300kHz
1.2VOUT
1.8VOUT
1.2VOUT
65
LOAD CURRENT (A)
75
9
75
55
1
8
80
60
55
0
7
5VOUT
95
90
65
6
100
5VOUT
90
70
5
FIGURE 7. EFFICIENCY vs LOAD, VIN = 12V, 500kHz
100
50
4
2.5VOUT
LOAD CURRENT (A)
FIGURE 6. EFFICIENCY vs LOAD, VIN = 12V, 300kHz
95
1.8VOUT
0.9VOUT
9
50
0
1
2
3
4
5
6
7
8
9
LOAD CURRENT (A)
FIGURE 11. EFFICIENCY vs LOAD, VIN = 5V, 500kHz
FN8746.0
August 5, 2015
ISL70003ASEH
Typical Performance Curves
100
100
95
95
90
90
85
85
EFFICIENCY (%)
EFFICIENCY (%)
Unless otherwise noted, Test platform is the ISL70003ASEHEV1Z where VIN = 12V,
VOUT = 3.3V, IOUT = 3A, fSW = 500kHz, CIN = 4x 100µF + 5x1µF, LOUT = 3.3µH, COUT = 1x 150µF + 1µF, TCASE = +25°C, All outputs active. (Continued)
80
0.9VOUT
75
70
1.2VOUT
65
1.5VOUT
1.8VOUT
2.5VOUT
60
75
0.9VOUT
70
1.2VOUT
65
2.5VOUT
0
1
2
3
4
5
6
7
8
50
9
0
1
2
95
95
90
90
EFFICIENCY (%)
EFFICIENCY (%)
100
TC = -55°C
80
TC = +125°C
75
TC = +85°C
TC = +25°C
65
3
4
5
6
8
9
7
8
60
9
TC = -55°C
TC = +125°C
0
1
2
LOAD CURRENT (A)
3
4
TC = +25°C
5
6
7
8
9
LOAD CURRENT (A)
FIGURE 14. EFFICIENCY vs LOAD, VIN = 12V, VOUT = 5V, 300kHz
FIGURE 15. EFFICIENCY vs LOAD, VIN = 12V, VOUT = 3.3V, 500kHz
100
100
95
95
90
TC = -55°C
85
80
TC = +85°C
TC = +25°C
75
TC = +125°C
70
EFFICIENCY (%)
90
EFFICIENCY (%)
7
TC = +85°C
75
65
2
6
80
70
1
5
85
70
0
4
FIGURE 13. EFFICIENCY vs LOAD, VIN = 3.3V, 500kHz
100
85
3
LOAD CURRENT (A)
FIGURE 12. EFFICIENCY vs LOAD, VIN = 3.3V, 300kHz
85
80
TC = +125°C
75
TC = -55°C
TC = +25°C
TC = +85°C
70
65
65
60
1.8VOUT
55
LOAD CURRENT (A)
60
1.5VOUT
60
55
50
80
0
1
2
3
4
5
6
7
8
9
LOAD CURRENT (A)
FIGURE 16. EFFICIENCY vs LOAD, VIN = 5V, VOUT = 3.3V, 500kHz
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16
60
0
1
2
3
4
5
6
7
8
9
LOAD CURRENT (A)
FIGURE 17. EFFICIENCY vs LOAD, VIN = 5V, VOUT = 2.5V, 500kHz
FN8746.0
August 5, 2015
ISL70003ASEH
Typical Performance Curves
100
100
95
95
90
90
EFFICIENCY (%)
EFFICIENCY (%)
Unless otherwise noted, Test platform is the ISL70003ASEHEV1Z where VIN = 12V,
VOUT = 3.3V, IOUT = 3A, fSW = 500kHz, CIN = 4x 100µF + 5x1µF, LOUT = 3.3µH, COUT = 1x 150µF + 1µF, TCASE = +25°C, All outputs active. (Continued)
85
TC = +125°C
80
TC = +25°C
75
70
TC = -55°C
TC = +85°C
80
75
TC = +125°C
70
65
60
TC = -55°C
85
TC = +25°C
65
0
1
2
3
4
5
6
7
8
60
9
TC = +85°C
0
1
2
LOAD CURRENT (A)
5
6
POWER LOSS (W)
POWER LOSS (W)
7
4
5VOUT
2
0.9VOUT
1
5
7
8
9
5VOUT
3
0.9VOUT
2
1
0
1
2
3
4
5
6
7
8
0
9
0
1
2
4
5
6
7
8
9
FIGURE 21. POWER LOSS, VIN = 12V, 500kHz
6
5
5
POWER LOSS (W)
6
2.5VOUT
4
3
LOAD CURRENT (A)
FIGURE 20. POWER LOSS, VIN = 12V, 300kHz
POWER LOSS (W)
6
4
LOAD CURRENT (A)
3
0.9VOUT
2
1
0
5
FIGURE 19. EFFICIENCY vs LOAD, VIN = 3.3V, VOUT = 1.2V, 500kHz
6
0
4
LOAD CURRENT (A)
FIGURE 18. EFFICIENCY vs LOAD, VIN = 3.3V, VOUT = 2.5V, 300kHz
3
3
4
2.5VOUT
3
0.9VOUT
2
1
0
1
2
3
4
5
6
LOAD CURRENT (A)
7
8
FIGURE 22. POWER LOSS, VIN = 3.3V, 300kHz
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9
0
0
1
2
3
4
5
6
7
8
9
LOAD CURRENT (A)
FIGURE 23. POWER LOSS, VIN = 3.3V, 500kHz
FN8746.0
August 5, 2015
ISL70003ASEH
Typical Performance Curves
Unless otherwise noted, Test platform is the ISL70003ASEHEV1Z where VIN = 12V,
VOUT = 3.3V, IOUT = 3A, fSW = 500kHz, CIN = 4x 100µF + 5x1µF, LOUT = 3.3µH, COUT = 1x 150µF + 1µF, TCASE = +25°C, All outputs active. (Continued)
0.05
0.00
5VOUT
LOAD REGULATION (%)
LOAD REGULATION (%)
0
-0.05
0.9VOUT
-0.10
1.2VOUT
-0.15
1.5VOUT
2.5VOUT
-0.20
1.8VOUT
-0.25
-0.30
0
1
2
3
4
5
6
7
8
-0.05
-0.10
PVIN = 3V
-0.15
-0.20
PVIN = 5V
PVIN = 8V
-0.25
-0.30
9
PVIN = 13.3V
0
1
2
3
OUTPUT CURRENT (A)
FIGURE 24. LOAD REGULATION vs VOUT, PVIN = 12V
VOUT DELTA NORMALIZED TO
PVIN = 3V (%)
LOAD REGULATION (%)
-0.05
500kHz
-0.10
300kHz
-0.15
-0.20
-0.25
0
1
2
3
4
5
6
7
8
0.03
7
8
9
0.01
-0.01
2.5VOUT
-0.03
-0.05
3
9
1.5VOUT
4
5
6
7
LOAD CURRENT (A)
604
604
REFERENCE VOLTAGE (mV)
606
PVIN = 13.2V
600
PVIN = 3V
598
596
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 28. REFERENCE VOLTAGE vs TEMPERATURE
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18
9
10
11
12
13
14
FIGURE 27. LINE REGULATION, VOUT = 1.0V, LOAD = 3A
606
602
8
PVIN (V)
FIGURE 26. LOAD REGULATION vs SWITCHING FREQUENCY
REFERENCE VOLTAGE (mV)
6
0.05
0.00
594
-60
5
FIGURE 25. LOAD REGULATION vs PVIN, VOUT = 1.0V
0.05
-0.30
4
OUTPUT CURRENT (A)
140
-55°C
602
600
598
+25°C
+125°C
596
594
2
4
6
8
10
12
14
INPUT VOLTAGE (V)
FIGURE 29. REFERENCE VOLTAGE vs VIN
FN8746.0
August 5, 2015
ISL70003ASEH
Typical Performance Curves
Unless otherwise noted, Test platform is the ISL70003ASEHEV1Z where VIN = 12V,
VOUT = 3.3V, IOUT = 3A, fSW = 500kHz, CIN = 4x 100µF + 5x1µF, LOUT = 3.3µH, COUT = 1x 150µF + 1µF, TCASE = +25°C, All outputs active. (Continued)
6.00
500kHz
5.75
495
PVIN = 13.2V
PVIN = 3V
445
MODULATOR GAIN (V/V)
SWITCHING FREQUENCY (kHz)
545
395
PVIN = 3V
345
295
-40
-20
0
20
40
60
5.25
5.00
4.75
300kHz
4.50
4.25
PVIN = 13.2V
245
-60
5.50
80
100
120
140
TEMPERATURE (°C)
FIGURE 30. SWITCHING FREQUENCY vs TEMPERATURE
ENABLE, 5V/DIV
4.00
2
4
6
8
10
12
14
INPUT VOLTAGE (V)
FIGURE 31. MODULATOR GAIN vs VIN
ENABLE, 5V/DIV
LXx VOLTAGE, 5V/DIV
INDUCTOR CURRENT, 2A/DIV
OUTPUT VOLTAGE, 2V/DIV
OUTPUT VOLTAGE, 2V/DIV
PGOOD, 10V/DIV
FIGURE 32. MONOTONIC SOFT-START WITH NO LOAD, CCM
19
FIGURE 33. MONOTONIC SOFT-START WITH 6A LOAD, CCM
ENABLE, 5V/DIV
ENABLE, 5V/DIV
LXx VOLTAGE, 5V/DIV
LXx VOLTAGE, 5V/DIV
OUTPUT VOLTAGE, 2V/DIV
OUTPUT VOLTAGE, 2V/DIV
PGOOD, 10V/DIV
PGOOD, 10V/DIV
FIGURE 34. MONOTONIC SOFT-START WITH 1.5V PREBIASED LOAD
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PGOOD, 10V/DIV
FIGURE 35. MONOTONIC SOFT-START WITH NO LOAD, DEM
FN8746.0
August 5, 2015
ISL70003ASEH
Typical Performance Curves
Unless otherwise noted, Test platform is the ISL70003ASEHEV1Z where VIN = 12V,
VOUT = 3.3V, IOUT = 3A, fSW = 500kHz, CIN = 4x 100µF + 5x1µF, LOUT = 3.3µH, COUT = 1x 150µF + 1µF, TCASE = +25°C, All outputs active. (Continued)
LXx VOLTAGE, 5V/DIV
INDUCTOR CURRENT, 1A/DIV
OUTPUT VOLTAGE, 20mV/DIV
FIGURE 36. STEADY STATE OPERATION NO LOAD, CCM
LXx VOLTAGE, 5V/DIV
INDUCTOR CURRENT, 2A/DIV
OUTPUT VOLTAGE, 20mV/DIV
FIGURE 37. STEADY STATE OPERATION 6A LOAD, CCM
INDUCTOR CURRENT, 2A/DIV
LXx VOLTAGE, 5V/DIV
INDUCTOR CURRENT, 0.5A/DIV
OUTPUT VOLTAGE, 20mV/DIV
FIGURE 38. DIODE EMULATION OPERATION, VOUT = 1.2V, 125mA LOAD
OUTPUT VOLTAGE, 200mV/DIV
FIGURE 39. 6A LOAD TRANSIENT RESPONSE, DIODE EMULATION
INDUCTOR CURRENT, 2A/DIV
INDUCTOR CURRENT, 2A/DIV
OUTPUT VOLTAGE, 50mV/DIV
FIGURE 40. 3A LOAD TRANSIENT RESPONSE
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OUTPUT VOLTAGE, 50mV/DIV
FIGURE 41. 6A LOAD TRANSIENT RESPONSE
FN8746.0
August 5, 2015
ISL70003ASEH
Typical Performance Curves
Unless otherwise noted, Test platform is the ISL70003ASEHEV1Z where VIN = 12V,
VOUT = 3.3V, IOUT = 3A, fSW = 500kHz, CIN = 4x 100µF + 5x1µF, LOUT = 3.3µH, COUT = 1x 150µF + 1µF, TCASE = +25°C, All outputs active. (Continued)
LXx VOLTAGE, 5V/DIV
LXx VOLTAGE, 5V/DIV
INDUCTOR CURRENT, 10A/DIV
INDUCTOR CURRENT, 5A/DIV
OUTPUT VOLTAGE, 2V/DIV
OUTPUT VOLTAGE, 2V/DIV
SS VOLTAGE, 2V/DIV
PGOOD, 10V/DIV
FIGURE 43. HICCUP RESPONSE IN OCP
FIGURE 42. OVERCURRENT RESPONSE
Functional Description
capability at TJ = +125°C. The block diagram in Figure 44 shows
a top level view of the individual power blocks.
The ISL70003ASEH is a monolithic synchronous buck regulator
IC with integrated power MOSFETs. The device utilizes
voltage-mode control with feed-forward and switches at a
nominal frequency of 500kHz or 300kHz. It is fabricated on a
0.6μm BiCMOS junction isolated process optimized for power
management applications. With this device and a handful of
external components, a complete synchronous buck DC/DC
converter can be readily implemented. The converter accepts an
input voltage ranging from 3V to 13.2V and provides a tightly
regulated output voltage ranging from 0.6V to ~90% of the input
voltage at output currents ranging from 0A to 9A. Typical
applications include Point Of Load (POL) regulation for FPGAs,
CPLDs, DSPs, DDR memory and microprocessors.
Power Blocks
PVIN1
LX1
PGND1
POWER BLOCK 1
POWER BLOCK 6
OCPB and IMON
PVIN6
LX6
PGND6
PVIN2
LX2
PGND2
POWER BLOCK 2
POWER BLOCK 7
PVIN7
LX7
PGND7
PVIN3
LX3
PGND3
POWER BLOCK 3
POWER BLOCK 8
PVIN8
LX8
PGND8
PVIN4
LX4
PGND4
POWER BLOCK 4
POWER BLOCK 9
PVIN9
LX9
PGND9
PVIN5
LX5
PGND5
POWER BLOCK 5
and OCPA
POWER BLOCK 10
PVIN10
LX10
PGND10
Note: Shaded blocks indicate pilot current and current sensors.
FIGURE 44. POWER BLOCK DIAGRAM
The power output stage of the regulator consists of ten power
blocks that are paralleled to provide full 9A output current
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21
SEL1 and SEL2 pins allow users to disable power blocks in order
to reduce switching losses in light load applications. Depending
on the state of these pins the ISL70003ASEH can operate with 2,
4, or 10 active power blocks and also be placed in a sleep mode.
Each power block has a power supply input pin, PVINx, a phase
output pin, LXx and a power supply ground pin, PGNDx. All PVINx
pins must be connected to a common power supply rail and all
PGNDx pins must be connected to a common ground. LXx pins
should be connected to the output inductor based on the
required load current and the state of the SEL1, SEL2 pins, but
must include the LX5 and LX6 pins. The unused LXx pins should
be left unconnected.
Scaled pilot devices associated with power blocks 5 and 6
provide current feedback for overcurrent detection and the IMON
current monitor feature. Power blocks 5 and 6 must be
connected to the output inductor at all times for proper
operation.
Initialization
The ISL70003ASEH initializes based on the state of the EN input
and POR input. Successful initialization prompts a soft-start
interval and the regulator begins slowly ramping the output
voltage. Once the commanded output voltage is within the
proper window of operation, the power-good signal changes state
from low to high indicating proper regulator operation.
Enable
The EN pin accepts TTL/CMOS logic input as described in the
Electrical Specifications” table on page 11. When the voltage on
the EN pin exceeds its logic rising threshold, the controller
monitors the POR voltage before initiating the soft-start function
for the PWM regulator. When EN is pulled low, the device enters
shutdown mode and the supply current drops to a typical value of
1.5mA. All internal power devices are held in a high impedance
state while in shutdown mode. Due to the internal 5V clamp, the
EN pin should be driven no higher than 5V or excessive leakage
current may be seen on the pin. In standalone applications the
FN8746.0
August 5, 2015
ISL70003ASEH
EN pin may be tied to an input voltage >5V through a 50kΩ
resistor to minimize the current into the EN pin. The current
should not be allowed to exceed 160µA at any operating voltage.
Equation 2 defines the relationship between the resistor divider,
sink current and POR rising level (VPORR).
R1
V PORR = V R  1 + ------- + I POR  R 1
R
(EQ. 2)
2
Once the voltage at the POR pin reaches the enable threshold,
the IPOR current sink turns off.
VIN > 5.0V
PVINx
5V
INT. REG.
With the part enabled and the IPOR current sink off, the falling level
(VPORF) is set by the resistor divider network and is defined by
Equation 3.
R1
51kΩ
ENABLE
COMPARATOR
-
(EQ. 3)
2
EN
+
POR
LOGIC
R1
V PORF = V R  1 + ------R
The difference between the POR rising and falling levels provides
adjustable hysteresis so that noise on VIN does not interfere with
the enabling or disabling of the regulator.
VR
Soft-start
The ISL70003ASEH soft-start function uses an internal current
source and an external capacitor to reduce stresses and surge
current during start-up.
FIGURE 45. ENABLE TO VIN FOR >5.0 INPUT VOLTAGE
Power-on Reset
After the EN input requirements are met, the ISL70003ASEH
remains in shutdown until the voltage at the POR pin rises above
its threshold. The POR circuitry prevents the controller from
attempting to soft-start before sufficient bias is present at the
PVINx pins.
As shown in Figure 46 on page 22, the POR circuit features a
comparator type input. The POR circuit allows the level of the
input voltage to precisely gate the turn-on/turn-off of the
regulator. An internal IPOR current sink with a typical value of
12µA is only active when the voltage on the POR pin is below the
enable threshold so it can pull the POR pin low. As VIN rises, the
POR enable level is set by the resistor divider (R1 and R2) from
VIN and the internal sink current source, IPOR.
VR = 0.6V
IPOR = 12µA
CPOR = 10nF
VIN
5V
V REF
t SS = C SS  --------------I
PVINx
INT. REG
Once the POR and enable circuits are satisfied, the regulator
waits 32 clock cycles and then initiates a soft-start. Figure 47
shows that the soft-start circuit clamps the error amplifier
reference voltage to the voltage on an external soft-start
capacitor connected to the SS pin. The soft-start capacitor is
charged by an internal ISS current source. As the soft-start
capacitor is charged, the output voltage slowly ramps to the set
point determined by the reference voltage and the feedback
network. Once the voltage on the SS pin is equal to the internal
reference voltage, the soft-start interval is complete. Following
the soft-start interval is a delay to power good being signaled.
The soft-start output ramp interval is defined in Equation 4 and is
adjustable from approximately 2ms to 200ms. The value of the
soft-start capacitor, CSS, should range from 82nF to 8.2µF,
inclusive. The peak inrush current can be computed from
Equation 5. The soft-start interval should be selected long
enough to insure that the peak inrush current plus the peak
output load current does not exceed the overcurrent trip level of
the regulator.
(EQ. 4)
SS
V OUT
I INRUSH = C OUT  ---------------t
(EQ. 5)
SS
VIN
POR
COMPARATOR
R1
POR
+
POR
LOGIC
-
VR
CPOR
The soft-start capacitor is immediately discharged by a 3.0Ω
resistor whenever POR conditions are not met or EN is pulled low.
The soft-start discharge time is equal to 256 clock cycles.
R2
IPOR
FIGURE 46. POR CIRCUIT
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FN8746.0
August 5, 2015
ISL70003ASEH
0.666V
VOUT
VREF = 0.6V
ISS = 23µA
RD = 2.2Ω
+
OV
RT
-
RB
+
FB
ERROR
AMPLIFIER
PWM
LOGIC
PGOOD
+
+
UV
-
SS
NI
VREF
CSS
FB
0.534V
COUNTER/
POR/ ON-OFF
CONTROL
-
RD
OCP
+
ISS
UVP
0.45V
-
CREF
FIGURE 47. SOFT-START CIRCUIT
Power-good
A power-good indicator is the final step of initialization. After a
successful soft-start, the PGOOD pin releases and the voltage
rises with an external pull-up resistor. The power-good signal
transitions low immediately when the EN pin is pulled low.
The PGOOD pin is an open-drain logic output and can be pulled
up to any voltage from 0V to 13.2V. The pull-up resistor should
have a nominal value from 1kΩ to 10kΩ. The PGOOD pin should
be bypassed to DGND with a 10nF ceramic capacitor to mitigate
SEE.
ISEN
OCP
+
REF
OCSETB
+
-
VREF
ISEN
OCSETA
FIGURE 48. POWER-GOOD AND OC PROTECTION CIRCUITRY
Undervoltage Protection
A hysteretic comparator monitors the FB pin of the regulator. The
feedback voltage is compared to an undervoltage threshold that is a
fixed percentage of the reference voltage, typically 75%. Once the
comparator trips, indicating a valid undervoltage condition, an
undervoltage counter increments. The counter is reset if the
feedback voltage rises back above the undervoltage threshold plus
a specified amount of hysteresis outlined in the “Electrical
Specifications” table on page 13. If there are 4 consecutive
undervoltage detections the counter will overflow and the
undervoltage protection logic shuts down the regulator, pulling
PGOOD low.
The ISL70003ASEH actively monitors the output voltage and
current to detect fault conditions. Fault conditions trigger
protective measures to prevent damage to the regulator and the
external load device. One common power-good indication signal
is provided for linking to external system monitors. The
schematic in Figure 48 on page 23 outlines the interaction
between the fault monitors and the power-good signal.
After the regulator shuts down, it enters a delay interval,
approximately equivalent to 512 clock cycles plus 1 soft-start
intervals, allowing the device to cool. The undervoltage counter is
reset entering the delay interval. The protection logic initiates a
normal soft-start once the delay interval ends. If the output
successfully soft starts, the power-good signal goes high and normal
operation continues. If undervoltage conditions continue to exist
during the soft-start interval, the undervoltage counter must
overflow before the regulator shuts down again. This hiccup mode
continues indefinitely until the output soft starts successfully.
Undervoltage and Overvoltage Monitor
Overcurrent Protection
The power-good pin (PGOOD) is an open-drain logic output which
indicates that the converter is operating properly and the output
voltage is within a set window. The undervoltage (UV) and
overvoltage (OV) comparators create the output voltage window.
The power-good circuitry monitors the FB pin and compares it to
the rising and falling thresholds shown in the “Electrical
Specifications” table on page 13. If the feedback voltage
exceeds the typical rising limit of 111% of the reference voltage,
the PGOOD pin pulls low. The PGOOD pin continues to pull low
until the feedback voltage falls to a typical of 107.5% of the
reference voltage. If the feedback voltage drops below a typical
of 89% of the reference voltage, the PGOOD pin pulls low. The
PGOOD pin continues to pull low until the feedback voltage rises
to a typical 92.5% of the reference voltage. The PGOOD pin then
releases and signals the return of the output voltage within the
power-good window.
A pilot device integrated into the PMOS transistor of Power Blocks
5 and 6 sample the current each cycle. This current feedback is
scaled and compared to an overcurrent threshold based on the
resistor value tied from pins OCSETA and OCSETB to AGND.
Fault Monitoring and Protection
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23
Upon detection of an overcurrent condition, the upper MOSFET
will be immediately turned off and will not be turned on again
until the next switching cycle. Upon detection of the initial
overcurrent condition, the overcurrent fault counter is set to 1. If,
on the subsequent cycle, another overcurrent condition is
detected, the OC fault counter will increment. However, if the
sampled current falls below the threshold the counter is reset. If
there are 4 sequential OC fault detections, the counter will
overflow and the regulator will be shut down under an
overcurrent fault condition, pulling PGOOD low.
FN8746.0
August 5, 2015
ISL70003ASEH
Switching Frequency Selection
ϭϬ
There are a number of variables to consider when choosing the
switching frequency. A high switching frequency increases the
switching losses but may lead to a decrease in output filter size. A
lower switching frequency may increase efficiency but may lead to
more output voltage ripple and increased output filter size.
LOAD CURRENT, 5A/DIV
ϵ
ϴ
ϳ
0A
ϲ
OUTPUT VOLTAGE, 1V/DIV
ϱ
ϰ
ϯ
0V
Ϯ
SOFT-START VOLTAGE, 1V/DIV
ϭ
Ϭ
5ms/DIV
0V
FIGURE 49. OVERCURRENT BEHAVIOR IN HICCUP MODE
After the regulator shuts down, it enters a delay interval, allowing
the device to cool. The delay interval is approximately equal to
512 clock cycles plus 1 soft-start intervals. The overcurrent
counter is reset entering the delay interval. The protection logic
initiates a normal soft-start once the delay interval ends. If the
output successfully soft starts, the power-good signal goes high
and normal operation continues. If overcurrent conditions
continue to exist during the soft-start interval, the overcurrent
counter must overflow before the regulator shutdowns the output
again. This hiccup mode continues indefinitely until the output
soft starts successfully (see Figure 49).
On the ISL70003ASEH, the switching frequency is determined by
the state of the TTL/CMOS compatible FSEL pin. A logic low will
set the regulator to operate with a 500kHz switching frequency,
while a logic high sets a 300kHz switching frequency.
Synchronization
The ISL70003ASEH, can be synchronized to an external clock
with a frequency range of 500kHz ±15% or 300kHz ±15%,
depending on the state of the FSEL pin.
The SYNC pin accepts the external clock signal and the regulator
will be synchronized in phase with the external clock. During
start-up the regulator will use its internal oscillator to regulate
the output voltage. Once soft-start is complete and PGOOD is
released, the regulator will synchronize to the external clock
signal. This feature allows the ISL70003ASEH regulator to be the
power source to the external components that will be providing
the external clock without the requirement that a signal must be
present at the SYNC pin before start-up.
Output Voltage Selection
Load Regulation
The ISL70003ASEH is a metal only revision of the ISL70003SEH
specifically to improve load regulation across the wider 9A output
current rating. Although the load regulation is now improved by an
order of magnitude there are performance generalities to be
aware of; higher temperature, lower PVIN and higher VOUT/PVIN
ratio all yield tighter load regulation performance. The switching
frequency has no deterministic effect, producing differences 1
order of magnitude less than the other condition considerations.
Figure 2 on page 2 and Figures 24, 25, 26, 27 on page 18
illustrate performance trends for a sampling of these conditions.
VOUT
CO
R1
ERROR
AMPLIFIER
+
VREF
FB
NI
R4
REF
FIGURE 50. OUTPUT VOLTAGE SELECTION
Voltage Feed-forward
Feed-forward is used to maintain a constant modulator gain and
achieve optimum loop response over a wide input voltage range.
A resistor from PVINx to RTCT and a capacitor from RTCT to
PGNDx are used to adjust the amplitude of the sawtooth ramp
proportional to the input voltage. The capacitor value must be
chosen so that it is large enough for mitigation of single event
transients but low enough for the internal MOSFET device to pull
the pin to ground. The following table gives the recommended
values for RT and CT for a given switching frequency. These
values will achieve a constant modulator gain across the
complete input voltage range.
FSEL STATE
fSW (kHz)
RT (kΩ)
CT (pF)
MODULATOR
GAIN (TYP)
0
500
22
370
5
1
300
36
370
4.8
24
LO
CREF
Application Information
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LXx
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage
relative to the reference voltage. The reference voltage and the
noninverting input to the error amplifier are not internally
connected, therefore, for standalone applications the REF pin
must be tied to the NI pin (see Figure 50). The REF pin should be
bypassed to AGND with a 220nF ceramic capacitor to mitigate
SEE. It should be noted that no current (sourcing or sinking) is
available from the REF pin.
The output voltage programming resistor, R4, will depend on the
value chosen for the feedback resistor R1 and the desired output
voltage of the regulator. The value for the feedback resistor is
typically between 5kΩ and 25kΩ.
If the output voltage desired is 0.6V, then R4 is left unpopulated.
R 1  0.6V
R 4 = -----------------------------------------V OUT – 0.6V
(EQ. 6)
FN8746.0
August 5, 2015
ISL70003ASEH
Setting the Overcurrent Protection Level
The ISL70003ASEH features dual redundancy in the overcurrent
detection circuitry, which helps avoid false overcurrent triggering
due to single event effects. Two external resistors from pins
OCSETA and OCSETB to AGND set the level of the overcurrent
protection (OCP) trip point. The OCP circuit senses the peak
current across a pilot device not the average current so it is
important to determine the overcurrent trip point (IOCP) greater
than the maximum output continuous current (IMAX) plus half
the maximum inductor ripple current (ΔI).
Use Equation 7 to determine the peak-to-peak inductor ripple
current:
V IN – V OUT
I = --------------------------------  D
f SW  L
(EQ. 7)
Where fSW is the switching frequency, L is the output inductor
value and D is duty cycle. Once an IOCP value is chosen that
satisfies Equation 8:
I
I OCP  I MAX + ----2
(EQ. 8)
Equation 9 may be used to determine the value of ROCSETA and
ROCSETB with all 10 power blocks active.
36024
R OCSET  A B  = ---------------I OCP
(EQ. 9)
The minimum value for ROCSET(A,B) is 2.87kΩ, which is
equivalent to a 12.5A IOCP level.
Disabling the Power Blocks
The ISL70003ASEH offers two TTL/CMOS compatible power
block select pins, SEL1 and SEL2, which form a 2-bit logic input
that are used to turn off the internal power blocks. Depending on
the state of the SEL1 and SEL2 pins, the ISL70003ASEH can
operate with 2, 4 or 10 power blocks on or have all the outputs in
a tri-state mode. This allows the designer to reduce switching
losses in low current applications, where all power blocks are not
needed to supply the load current. Table 1 compares the logic
state of SEL1 and SEL2 with the current capability of the
regulator and the number of active LXx pins.
With both SEL pins in a logic high state, the ISL70003ASEH is in
a low power sleep mode where all outputs are tri-stated. Once
the logic activates the power blocks, the regulator ramps the
output voltage to its set value within a soft-start interval,
however, the device no longer goes through the preinitialization
phase.
Transitions between the number of active LXx pins through the
use of SEL1 and SEL2 should not be done while the part is
operating. On the fly transitions will cause glitches on the output
voltage which may exceed transient requirements. It is
recommended to place the ISL70003ASEH in standby mode, by
pulling SEL1 and SEL2 HIGH, then change the number of active
LXx pins.
The overcurrent trip point scales depending on the number of
active power blocks. Equation 10 may be used to determine the
value of ROCSETA and ROCSETB when less than 10 power blocks
are active:
3602.4  N
R OCSET  A B  = ----------------------------I OCP
Where N is the number of active power block phases.
IMON Current Sense Output
The ISL70003ASEH provides a current monitor function through
IMON. Current monitoring informs designers if downstream loads
are operating as expected. It is also useful in the prototype and
debug phase of the design and during normal operation to
measure the overall performance of a system. The IMON pin
outputs a high speed analog current source that is proportional
to the sensed peak current through the ISL70003ASEH. In typical
applications, a resistor RIMON is connected to the IMON pin to
convert the sensed current to voltage, VIMON, which is
proportional to the peak current, as shown in Equation 11:
V IMON = 100  10
– 6 I SAMPLE  R IMON
 --------------------------------------------------N
SEL2
STATE
SEL1
STATE
ACTIVE LXx PINS
LOAD CAPABILITY
(TJ = +125°C)
0
0
All
9A
0
1
5, 6, 7, 8
3.6A
1
0
5, 6
1.8A
1
1
None
N/A
(EQ. 11)
Where VIMON is the voltage at the IMON pin, RIMON is the resistor
between the IMON pin and AGND, ISAMPLE is the current through
the converter at the time IMON samples the current, and N is the
number of active power blocks. ISAMPLE may be calculated from
Equation 12.
t SAMPLE  f SW
I
I SAMPLE = I LOAD + ----- –  I  ------------------------------------------

1 – D
2 
TABLE 1. LOGIC STATE COMPARISON
(EQ. 10)
(EQ. 12)
Where tSAMPLE is the time it takes the IMON circuitry to sample
the current (300ns, max.), ILOAD is the load current and ΔI is the
inductor peak-to-peak ripple current as calculated in Equation 7.
A small capacitor should be placed between the IMON pin and
AGND to reduce the noise impact and mitigate single event
transients. If this pin is not used, it is best connected to VREFA. It
is also acceptable to tie to GND through a resistor.
Figures 51 and 52 show the response of the IMON current
monitor due to a load step with a RIMON = 10kΩ and 100pF
ceramic capacitor in parallel.
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FN8746.0
August 5, 2015
ISL70003ASEH
Diode Emulation
Diode Emulation (DE) allows for higher converter efficiency under
light load situations. In DE mode, the low-side MOSFET conducts
when the current is flowing from source to drain and does not
allow reverse current, emulating a diode. As shown in Figure 54,
when the LGATE signal is HIGH, the low-side MOSFET carries
current, creating negative voltage on the phase node due to the
voltage drop across the ON-resistance. When the DE pin is pulled
HIGH, the ISL70003ASEH will be in diode emulation mode and
detect the zero current crossing of the inductor current and turn
off the lower MOSFET to prevent the inductor current from
reversing direction and creating unnecessary power loss. This
ensures that discontinuous conduction mode (DCM) is achieved.
Since diode emulation prevents the low-side MOSFET from
sinking current, no negative spike at the output is generated
during prebiased startup when DE mode is active.
VIMON VOLTAGE
200mV/DIV
INDUCTOR
CURRENT
2A/DIV
TIME (5µs/DIV)
FIGURE 51. IMON RESPONSE TO 6A LOAD STEP
After a significantly fast load release transient, diode emulation
will not allow the converter to bring the output voltage back down
following the hump created by the inductor energy dump into the
output capacitor bank. The ISL70003ASEH overcomes this issue
by monitoring the output of the error amplifier and allowing the
low-side MOSFET to turn on and sink the necessary current
needed to properly regulate the output voltage. The same
mechanism allows the converter to properly regulate the output
voltage when starting into a prebiased condition where the
prebias level is greater than the desired output voltage.
VIMON VOLTAGE
200mV/DIV
INDUCTOR
CURRENT
2A/DIV
TIME (5µs/DIV)
FIGURE 52. IMON RESPONSE TO 6A LOAD RELEASE
LXx
Although the IMON output reflects the peak current sensed, it
can be also used to approximate the DC output current with a
more accurate approximation at higher current levels and lower
PVIN voltage. Figure 53 shows a graph normalized to 100µA of
IMON current to 1A of output current across a 10kΩ resistor.
2.0
UGATE
LGATE
IL
IMON WITH 10K to GND
(NORMALIZED TO 100µA/A)
1.8
FIGURE 54. DIODE EMULATION
13.2VIN_5VOUT
1.6
The DE pin is not intended to actively change states while the
regulator is operating. If any part of the inductor current is below
zero and the DE pin changes state there will be a glitch on the
output voltage. However, if the state of the DE pin changes state
when the inductor current is positive, no change in the operation
of the regulator will be seen.
5VIN_1.5VOUT
1.4
3.0VIN_1.5VOUT
1.2
1.0
0.8
DDR Application
1
2
3
4
5
6
7
8
9
OUTPUT CURRENT (A)
FIGURE 53. IMON TO DC IOUT
It is important to note that if the on time of the lower NMOS FET
is shorter than the IMON current sense time (300ns max), the
IMON output is tri-stated after 4 consecutive failed sense
occurrences.
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High throughput Double Data Rate (DDR) memory ICs are
replacing traditional memory ICs in space applications. A novel
feature associated with this type of memory are the referencing
and data bus termination techniques. These techniques employ
a reference voltage, VREF, that tracks the center point of VDDQ
and VSS voltages, and an additional VTT power source where all
terminating resistors are connected. Despite the additional
power source, the overall memory power consumption is reduced
compared to traditional termination.
FN8746.0
August 5, 2015
ISL70003ASEH
The added power source has a cluster of requirements that
should be observed and considered. Due to the reduced
differential thresholds of DDR memory, the termination power
supply voltage, V TT, closely tracks VDDQ/2 voltage.
Another very important feature of the termination power supply
is the capability to operate at equal efficiency in sourcing and
sinking modes. The VTT supply regulates the output voltage with
the same degree of precision when current is flowing from the
supply to the load, and when the current is diverted back from
the load into the power supply.
The ISL70003ASEH regulator possesses several important
enhancements that allow reconfiguration for DDR memory
applications. Two ISL70003ASEH ICs will provide all three
voltages required in a DDR memory compliant system.
DDR Configuration
VDDQ
ISL70003ASEH 1/2
RT1
FB
RB1
VDDQ
NI
-
ERROR
AMPLIFIER
VIN
PVINx
LO
LXx
+
VDDQ
CO1
REF
PGNDx
VREF
RT1
RB1
ISL70003ASEH 2/2
VTT
NI
RT2
FB
RB2
VDDQ
B+
B-
+
ERROR
AMPLIFIER
+
BUFFER
AMPLIFIER
VIN
PVINx
LXx
PGNDx
LO
VTT
CO2
-
R
OUTB
VREF
CO3
R
FIGURE 55. SIMPLIFIED DDR APPLICATION SCHEMATIC
In the DDR application presented in Figure 55, an independent
architecture is implemented to generate the voltages needed for
DDR memory applications. Consequently, both VDDQ and VTT are
derived independently from the main power source. The first
regulator supplies the 2.5V for the VDDQ voltage. The output
voltage is set by external dividers RT1 and RB1. The second
regulator generates the VTT rail typically = VDDQ/2. The resistor
divider network RT2 and RB2 are used to set the output voltage to
1.25V. The VDDQ rail has an additional voltage divider network
consisting of RT1 and RB1, the midpoint is connected to the
noninverting input pin of the V TT regulator’s error amplifier (NI),
effectively providing a tracking function for the VTT voltage.
The noninverting input of the buffer amplifier is connected to the
center point of the external R/R divider from the VDDQ output.
The output of the buffer is tied back to the inverting input for
unity gain configuration. The buffer output voltage serves as a
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1.25V reference (VREF) for the DDR memory devices. Sourcing
capability of the buffer amplifier is 10mA typical (20mA max)
and needs a minimum of 1µF load capacitance for stability.
Diode emulation mode of operation must be disabled on the V TT
regulator to allow sinking capability. In the event both channels
are enabled simultaneously, the soft-start capacitor on the VDDQ
regulator should be two to three times larger than the soft-start
capacitor on the VTT regulator. This allows the VDDQ regulator
voltage to be the lowest input into the error amplifier of the VTT
regulator and dominate the soft-start ramp. However, if the VTT
regulator is enabled later than the VDDQ, the soft-start capacitor
can be any value based on design goals.
Each regulator has its own fault protections and must be
individually configured. All the sink current on the VTT regulator is
provided by the VDDQ rail, the overcurrent protection on the
VDDQ rail will limit the amount of current that the VTT rail will
sink.
When sinking current or at a no load condition, the inductor
valley current is negative, see Figure 36. During any time when
the inductor valley current is negative and the ISL70003A is
exposed to a heavy ion environment the abs max PVIN voltage
must be ≤13.7V, see Note 5 on page 11.
SEL1 and SEL2 may be tied together and used to place the V TT
regulator in sleep mode, common to DDR applications. The
outputs will be tri-stated, however the buffer amplifier is still
active and the VREF voltage will be present even if the VTT is in
sleep mode. When SEL1 and SEL2 are asserted low, the V TT
regulator will ramp-up the voltage. The ramp is controlled and
timing is based on soft-start capacitor value.
Refer to Figure 5 on page 10 for complete DDR power solution
typical application circuit schematic.
Operational Envelope
The ISL70003ASEH, is rated for operation across a PVIN of 3V to
13.2V, for a VOUT of 0.6V to ~11.9V, and an output current up to
9A, with a 500kHz switching frequency and to a +125°C die
temperature. While rated to these conditions, operation is not
simultaneously all inclusive as there are combinations of these
conditions, particularly at the extremes, where it will not operate,
thus defining a conditional operation envelope.
Figures 13 and 18 show the reduced output current capability for
the PVIN = 3.3V, VOUT = 2.5V condition illustrating one corner of
the envelope where the ratio of VOUT to PVIN is too high in
combination with the temperature and current extremes. The
converter runs into regulation issues with a 500kHz switching
frequency due to inadequate off time being realized under these
conditions. Another conditional operation corner, being the
situation where the ratio of VOUT to PVIN is too low and the result
is current limiting. In both of these extreme conditions the
maximum output current capability is reduced and output
accuracy is compromised.
These graphs are to be considered illustrative of the operation
envelope and not guidance. Users must characterize and
evaluate their circuit performance to their satisfaction when
approaching the extreme conditions of voltage, current and
temperature.
FN8746.0
August 5, 2015
ISL70003ASEH
High Current Protection Clamp
When using the ISL70003ASEH to output >6A it is necessary to
implement a LX to PGND Schottky diode clamp to prevent
damage to the lower power FET devices. The MBRS320T3G diode
is used on the ISL70003ASEHEV1Z evaluation platform.
Derating Current Capability
Most space programs issue specific derating guidelines for parts,
but these guidelines take the pedigree of the part into account.
For instance, a device built to MIL-PRF-38535, such as the
ISL70003ASEH, is already heavily derated from a current density
standpoint. However, a mil-temp or commercial IC that is
up-screened for use in space applications may need additional
current derating to ensure reliable operation because it was not
built to the same standards as the ISL70003ASEH.
V IN – V OUT V OUT
I = --------------------------------------------  ---------------f SW  L
V IN
V OUT = I  ESR
(EQ. 13)
Increasing the value of inductance reduces the ripple current and
output voltage ripple. However, the large inductance values
reduce the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a load
transient is the time required to change the inductor current. The
response time is the time required to slew the inductor current
from an initial current value to the transient current level. During
this interval the difference between the inductor current and the
transient current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the application of
load and the removal of load. Equation 14, gives the approximate
response time interval for application and removal of a transient
load.
tRISE =
L x ITRAN
VIN - VOUT
tFALL =
L x ITRAN
(EQ. 14)
VOUT
Where ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. The worst case response
time can be either at the application or removal of load. Be sure
to check both Equations 13 and 14 at the minimum and
maximum output levels for the worst case response time.
FIGURE 56. CURRENT vs TEMPERATURE
Figure 56 shows the wear out maximum average output current
of the ISL70003ASEH with respect to junction temperature for
0.1% failure at 100k hours of operation. This plot takes into
account the worst-case current share mismatch in the power
blocks and the current density requirement of MIL-PRF-38535
(< 2 x 105 A/cm2). The plot clearly shows that the
ISL70003ASEH can handle 7A at +150°C from a worst-case
current density standpoint, but the part is rated to 6A. Therefore,
no further current derating of the ISL70003ASEH is needed.
General Design Guide
This design guide is intended to provide a high-level explanation
of the steps necessary to design the power stage and feedback
compensation network of a single phase power converter. It is
assumed that the reader is familiar with many of the basic skills
and techniques in switch mode power supply design. In addition
to this guide, Intersil provides an evaluation board that includes
schematic, bills of materials and board layout.
Output Inductor Selection
The output inductor is selected to minimize the converter’s
response time to a load transient and meet steady state output
voltage ripple requirements. The inductor value determines the
converter’s inductor ripple current and the output voltage ripple
is a function of the inductor ripple current. The output voltage
ripple and the inductor ripple current are approximated by using
Equation 13:
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28
Output Capacitor Selection
An output capacitor is required to filter the inductor current and
supply the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current. The
load transient requirements are a function of the slew rate (di/dt)
and the magnitude of the transient load current. These
requirements are generally met with a mix of capacitors and
careful layout.
High-frequency capacitors initially supply the transient and slow
the current load rate seen by the bulk capacitors. The bulk filter
capacitor values are generally determined by the ESR (Effective
Series Resistance) and voltage rating requirements rather than
actual capacitance requirements.
High-frequency decoupling capacitors should be placed as close
to the power pins of the load as physically possible. Be careful
not to add inductance in the circuit board wiring that could
cancel the usefulness of these low inductance components.
The shape of the output voltage waveform during a load transient
that represents the worst case loading conditions will ultimately
determine the number of output capacitors and their type. When
this load transient is applied to the converter, most of the energy
required by the load is initially delivered from the output
capacitors. This is due to the finite amount of time required for
the inductor current to slew up to the level of the output current
required by the load. This phenomenon results in a temporary dip
in the output voltage. At the very edge of the transient, the
Equivalent Series Inductance (ESL) of each capacitor induces a
spike that adds on top of the existing voltage drop due to the
Equivalent Series Resistance (ESR).
FN8746.0
August 5, 2015
ISL70003ASEH
After the initial spike, attributable to the ESR and ESL of the
capacitors, the output voltage experiences sag. This sag is a
direct consequence of the amount of capacitance on the output.
1
ESL = -----------------------------------------------------2
C  2 ²  ² f res 
(EQ. 17)
Where: fres is the frequency where the lowest impedance is
achieved (resonant frequency).
The ESL of the capacitors becomes a concern when designing
circuits that supply power to loads with high rates of change in
the current.
ΔVHUMP
VOUT
ΔVESR
Input Capacitor Selection
ΔVSAG
ΔVESL
IOUT
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capacitors for
high-frequency decoupling and bulk capacitors to supply the
current needed each time the upper MOSFET turns on. Place the
small ceramic capacitors physically close to the MOSFETs and
between the drain of the upper MOSFET and the source of the
lower MOSFET.
ITRAN
FIGURE 57. TYPICAL TRANSIENT RESPONSE
During the removal of the same output load, the energy stored in
the inductor is dumped into the output capacitors. This energy
dumping creates a temporary hump in the output voltage. This
hump, as with the sag, can be attributed to the total amount of
capacitance on the output. Figure 57 shows a typical response to
a load transient.
The amplitudes of the different types of voltage excursions can
be approximated using Equation 15.
dI tran
V ESL = ESL ² --------------------dt
V ESR = ESR ² I tran
The important parameters for the bulk input capacitance are the
voltage rating and the RMS current rating. For reliable operation,
select bulk capacitors with voltage and current ratings above the
maximum input voltage and largest RMS current required by the
circuit. Their voltage rating should be at least 1.25x greater than
the maximum input voltage, while a voltage rating of 1.5x is a
conservative guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
The maximum RMS current through the input capacitors may be
closely approximated using Equation 18:
2
V OUT
V OUT 
2 
1  V IN – V OUT V OUT 
---------------- x  I OUT
x 1 – ---------------- + --------- x  ---------------------------------- x ---------------- 


V IN
MAX
V IN 
V IN  
12  Lxf OSC
2
L OUT ² I tran
V SAG = ---------------------------------------------------------------------------C OUT ²  V IN – V OUT 
2
L OUT ² I tran
V HUMP = ------------------------------------------------C OUT ² V OUT
(EQ. 15)
Where Itran = Output Load Current Transient and COUT = Total
Output Capacitance
In a typical converter design, the ESR of the output capacitor
bank dominates the transient response. The ESR and the ESL are
typically the major contributing factors in determining the output
capacitance. The number of output capacitors can be
determined by using Equation 16, which relates the ESR and ESL
of the capacitors to the transient load step and the voltage limit
(ΔVo).
ESL ² dI tran
------------------------------------------+ ESR ² Itran
dt
Number of Capacitors = --------------------------------------------------------------------------------------------V o
(EQ. 16)
(EQ. 18)
For surface mount designs, solid tantalum capacitors can be
used, but caution must be exercised with regard to the capacitor
surge current rating. These capacitors must be capable of
handling the surge current at power-up. Some capacitor series
available from reputable manufacturers are surge current tested.
Feedback Compensation
Figure 58 highlights the voltage-mode control loop for a
synchronous rectified buck converter. The output voltage (VOUT)
is regulated to the reference voltage level. The error amplifier
output (VEA) is compared with the oscillator (OSC) triangular
wave to provide a pulse-width modulated (PWM) wave with an
amplitude of VIN at the PHASE node. The PWM wave is smoothed
by the output filter (LO and CO).
If ΔVSAG and/or ΔVHUMP are found to be too large for the output
voltage limits, then the amount of capacitance may need to be
increased. In this situation, a trade-off between output
inductance and output capacitance may be necessary.
The ESL of the capacitors, which is an important parameter in
the previous equations, is not usually listed in databooks.
Practically, it can be approximated using Equation 17 if an
Impedance vs Frequency curve is given for a specific capacitor:
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29
FN8746.0
August 5, 2015
ISL70003ASEH
VIN
PWM
COMPARATOR
+
ΔVOSC
100
LO
DRIVER
PHASE
VEA
40
20
20LOG
(R2/R1)
20LOG
(VIN/DVOSC)
0
-60
fLC
10
100
1k
DETAILED COMPENSATION COMPONENTS
C2
1. Pick gain (R2/R1) for desired converter bandwidth.
FB
2. Place 1st zero below filter’s double pole (~75% FLC).
R4
3. Place 2nd zero at filter’s double pole.
4. Place 1st pole at the ESR zero.
REFERENCE
5. Place 2nd pole at half the switching frequency.
R 1

V
= 0.6 ¥  1 + -------
OUT
R 4

6. Check gain against error amplifier’s open-loop gain.
FIGURE 58. VOLTAGE-MODE BUCK CONVERTER COMPENSATION
The modulator transfer function is the small-signal transfer
function of VOUT/VEA . This function is dominated by a DC Gain and
the output filter (LO and CO), with a double pole break frequency at
fLC and a zero at fESR . The DC gain of the modulator is simply the
input voltage (VIN) divided by the peak-to-peak oscillator voltage
ΔVOSC . The ISL70003ASEH incorporates a feed-forward loop that
accounts for changes in the input voltage. This maintains a
constant modulator gain of 5, typical.
Modulator Break Frequency Equations
LC =
1
-----------------------------------------2 x L O x C O
1
f ESR = ------------------------------------------2 x ESR x C O
(EQ. 19)
The compensation network consists of the error amplifier and
the impedance networks ZIN and ZFB. The goal of the
compensation network is to provide a closed loop transfer
function with the highest 0dB crossing frequency (f0dB) and
adequate phase margin. Phase margin is the difference between
the closed loop phase at f0dB and 180°.
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10M
Equation 20 relates the compensation network’s poles, zeros
and gain to the components (R1 , R2 , R3 , C1 , C2 and C3) in
Figure 58. Use these guidelines for locating the poles and zeros
of the compensation network:
R3
R1
VERR
+
1M
VOUT
ZIN
C3
R2
fESR
10k
100k
FREQUENCY (Hz)
FIGURE 59. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
ZFB
C1
COMPENSATION
GAIN
CLOSED LOOP
GAIN
MODULATOR
GAIN
-40
REFERENCE
ERROR
AMP
fP2
OPEN LOOP
ERROR AMP GAIN
-20
ZIN
+
fP1
60
CO
ESR
(PARASITIC)
ZFB
fZ1 fZ2
80
VOUT
GAIN (dB)
DRIVER
OSC
30
7. Estimate phase margin - repeat if necessary.
Compensation Break Frequency Equations
1
f Z1 = -----------------------------------2 x R 2 x C 1
1
f P1 = -------------------------------------------------------- C 1 x C 2
2 x R 2 x  ----------------------
 C1 + C2 
1
f Z2 = ------------------------------------------------------2 x  R 1 + R 3  x C 3
1
f P2 = -----------------------------------2 x R 3 x C 3
(EQ. 20)
Figure 59 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual modulator gain has a high gain
peak due to the high Q factor of the output filter and is not shown
in Figure 59. Using the guidelines provided should give a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at fP2 with the capabilities of the error
amplifier. The closed loop gain is constructed on the graph of
Figure 59 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying the
modulator transfer function to the compensation transfer
function and plotting the gain. The compensation gain uses
external impedance networks ZFB and ZIN to provide a stable,
high bandwidth (BW) overall loop. A stable control loop has a
gain crossing with -20dB/decade slope and a phase margin
greater than +45°. Include worst case component variations
when determining phase margin. A more detailed explanation of
voltage mode control of a buck regulator can be found in Tech
Brief TB417, entitled “Designing Stable Compensation Networks
for Single Phase Voltage Mode Buck Regulators”.
FN8746.0
August 5, 2015
ISL70003ASEH
PCB Design
LX Connection
PCB design is critical to high frequency switching regulator
performance. Careful component placement and trace routing
are necessary to reduce voltage spikes and minimize
undesirable voltage drops. Selection of a suitable thermal
interface material is also required for optimum heat dissipation
and to provide lead strain relief.
Optimize load regulation by reducing noise from the power and
digital grounds into the analog ground by splitting ground into 3
planes; analog, digital and power. Bypass or ground pins
accordingly to their design preferred ground, see pin description
table and Figure 4 for guidance. Independently tie each of the
analog and digital grounds to power ground via a single trace in a
low noise area.
PCB Plane Allocation
A minimum of four layers of two ounce copper are
recommended. Layer 2 should be a dedicated ground plane with
all critical component ground connections made with vias to this
layer. Layer 3 should be a dedicated power plane split between
the input and output power rails. Layers 1 and 4 should be used
primarily for signals, but can also provide additional power and
ground islands as required.
PCB Component Placement
Locate the output voltage resistive divider as close as possible to
the FB pin of the IC. The top leg of the divider should connect
directly to the output of the inductor via a kelvin trace and the
bottom leg of the divider should connect directly to AGND pin.
This AGND connection should also be a kelvin trace connected to
the closest ground to the inductor output. The junction of the
resistive divider should connect directly to the FB pin.
Place a Schottky clamp diode as close as possible to the LXx and
PGNDx pins of the IC. A small series R-C snubber connected from
the LXx pins to the PGNDx pins may be used to damp highfrequency ringing on the LXx pins, see Figure 60.
LOUT
RS
3A
VOUT
COUT
CS
ERROR
AMPLIFIER
+
Keep all other signal traces as short as possible.
Lead Strain Relief
The package leads protrude from the bottom of the package and
the leads need forming to provide strain relief. On the heatsink
option of the package R64.C, the lead forming should be made
so that the bottom of the heatsink and the formed leads are
flush.
Heatsink Mounting Guidelines
The R64.C package option has a heatsink mounted on the
underside of the package. The following JESD-51x series
guidelines may be used to mount the package:
1. Place a thermal land on the PCB under the heatsink.
2. The land should be approximately the same size as to 1mm
larger than the 10.16x10.16mm heatsink.
3. Place an array of thermal vias below the thermal land.
Components should be placed as close as possible to the IC to
minimize stray inductance and resistance. Prioritize the
placement of bypass capacitors on the pins of the IC in the order
shown: REF, SS, AVDD, DVDD, PVINx (high-frequency capacitors),
EN, PGOOD, PVINx (bulk capacitors).
LXx
Use a small island of copper to connect the LXx pins of the IC to
the output inductor on layers 1 and 4. Void the copper on layers 2
and 3 adjacent to the island to minimize capacitive coupling to
the power and ground planes. Place most of the island on layer 4
to minimize the amount of copper that must be voided from the
ground plane (layer 2).
- Via array size: ~9x9 = 81 thermal vias.
- Via diameter: ~0.3mm drill diameter with plated copper on
the inside of each via.
- Via pitch: ~1.2mm.
- Vias should drop to and contact as much metal area as
feasible to provide the best thermal path.
Heatsink Electrical Potential
The heatsink is connected to pin 50 within the package; thus the
PCB design and potential applied to pin 50 will therefore define
the heatsink potential.
Heatsink Mounting Materials
In the case of electrically conductive mounting methods
(conductive epoxy, solder, etc.) the thermal land, vias and
connected plane(s) below must be the same potential as pin 50.
In the case of electrically nonconductive mounting methods
(nonconductive epoxy), the heatsink and pin 50 could have
different electrical potential than the thermal land, vias and
connected plane(s) below.
RT
PGNDx
FB
RB
NI
REF
CREF
FIGURE 60. SCHOTTKY DIODE AND R-C SNUBBER
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FN8746.0
August 5, 2015
ISL70003ASEH
Package Characteristics
BACKSIDE FINISH
Silicon
Weight of Packaged Device
PROCESS
2.65 Grams (typical) - R64.C Package
0.6µM BiCMOS Junction Isolated
Lid Characteristics
ASSEMBLY RELATED INFORMATION
Finish: Gold
Lid Potential: PGND
Substrate and Lid Potential
PGND
Die Characteristics
ADDITIONAL INFORMATION
Die Dimensions
Worst Case Current Density
8300µm x 8300µm (327 mils x 327 mils)
Thickness: 300µm ± 25.4µm (12 mils ± 1 mil)
<2 x 105 A/cm2
Transistor Count
Interface Materials
26,144
GLASSIVATION
Type: Silicon Oxide and Silicon Nitride
Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm
TOP METALLIZATION
Type: AlCu (99.5%/0.5%)
Thickness: 2.7µm ±0.4µm
Metallization Mask Layout
LX8
PVIN8
PGND8
LX7
PGND7
PVIN7
LX6
PVIN6
PGND6
LX5
PGND5
PVIN5
LX4
PVIN4
PGND4
LX3
PGND3
PVIN3
ISL70003ASEH
DE
PVIN2
PVIN9
LX2
LX9
PGND2
PGND9
PGND1
PGND10
LX1
LX10
PVIN1
PVIN10
SEL2
SEL1
IMON
SGND
OCSETA
PGOOD
OCSETB
GND
GND
GND
GND
GND
BUFIN+
BUFINBUFOUT
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32
SYNC
SS
RTCT
F300
ENABLE
VREFD
VDDD
VREF_OUTS
GNDD
GNDA
VDDA
VREFA
VERR
POR_VIN
FB
ORIGIN
NI
VREF
FN8746.0
August 5, 2015
ISL70003ASEH
TABLE 2. LAYOUT X-Y COORDINATES
PAD NUMBER
X
(µm)
Y
(µm)
dX
(µm)
dY
(µm)
BOND WIRES
SIZE (0.001”)
NI
1
0
0
135
135
1.5
FB
2
452
0
135
135
1.5
Verr
3
929
0
135
135
1.5
POR_VIN
4
1371
0
135
135
1.5
VrefA
5
1854
58
254
254
3
VDDA
6
2577
60
254
254
3
GNDA
7
3104
60
254
254
3
GNDD
8
3589
60
254
254
3
Vref OUTs
9
4035
60
254
254
3
VDDD
10
4713
60
254
254
3
VrefD
11
5420
60
254
254
3
ENABLE
12
5846
0
135
135
1.5
RtCt
13
6274
0
135
135
1.5
F300
14
6579
0
135
135
1.5
Sync
15
6976
0
135
135
1.5
SS Cap
16
7201
51
135
135
1.5
TDI
17
7201
345
135
135
1.5
Zap
18
7201
639
135
135
1.5
TDO
19
7201
934
135
135
1.5
TST Trim
20
7201
1228
135
135
1.5
TCLK
21
7201
1522
135
135
1.5
Pgood
22
7201
1902
135
135
1.5
SEL1
23
7201
2275
135
135
1.5
SEL2
24
7201
2569
135
135
1.5
PVin10
25
7140
3285
254
254
3
LX10
26
6350
3771
254
254
3
PGND10
27
5387
4179
254
254
3
PGND9
28
5387
4625
254
254
3
LX9
29
6350
5033
254
254
3
PVin9
30
7140
5518
254
254
3
Deon
31
7220
6303
135
135
1.5
PVin8
32
7140
7578
254
254
3
LX8
33
6655
6788
254
254
3
PGND8
34
6247
5825
254
254
3
PGND7
35
5801
5825
254
254
3
LX7
36
5393
6788
254
254
3
PVin7
37
4908
7578
254
254
3
PVin6
38
4497
7578
254
254
3
LX6
39
4011
6788
254
254
3
PAD NAME
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FN8746.0
August 5, 2015
ISL70003ASEH
TABLE 2. LAYOUT X-Y COORDINATES (Continued)
PAD NUMBER
X
(µm)
Y
(µm)
dX
(µm)
dY
(µm)
BOND WIRES
SIZE (0.001”)
PGND6
40
3603
5825
254
254
3
PGND5
41
3157
5825
254
254
3
LX5
42
2749
6788
254
254
3
PVin5
43
2264
7578
254
254
3
PVin4
44
1853
7578
254
254
3
LX4
45
1367
6788
254
254
3
PGND4
46
960
5825
254
254
3
PGND3
47
514
5825
254
254
3
LX3
48
106
6788
254
254
3
PVin3
49
-379
7578
254
254
3
PVIN2
50
-379
5518
254
254
3
LX2
51
411
5033
254
254
3
PGND2
52
1374
4625
254
254
3
PGND1
53
1374
4179
254
254
3
LX1
54
411
3771
254
254
3
PVin1
55
-379
3285
254
254
3
Imon
56
-438
2561
135
135
1.5
sgnd
57
-438
2201
135
135
1.5
OCSETA
58
-438
1841
135
135
1.5
OCSETB
59
-438
1481
135
135
1.5
Buf IN +
60
-438
1121
135
135
1.5
Buf IN -
61
-438
761
135
135
1.5
Buf OUT
62
-438
401
135
135
1.5
Vref
63
-438
41
135
135
1.5
PAD NAME
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FN8746.0
August 5, 2015
ISL70003ASEH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
August 5, 2015
FN8746.0
CHANGE
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/supportl
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN8746.0
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ISL70003ASEH
Package Outline Drawing
R64.C
64 CERAMIC QUAD FLATPACK PACKAGE (CQFP) WITH BOTTOM HEATSINK
Rev 1, 10/13
1.118 (28.40)
1.080 (27.43)
0.567 (14.40)
0.547 (13.90)
0.290 (7.37)
0.255 (6.48)
64
0.025 (0.635) BSC
1
49
PIN 1
INDEX AREA
48
0.567 (14.40)
0.547 (13.90)
1.118 (28.40)
1.080 (27.43)
0.010 (0.25)
0.006 (0.15)
33
16
17
32
SEE DETAIL "A"
TOP VIEW
0.0075 (0.188)
0.005 (0.125)
0.135 (3.43)
0.111 (2.82)
SIDE VIEW
HEATSINK
0.405 (10.29)
0.395 (10.03)
0.380 (9.655)
0.370 (9.395)
0.100 (2.537)
0.085 (2.157)
0.008 (0.20)
REF
0.048 (1.22)
REF
0.026 (0.66) MIN. 2
HEATSINK
DETAIL "A"
PIN 1
INDEX AREA
0.405 (10.29)
0.395 (10.03)
1
64
NOTES:
1. All dimensions are in inches (millimeters)
BOTTOM VIEW
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36
2. Dimension shall be measured at point of exit
(beyond the meniscus) of the lead from the body.
FN8746.0
August 5, 2015