AD AD8104 600 mhz, 32 16 buffered analog crosspoint switch Datasheet

600 MHz, 32 × 16 Buffered
Analog Crosspoint Switch
AD8104/AD8105
APPLICATIONS
Routing of high speed signals including
RGB and component video routing
KVM
Compressed video (MPEG, wavelet)
Data communications
GENERAL DESCRIPTION
The AD8104/AD8105 are high speed, 32 × 16 analog crosspoint
switch matrices. They offer 600 MHz bandwidth and slew rate of
1800 V/μs for high resolution computer graphics (RGB) signal
switching. With less than −70 dB of crosstalk and −90 dB isolation (@ 5 MHz), the AD8104/AD8105 are useful in many high
speed applications. The 0.1 dB flatness, which is greater than
50 MHz, makes the AD8104/AD8105 ideal for composite video
switching.
The AD8104/AD8105 include 16 independent output buffers
that can be placed into a high impedance state for paralleling
crosspoint outputs so that off-channels present minimal loading
to an output bus. The AD8104 has a differential gain of +1,
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5
VDD
DGND
AD8104/
AD8105
A0
A1
A2
A3
SER/PAR
0
192-BIT SHIFT REGISTER
WITH 6-BIT
PARALLEL LOADING
DATA IN
96
96
UPDATE
PARALLEL LATCH
RESET
DATA
OUT
NO
CONNECT
96
DECODE
16 × 6:32 DECODERS
INPUT
RECEIVER
G = +1*
G = +2**
512
16
OUTPUT
BUFFER
G = +1
2
ENABLE/DISABLE
2
SWITCH
MATRIX
*AD8104 ONLY
**AD8105 ONLY
VPOS
VNEG
16 OUTPUT PAIRS
1
SET INDIVIDUAL, OR
RESET ALL OUTPUTS TO OFF
WE
CLK
32 INPUT PAIRS
High channel count, 32 × 16 high speed, nonblocking
switch array
Differential or single-ended operation
Differential G = +1 (AD8104) or G = +2 (AD8105)
Pin compatible with AD8117/AD8118, 32 × 32 switch arrays
Flexible power supplies
Single +5 V supply, or dual ±2.5 V supplies
Serial or parallel programming of switch array
High impedance output disable allows connection of
multiple devices with minimal loading on output bus
Excellent video performance
>50 MHz 0.1 dB gain flatness
0.05% differential gain error (RL = 150 Ω)
0.05° phase error (RL = 150 Ω)
Excellent ac performance
Bandwidth: 600 MHz
Slew rate: 1800 V/μs
Settling time: 2.5 ns to 1%
Low power of 1.7 W
Low all hostile crosstalk
< −70 dB @ 5 MHz
< −40 dB @ 600 MHz
Reset pin allows disabling of all outputs (connected through
a capacitor to ground provides power-on reset capability)
304-ball BGA package (31 mm × 31 mm)
VOCM
06612-001
FEATURES
Figure 1.
while the AD8105 has a differential gain of +2 for ease of use
in back-terminated load applications. They operate as fully
differential devices or can be configured for single-ended
operation. Either a single +5 V supply or dual ±2.5 V supplies
can be used, while consuming only 340 mA of idle current with
all outputs enabled. The channel switching is performed via a
double-buffered, serial digital control (which can accommodate
daisy-chaining of several devices), or via a parallel control,
allowing updating of an individual output without reprogramming the entire array.
The AD8104/AD8105 are packaged in a 304-ball BGA package
and are available over the extended industrial temperature
range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
AD8104/AD8105
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................7
Applications....................................................................................... 1
Pin Configuration and Function Descriptions..............................8
Functional Block Diagram .............................................................. 1
Truth Table and Logic Diagram ............................................... 13
General Description ......................................................................... 1
I/O Schematics................................................................................ 15
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 17
Specifications..................................................................................... 3
Theory of Operation ...................................................................... 25
Timing Characteristics (Serial Mode) ....................................... 5
Applications Information .............................................................. 26
Timing Characteristics (Parallel Mode) .................................... 6
Programming.............................................................................. 26
Absolute Maximum Ratings............................................................ 7
Operating Modes........................................................................ 27
Thermal Resistance ...................................................................... 7
Outline Dimensions ....................................................................... 36
Power Dissipation......................................................................... 7
Ordering Guide .......................................................................... 36
REVISION HISTORY
6/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD8104/AD8105
SPECIFICATIONS
VS = ±2.5 V at TA = 25°C, RL, diff = 200 Ω, VOCM = 0 V, differential I/O mode, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Gain Flatness
Propagation Delay
Settling Time
Slew Rate
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
Differential Phase Error
Crosstalk, All Hostile
Off Isolation, Input-to-Output
Input Voltage Noise
DC PERFORMANCE
Voltage Gain
Gain Error
Gain Matching
Differential Offset
Common-Mode Offset
OUTPUT CHARACTERISTICS
Output Impedance
Output Disable Capacitance
Output Leakage Current
Output Voltage Range
VOCM Input Range
Output Swing Limit
Output Current
INPUT CHARACTERISTICS
Input Voltage Range
Common-Mode Rejection Ratio
Input Capacitance
Input Resistance
Input Offset Current
VOCM Input Bias Current
VOCM Input Impedance
Conditions
Min
AD8104/AD8105
Typ
Max
Unit
200 mV p-p, typical channel
2 V p-p, typical channel
0.1 dB, 200 mV p-p
0.1 dB, 2 V p-p
2 V p-p
1%, 2 V step
2 V step, peak
2 V step, 10% to 90%
600
420/525
100/50
70/50
1.3
2.5
1800
1500
MHz
MHz
MHz
MHz
ns
ns
V/μs
V/μs
NTSC or PAL, RL = 150 Ω
NTSC or PAL, RL = 150 Ω
f = 5 MHz
f = 10 MHz
f = 100 MHz
f = 600 MHz
f = 10 MHz, one channel
0.1 MHz to 50 MHz
0.05
0.05
−80/−70
−72/−68
−48/−50
−40/−50
−90
45/53
%
Degrees
dB
dB
dB
dB
dB
nV/√Hz
Differential
+1/+2
±1
±1
±1
±5
±25
V/V
%
%
%
mV
mV
No load
Channel-to-channel
DC, enabled
Disabled, differential
Disabled
Disabled
No load
VOUT, diff = 2 V p-p
VOUT, diff = 2.8 V p-p
Single-ended output
Maximum operating signal
Common mode, VIN, diff = 2 V p-p
Differential
f = 10 MHz
Any switch configuration
Differential
Rev. 0 | Page 3 of 36
2.8
−0.5
−0.25
−1.3
±3
±25
±90
0.1
30
4
1
3.8
+0.8
+0.6
+1.3
30
−2
+2
2/1
48
2
5
1
64
4
Ω
kΩ
pF
μA
V p-p
V
V
V
mA
V
V
dB
pF
kΩ
μA
μA
kΩ
AD8104/AD8105
Parameter
SWITCHING CHARACTERISTICS
Enable On Time
Switching Time, 2 V Step
Switching Transient (Glitch)
POWER SUPPLIES
Supply Current
Supply Voltage Range
PSRR
OPERATING TEMPERATURE RANGE
Temperature Range
θJA
θJC
Conditions
Min
AD8104/AD8105
Typ
Max
50% update to 1% settling
50% update to 1% settling
Differential
100
100
40
VPOS, outputs enabled, no load
VPOS, outputs disabled
VNEG, outputs enabled, no load
VNEG, outputs disabled
VDD, outputs enabled, no load
340
210
340
210
Unit
ns
ns
mV p-p
VNEG, VPOS, f = 1 MHz
VOCM, f = 1 MHz
4.5 to 5.5
85
75
mA
mA
mA
mA
mA
V
dB
dB
Operating (still air)
Operating (still air)
Operating (still air)
−40 to +85
14
1
°C
°C/W
°C/W
Rev. 0 | Page 4 of 36
420
240
420
240
1.2
AD8104/AD8105
TIMING CHARACTERISTICS (SERIAL MODE)
Specifications subject to change without notice.
Table 2.
Parameter
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to DATA OUT Valid
Propagation Delay, UPDATE to Switch On or Off
RESET Pulse Width
RESET Time
Symbol
t1
t2
t3
t4
t5
t6
t7
Min
40
50
50
150
10
90
120
Limit
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
60
200
1
WE
0
t2
t4
1
CLK
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
0
t1
t3
1
DATA IN
OUT15 (D5)
OUT15 (D4)
OUT0 (D0)
0
t5
1 = LATCHED
t6
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
UPDATE
0 = TRANSPARENT
t7
06612-002
1
DATA OUT
0
Figure 2. Timing Diagram, Serial Mode
Table 3. Logic Levels
VIH
RESET,
SER/PAR, CLK,
DATA IN,
UPDATE
VIL
RESET,
SER/PAR, CLK,
DATA IN,
UPDATE
VOH
DATA OUT
VOL
DATA OUT
IIH
RESET1,
SER/PAR, CLK,
DATA IN, UPDATE
IIL
RESET1,
SER/PAR, CLK,
DATA IN, UPDATE
IOH
DATA OUT
IOL
DATA OUT
2.0 V min
0.6 V max
VDD − 0.3 V
min
DGND +
0.5 V max
1 μA max
–1 μA min
−1 mA max
1 mA min
1
See Figure 15.
Rev. 0 | Page 5 of 36
AD8104/AD8105
TIMING CHARACTERISTICS (PARALLEL MODE)
Specifications subject to change without notice.
Table 4.
Parameter
Parallel Data Setup Time
WE Pulse Width
Parallel Data Hold Time
WE Pulse Separation
WE to UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On or Off
RESET Pulse Width
RESET Time
t2
1
Symbol
t1
t2
t3
t4
t5
t6
Min
80
110
150
90
10
90
Limit
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
60
200
t4
WE
0
t1
t3
1
D0 TO D5
A0 TO A3
0
t5
t6
06612-003
1 = LATCHED
UPDATE
0 = TRANSPARENT
Figure 3. Timing Diagram, Parallel Mode
Table 5. Logic Levels
VIH
RESET, SER/PAR,
WE, D0, D1, D2,
D3, D4, D5, A0,
A1, A2, A3,
UPDATE
VIL
RESET, SER/PAR,
WE, D0, D1, D2,
D3, D4, D5, A0,
A1, A2, A3,
UPDATE
VOH
DATA OUT
VOL
DATA OUT
IIH
RESET 1 , SER/PAR, WE,
D0, D1, D2, D3, D4,
D5, A0, A1, A2, A3,
UPDATE
IIL
RESET1, SER/PAR,
WE, D0, D1, D2,
D3, D4, D5, A0, A1,
A2, A3, UPDATE
IOH
DATA OUT
IOL
DATA OUT
2.0 V min
0.6 V max
Disabled
Disabled
1 μA max
–1 μA min
Disabled
Disabled
1
See Figure 15.
Rev. 0 | Page 6 of 36
AD8104/AD8105
ABSOLUTE MAXIMUM RATINGS
POWER DISSIPATION
Table 6.
Rating
6V
The AD8104/AD8105 are operated with ±2.5 V or +5 V
supplies and can drive loads down to 100 Ω, resulting in a large
range of possible power dissipations. For this reason, extra care
must be taken derating the operating conditions based on
ambient temperature.
6V
+0.5 V to −2.5 V
8V
VNEG to VPOS
±2 V
VDD
(VPOS − 1 V) to (VNEG + 1 V)
Momentary
80 mA
−65°C to +125°C
−40°C to +85°C
300°C
Packaged in a 304-ball BGA, the AD8104/AD8105 junction-toambient thermal impedance (θJA) is 14°C/W. For long-term
reliability, the maximum allowed junction temperature of the
die should not exceed 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
stresses exerted on the die by the package. Exceeding a junction
temperature of 175°C for an extended period can result in
device failure. The following curve shows the range of allowed
internal die power dissipations that meet these conditions over
the −40°C to +85°C ambient temperature range. When using
Table 6, do not include external load power in the maximum
power calculation, but do include load current dropped on the
die output transistors.
8
TJ = 150°C
150°C
MAXIMUM POWER (W)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
4
15
35
45
55
65
75
85
Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature
Table 7. Thermal Resistance
θJC
1
25
AMBIENT TEMPERATURE (°C)
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
θJA
14
6
5
THERMAL RESISTANCE
Package Type
304-Ball BGA
7
06612-004
Parameter
Analog Supply Voltage
(VPOS – VNEG)
Digital Supply Voltage
(VDD – DGND)
Ground Potential Difference
(VNEG – DGND)
Maximum Potential Difference
(VDD – VNEG)
Common-Mode Analog Input
Voltage
Differential Analog Input Voltage
Digital Input Voltage
Output Voltage
(Disabled Analog Output)
Output Short-Circuit Duration
Output Short-Circuit Current
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(Soldering, 10 sec)
Junction Temperature
ESD CAUTION
θJB
6.5
ψJT
0.6
ψJB
5.7
Unit
°C/W
Rev. 0 | Page 7 of 36
AD8104/AD8105
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
VPOS
VPOS
VPOS
VPOS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VPOS
VPOS
VPOS
A
B
VPOS
VPOS
VPOS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VPOS
VPOS
VPOS
VPOS
B
C
VPOS
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VPOS
C
D
IN16
VPOS
VPOS
VNEG
VOCM
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VOCM
VNEG
VPOS
IP0
VPOS
D
E
IP16
IN17
VNEG
VOCM
VOCM
VNEG
IN0
IP1
E
F
IN18
IP17
VNEG
VDD
VDD
VNEG
IP2
IN1
F
G
IP18
IN19
VNEG
DGND
DGND
VNEG
IN2
IP3
G
H
IN20
IP19
VNEG
RESET
DATA
OUT
VNEG
IP4
IN3
H
J
IP20
IN21
VNEG
CLK
VNEG
IN4
IP5
J
VNEG
WE
DATA
IN
VNEG
IP6
IN5
K
SER/
PAR
VPOS
IN6
IP7
L
DGND
VPOS
IP8
IN7
M
K
IN22
IP21
L
IP22
IN23
VPOS
D5
M
IN24
IP23
VPOS
D4
N
IP24
IN25
VPOS
D3
A3
VPOS
IN8
IP9
N
P
IN26
IP25
VNEG
D2
A2
VNEG
IP10
IN9
P
R
IP26
IN27
VNEG
D1
A1
VNEG
IN10
IP11
R
T
IN28
IP27
VNEG
D0
A0
VNEG
IP12
IN11
T
U
IP28
IN29
VNEG
VDD
VDD
VNEG
IN12
IP13
U
V
IN30
IP29
VNEG
DGND
DGND
VNEG
IP14
IN13
V
W
IP30
IN31
VNEG
VOCM
VOCM
VNEG
IN14
IP15
W
Y
VPOS
IP31
VPOS
VNEG
VOCM
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VOCM
VNEG
VPOS
VPOS
IN15
Y
AA
VPOS
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VPOS
AA
AB
VPOS
VPOS
VPOS
VPOS
ON14
OP14
ON12
OP12
ON10
OP10
ON8
OP8
ON6
OP6
ON4
OP4
ON2
OP2
ON0
OP0
VPOS
VPOS
VPOS
AB
AC
VPOS
VPOS
VPOS
ON15
OP15
ON13
OP13
ON11
OP11
ON9
OP9
ON7
OP7
ON5
OP5
ON3
OP3
ON1
OP1
VPOS
VPOS
VPOS
VPOS
AC
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AD8104/AD8105
BOTTOM VIEW
(Not to Scale)
Figure 5. Package Bottom View
Rev. 0 | Page 8 of 36
06612-005
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
A
VPOS
VPOS
VPOS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VPOS
VPOS
VPOS
VPOS
A
B
VPOS
VPOS
VPOS
VPOS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VPOS
VPOS
VPOS
B
C
VPOS
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VPOS
C
D
VPOS
IP0
VPOS
VNEG
VOCM
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VOCM
VNEG
VPOS
VPOS
IN16
D
E
IP1
IN0
VNEG
VOCM
VOCM
VNEG
IN17
IP16
E
F
IN1
IP2
VNEG
VDD
VDD
VNEG
IP17
IN18
F
G
IP3
IN2
VNEG
DGND
DGND
VNEG
IN19
IP18
G
H
IN3
IP4
VNEG
DATA
OUT
RESET
VNEG
IP19
IN20
H
J
IP5
IN4
VNEG
CLK
VNEG
IN21
IP20
J
VNEG
DATA
IN
WE
VNEG
IP21
IN22
K
D5
VPOS
IN23
IP22
L
D4
VPOS
IP23
IN24
M
K
IN5
IP6
L
IP7
IN6
VPOS
SER/
PAR
M
IN7
IP8
VPOS
DGND
N
IP9
IN8
VPOS
A3
D3
VPOS
IN25
IP24
N
P
IN9
IP10
VNEG
A2
D2
VNEG
IP25
IN26
P
R
IP11
IN10
VNEG
A1
D1
VNEG
IN27
IP26
R
T
IN11
IP12
VNEG
A0
D0
VNEG
IP27
IN28
T
U
IP13
IN12
VNEG
VDD
VDD
VNEG
IN29
IP28
U
V
IN13
IP14
VNEG
DGND
DGND
VNEG
IP29
IN30
V
W
IP15
IN14
VNEG
VOCM
VOCM
VNEG
IN31
IP30
W
Y
IN15
VPOS
VPOS
VNEG
VOCM
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VOCM
VNEG
VPOS
IP31
VPOS
Y
AA
VPOS
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VPOS
AA
AB
VPOS
VPOS
VPOS
OP0
ON0
OP2
ON2
OP4
ON4
OP6
ON6
OP8
ON8
OP10
ON10
OP12
ON12
OP14
ON14
VPOS
VPOS
VPOS
VPOS
AB
AC
VPOS
VPOS
VPOS
VPOS
OP1
ON1
OP3
ON3
OP5
ON5
OP7
ON7
OP9
ON9
OP11
ON11
OP13
ON13
OP15
ON15
VPOS
VPOS
VPOS
AC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
AD8104/AD8105
TOP VIEW
(Not to Scale)
Figure 6. Package Top View
Table 8. Ball Grid Description
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
Mnemonic
VPOS
VPOS
VPOS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Description
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
Ball No.
A15
A16
A17
A18
A19
A20
A21
A22
A23
B1
B2
B3
B4
B5
Rev. 0 | Page 9 of 36
Mnemonic
NC
NC
NC
NC
NC
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
NC
Description
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
No Connect.
06612-006
AD8104/AD8105
AD8104/AD8105
Ball No.
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
D1
D2
D3
D4
D5
Mnemonic
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VPOS
VPOS
IP0
VPOS
VNEG
VOCM
D6
D7
D8
D9
D10
D11
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
Description
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Input Number 0, Positive Phase.
Analog Positive Power Supply.
Analog Negative Power Supply.
Output Common-Mode Reference
Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
Ball No.
D12
D13
D14
D15
D16
D17
D18
D19
Mnemonic
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VOCM
D20
D21
D22
VNEG
VPOS
VPOS
D23
E1
E2
E3
E4
IN16
IP1
IN0
VNEG
VOCM
Input Number 16, Negative Phase.
Input Number 1, Positive Phase.
Input Number 0, Negative Phase.
Analog Negative Power Supply.
Output Common-Mode Reference
Supply.
E20
VOCM
Output Common-Mode Reference
Supply.
E21
E22
E23
F1
F2
F3
F4
F20
F21
F22
F23
G1
G2
G3
G4
G20
G21
G22
G23
H1
H2
H3
H4
H20
H21
H22
H23
J1
J2
J3
J4
J20
VNEG
IN17
IP16
IN1
IP2
VNEG
VDD
VDD
VNEG
IP17
IN18
IP3
IN2
VNEG
DGND
DGND
VNEG
IN19
IP18
IN3
IP4
VNEG
DATA OUT
RESET
VNEG
IP19
IN20
IP5
IN4
VNEG
CLK
UPDATE
Analog Negative Power Supply.
Input Number 17, Negative Phase.
Input Number 16, Positive Phase.
Input Number 1, Negative Phase.
Input Number 2, Positive Phase.
Analog Negative Power Supply.
Logic Positive Power Supply.
Logic Positive Power Supply.
Analog Negative Power Supply.
Input Number 17, Positive Phase.
Input Number 18, Negative Phase.
Input Number 3, Positive Phase.
Input Number 2, Negative Phase.
Analog Negative Power Supply.
Logic Negative Power Supply.
Logic Negative Power Supply.
Analog Negative Power Supply.
Input Number 19, Negative Phase.
Input Number 18, Positive Phase.
Input Number 3, Negative Phase.
Input Number 4, Positive Phase.
Analog Negative Power Supply.
Control Pin: Serial Data Out.
Control Pin: Second Rank Data Reset.
Analog Negative Power Supply.
Input Number 19, Positive Phase.
Input Number 20, Negative Phase.
Input Number 5, Positive Phase.
Input Number 4, Negative Phase.
Analog Negative Power Supply.
Control Pin: Serial Data Clock.
Control Pin: Second Rank Write Strobe.
Rev. 0 | Page 10 of 36
Description
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Output Common-Mode Reference
Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
AD8104/AD8105
Ball No.
J21
J22
J23
K1
K2
K3
K4
K20
K21
K22
K23
L1
L2
L3
L4
L20
L21
L22
L23
M1
M2
M3
M4
M20
M21
M22
M23
N1
N2
N3
N4
N20
N21
N22
N23
P1
P2
P3
P4
P20
P21
P22
P23
R1
R2
R3
R4
R20
R21
R22
R23
T1
Mnemonic
VNEG
IN21
IP20
IN5
IP6
VNEG
DATA IN
WE
VNEG
IP21
IN22
IP7
IN6
VPOS
SER/PAR
D5
VPOS
IN23
IP22
IN7
IP8
VPOS
DGND
D4
VPOS
IP23
IN24
IP9
IN8
VPOS
A3
D3
VPOS
IN25
IP24
IN9
IP10
VNEG
A2
D2
VNEG
IP25
IN26
IP11
IN10
VNEG
A1
D1
VNEG
IN27
IP26
IN11
Description
Analog Negative Power Supply.
Input Number 21, Negative Phase.
Input Number 20, Positive Phase.
Input Number 5, Negative Phase.
Input Number 6, Positive Phase.
Analog Negative Power Supply.
Control Pin: Serial Data In.
Control Pin: First Rank Write Strobe.
Analog Negative Power Supply.
Input Number 21, Positive Phase.
Input Number 22, Negative Phase.
Input Number 7, Positive Phase.
Input Number 6, Negative Phase.
Analog Positive Power Supply.
Control Pin: Serial/Parallel Mode Select.
Control Pin: Input Address Bit 5.
Analog Positive Power Supply.
Input Number 23, Negative Phase.
Input Number 22, Positive Phase.
Input Number 7, Negative Phase.
Input Number 8, Positive Phase.
Analog Positive Power Supply.
Logic Negative Power Supply
Control Pin: Input Address Bit 4.
Analog Positive Power Supply.
Input Number 23, Positive Phase.
Input Number 24, Negative Phase.
Input Number 9, Positive Phase.
Input Number 8, Negative Phase.
Analog Positive Power Supply.
Control Pin: Output Address Bit 3.
Control Pin: Input Address Bit 3.
Analog Positive Power Supply.
Input Number 25, Negative Phase.
Input Number 24, Positive Phase.
Input Number 9, Negative Phase.
Input Number 10, Positive Phase.
Analog Negative Power Supply.
Control Pin: Output Address Bit 2.
Control Pin: Input Address Bit 2.
Analog Negative Power Supply.
Input Number 25, Positive Phase.
Input Number 26, Negative Phase.
Input Number 11, Positive Phase.
Input Number 10, Negative Phase.
Analog Negative Power Supply.
Control Pin: Output Address Bit 1.
Control Pin: Input Address Bit 1.
Analog Negative Power Supply.
Input Number 27, Negative Phase.
Input Number 26, Positive Phase.
Input Number 11, Negative Phase.
Ball No.
T2
T3
T4
T20
T21
T22
T23
Mnemonic
IP12
VNEG
A0
D0
VNEG
IP27
IN28
Description
Input Number 12, Positive Phase.
Analog Negative Power Supply.
Control Pin: Output Address Bit 0.
Control Pin: Input Address Bit 0.
Analog Negative Power Supply.
Input Number 27, Positive Phase.
Input Number 28, Negative Phase.
U1
U2
U3
U4
U20
U21
U22
U23
IP13
IN12
VNEG
VDD
VDD
VNEG
IN29
IP28
Input Number 13, Positive Phase.
Input Number 12, Negative Phase.
Analog Negative Power Supply.
Logic Positive Power Supply.
Logic Positive Power Supply.
Analog Negative Power Supply.
Input Number 29, Negative Phase.
Input Number 28, Positive Phase.
V1
V2
V3
V4
V20
V21
V22
V23
W1
W2
W3
W4
IN13
IP14
VNEG
DGND
DGND
VNEG
IP29
IN30
IP15
IN14
VNEG
VOCM
W20
VOCM
W21
W22
W23
Y1
Y2
Y3
Y4
Y5
VNEG
IN31
IP30
IN15
VPOS
VPOS
VNEG
VOCM
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
Input Number 13, Negative Phase.
Input Number 14, Positive Phase.
Analog Negative Power Supply.
Logic Negative Power Supply.
Logic Negative Power Supply.
Analog Negative Power Supply.
Input Number 29, Positive Phase.
Input Number 30, Negative Phase.
Input Number 15, Positive Phase.
Input Number 14, Negative Phase.
Analog Negative Power Supply.
Output Common-Mode Reference
Supply.
Output Common-Mode Reference
Supply.
Analog Negative Power Supply.
Input Number 31, Negative Phase.
Input Number 30, Positive Phase.
Input Number 15, Negative Phase.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Negative Power Supply.
Output Common-Mode Reference
Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Rev. 0 | Page 11 of 36
AD8104/AD8105
Ball No.
Y19
Mnemonic
VOCM
Y20
Y21
Y22
Y23
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
VNEG
VPOS
IP31
VPOS
VPOS
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
OP0
ON0
OP2
ON2
OP4
ON4
Description
Output Common-Mode Reference
Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
Input Number 31, Positive Phase.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Output Number 0, Positive Phase.
Output Number 0, Negative Phase.
Output Number 2, Positive Phase.
Output Number 2, Negative Phase.
Output Number 4, Positive Phase.
Output Number 4, Negative Phase.
Ball No.
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
Rev. 0 | Page 12 of 36
Mnemonic
OP6
ON6
OP8
ON8
OP10
ON10
OP12
ON12
OP14
ON14
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
OP1
ON1
OP3
ON3
OP5
ON5
OP7
ON7
OP9
ON9
OP11
ON11
OP13
ON13
OP15
ON15
VPOS
VPOS
VPOS
Description
Output Number 6, Positive Phase.
Output Number 6, Negative Phase.
Output Number 8, Positive Phase.
Output Number 8, Negative Phase.
Output Number 10, Positive Phase.
Output Number 10, Negative Phase.
Output Number 12, Positive Phase.
Output Number 12, Negative Phase.
Output Number 14, Positive Phase.
Output Number 14, Negative Phase.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Output Number 1, Positive Phase.
Output Number 1, Negative Phase.
Output Number 3, Positive Phase.
Output Number 3, Negative Phase.
Output Number 5, Positive Phase.
Output Number 5, Negative Phase.
Output Number 7, Positive Phase.
Output Number 7, Negative Phase.
Output Number 9, Positive Phase.
Output Number 9, Negative Phase.
Output Number 11, Positive Phase.
Output Number 11, Negative Phase.
Output Number 13, Positive Phase.
Output Number 13, Negative Phase.
Output Number 15, Positive Phase.
Output Number 15, Negative Phase.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
AD8104/AD8105
TRUTH TABLE AND LOGIC DIAGRAM
Table 9. Operation Truth Table
DATA
INPUT
X
DATA
OUTPUT
X
RESET
0
X
Datai 1
Datai-192
1
0
X
D0…D5 2
A0…A3 3
1
1
0
X
X
1
X
X
X
X
N/A in
parallel
mode
N/A in
parallel
mode
X
1
1
WE
X
UPDATE
X
1
X
0
X
1
1
CLK
X
1
Datai: serial data.
D0…D5: data bits.
3
A0…A3: address bits.
2
Rev. 0 | Page 13 of 36
SER/PAR
Operation/Comment
Asynchronous reset. All outputs are
disabled. Remainder of logic in 192-bit shift
register is unchanged.
Serial mode. The data on the serial DATA IN
line is loaded into the serial register. The first
bit clocked into the serial register appears
at DATA OUT 192 clock cycles later.
Parallel mode. The data on parallel lines D0
to D5 are loaded into the shift register
location addressed by A0 to A3.
Switch matrix update. Data in the 192-bit
shift register transfers into the parallel
latches that control the switch array.
No change in logic.
OUTPUT
ADDRESS
A0
A1
A2
A3
4 TO 16 DECODER
CLK
WE
DATA IN
(SERIAL)
Figure 7. Logic Diagram
Rev. 0 | Page 14 of 36
RESET
UPDATE
OUT15 EN
OUT14 EN
OUT13 EN
OUT12 EN
OUT11 EN
OUT10 EN
OUT9 EN
OUT8 EN
OUT7 EN
OUT6 EN
OUT5 EN
OUT4 EN
OUT3 EN
OUT2 EN
OUT1 EN
OUT0 EN
(OUTPUT ENABLE)
SER/PAR
D0
D1
D2
D3
D4
D5
OUT0
B0
CLR Q
ENA D
S
D1
Q D Q
D0 CLK
OUT0
B1
CLR Q
ENA D
S
D1
Q
Q D
D0 CLK
OUT0
B2
CLR Q
ENA D
S
D1
Q D Q
D0 CLK
512
OUT0
B4
CLR Q
ENA D
S
D1
Q DQ
D0 CLK
OUT0
EN
CLR Q
ENA D
S
D1
Q D Q
D0 CLK
SWITCH MATRIX
OUT0
B3
CLR Q
ENA D
S
D1
Q
Q D
D0 CLK
OUT1
B0
CLR Q
ENA D
S
D1
Q D Q
D0 CLK
DECODE
OUT14
EN
CLR Q
ENA D
S
D1
Q D Q
D0 CLK
OUT15
B0
CLR Q
ENA D
S
D1
Q DQ
D0 CLK
OUT15
B2
CLR Q
ENA D
S
D1
Q D Q
D0 CLK
16
OUTPUT ENABLE
OUT15
B1
CLR Q
ENA D
S
D1
Q D Q
D0 CLK
OUT15
B3
CLR Q
ENA D
S
D1
Q D Q
D0 CLK
OUT15
B4
CLR Q
ENA D
S
D1
D Q
Q
D0 CLK
OUT15
EN
CLR Q
ENA D
S
D1
Q
Q D
D0 CLK
DATA OUT
(SERIAL)
06612-007
PARALLEL DATA
AD8104/AD8105
AD8104/AD8105
I/O SCHEMATICS
IPn
1.3pF
2500Ω
1.3pF
2500Ω
06612-008
INn
06612-012
0.3pF
OPn, ONn
Figure 12. AD8104/AD8105 Receiver Simplified Equivalent Circuit When
Driving Differentially
Figure 8. AD8104/AD8105 Enabled Output
(see also ESD Protection Map, Figure 18)
OPn
IPn
3.4pF
3.33kΩ AD8104 G = +1
3.76kΩ AD8105 G = +2
1.6pF
30kΩ
06612-013
0.4pF
INn
3.4pF
06612-009
ONn
Figure 13. AD8104/AD8105 Receiver Simplified Equivalent Circuit When
Driving Single-Ended
Figure 9. AD8104/AD8105 Disabled Output
(see also ESD Protection Map, Figure 18)
2500Ω
IPn
2538Ω
1.3pF
VOCM
2538Ω
VNEG
Figure 10. AD8104 Receiver (see also ESD Protection Map, Figure 18)
2500Ω
IPn
5075Ω
VDD
1.3pF
25kΩ
0.3pF
2500Ω
5075Ω
06612-011
RESET
1.3pF
INn
Figure 14. VOCM Input (see also ESD Protection Map, Figure 18)
1kΩ
DGND
Figure 11. AD8105 Receiver (see also ESD Protection Map, Figure 18)
Rev. 0 | Page 15 of 36
06612-015
2500Ω
06612-010
1.3pF
INn
06612-014
0.3pF
Figure 15. Reset Input (see also ESD Protection Map, Figure 18)
AD8104/AD8105
VPOS
1kΩ
DGND
VNEG
VDD
06612-017
DATA OUT
DGND
DGND
Figure 18. ESD Protection Map
Figure 16. Logic Input (see also ESD Protection Map, Figure 18)
Figure 17. Logic Output (see also ESD Protection Map, Figure 18)
Rev. 0 | Page 16 of 36
06612-018
CLK, RESET,
SER/PAR, WE,
UPDATE,
DATA IN,
DATA OUT,
A[3:0], D[5:0]
IPn, INn,
OPn, ONn,
VOCM
06612-016
CLK, SER/PAR, WE,
UPDATE, DATA IN,
A[3:0], D[5:0]
VDD
AD8104/AD8105
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±2.5 V at TA = 25°C, RL, diff = 200 Ω, VOCM = 0 V, differential I/O mode, unless otherwise noted.
200
10
180
AD8105
6
160
4
140
120
AD8104
0
100
–2
80
–4
60
–6
40
–8
–10
1
100
10
06612-022
COUNT
2
06612-019
GAIN (dB)
8
20
0
1000
540
560
580
FREQUENCY (MHz)
640
660
700
800
AD8105
6
4
2
AD8104
0
–2
–4
06612-020
–6
–8
1
10
–1.0
–1.5
–2.0
1000
100
–0.5
06612-023
NORMALIZED BANDWIDTH ERROR (%)
0
8
0
2
FREQUENCY (MHz)
4
6
8
10
12
14
16
NUMBER OF ENABLED CHANNELS
Figure 20. AD8104, AD8105 Large Signal Frequency Response, 2 V p-p
Figure 23. AD8104 Bandwidth Error vs. Enabled Channels
10
0
DIFFERENTIAL OUT
8
–10
6
10pF
4
5pF
–20
2pF
2
CMR (dB)
NORMALIZED GAIN (dB)
680
Figure 22. AD8104 −3 dB Bandwidth Histogram,
One Device, All 512 Channels
10
GAIN (dB)
620
FREQUENCY (MHz)
Figure 19. AD8104, AD8105 Small Signal Frequency Response, 200 mV p-p
–10
600
0
–2
0pF
–4
–30
–40
–50
–6
–10
0
10
100
–70
300k
1000
FREQUENCY (MHz)
06612-024
–60
06612-021
–8
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 21. AD8104 Small Signal Frequency Response with Capacitive Loads,
200 mV p-p
Rev. 0 | Page 17 of 36
Figure 24. AD8104, AD8105 Common-Mode Rejection
2G
AD8104/AD8105
0
–15
DIFFERENTIAL OUT
DIFFERENTIAL IN/OUT
VNEG AGGRESSOR
–25
–20
–35
CROSSTALK (dB)
VPOS AGGRESSOR
PSR (dB)
–45
–55
VOCM AGGRESSOR
–65
–40
–60
–75
06612-025
–95
0.1
1
10
100
–100
300k
1000
06612-028
–80
–85
1M
Figure 25. AD8104 Power Supply Rejection
10
10M
0
SINGLE-ENDED OUT
0
DIFFERENTIAL IN/OUT
–20
–5
VOCM AGGRESSOR
CROSSTALK (dB)
–15
–20
VNEG AGGRESSOR
–30
–35
–40
–60
VPOS AGGRESSOR
–80
06612-026
–40
–45
1
10
100
–100
300k
1000
06612-029
PSR (dB)
–10
–50
0.1
1M
FREQUENCY (MHz)
10M
100M
1G
FREQUENCY (Hz)
Figure 29. AD8105 Crosstalk, One Adjacent Channel
Figure 26. AD8104 Power Supply Rejection, Single-Ended
0
180
SINGLE-ENDED IN/OUT
DIFFERENTIAL OUT
160
–20
140
AD8105
80
60
40
AD8104
10k
–60
–80
20
0
1k
–40
100k
–100
300k
1M
06612-030
100
CROSSTALK (dB)
120
06612-027
NOISE SPECTRAL DENSITY (nV/ Hz)
1G
Figure 28. AD8104 Crosstalk, One Adjacent Channel
5
–25
100M
FREQUENCY (Hz)
FREQUENCY (MHz)
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30. AD8104 Crosstalk, One Adjacent Channel, Single-Ended
Figure 27. AD8104, AD8105 Noise Spectral Density, RTO
Rev. 0 | Page 18 of 36
AD8104/AD8105
0
0
SINGLE-ENDED IN/OUT
–20
CROSSTALK (dB)
–20
–40
–60
–80
–40
–60
–80
–100
300k
06612-031
–100
1M
10M
100M
–120
300k
1G
06612-034
CROSSTALK (dB)
SINGLE-ENDED IN/OUT
1M
Figure 31. AD8105 Crosstalk, One Adjacent Channel, Single-Ended
0
SINGLE-ENDED IN/OUT
–20
–40
CROSSTALK (dB)
CROSSTALK (dB)
–20
–60
–80
–40
–60
–80
06612-032
–100
1M
10M
100M
–100
300k
1G
1M
FREQUENCY (Hz)
0
100M
1G
Figure 35. AD8105 Crosstalk, All Hostile, Single-Ended
0
DIFFERENTIAL IN/OUT
DIFFERENTIAL IN/OUT
–20
FEEDTHROUGH (dB)
–20
–40
–60
–40
–60
1M
10M
100M
–100
300k
1G
06612-036
–80
–80
06612-033
CROSSTALK (dB)
10M
FREQUENCY (Hz)
Figure 32. AD8104 Crosstalk, All Hostile
–100
300k
1G
Figure 34. AD8104 Crosstalk, All Hostile, Single-Ended
DIFFERENTIAL IN/OUT
–120
300k
100M
06612-035
0
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 33. AD8105 Crosstalk, All Hostile
Figure 36. AD8104 Crosstalk, Off Isolation
Rev. 0 | Page 19 of 36
1G
2G
AD8104/AD8105
0
30000
SINGLE-ENDED IN/OUT
25000
OUTPUT IMPEDANCE (Ω)
–40
–60
–80
20000
15000
10000
06612-037
5000
1M
10M
100M
1G
06612-040
FEEDTHROUGH (dB)
–20
–100
300k
DIFFERENTIAL OUT
0
100k
2G
1M
10M
FREQUENCY (Hz)
Figure 37. AD8104 Crosstalk, Off Isolation, Single-Ended
6000
100M
1G
FREQUENCY (Hz)
Figure 40. AD8104, AD8105 Output Impedance, Disabled
1000
DIFFERENTIAL IN
AD8105
5000
OUTPUT IMPEDANCE (Ω)
INPUT IMPEDANCE (Ω)
AD8104
4000
3000
2000
100
10
1
1M
10M
100M
06612-041
0
300k
06612-038
1000
0.1
100k
1G
1M
10M
FREQUENCY (Hz)
100M
1G
FREQUENCY (Hz)
Figure 38. AD8104, AD8105 Input Impedance
Figure 41. AD8104, AD8105 Output Impedance, Enabled
0.4
4500
SINGLE-ENDED IN
4000
0.3
AD8104
0.2
VOUT (V, DIFF)
3000
2500
2000
1500
0
–0.1
–0.3
1M
10M
100M
–0.4
1G
06612-042
500
0
300k
0.1
–0.2
1000
06612-039
INPUT IMPEDANCE (Ω)
3500
AD8105
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
TIME (ns)
FREQUENCY (Hz)
Figure 39. AD8104, AD8105 Input Impedance, Single-Ended
Figure 42. AD8104 Small Signal Pulse Response, 200 mV p-p
Rev. 0 | Page 20 of 36
AD8104/AD8105
3
1.5
0.20
UPDATE
0.15
1.0
2
0.5
1
0
0
0
–0.05
P-CHANNEL
–1.0
–0.20
06612-043
–0.15
0
1
2
3
4
5
6
7
8
9
–1
–0.5
–0.10
VOUT
–1.5
–40
10 11 12 13 14 15
–2
–20
0
20
40
60
80
100
–3
120
06612-046
VOUT (V, DIFF)
VOUT (V, SE)
N-CHANNEL
0.05
UPDATE (V)
0.10
TIME (ns)
TIME (ns)
Figure 46. AD8104 Switching Time
Figure 43. AD8104 Small Signal Pulse Response, Single-Ended, 200 mV p-p
2.0
1.5
2
5000
1
4000
0
3000
0.5
0
–0.5
VOUT
–1
2000
–2
1000
SLEW RATE (V/µs)
VOUT (V, DIFF)
VOUT (V, DIFF)
1.0
–1.0
–3
0
1
2
3
4
5
6
7
8
9
–1000
–4
10 11 12 13 14 15
0
1
2
3
4
5
TIME (ns)
TIME (ns)
06612-047
–2.0
0
SLEW RATE
06612-044
–1.5
Figure 47. AD8104 Large Signal Rising Edge and Slew Rate
Figure 44. AD8104 Large Signal Pulse Response, 2 V p-p
3500
2
1.0
0.8
VOUT
1
2500
0.2
0
–0.2
P-CHANNEL
–0.4
06612-045
–0.6
–0.8
–1.0
0
1
2
3
4
5
6
7
8
9
0
1500
–1
500
SLEW RATE
–2
–500
–3
–1500
–2500
–4
0
10 11 12 13 14 15
1
2
3
4
5
1ns/DIV
TIME (ns)
Figure 45. AD8104 Large Signal Pulse Response, Single-Ended, 2 V p-p
Rev. 0 | Page 21 of 36
Figure 48. AD8104 Large Signal Falling Edge and Slew Rate
06612-048
N-CHANNEL
VOUT (V, DIFF)
VOUT (V, SE)
0.4
SLEW RATE (V/µs)
0.6
AD8104/AD8105
0.014
5
DIFFERENTIAL PHASE ERROR (%)
0.012
3
2
1
0
10
20
30
40
50
60
70
80
0.008
0.006
0.004
0.002
0
–0.002
06612-049
0
–40 –30 –20 –10
0.010
–0.004
–700
90 100
06612-052
OFFSET (mV)
4
–500
–300
–100
100
300
500
700
VIN, DIFF (mV)
TEMPERATURE (ºC)
Figure 49. AD8104 VOS vs. Temperature with All Outputs Enabled
Figure 52. AD8104 Phase vs. DC Voltage, Carrier Frequency = 3.58 MHz,
Subcarrier Amplitude = 600 mV p-p, Differential
50
2.0
40
1.5
10pF
5pF
1.0
2pF
VOUT (V, DIFF)
20
10
0
0.5
0pF
0
–0.5
–1.0
–20
–0.10 –0.08 –0.06 –0.04 –0.02
–1.5
06612-050
–10
0
0.02
0.04
0.06
0.08
06612-053
VOUT (mV, DIFF)
30
–2.0
0.10
0
2
4
6
TIME (µs)
8
10
12
14
16
18
TIME (ns)
Figure 50. AD8104 Switching Transient (Glitch)
Figure 53. AD8104 Large Signal Pulse Response with Capacitive Loads
0.020
0.4
5pF
0.2
2pF
VOUT (V, DIFF)
0.010
0.005
0
0.1
0pF
0
–0.1
–0.2
–0.005
–500
–300
–100
100
300
500
06612-054
–0.010
–700
–0.3
06612-051
DIFFERENTIAL GAIN ERROR (%)
10pF
0.3
0.015
–0.4
700
0
VIN, DIFF (mV)
2
4
6
8
10
12
14
16
18
TIME (ns)
Figure 51. AD8104 Gain vs. DC Voltage, Carrier Frequency = 3.58 MHz,
Subcarrier Amplitude = 600 mV p-p, Differential
Figure 54. AD8104 Small Signal Pulse Response with Capacitive Loads
Rev. 0 | Page 22 of 36
AD8104/AD8105
2.8
IDD (SERIAL MODE)
0.8
1.6
0.6
1.2
0.4
0.8
0.4
VOUT
IPOS AND INEG CURRENT (mA)
2.0
UPDATE (V)
2.4
1.0
0.2
500
750
IDD (PARALLEL MODE)
400
–0.2
–50
–30
–10
10
30
50
70
90
110
130
–0.4
150
TIME (ns)
650
IPOS AND INEG
(ALL OUTPUTS ENABLED)
300
200
550
450
IPOS AND INEG
(ALL OUTPUTS DISABLED)
0
0
100
–35 –25 –15 –5
5
15
25
35
45
55
65
75
85
350
95
TEMPERATURE (°C)
Figure 55. AD8104 Enable Time
Figure 58. AD8104, AD8105 Quiescent Supply Currents vs. Temperature
1.4
1.2
850
IDD CURRENT (µA)
UPDATE
06612-055
VOUT (V, DIFF)
1.2
600
06612-058
1.4
UPDATE
2.8
360
2.4
340
1040
960
IPOS, INEG
0.4
0.8
0.2
0
–10
10
30
50
70
90
110
130
800
IDD SERIAL
280
720
260
0.4
240
560
0
220
480
–0.4
150
200
TIME (ns)
Figure 56. AD8104 Disable Time
1
2
3
5
6
7
8
400
10 11 12 13 14 15 16
9
CHANNELS
65
3.25
60
–0.01
2.75
OUTPUT ERROR (%)
50
–0.02
–0.03
06612-057
–0.04
–25
0
25
50
75
3.00
(VOUT – VIN)/VOUT
55
GAIN (dB)
4
Figure 59. AD8104, AD8105 Quiescent Supply Currents vs. Enabled Outputs
0
–0.05
–50
640
IDD PARALLEL
2.50
VIN
45
2.25
40
2.00
35
1.75
30
1.50
VOUT
25
1.25
20
1.00
15
0.75
10
0.50
5
0.25
0
0
–5
100
–0.25
0
TEMPERATURE (°C)
1
2
3
4
5
TIME (ns)
Figure 57. AD8104 DC Gain vs. Temperature
Figure 60. AD8104 Settling Time
Rev. 0 | Page 23 of 36
6
7
(V, DIFF)
–30
300
06612-060
–0.2
–50
880
IDD (µA)
1.2
IPOS AND INEG (mA)
0.6
UPDATE (V)
1.6
320
06612-056
VOUT (V, DIFF)
0.8
VOUT
06612-059
2.0
1.0
AD8104/AD8105
5
2.0
4
1.5
VOUTP
1.0
2
1
VOUT (V, SE)
0
–1
0.5
VINP
0
–0.5
–2
–1.0
–3
–1.5
06612-061
–4
–5
0
1
2
3
4
5
6
VOUTN
VINN
06612-063
OUTPUT/INPUT (%)
3
–2.0
7
100
0
200
300
TIME (ns)
Figure 61. AD8104 Settling Time (Zoom)
–30
VINP
700
VOUT = 2V p-p, DIFF
–50
DISTORTION (dBc)
1.0
0.5
0
–0.5
–1.0
THIRD
HARMONIC
–60
–70
SECOND
HARMONIC
–80
VOUTN
–2.0
VINN
–2.5
0
100
200
300
400
500
–90
600
–100
0.1
700
TIME (ns)
06612-064
–1.5
06612-062
VOUT (V, SE)
600
–40
VOUTP
1.5
500
Figure 63. AD8105 Overdrive Recovery, Single-Ended
2.5
2.0
400
TIME (ns)
1
10
100
FREQUENCY (MHz)
Figure 62. AD8104 Overdrive Recovery, Single-Ended
Figure 64. AD8104 Harmonic Distortion
Rev. 0 | Page 24 of 36
1000
AD8104/AD8105
THEORY OF OPERATION
The AD8104/AD8105 are fully differential crosspoint arrays
with 16 outputs, each of which can be connected to any one
of 32 inputs. Organized by output row, 32 switchable input
transconductance stages are connected to each output buffer to
form 32-to-1 multiplexers. There are 16 of these multiplexers,
each with its inputs wired in parallel, for a total array of 512
transconductance stages forming a multicast-capable crosspoint
switch.
Decoding logic for each output selects one (or none) of the
transconductance stages to drive the output stage. The enabled
transconductance stage drives the output stage, and feedback
forms a closed-loop amplifier with a differential gain of +1 (the
difference between the output voltages is equal to the difference
between the input voltages). A second feedback loop controls
the common-mode output level, forcing the average of the
differential output voltages to match the voltage on the VOCM
reference pin. Although each output has an independent
common-mode control loop, the VOCM reference is common
for the entire chip, and as such needs to be driven with a low
impedance to avoid crosstalk.
Each differential input to the AD8104/AD8105 is buffered by a
receiver. The purpose of this receiver is to provide an extended
input common-mode range, and to remove this common mode
from the signal chain. Like the output multiplexers, the input
receiver has both a differential loop and a common-mode
control loop. A mask-programmable feedback network sets the
closed-loop differential gain. For the AD8104, this differential
gain is +1, and for the AD8105, this differential gain is +2. The
receiver has an input stage that does not respond to the
common mode of the signal. This architecture, along with the
attenuating feedback network, allows the user to apply input
voltages that extend from rail to rail. Excess differential loop
gain bandwidth product reduces the effect of the closed-loop
gain on the bandwidth of the device.
The output stage of the AD8104/AD8105 is designed for low
differential gain and phase error when driving composite video
signals. It also provides slew current for fast pulse response
when driving component video signals. Unlike many multiplexer designs, these requirements are balanced such that large
signal bandwidth is very similar to small signal bandwidth. The
design load is 150 Ω, but provisions are made to drive loads
as low as 75 Ω as long as on-chip power dissipation limits are
not exceeded.
The outputs of the AD8104/AD8105 can be disabled to
minimize on-chip power dissipation. When disabled, there is a
feedback network of 25 kΩ between the differential outputs.
This high impedance allows multiple ICs to be bussed together
without additional buffering. Care must be taken to reduce
output capacitance, which results in more overshoot and
frequency domain peaking. A series of internal amplifiers drive
internal nodes such that a wideband high impedance is
presented at the disabled output, even while the output bus is
under large signal swings. When the outputs are disabled and
driven externally, the voltage applied to them should not exceed
the valid output swing range for the AD8104/AD8105 in order
to keep these internal amplifiers in their linear range of
operation. Applying excess differential voltages to the disabled
outputs can cause damage to the AD8104/AD8105 and should
be avoided (see the Absolute Maximum Ratings section for
guidelines).
The connection of the AD8104/AD8105 is controlled by a
flexible TTL-compatible logic interface. Either parallel or serial
loading into a first rank of latches preprograms each output. A
global update signal moves the programming data into the
second rank of latches, simultaneously updating all outputs. In
serial mode, a serial-out pin allows devices to be daisy-chained
together for single-pin programming of multiple ICs. A poweron reset pin is available to avoid bus conflicts by disabling all
outputs. This power-on reset clears the second rank of latches,
but does not clear the first rank of latches. In parallel mode, to
quickly clear the first rank, a broadcast parallel programming
feature is available. In serial mode, preprogramming individual
inputs is not possible and the entire shift register needs to
be flushed.
The AD8104/AD8105 can operate on a single +5 V supply,
powering both the signal path (with the VPOS/VNEG supply
pins), and the control logic interface (with the VDD/DGND
supply pins). However, to easily interface to ground-referenced
video signals, split supply operation is possible with ±2.5 V
supplies. In this case, a flexible logic interface allows the control
logic supplies (VDD/DGND) to be run off +2 V/0 V to
+5 V/0 V while the core remains on split supplies. Additional
flexibility in the analog output common-mode level facilitates
unequal split supplies. If +3 V/–2 V supplies to +2 V/–3 V
supplies are desired, the VOCM pin can still be set to 0 V for
ground-referenced video signals.
Rev. 0 | Page 25 of 36
AD8104/AD8105
APPLICATIONS INFORMATION
PROGRAMMING
The AD8104/AD8105 have two options for changing the
programming of the crosspoint matrix. In the first option, a
serial word of 192 bits can be provided to update the entire
matrix each time. The second option allows for changing the
programming of a single output via a parallel interface. The
serial option requires fewer signals, but more time (clock cycles)
for changing the programming, while the parallel programming
technique requires more signals, but can change a single output
at a time and requires fewer clock cycles to complete programming.
Therefore, the data for the last device in the chain should come
at the beginning of the programming sequence. The length of
the programming sequence is 192 bits times the number of
devices in the chain.
Parallel Programming Description
Serial Programming Description
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
In fact, parallel programming allows the modification of a
single output at a time. Because this takes only one WE/UPDATE
cycle, significant time savings can be realized by using parallel
programming.
The serial programming mode uses the CLK, DATA IN, UPDATE,
and SER/PAR device pins. The first step is to assert a low on
SER/PAR in order to enable the serial programming mode. The
parallel clock WE should be held high during the entire serial
programming operation.
One important consideration in using parallel programming is
that the RESET signal does not reset all registers in the AD8104/
AD8105. When taken low, the RESET signal only sets each
output to the disabled state. This is helpful during power-up to
ensure that two parallel outputs are not active at the same time.
The UPDATE signal should be high during the time that data is
shifted into the serial port of the device. Although the data still
shifts in when UPDATE is low, the transparent, asynchronous
latches allow the shifting data to reach the matrix. This causes
the matrix to try to update to every intermediate state as
defined by the shifting data.
After initial power-up, the internal registers in the device
generally have random data, even though the RESET signal has
been asserted. If parallel programming is used to program one
output, then that output will be properly programmed, but the
rest of the device will have a random program state depending
on the internal register content at power-up. Therefore, when
using parallel programming, it is essential that all outputs be
programmed to a desired state after power-up. This ensures that
the programming matrix is always in a known state. From then
on, parallel programming can be used to modify a single output
or more at a time.
The data at DATA IN is clocked in at every falling edge of CLK.
A total of 192 bits must be shifted in to complete the programming. For each of the 16 outputs, there are five bits (D0 to D4)
that determine the source of its input followed by one bit (D5)
that determines the enabled state of the output. If D5 is low
(output disabled), the five associated bits (D0 to D4) do not
matter, because no input is switched to that output. These
comprise the first 96 bits of DATA IN. The remaining 96 bits
of DATA IN should be set to zero. If a string of 96 zeros is not
suffixed to the first 96 bits of DATA IN, a certain test mode is
employed that can cause the device to draw up to 40% more
supply current.
The most significant output address data, the enable bit (D5), is
shifted in first, followed by the input address (D4 to D0) entered
sequentially with D4 first and D0 last. Each remaining output is
programmed sequentially, until the least significant output
address data is shifted in. At this point, UPDATE can be taken
low, which programs the device according to the data that was
just shifted in. The UPDATE latches are asynchronous and
when UPDATE is low, they are transparent.
If more than one AD8104/AD8105 device is to be serially
programmed in a system, the DATA OUT signal from one
device can be connected to the DATA IN of the next device to
form a serial chain. All of the CLK, UPDATE, and SER/PAR
pins should be connected in parallel and operated as described
previously. The serial data is input to the DATA IN pin of the
first device of the chain, and it ripples through to the last.
In similar fashion, if UPDATE is taken low after initial powerup, the random power-up data in the shift register will be
programmed into the matrix. Therefore, in order to prevent the
crosspoint from being programmed into an unknown state, do
not apply a low logic level to UPDATE after power is initially
applied. Programming the full shift register one time to a
desired state, by either serial or parallel programming after
initial power-up, eliminates the possibility of programming the
matrix to an unknown state.
To change the programming of an output via parallel programming, SER/PAR and UPDATE should be taken high. The serial
programming clock, CLK, should be left high during parallel
programming. The parallel clock, WE, should start in the high
state. The 4-bit address of the output to be programmed should
be put on A0 to A3. The first five data bits (D0 to D4) should
contain the information that identifies the input that is programmed to the output that is addressed. The sixth data bit
(D5) determines the enabled state of the output. If D5 is low
(output disabled), then the data on D0 to D4 does not matter.
After the desired address and data signals have been established,
they can be latched into the shift register by a high to low
transition of the WE signal. The matrix is not programmed,
Rev. 0 | Page 26 of 36
AD8104/AD8105
mode rejection ratio (CMRR). Differential operation offers a
great noise benefit for signals that are propagated over distance
in a noisy environment.
RF
RG
IN+
OUT–
RCVR
VOCM
IN–
Reset
OUT+
RG
When powering up the AD8104/AD8105, it is usually desirable
to have the outputs come up in the disabled state. The RESET
pin, when taken low, causes all outputs to be in the disabled state.
However, the UPDATE signal does not reset all registers in the
AD8104/AD8105. This is important when operating in the
parallel programming mode. Refer to the Parallel Programming
Description section for information about programming internal
registers after power-up. Serial programming programs the entire
matrix each time; therefore, no special considerations apply.
Since the data in the shift register is random after power-up, it
should not be used to program the matrix, or the matrix can
enter unknown states. To prevent this, do not apply a logic low
signal to UPDATE initially after power-up. The shift register
should first be loaded with the desired data, and then UPDATE
can be taken low to program the device.
The RESET pin has a 20 kΩ pull-up resistor to VDD that can be
used to create a simple power-up reset circuit. A capacitor from
RESET to ground holds RESET low for some time while the rest
of the device stabilizes. The low condition causes all the outputs
to be disabled. The capacitor then charges through the pull-up
resistor to the high state, thus allowing full programming
capability of the device.
Because the AD8104/AD8105 have random data in the internal
registers at power-up, the device may power up in a test state
where the supply current is larger than typical. Therefore, the
RESET pin should be used to disable all outputs and bring the
device out of any test mode.
OPERATING MODES
The AD8104/AD8105 has fully differential inputs and outputs.
The inputs and outputs can also be operated in a single-ended
fashion. This presents several options for circuit configurations
that require different gains and treatment of terminations, if
they are used.
Differential Input
TO SWITCH MATRIX
RF
06612-065
however, until the UPDATE signal is taken low. It is thus possible
to latch in new data for several or all of the outputs first via
successive negative transitions of WE while UPDATE is held
high, and then have all the new data take effect when UPDATE
goes low. This technique should be used when programming
the device for the first time after power-up when using parallel
programming.
Figure 65. Input Receiver Equivalent Circuit
The circuit configuration used by the differential input receivers
is similar to that of several Analog Devices, Inc. general-purpose
differential amplifiers, such as the AD8131. It is a voltage
feedback amplifier with internal gain setting resistors. The
arrangement of feedback makes the differential input impedance appear to be 5 kΩ across the inputs.
R IN , dm = 2 × RG = 5 kΩ
This impedance creates a small differential termination error if
the user does not account for the 5 kΩ parallel element, although
this error is less than 1% in most cases. Additionally, the source
impedance driving the AD8104/AD8105 appears in parallel
with the internal gain-setting resistors, such that there may be a
gain error for some values of source resistance. The AD8104/
AD8105 are adjusted such that its gains are correct when driven
by a back-terminated 75 Ω source impedance at each input
phase (37.5 Ω effective impedance to ground at each input pin,
or 75 Ω differential source impedance across pairs of input
pins). If a different source impedance is presented, the differential
gain of the AD8104/AD8105 can be calculated by
Gdm =
VOUT,dm
VIN ,dm
=
RF
RG + RS
where:
RG = 2.5 kΩ.
RS is the user single-ended source resistance (such as 37.5 Ω for
a back-terminated 75 Ω source).
RF = 2.538 kΩ for the AD8104 and 5.075 kΩ for the AD8105.
In the case of the AD8104,
Gdm =
2.538 kΩ
2.5 kΩ + RS
In the case of the AD8105,
Each differential input to the AD8104/AD8105 is applied to a
differential receiver. These receivers allow the user to drive the
inputs with a differential signal with an uncertain commonmode voltage, such as from a remote source over twisted pair.
The receivers respond only to the difference in input voltages,
and will restore a common-mode voltage suitable for the
internal signal path. Noise or crosstalk that is present in both
inputs is rejected by the input stage, as specified by its commonRev. 0 | Page 27 of 36
Gdm =
5.075 kΩ
2.5 kΩ + RS
AD8104/AD8105
When operating with a differential input, care must be taken to
keep the common mode, or average, of the input voltages within
the linear operating range of the AD8104/AD8105 receiver. This
common-mode range can extend rail-to-rail, provided the
differential signal swing is small enough to avoid forward
biasing the ESD diodes (it is safest to keep the common mode
plus differential signal excursions within the supply voltages
of the part). See the Specifications section for guaranteed
input range.
The differential output of the AD8104/AD8105 receiver is
linear for a peak of 1.4 V of output voltage difference (1.4 V
peak input difference for the AD8104, and 0.7 V peak input
difference for the AD8105). Taking the output differentially,
using the two output phases, this allows 2.8 V p-p of linear
output signal swing. Beyond this level, the signal path can
saturate and limits the signal swing. This is not a desired
operation, as the supply current increases and the signal path is
slow to recover from clipping. The absolute maximum allowed
differential input signal is limited by the long-term reliability of
the input stage. The limits in the Absolute Maximum Ratings
section should be observed in order to avoid degrading device
performance permanently.
R IN =
INn
In most cases, a single-ended input signal is referred to midsupply, typically ground. In this case, the undriven differential input
can be connected to ground. For best dynamic performance and
lowest offset voltage, this unused input should be terminated
with an impedance matching the driven input, instead of being
directly shorted to ground. Due to the differential feedback of
the receiver, there is high frequency signal current in the
undriven input and it should be treated as a signal line in the
board design.
AD8104
IPn
INn
75Ω
OPn
RCVR
ONn
06612-067
75Ω
(OR 37.5Ω)
OPn
RCVR
ONn
Figure 67. Example of Input Driven Single-Ended
50Ω
AC Coupling of Inputs
06612-066
50Ω
2 × (RG + RS + RF )
where:
RG = 2.5 kΩ.
RS is the user single-ended source resistance (such as 37.5 Ω for
a back-terminated 75 Ω source).
RF = 2.538 kΩ for the AD8104 and 5.075 kΩ for the AD8105.
AD8104
IPn
1−
RG + RS
RF
Figure 66. Example of Input Driven Differentially
Single-Ended Input
The AD8104/AD8105 input receivers can be driven singleendedly (unbalanced). From the standpoint of the receiver,
there is very little difference between signals applied positive
and negative in two phases to the input pair vs. a signal applied
to one input only with the other input held at a constant
potential. One small difference is that the common mode
between the input pins is changing if only one input is moving,
and there is a very small common-mode to differential
conversion gain in the receiver that adds an additional gain
error to the output (see the common-mode rejection ratio for
the input stage in the Specifications section). For low
frequencies, this gain error is negligible. The common-mode
rejection ratio degrades with increasing frequency.
When operating the AD8104/AD8105 receivers single-endedly,
the observed input resistance at each input pin is lower than in
the differential input case, due to a fraction of the receiver
internal output voltage appearing as a common-mode signal on
its input terminals, bootstrapping the voltage on the input
resistance. This single-ended input resistance can be calculated
by the equation
It is possible to ac couple the inputs of the AD8104/AD8105
receiver. This is simplified because the bias current does not
need to be supplied externally. A capacitor in series with the
inputs to the AD8104/AD8105 creates a high-pass filter with
the input impedance of the device. This capacitor needs to be
sized such that the corner frequency is low enough for
frequencies of interest.
Differential Output
Benefits of Differential Operation
The AD8104/AD8105 have a fully differential switch core, with
differential outputs. The two output voltages move in opposite
polarity, with a differential feedback loop maintaining a fixed
output stage differential gain of +1 (the different overall signal
path gains between the AD8104 and AD8105 are set in the
input stage for best signal-to-noise ratio). This differential
output stage provides a benefit of crosstalk-canceling due to
parasitic coupling from one output to another being equal and
out of phase. Additionally, if the output of the device is utilized
in a differential design, noise, crosstalk, and offset voltages
generated on-chip that are coupled equally into both outputs are
cancelled by the common-mode rejection ratio of the next
device in the signal chain. By utilizing the AD8104/AD8105
outputs in a differential application, the best possible noise and
offset specifications can be realized.
Rev. 0 | Page 28 of 36
AD8104/AD8105
Differential Gain
The specified signal path gain of the AD8104/AD8105 refers to
its differential gain. For the AD8104, the gain of +1 means that
the difference in voltage between the two output terminals is
equal to the difference applied between the two input terminals.
For the AD8105, the ratio of output difference voltage to
applied input difference voltage is +2.
back-termination, and helps shorten settling time by terminating
reflected signals when driving a load that is not accurately
terminated at the load end. A side effect of back-termination is
an attenuation of the output signal by a factor of two. In this
case, a gain of two is usually necessary somewhere in the signal
path to restore the signal.
AD8104/
AD8105
The common mode, or average voltage of the pair of output
signals is set by the voltage on the VOCM pin. This voltage is
typically set to midsupply (often ground), but can be moved
approximately ±0.5 V to accommodate cases where the desired
output common-mode voltage may not be midsupply (as in the
case of unequal split supplies). Adjusting VOCM can limit
differential swing internally below the specifications listed in
Table 1.
Regardless of the differential gain of the device, the commonmode gain for the AD8104 and AD8105 is +1 to the output.
This means that the common mode of the output voltages
directly follows the reference voltage applied to the VOCM input.
The VOCM reference is a high speed signal input, common to
all output stages on the device. It requires only small amounts of
bias current, but noise appearing on this pin is buffered to the
outputs of all the output stages. As such, the VOCM node should
be connected to a low noise, low impedance voltage to avoid
being a source of noise, offset, and crosstalk in the signal path.
Termination
The AD8104/AD8105 are designed to drive 150 Ω on each
output (or an effective 300 Ω differential), but the output stage
is capable of supplying the current to drive 100 Ω loads (200 Ω
differential) over the specified operating temperature range. If
care is taken to observe the maximum power derating curves,
the output stage can drive 75 Ω loads with slightly reduced slew
rate and bandwidth (an effective 150 Ω differential load).
Termination at the load end is recommended for best signal
integrity. This load termination is often a resistor to a ground
reference on each individual output. By terminating to the
same voltage level that drives the VOCM reference, the power
dissipation due to dc termination current is reduced. In
differential signal paths, it is often desirable to terminate
differentially, with a single resistor across the differential
outputs at the load end. This is acceptable for the AD8104/
AD8105, but when the device outputs are placed in a disabled
state, a small amount of dc bias current is required if the output
is to present as a high impedance over an excursion of output
bus voltages. If the AD8104/AD8105 disabled outputs are
floated (or simply tied together by a resistor), internal nodes
saturate and an increase in disabled output current may
be observed.
For best pulse response, it is often desirable to place a series
resistor in each output to match the characteristic impedance
and termination of the output trace or cable. This is known as
OPn
50Ω
ONn
06612-068
50Ω
+
100Ω
–
Figure 68. Example of Back-Terminated Differential Load
Single-Ended Output
Usage
The AD8104/AD8105 output pairs can be used single-endedly,
taking only one output and not using the second. This is often
desired to reduce the routing complexity in the design, or
because a single-ended load is being driven directly. This mode
of operation produces good results, but has some shortcomings
when compared to taking the output differentially. When
observing the single-ended output, noise that is common to
both outputs appears in the output signal. This includes thermal
noise in the chip biasing, as well as crosstalk that is coupled into
the signal path. This component noise and crosstalk is equal in
both outputs, and as such can be ignored by a differential
receiver with a high common-mode rejection ratio. However,
when taking the output single-ended, this noise is present with
respect to the ground (or VOCM) reference and is not rejected.
When observing the output single-ended, the distribution of
offset voltages appears greater. In the differential case, the
difference between the outputs when the difference between the
inputs is zero is a small differential offset. This offset is created
from mismatches in components of the signal path, which must
be corrected by the finite differential loop gain of the device. In
the single-ended case, this differential offset is still observed,
but an additional offset component is also relevant. This
additional component is the common-mode offset, which is a
difference between the average of the outputs and the VOCM
reference. This offset is created by mismatches that affect the
signal path in a common-mode manner, and is corrected by the
finite common-mode loop gain of the device. A differential
receiver would reject this common-mode offset voltage, but in
the single-ended case, this offset is observed with respect to the
signal ground. The single-ended output sums half the differential offset voltage and all of the common-mode offset voltage for
a net increase in observed offset.
Rev. 0 | Page 29 of 36
AD8104/AD8105
Single-Ended Gain
The AD8104/AD8105 operate as a closed-loop differential
amplifier. The primary control loop forces the difference
between the output terminals to be a ratio of the difference
between the input terminals. One output increases in voltage,
while the other decreases an equal amount to make the total
difference correct. The average of these output voltages is forced
to be equal to the voltage on the VOCM terminal by a second
control loop. If only one output terminal is observed with
respect to the VOCM terminal, only half of the difference
voltage is observed. This implies that when using only one
output of the device, half of the differential gain is observed. An
AD8104 taken with single-ended output appears to have a gain
of +0.5. An AD8105 has a single-ended gain of +1.
This factor of one half in the gain increases the noise of the
device when referred to the input, contributing to higher noise
specifications for single-ended output designs.
output draws current from the positive supply, the other output
draws current from the negative supply. When the phase
alternates, the first output draws current from the negative
supply and the second from the positive supply. The effect is
that a more constant current is drawn from each supply, such
that the crosstalk-inducing supply fluctuation is minimized.
A third benefit of driving balanced loads can be seen if one
considers that the output pulse response changes as load
changes. The differential signal control loop in the AD8104/
AD8105 forces the difference of the outputs to be a fixed ratio
to the difference of the inputs. If the two output responses are
different due to loading, this creates a difference that the control
loop sees as signal response error, and it attempts to correct this
error. This distorts the output signal from the ideal response if
the two outputs were balanced.
AD8104/
AD8105
Termination
One component of crosstalk is magnetic, coupling by mutual
inductance between output package traces and bond wires that
carry load current. In a differential design, there is coupling
from one pair of outputs to other adjacent pairs of outputs. The
differential nature of the output signal simultaneously drives the
coupling field in one direction for one phase of the output, and
in an opposite direction for the other phase of the output. These
magnetic fields do not couple exactly equal into adjacent output
pairs due to different proximities, but they do destructively
cancel the crosstalk to some extent. If the load current in each
output is equal, this cancellation is greater, and less adjacent
crosstalk is observed (regardless if the second output is actually
being used).
A second benefit of balancing the output loads in a differential
pair is to reduce fluctuations in current requirements from the
power supply. In single-ended loads, the load currents alternate
from the positive supply to the negative supply. This creates a
parasitic signal voltage in the supply pins due to the finite
resistance and inductance of the supplies. This supply fluctuation
appears as crosstalk in all outputs, attenuated by the power
supply rejection ratio (PSRR) of the device. At low frequencies,
this is a negligible component of crosstalk, but PSRR falls off as
frequency increases. With differential, balanced loads, as one
75Ω
75Ω
ONn
When operating the AD8104/AD8105 with a single-ended
output, the preferred output termination scheme is a resistor at
the load end to the VOCM voltage. A back-termination can be
used, at an additional cost of one half the signal gain.
In single-ended output operation, the complementary phase of
the output is not used, and may or may not be terminated
locally. Although the unused output can be floated to reduce
power dissipation, there are several reasons for terminating the
unused output with a load resistance matched to the load on the
signal output.
OPn
06612-069
150Ω
Figure 69. Example of Back-Terminated Single-Ended Load
Decoupling
The signal path of the AD8104/AD8105 is based on high openloop gain amplifiers with negative feedback. Dominant-pole
compensation is used on-chip to stabilize these amplifiers over
the range of expected applied swing and load conditions. To
guarantee this designed stability, proper supply decoupling is
necessary with respect to both the differential control loops and
the common-mode control loops of the signal path. Signalgenerated currents must return to their sources through low
impedance paths at all frequencies in which there is still loop
gain (up to 700 MHz at a minimum). A wideband parallel
capacitor arrangement is necessary to properly decouple the
AD8104/AD8105.
The signal path compensation capacitors in the AD8104/
AD8105 are connected to the VNEG supply. At high frequencies,
this limits the power supply rejection ratio (PSRR) from the
VNEG supply to a lower value than that from the VPOS supply.
If given a choice, an application board should be designed such
that the VNEG power is supplied from a low inductance plane,
subject to a least amount of noise.
The VOCM should be considered a reference pin and not a
power supply. It is an input to the high speed, high gain
common-mode control loop of all receivers and output drivers.
In the single-ended output sense, there is no rejection from
noise on the VOCM net to the output. For this reason, care
must be taken to produce a low noise VOCM source over the
entire range of frequencies of interest. This is not only
important to single-ended operation, but to differential
Rev. 0 | Page 30 of 36
AD8104/AD8105
VPOS
operation as well, as there is a common-mode-to-differential
gain conversion that becomes greater at higher frequencies.
IOUTPUT, QUIESCENT
During operation of the AD8104/AD8105, transient currents
flow into the VOCM net from the amplifier control loops.
Although the magnitude of these currents are small (10 μA to
20 μA per output), they can contribute to crosstalk if they flow
through significant impedances. Driving VOCM with a low
impedance, low noise source is desirable.
QNPN
QPNP
IOUTPUT
VNEG
Figure 71. Simplified Output Stage
Example
8
MAXIMUM POWER (W)
TJ = 150°C
For the AD8104/AD8105, in an ambient temperature of 85°C,
with all 16 outputs driving 1 V rms into 100 Ω loads and power
supplies at ±2.5 V, follow these steps:
7
1.
6
Calculate power dissipation of AD8104/AD8105 using data
sheet quiescent currents. Disregard VDD current, as it is
insignificant.
PD , QUIESCENT = (VPOS × I VPOS ) + (VNEG × I VNEG )
PD ,QUIESCENT = (2.5 V× 340 mA ) + (2.5 V× 340 mA ) = 1.7 W
06612-070
5
25
35
45
55
65
75
2.
85
AMBIENT TEMPERATURE (°C)
θ JA
PD ,OUTPUT = (2.5 V − 1 V ) × (1 V / 100 Ω ) = 15 mW
(1)
As an example, if the AD8104/AD8105 is enclosed in an environment at 45°C (TA), the total on-chip dissipation under all
load and supply conditions must not be allowed to exceed 7.0 W.
There are 16 output pairs, or 32 output currents.
nPD ,OUTPUT = 32 × 15 mW = 0.48 W
3.
When calculating on-chip power dissipation, it is necessary to
include the rms current being delivered to the load, multiplied
by the rms voltage drop on the AD8104/AD8105 output
devices. For a sinusoidal output, the on-chip power dissipation
due to the load can be approximated by
(
)
PD , OUTPUT = VPOS − VOUTPUT , RMS × I OUTPUT , RMS
The curve in Figure 70 was calculated from
TJUNCTION , MAX − TAMBIENT
Calculate power dissipation from loads. For a differential
output and ground-referenced load, the output power is
symmetrical in each output phase.
(
Figure 70. Maximum Die Power Dissipation vs. Ambient Temperature
PD , MAX =
06612-071
IOUTPUT, QUIESCENT
Power Dissipation
Calculation of Power Dissipation
4
15
VOUTPUT
Subtract the quiescent output stage current for number of
loads (32 in this example). The output stage is either
standing, or driving a load, but the current only needs to
be counted once (valid for output voltages > 0.5 V).
PDQ , OUTPUT = (VPOS − VNEG ) × I OUTPUT , QUIESCENT
PDQ , OUTPUT = (2.5 V − (−2.5 V)) × 1.65 mA = 8.25 mW
)
There are 16 output pairs, or 32 output currents.
PD , OUTPUT = VPOS − VO UTPUT , RMS × I OUTPUT , RMS
For nonsinusoidal output, the power dissipation should be
calculated by integrating the on-chip voltage drop multiplied by
the load current over one period.
The user can subtract the quiescent current for the Class AB
output stage when calculating the loaded power dissipation. For
each output stage driving a load, subtract a quiescent power
according to
PDQ , OUTPUT = (VPOS − VNEG ) × I OUTPUT , QUIESCENT
where IOUTPUT, QUIESCENT = 1.65 mA for each single-ended output pin.
nPDQ ,OUTPUT = 32 × 8.25 mW = 0.26 W
4.
Verify that the power dissipation does not exceed the
maximum allowed value.
PD , ON − CHIP = PD , QUIESCENT + nPD , OUTPUT − nPDQ , OUTPUT
PD ,ON −CHIP = 1.7 W + 0.48 W − 0.26 W = 1.9 W
From Figure 70 or Equation 1, this power dissipation is below
the maximum allowed dissipation for all ambient temperatures
up to and including 85°C.
For each disabled output, the quiescent power supply current in
VPOS and VNEG drops by approximately 9 mA.
Rev. 0 | Page 31 of 36
AD8104/AD8105
Short-Circuit Output Conditions
Although there is short-circuit current protection on the
AD8104/AD8105 outputs, the output current can reach values
of 80 mA into a grounded output. Any sustained operation
with too many shorted outputs can exceed the maximum die
temperature and can result in device failure (see the Absolute
Maximum Ratings section).
Crosstalk
Many systems, such as broadcast video and KVM switches, that
handle numerous analog signal channels, have strict requirements for keeping the various signals from influencing any of
the others in the system. Crosstalk is the term used to describe
the coupling of the signals of other nearby channels to a given
channel.
When there are many signals in close proximity in a system, as
is undoubtedly the case in a system that uses the AD8104/AD8105,
the crosstalk issues can be quite complex. A good understanding
of the nature of crosstalk and some definition of terms is
required in order to specify a system that uses one or more
crosspoint devices.
Types of Crosstalk
Crosstalk can be propagated by means of any of three methods.
These fall into the categories of electric field, magnetic field,
and sharing of common impedances. This section explains
these effects.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter
propagates across a stray capacitance (for example, free space),
couples with the receiver, and induces a voltage. This voltage is
an unwanted crosstalk signal in any channel that receives it.
Currents flowing in conductors create magnetic fields that
circulate around the currents. These magnetic fields then
generate voltages in any other conductors whose paths they
link. The undesired induced voltages in these other channels
are crosstalk signals. The channels that crosstalk can be said to
have a mutual inductance that couples signals from one channel
to another.
are common mode to the signal and can be rejected by a
differential receiver.
Areas of Crosstalk
A practical AD8104/AD8105 circuit must be mounted to some
sort of circuit board in order to connect it to power supplies and
measurement equipment. Great care has been taken to create an
evaluation board that adds minimum crosstalk to the intrinsic
device. This, however, raises the issue that a system’s crosstalk is
a combination of the intrinsic crosstalk of the devices in
addition to the circuit board to which they are mounted. It is
important to try to separate these two areas when attempting to
minimize the effect of crosstalk.
In addition, crosstalk can occur among the inputs to a crosspoint and among the outputs. It can also occur from input to
output. Techniques are discussed in the following sections for
diagnosing which part of a system is contributing to crosstalk.
Measuring Crosstalk
Crosstalk is measured by applying a signal to one or more
channels and measuring the relative strength of that signal on a
desired selected channel. The measurement is usually expressed
as dB down from the magnitude of the test signal. The crosstalk
is expressed by
⎛ A (s ) ⎞
⎟
XT = 20 log 10 ⎜ SEL
⎜A
⎟
(
)
s
⎝ TEST ⎠
where:
s = jω, the Laplace transform variable.
ASEL(s) is the amplitude of the crosstalk induced signal in the
selected channel.
ATEST(s) is the amplitude of the test signal.
It can be seen that crosstalk is a function of frequency, but not a
function of the magnitude of the test signal (to first order). In
addition, the crosstalk signal will have a phase relative to the
test signal associated with it.
A network analyzer is most commonly used to measure
crosstalk over a frequency range of interest. It can provide both
magnitude and phase information about the crosstalk signal.
The power supplies, grounds, and other signal return paths of a
multichannel system are generally shared by the various
channels. When a current from one channel flows in one of
these paths, a voltage that is developed across the impedance
becomes an input crosstalk signal for other channels that share
the common impedance.
As a crosspoint system or device grows larger, the number of
theoretical crosstalk combinations and permutations can
become extremely large. For example, in the case of the 32 × 16
matrix of the AD8104/AD8105, look at the number of crosstalk
terms that can be considered for a single channel, for example,
the input IN00. IN00 is programmed to connect to one of the
AD8104/AD8105 outputs where the measurement can be made.
All these sources of crosstalk are vector quantities; therefore, the
magnitudes cannot simply be added together to obtain the total
crosstalk. In fact, there are conditions where driving additional
circuits in parallel in a given configuration can actually reduce
the crosstalk. Because the AD8104/AD8105 are fully differential
designs, many sources of crosstalk either destructively cancel, or
First, the crosstalk terms associated with driving a test signal
into each of the other 31 inputs can be measured one at a time,
while applying no signal to IN00. Then the crosstalk terms
associated with driving a parallel test signal into all 31 other
inputs can be measured two at a time in all possible
combinations, then three at a time, and so on, until, finally,
Rev. 0 | Page 32 of 36
AD8104/AD8105
there is only one way to drive a test signal into all 31 other
inputs in parallel.
Each of these cases is legitimately different from the others and
may yield a unique value, depending on the resolution of the
measurement system, but it is hardly practical to measure all
these terms and then specify them. In addition, this describes
the crosstalk matrix for just one input channel. A similar
crosstalk matrix can be proposed for every other input. In
addition, if the possible combinations and permutations for
connecting inputs to the other outputs (not used for measurement) are taken into consideration, the numbers rather quickly
grow to astronomical proportions. If a larger crosspoint array of
multiple AD8104/AD8105s is constructed, the numbers grow
larger still.
Obviously, some subset of all these cases must be selected to be
used as a guide for a practical measure of crosstalk. One
common method is to measure all-hostile crosstalk; this means
that the crosstalk to the selected channel is measured while all
other system channels are driven in parallel. In general, this
yields the worst crosstalk number, but this is not always the
case, due to the vector nature of the crosstalk signal.
Other useful crosstalk measurements are those created by one
nearest neighbor or by the two nearest neighbors on either side.
These crosstalk measurements are generally higher than those
of more distant channels, so they can serve as a worst-case
measure for any other one-channel or two-channel crosstalk
measurements.
Input and Output Crosstalk
Capacitive coupling is voltage-driven (dV/dt), but is generally a
constant ratio. Capacitive crosstalk is proportional to input or
output voltage, but this ratio is not reduced by simply reducing
signal swings. Attenuation factors must be changed by changing
impedances (lowering mutual capacitance), or destructive
canceling must be utilized by summing equal and out of phase
components. For high input impedance devices such as the
AD8104/AD8105, capacitances generally dominate inputgenerated crosstalk.
Inductive coupling is proportional to current (dI/dt), and often
scales as a constant ratio with signal voltage, but also shows a
dependence on impedances (load current). Inductive coupling
can also be reduced by constructive canceling of equal and out
of phase fields. In the case of driving low impedance video
loads, output inductances contribute highly to output crosstalk.
The flexible programming capability of the AD8104/AD8105
can be used to diagnose whether crosstalk is occurring more on
the input side or the output side. Some examples are illustrative.
A given input pair (IN07 in the middle for this example) can be
programmed to drive OUT07 (also in the middle). The inputs
to IN07 are just terminated to ground (via 50 Ω or 75 Ω) and no
signal is applied.
All the other inputs are driven in parallel with the same test
signal (practically provided by a distribution amplifier), with all
other outputs except OUT07 disabled. Since grounded IN07
is programmed to drive OUT07, no signal should be present.
Any signal that is present can be attributed to the other 31
hostile input signals, because no other outputs are driven
(they are all disabled). Thus, this method measures the all
hostile input contribution to crosstalk into IN07. Of course, the
method can be used for other input channels and combinations
of hostile inputs.
For output crosstalk measurement, a single input channel is
driven (IN00, for example) and all outputs other than a given
output (IN07 in the middle) are programmed to connect to
IN00. OUT07 is programmed to connect to IN15 (far away
from IN00), which is terminated to ground. Thus OUT07
should not have a signal present since it is listening to a quiet
input. Any signal measured at the OUT07 can be attributed to
the output crosstalk of the other 16 hostile outputs. Again, this
method can be modified to measure other channels and other
crosspoint matrix combinations.
Effect of Impedances on Crosstalk
The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower the
impedance of the drive source, the lower the magnitude of the
crosstalk. The dominant crosstalk mechanism on the input side
is capacitive coupling. The high impedance inputs do not have
significant current flow to create magnetically induced crosstalk.
However, significant current can flow through the input termination resistors and the loops that drive them. Thus, the PC
board on the input side can contribute to magnetically coupled
crosstalk.
From a circuit standpoint, the input crosstalk mechanism looks
like a capacitor coupling to a resistive load. For low frequencies,
the magnitude of the crosstalk is given by
XT = 20 log 10 [(RS C M ) × s ]
where:
RS is the source resistance.
CM is the mutual capacitance between the test signal circuit and
the selected circuit.
s is the Laplace transform variable.
From the preceding equation, it can be observed that this
crosstalk mechanism has a high-pass nature; it can also be
minimized by reducing the coupling capacitance of the input
circuits and lowering the output impedance of the drivers. If the
input is driven from a 75 Ω terminated cable, the input crosstalk
can be reduced by buffering this signal with a low output
impedance buffer.
Rev. 0 | Page 33 of 36
AD8104/AD8105
From a circuit standpoint, this output crosstalk mechanism
looks like a transformer with a mutual inductance between the
windings that drive a load resistor. For low frequencies, the
magnitude of the crosstalk is given by
⎛
s ⎞⎟
XT = 20 log 10 ⎜ M XY ×
⎜
RL ⎟⎠
⎝
where:
MXY is the mutual inductance of Output X to Output Y.
RL is the load resistance on the measured output.
This crosstalk mechanism can be minimized by keeping the
mutual inductance low and increasing RL. The mutual
inductance can be kept low by increasing the spacing of the
conductors and minimizing their parallel length.
PCB Layout
Extreme care must be exercised to minimize additional
crosstalk generated by the system circuit board(s). The areas
that must be carefully detailed are grounding, shielding, signal
routing, and supply bypassing.
The packaging of the AD8104/AD8105 is designed to help keep
the crosstalk to a minimum. On the BGA substrate, each pair is
carefully routed to predominately couple to each other, with
shielding traces separating adjacent signal pairs. The ball grid
array is arranged such that similar board routing can be achieved.
Only the outer two rows are used for signals, such that vias can
be used to take the input rows to a lower signal plane if desired.
The input and output signals have minimum crosstalk if they
are located between ground planes on layers above and below,
and separated by ground in between. Vias should be located as
close to the IC as possible to carry the inputs and outputs to the
inner layer. The input and output signals surface at the input
termination resistors and the output series back-termination
resistors. To the extent possible, these signals should also be
separated as soon as they emerge from the IC package.
applications are generally 50 Ω single-ended (and board
manufacturers have the most experience with this application).
CAT-5 cabling is usually driven as differential pairs of 100 Ω
differential impedance.
For flexibility, the AD8104/AD8105 do not contain on-chip
termination resistors. This flexibility in application comes with
some board layout challenges. The distance between the termination of the input transmission line and the AD8104/AD8105
die is a high impedance stub, and causes reflections of the input
signal. With some simplification, it can be shown that these
reflections cause peaking of the input at regular intervals in
frequency, dependent on the propagation speed (VP) of the
signal in the chosen board material and the distance (d)
between the termination resistor and the AD8104/AD8105. If
the distance is great enough, these peaks can occur in-band. In
fact, practical experience shows that these peaks are not high-Q,
and should be pushed out to three or four times the desired
bandwidth in order to not have an effect on the signal. For a
board designer using FR4 (VP = 144 × 106 m/s), this means the
AD8104/AD8105 input should be placed no farther than 1.5 cm
after the termination resistors, and preferably should be placed
even closer. The BGA substrate routing inside the AD8104/
AD8105 is approximately 1 cm in length and adds to the stub
length, so 1.5 cm PCB routing equates to d = 2.5 × 10−2 m in the
calculations.
f PEAK =
(2n + 1) × VP
4d
where n = {0, 1, 2, 3, …}.
In some cases, it is difficult to place the termination close to the
AD8104/AD8105 due to space constraints, differential routing,
and large resistor footprints. A preferable solution in this case is
to maintain a controlled transmission line past the AD8104/
AD8105 inputs and terminate the end of the line. This is known
as fly-by termination. The input impedance of the AD8104/
AD8105 is large enough and stub length inside the package is
small enough that this works well in practice. Implementation
of fly-by input termination often includes bringing the signal in
on one routing layer, then passing through a filled via under the
AD8104/AD8105 input ball, then back out to termination on
another signal layer. In this case, care must be taken to tie the
reference ground planes together near the signal via if the signal
layers are referenced to different ground planes.
PCB Termination Layout
As frequencies of operation increase, the importance of proper
transmission line signal routing becomes more important. The
bandwidth of the AD8104/AD8105 is large enough that using
high impedance routing does not provide a flat in-band
frequency response for practical signal trace lengths. It is
necessary for the user to choose a characteristic impedance
suitable for the application and properly terminate the input
and output signals of the AD8104/AD8105. Traditionally, video
applications have used 75 Ω single-ended environments. RF
IPn
INn
75Ω
AD8104/
AD8105
OPn
ONn
06612-072
On the output side, the crosstalk can be reduced by driving a
lighter load. Although the AD8104/AD8105 are specified with
excellent differential gain and phase when driving a standard
150 Ω video load, the crosstalk is higher than the minimum
obtainable due to the high output currents. These currents
induce crosstalk via the mutual inductance of the output pins
and bond wires of the AD8104/AD8105.
Figure 72. Fly-By Input Termination, Grounds for the Two Transmission Lines
Shown Must be Tied Together Close to the INn Pin
Rev. 0 | Page 34 of 36
AD8104/AD8105
If multiple AD8104/AD8105s are to be driven in parallel, a flyby input termination scheme is very useful, but the distance
from each AD8104/AD8105 input to the driven input transmission line is a stub that should be minimized in length and
parasitics using the discussed guidelines.
system). This is not often practical as trace widths become large.
In most cases, the best practical solution is to place the halfcharacteristic impedance resistor as close as possible (preferably
less than 1.5 cm away) and to reduce the parasitics of the stub
(by removing the ground plane under the stub, for example).
In either case, the designer must decide if the layout complexity
created by a balanced, terminated solution is preferable to
simply grounding the undriven input at the ball with no trace.
When driving the AD8104/AD8105 single-endedly, the
undriven input is often terminated with a resistance to balance
the input stage. It can be seen that by terminating the undriven
input with a resistor of one half the characteristic impedance,
the input stage is perfectly balanced (37.5 Ω, for example, to
balance the two parallel 75 Ω terminations on the driven input).
However, due to the feedback in the input receiver, there is high
speed signal current leaving the undriven input. To terminate
this high speed signal, proper transmission line techniques
should be used. One solution is to adjust the trace width to
create a transmission line of half the characteristic impedance
and terminate the far end with this resistance (37.5 Ω in a 75 Ω
Although the examples discussed so far are for input termination, the theory is similar for output back-termination. Taking
the AD8104/AD8105 as an ideal voltage source, any distance of
routing between the AD8104/AD8105 and a back-termination
resistor will be an impedance mismatch that potentially creates
reflections. For this reason, back-termination resistors should
also be placed close to the AD8104/AD8105. In practice,
because back-termination resistors are series elements, they
can be placed close to the AD8104/AD8105 outputs.
VPOS
VDD
J3
PC_VDD
PLD_VDD
VPOS
VDD
ANALOG
SMA
50Ω
IN[31:0],
IP[31:0]
PC
PARALLEL
PORT
IN[31:0], IP[31:0]
50Ω
LOGIC
ISOLATORS
CLK
RESET
WE
UPDATE
DATA IN
DATA OUT
D0 TO D5
A0 TO A3
CPLD
ON[15:0], OP[15:0]
AD8104/
AD8105
SMA
ON[15:0],
OP[15:0]
VOCM
LOGIC
DGND
VNEG
J8,
W3 TO W7
VNEG
GND
Figure 73. Evaluation Board Simplified Schematic
Rev. 0 | Page 35 of 36
06612-073
PC_GND
AD8104/AD8105
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
31.00
BSC SQ
23
6
4
2
22 20 18 16 14 12 10 8
21 19 17 15 13 11
9
5
3
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
BALL A1
INDICATOR
27.94
BSC SQ
TOP VIEW
BOTTOM
VIEW
1.27
BSC
DETAIL A
DETAIL A
*1.765 MAX
1.07
0.99
0.92
0.70
0.63
0.56
0.10 MIN
COPLANARITY
0.20
SEATING
PLANE
*COMPLIANT TO JEDEC STANDARDS MO-192-BAN-2
WITH THE EXCEPTION TO PACKAGE HEIGHT.
022206-A
0.25 MIN
(4 )
0.90
0.75
0.60
BALL DIAMETER
Figure 74. 304-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]
(BP-304)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8104ABPZ 1
AD8105ABPZ1
AD8104-EVAL
AD8105-EVAL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
304-Ball Ball Grid Array Package, Thermally Enhanced [BGA_ED]
304-Ball Ball Grid Array Package, Thermally Enhanced [BGA_ED]
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06612-0-6/07(0)
Rev. 0 | Page 36 of 36
Package Option
BP-304
BP-304