256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 2.5V I/O, Burst Counter Pipelined Outputs Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V65602 IDT71V65802 Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71V65602/5802 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V65602/5802 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values. There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated. The IDT71V65602/5802 have an on-chip burst counter. In the burst mode, the IDT71V65602/5802 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. TheLBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/ LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). The IDT71V65602/5802 SRAM utilize IDT's latest high-performance CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA). 256K x 36, 512K x 18 memory configurations Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE W (READ/WRITE) control pin Single R/W Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications 4-word burst capability (interleaved or linear) BW1 - BW4) control (May tie active) Individual byte write (BW Three chip enables for simple depth expansion 3.3V power supply (±5%) 2.5V I/O Supply (VDDQ) Power down controlled by ZZ input Packaged in a JEDEC standard 100-pin plastic thin quad and flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA) Description The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit (9 Megabit) synchronous SRAMs. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Pin Description Summary A0-A18 Address Inputs Input Synchronous CE1, CE2, CE2 Chip Enables Input Synchronous OE Output Enable Input Asynchronous R/W Read/Write Signal Input Synchronous CEN Clock Enable Input Synchronous BW1, BW2, BW3, BW4 Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV/LD Advance burst address / Load new address Input Synchronous LBO Linear / Interleaved Burst Order Input Static ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 5303 tbl 01 ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc. OCTOBER 2004 1 ©2004 Integrated Device Technology, Inc. DSC-5303/05 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Pin Definitions(1) Symbol Pin Function I/O Active Description A0-A18 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, ADV/LD low, CEN low, and true chip enables. ADV/LD Advance / Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/ LD is sampled hig h then the internal burst counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled high. R/W Read / Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the current cycle takes place two clock cycles later. CEN Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock. BW1-BW4 Individual Byte Write Enables I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles (When R/ W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/ W is sampled high. The appropriate byte(s) of data are written into the device two cycles later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word. CE1, CE2 Chip Enables I LOW Synchronous active low chip enable. CE1 and CE2 are used with CE 2 to enable the IDT71V65602/5802. (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The ZBTTM has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated. CE2 Chip Enable I HIGH Synchronous active high chip enable. CE 2 is used with CE1 and CE2 to enable the chip. CE2 has inverted polarity but otherwise identical to CE1 and CE2. CLK Clock I N/A This is the clock input to the IDT71V65602/5802. Except for OE, all timing references for the device are made with respect to the rising edge of CLK. I/O0-I/O31 I/OP1-I/OP4 Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and triggered by the rising edge of CLK. LBO Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low the Linear burst sequence is selected. LBO is a static input and it must not change during device operation. OE Output Enable I LOW Asynchronous output enable. OE must be low to read data from the IDT71V65602/5802. When OE is high the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied low. ZZ Sleep Mode I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down 71V65602/5802 to the lowest power consumption level. Data retention is guaranteed in Sleep Mode. VDD Power Supply N/A N/A 3.3V core power supply. VDDQ Power Supply N/A N/A 2.5V I/O Supply. VSS Ground N/A N/A Ground. 5303 tbl 02 NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.42 2 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Functional Block Diagram LBO Address A [0:17] 256Kx36 BIT MEMORY ARRAY D Q Address D Q Control CE1, CE2, CE2 R/W Input Register CEN ADV/LD BWx D DI DO Control Logic Q Clk Mux Sel D Clk Clock Output Register Q Gate OE 5303 drw 01a Data I/O [0:31], I/O P[1:4] 6.42 3 , IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Functional Block Diagram LBO 512x18 BIT MEMORY ARRAY Address A [0:18] D Q Address D Q Control CE1, CE2, CE2 R/W Input Register CEN ADV/LD BWx D DI DO Control Logic Q Clk Mux Sel D Clk Clock Output Register Q Gate OE 5303 drw 01 Data I/O [0:15], I/O P[1:2] Recommended DC Operating Conditions Symbol Parameter Min. Typ. Max. Unit VDD Core Supply Voltage 3.135 3.3 3.465 V V DDQ I/O Supply Voltage 2.375 2.5 2.625 V VSS Supply Voltage 0 0 0 V 1.7 ____ VDD+0.3 V 1.7 ____ VDDQ +0.3 V ____ 0.7 VIH VIH VIL Input High Voltage - Inputs Input High Voltage - I/O Input Low Voltage (1) -0.3 NOTES: 1. VIL (min.) = –1.0V for pulse width less than tCYC /2, once per cycle. V 5303 tbl 03 6.42 4 , IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Recommended Operating Temperature and Supply Voltage Grade Ambient Temperature(1) VSS VDD VDDQ Commercial 0° C to +70° C 0V 3.3V± 5% 2.5V± 5% Industrial -40° C to +85° C 0V 3.3V± 5% 2.5V± 5% 5303tbl 05 NOTES: 1. During production testing, the case temperature equals the ambient temperature. BW3 BW2 BW1 CE2 VDD VSS CLK R/W CEN OE ADV/LD NC(2) A17 A8 A9 CE2 BW4 A6 A7 CE1 Pin Configuration - 256K x 36 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3 I/O16 I/O17 VDDQ VSS I/O18 I/O19 I/O20 I/O21 VSS VDDQ I/O22 I/O23 VDD(1) VDD VDD(1) VSS I/O24 I/O25 VDDQ VSS I/O26 I/O27 I/O28 I/O29 VSS VDDQ I/O30 I/O31 I/OP4 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 71 10 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 19 63 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 51 30 I/OP2 I/O15 I/O14 VDDQ VSS I/O13 I/O12 I/O11 I/O10 VSS VDDQ I/O9 I/O8 VSS VDD(1) VDD ZZ I/O7 I/O6 VDDQ VSS I/O5 I/O4 I/O3 I/O2 VSS VDDQ I/O1 I/O0 I/OP1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A10 A11 A12 A13 A14 A15 A16 VSS VDD DNU(3) DNU(3) DNU(3) LBO A5 A4 A3 A2 A1 A0 DNU(3) 5303 drw 02 , Top View 100 TQFP NOTES: 1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH. 2. Pin 84 is reserved for a future 16M. 3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows these pins to be left unconnected, tied Low (VSS ) or tied High (VDD). 6.42 5 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) CE2 NC NC BW2 BW1 CE2 VDD VSS CLK R/W CEN OE ADV/LD NC(2) A18 A8 A9 A6 A7 CE1 Pin Configuration - 512K x 18 Symbol 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC NC 1 80 2 79 3 78 VDDQ VSS NC NC I/O8 I/O9 VSS VDDQ I/O10 I/O11 VDD(1) VDD VDD(1) VSS I/O12 I/O13 VDDQ VSS I/O14 I/O15 I/OP2 NC VSS VDDQ NC NC NC 4 77 5 6 76 75 7 74 8 73 9 72 71 10 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 24 58 57 25 56 26 55 27 54 28 53 29 52 30 51 , Com mercial & Industrial Unit VTERM(2) Terminal Voltage with Respect to GND -0.5 to +4.6 V VTERM(3,6) Terminal Voltage with Respect to GND -0.5 to VDD V VTERM(4,6) Terminal Voltage with Respect to GND -0.5 to VDD +0.5 V VTERM(5,6) Terminal Voltage with Respect to GND -0.5 to VDDQ +0.5 V -0 to +70 o Industrial -40 to +85 o TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -55 to +125 o PT Power Dissipation 2.0 W IOUT DC Output Current 50 mA Commercial TA(7) C C C C 5303 tbl 06 5303 drw 02a NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. VDDQ terminals only. 4. Input terminals only. 5. I/O terminals only. 6. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp up. 7. During production testing, the case temperature equals T A. A11 A12 A13 A14 A15 A16 A17 LBO A5 A4 A3 A2 A1 A0 DNU(3) DNU(3) VSS VDD DNU(3) DNU(3) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A10 NC NC VDDQ VSS NC I/OP1 I/O7 I/O6 VSS VDDQ I/O5 I/O4 VSS VDD(1) VDD ZZ I/O3 I/O2 VDDQ VSS I/O1 I/O0 NC NC VSS VDDQ NC NC NC Rating Top View 100 TQFP NOTES: 1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH . 2. Pin 84 is reserved for a future 16M. 3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows these pins to be left unconnected, tied Low (VSS ) or tied High (VDD). 100 TQFP Capacitance(1) (TA = +25° C, f = 1.0MHz) Symbol Parameter (1) CIN Input Capacitance CI/O I/O Capacitance 119 BGA Capacitance(1) Conditions Max. Unit VIN = 3dV 5 pF Symbol VOUT = 3dV 7 pF CIN Input Capacitance CI/O I/O Capacitance (TA = +25° C, f = 1.0MHz) 5303 tbl 07 165 fBGA Capacitance(1) Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions Max. Unit V IN = 3dV 7 pF V OUT = 3dV 7 pF 5303 tbl 07a (TA = +25° C, f = 1.0MHz) Symbol Parameter(1) Conditions Max. Unit VIN = 3dV TBD pF VOUT = 3dV TBD pF 5303 tbl 07b NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 6.42 6 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Pin Configuration - 256K X 36, 119 BGA 1 2 3 4 5 6 7 A VDDQ A6 A4 NC(2) A8 A16 VDDQ B NC CE2 A3 ADV/LD A9 CE2 NC NC A7 A2 VDD A12 A15 C D NC I/O16 I/OP3 VSS NC VSS I/OP2 I/O15 E I/O17 I/O18 VSS CE1 VSS I/O13 I/O14 F VDDQ I/O19 VSS OE VSS I/O12 VDDQ G I/O20 I/O21 BW3 A17 BW2 I/O11 I/O10 H I/O22 I/O23 VSS R/W VSS I/O9 I/O8 J VDDQ VDD VDD(1) VDD VDD(1) VDD VDDQ K I/O24 I/O26 VSS CLK VSS I/O6 I/O7 L I/O25 I/O27 BW4 NC BW1 I/O4 I/O5 M VDDQ I/O28 VSS CEN VSS I/O3 VDDQ N I/O29 I/O30 VSS A1 VSS I/O2 I/O1 P I/O31 I/OP4 VSS A0 VSS I/OP1 I/O0 R NC A5 LBO VDD A13 NC T NC U VDDQ 2 VDD(1) NC A10 A11 A14 DNU(3) DNU(3) DNU(3) DNU(3) NC DNU(3) ZZ VDDQ 5303 drw 13A , Top View Pin Configuration - 512K X 18, 119 BGA 1 2 3 4 5 6 7 A VDDQ A6 A4 NC(2) A8 A16 VDDQ B NC CE2 A3 ADV/LD A9 CE2 NC C NC A7 A2 VDD A13 A17 NC D I/O8 NC VSS NC VSS I/OP1 NC E NC I/O9 VSS CE1 VSS NC I/O7 F VDDQ NC VSS OE VSS I/O6 VDDQ G NC I/O10 BW2 A18 VSS NC I/O5 H I/O11 NC VSS R/W VSS I/O4 NC J VDDQ VDD VDD(1) VDD VDD(1) VDD VDDQ K NC I/O12 VSS CLK VSS NC I/O3 L I/O13 NC VSS NC BW1 I/O2 NC M VDDQ I/O14 VSS CEN VSS NC VDDQ N I/O15 NC VSS A1 VSS I/O1 NC P NC I/OP2 VSS A0 VSS NC I/O0 R NC A5 LBO VDD VDD(1) A12 NC T NC A10 A15 NC A14 A11 ZZ DNU(3) DNU(3) U VDDQ DNU(3) DNU(3) DNU(3) VDDQ 5303 drw 13B Top View NOTES: 1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH. 2. A4 is reserved for future 16M. 3. DNU = Do not use. Pin U2, U3, U4, U5 and U6 are reserved for respective JTAG pins: TMS, TDI, TCK, TDO and TRST. these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD). 6.42 7 The current die revision allows IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Pin Configuration - 256K X 36, 165 fBGA 1 2 3 4 5 6 7 8 9 10 11 A NC(2) A7 CE1 BW3 BW2 CE2 CEN ADV/LD A17 A8 NC B NC A6 CE 2 BW4 BW1 CLK R/ W OE NC(2) A9 NC(2) C I/OP3 NC VDDQ VSS VSS V SS V SS VSS V DDQ NC I/OP2 D I/O17 I/O16 VDDQ VDD VSS V SS V SS VDD V DDQ I/O15 I/O14 E I/O19 I/O18 VDDQ VDD VSS V SS V SS VDD V DDQ I/O13 I/O12 F I/O21 I/O20 VDDQ VDD VSS V SS V SS VDD V DDQ I/O11 I/O10 G I/O23 I/O22 VDDQ VDD VSS V SS V SS VDD V DDQ I/O9 I/O8 NC VDD VSS V SS V SS VDD NC NC ZZ (1) VDD (1) H VDD J I/O25 I/O24 VDDQ VDD VSS V SS V SS VDD V DDQ I/O7 I/O6 K I/O27 I/O26 VDDQ VDD VSS V SS V SS VDD V DDQ I/O5 I/O4 L I/O29 I/O28 VDDQ VDD VSS V SS V SS VDD V DDQ I/O3 I/O2 M I/O31 I/O30 VDDQ VDD VSS V SS V SS VDD V DDQ I/O1 I/O0 N I/OP4 NC VDDQ VSS DNU(3) NC V DD(1) VSS V DDQ NC I/OP1 (3) (3) (2) A5 A2 DNU A1 DNU A 10 A13 A14 NC A4 A3 DNU(3) A0 DNU(3) A 11 A12 A15 A16 P NC NC R LBO NC(2) 5303 tbl 25a Pin Configuration - 512K X 18, 165 fBGA 1 2 3 4 5 6 7 8 9 10 11 A NC(2) A7 CE1 BW2 NC CE2 CEN ADV /LD A18 A8 A10 B NC A6 CE 2 NC BW1 CLK R/ W OE NC(2) A9 NC(2) C NC NC VDDQ V SS V SS V SS V SS V SS VDDQ NC I/OP1 D NC I/O8 VDDQ V DD V SS V SS V SS V DD VDDQ NC I/O7 E NC I/O9 VDDQ V DD V SS V SS V SS V DD VDDQ NC I/O6 F NC I/O10 VDDQ V DD V SS V SS V SS V DD VDDQ NC I/O5 G NC I/O11 VDDQ V DD V SS V SS V SS V DD VDDQ NC I/O4 H VDD (1) VDD (1) NC V DD V SS V SS V SS V DD NC NC ZZ J I/O12 NC VDDQ V DD V SS V SS V SS V DD VDDQ I/O3 NC K I/O13 NC VDDQ V DD V SS V SS V SS V DD VDDQ I/O2 NC L I/O14 NC VDDQ V DD V SS V SS V SS V DD VDDQ I/O1 NC M I/O15 NC VDDQ V DD V SS V SS V SS V DD VDDQ I/O0 NC N I/OP2 NC VDDQ V SS DNU(3) NC VDD (1) V SS VDDQ NC NC P NC NC(2) A5 A2 DNU(3) A1 DNU(3) A11 A14 A15 NC R LBO (2) A3 (3) A0 (3) A 12 A13 A16 A17 NC A4 DNU DNU 5303 tbl25b NOTES: 1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH . 2. B9, B11, A1, R2 and P2 is reserved for future 18M, 36M, 72M, 144M and 288M, respectively. 3. DNU=Do not use. Pins P5, R5, P7, R7 and N5 are reserved for respective JTAG pins: TDI, TMS, TDO, TCK and TRST on future revisions. The current die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD). 6.42 8 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Synchronous Truth Table(1) CEN R/W Chip(5) Enable ADV/LD BWx ADDRESS USED PREVIOUS CYCLE CURRENT CYCLE I/O (2 cycles later) L L Select L Valid External X LOAD WRITE D(7) L H Select L X External X LOAD READ Q(7) L X X H Valid Internal LOAD WRITE / BURST WRITE BURST WRITE (Advance burst counter)(2) D(7) L X X H X Internal LOAD READ / BURST READ BURST READ (Advance burst counter)(2) Q(7) L X Deselect L X X X DESELECT or STOP(3) HiZ L X X H X X DESELECT / NOOP NOOP HiZ H X X X X X X SUSPEND(4) Previous Value 5303 tbl 08 NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle. 3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state two cycles after deselect is initiated. 4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/ Os remains unchanged. 5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false. 6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up. 7. Q - Data read from the device, D - data written to the device. Partial Truth Table for Writes(1) R/W BW 1 BW 2 BW 3(3) BW 4(3) READ H X X X X WRITE ALL BYTES L L L L L L L H H H OPERATION WRITE BYTE 1 (I/O[0:7], I/OP1)(2) (2) WRITE BYTE 2 (I/O[8:15], I/OP2) L H L H H (2,3) WRITE BYTE 3 (I/O[16:23], I/OP3) L H H L H WRITE BYTE 4 (I/O[24:31], I/OP4)(2,3) L H H H L NO WRITE L H H H H 5303 tbl 09 NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. Multiple bytes may be selected during the same cycle. 3. N/A for X18 configuration. 6.42 9 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Interleaved Burst Sequence Table (LBO=VDD) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 0 0 1 1 1 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address (1) 1 1 1 0 0 1 0 0 5303 tbl 10 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Linear Burst Sequence Table (LBO=VSS) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 1 0 1 1 0 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address (1) 1 1 0 0 0 1 1 0 5303 tbl 11 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Functional Timing Diagram(1) CYCLE n+29 n+30 n+31 n+32 n+33 n+34 n+35 n+36 n+37 A29 A30 A31 A32 A33 A34 A35 A36 A37 C29 C30 C31 C32 C33 C34 C35 C36 C37 D/Q27 D/Q28 D/Q29 D/Q30 D/Q31 D/Q32 D/Q33 D/Q34 D/Q35 CLOCK (2) ADDRESS (A0 - A17) (2) CONTROL (R/W, ADV/LD, BWx) (2) DATA I/O [0:31], I/O P[1:4] 5303 drw 03 NOTES: 1. This assumes CEN, CE1, CE2, CE2 are all true. 2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay from the rising edge of clock. 6.42 10 , IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles(2) Cycle Address R/ W ADV/ LD CE (1) CEN BWx OE I/O Comments n A0 H L L L X X X Load read n+1 X X H X L X X X Burst read n+2 A1 H L L L X L Q0 Load read n+3 X X L H L X L Q0+1 n+4 X X H X L X L Q1 NOOP n+5 A2 H L L L X X Z Load read n+6 X X H X L X X Z Burst read n+7 X X L H L X L Q2 Deselect or STOP n+8 A3 L L L L L L Q2+1 Load write n+9 X X H X L L X Z Burst write n+10 A4 L L L L L X D3 Load write n+11 X X L H L X X D3+1 n+12 X X H X L X X D4 NOOP n+13 A5 L L L L L X Z Load write n+14 A6 H L L L X X Z Load read n+15 A7 L L L L L X D5 Load write n+16 X X H X L L L Q6 Burst write n+17 A8 H L L L X X D7 Load read n+18 X X H X L X X D7+1 Burst read n+19 A9 L L L L L L Q8 Load write Deselect or STOP Deselect or STOP 5303 tbl 12 NOTES: 1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 2. H = High; L = Low; X = Don’t Care; Z = High Impedance. Read Operation(1) Cycle Address R/ W ADV/ LD CE (2) CEN BWx OE I/O Comments n A0 H L L L X X X Address and Control meet setup n+1 X X X X L X X X Clock Setup Valid n+2 X X X X X X L Q0 Contents of Address A0 Read Out NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 6.42 11 5303 tbl 13 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Burst Read Operation(1) Cycle Address R/W ADV/LD CE (2) CEN BWx OE I/O Comments n A0 H L L L X X X Address and Control meet setup n+1 X X H X L X X X Clock Setup Valid, Advance Counter n+2 X X H X L X L Q0 Address A0 Read Out, Inc. Count n+3 X X H X L X L Q0+1 Address A0+1 Read Out, Inc. Count n+4 X X H X L X L Q0+2 Address A0+2 Read Out, Inc. Count n+5 A1 H L L L X L Q0+3 Address A0+3 Read Out, Load A1 n+6 X X H X L X L Q0 Address A0 Read Out, Inc. Count n+7 X X H X L X L Q1 Address A1 Read Out, Inc. Count n+8 A2 H L L L X L Q1+1 Address A1+1 Read Out, Load A2 5303 tbl 14 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Write Operation(1) Cycle Address R/ W ADV/ LD CE (2) CEN BWx OE I/O Comments n A0 L L L L L X X Address and Control meet setup n+1 X X X X L X X X Clock Setup Valid n+2 X X X X L X X D0 Write to Address A0 5303 tbl 15 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Burst Write Operation(1) Cycle Address R/ W ADV/ LD CE (2) CEN BWx OE I/O Comments n A0 L L L L L X X Address and Control meet setup n+1 X X H X L L X X Clock Setup Valid, Inc. Count n+2 X X H X L L X D0 Address A0 Write, Inc. Count n+3 X X H X L L X D0+1 Address A0+1 Write, Inc. Count n+4 X X H X L L X D0+2 Address A0+2 Write, Inc. Count n+5 A1 L L L L L X D0+3 Address A0+3 Write, Load A1 n+6 X X H X L L X D0 Address A0 Write, Inc. Count n+7 X X H X L L X D1 Address A1 Write, Inc. Count n+8 A2 L L L L L X D1+1 Address A1+1 Write, Load A2 NOTES: 1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 6.42 12 5303 tbl 16 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Read Operation with Clock Enable Used(1) Cycle Address R/ W ADV/ LD CE (2) CEN BWx OE I/O Comments n A0 H L L L X X X Address and Control meet setup n+1 X X X X H X X X Clock n+1 Ignored n+2 A1 H L L L X X X Clock Valid n+3 X X X X H X L Q0 Clock Ignored, Data Q0 is on the bus. n+4 X X X X H X L Q0 Clock Ignored, Data Q0 is on the bus. n+5 A2 H L L L X L Q0 Address A0 Read out (bus trans.) n+6 A3 H L L L X L Q1 Address A1 Read out (bus trans.) n+7 A4 H L L L X L Q2 Address A2 Read out (bus trans.) 5303 tbl 17 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Write Operation with Clock Enable Used(1) Cycle Address R/ W ADV /LD CE (2) CEN BWx OE I/O Comments n A0 L L L L L X X Address and Control meet setup. n+1 X X X X H X X X Clock n+1 Ignored. n+2 A1 L L L L L X X Clock Valid. n+3 X X X X H X X X Clock Ignored. n+4 X X X X H X X X Clock Ignored. n+5 A2 L L L L L X D0 Write Data D0 n+6 A3 L L L L L X D1 Write Data D1 n+7 A4 L L L L L X D2 Write Data D2 5303 tbl 18 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 6.42 13 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Read Operation with Chip Enable Used(1) Cycle Address R/ W ADV/ LD CE (2) CEN BWx OE I/O(3) Comments n X X L H L X X ? Deselected. n+1 X X L H L X X ? Deselected. n+2 A0 H L L L X X Z Address and Control meet setup n+3 X X L H L X X Z Deselected or STOP. n+4 A1 H L L L X L Q0 Address A0 Read out. Load A 1. n+5 X X L H L X X Z Deselected or STOP. n+6 X X L H L X L Q1 Address A1 Read out. Deselected. n+7 A2 H L L L X X Z Address and control meet setup. n+8 X X L H L X X Z Deselected or STOP. n+9 X X L H L X L Q2 Address A2 Read out. Deselected. 5303 tbl 19 NOTES: 1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up. Write Operation with Chip Enable Used(1) Cycle Address R/W ADV/ LD CE (2) CEN BWx OE I/O(3) Comments n X X L H L X X ? Deselected. n+1 X X L H L X X ? Deselected. n+2 A0 L L L L L X Z Address and Control meet setup n+3 X X L H L X X Z Deselected or STOP. n+4 A1 L L L L L X D0 Address D0 Write in. Load A 1. n+5 X X L H L X X Z Deselected or STOP. n+6 X X L H L X X D1 Address D1 Write in. Deselected. n+7 A2 L L L L L X Z Address and control meet setup. n+8 X X L H L X X Z Deselected or STOP. n+9 X X L H L X X D2 Address D2 Write in. Deselected. NOTES: 1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 6.42 14 5303 tbl 20 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V +/-5%) Symbol Parameter Test Conditions Min. Max. Unit |ILI| Input Leakage Current VDD = Max., VIN = 0V to V DD ___ 5 µA |ILI| LBO Input Leakage Current(1) VDD = Max., VIN = 0V to V DD ___ 30 µA |ILO| Output Leakage Current VOUT = 0V to V DDQ, Device Deselected ___ 5 µA 0.4 V ___ V VOL Output Low Voltage IOL = +6mA, VDD = Min. ___ VOH Output High Voltage IOH = -6mA, VDD = Min. 2.0 NOTE: 5303 tbl 21 1. The LBO pin will be internally pulled to V DD if it is not actively driven in the application and the ZZ pin will be internally pulled to Vss if not actively driven. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (1) (VDD = 3.3V +/-5%) 150MHz Sym bol Param eter ID D IS B 1 IS B 2 IS B 3 Izz 133MHz 100MHz Com 'l Ind Com 'l Ind Com 'l Ind Op e rating Po we r Sup ply Current De vice Se le cte d , Outputs Op e n, ADV/ LD = X, V D D = M ax., V IN > V IH o r < V IL, f = fM A X (2 ) 325 345 300 320 250 270 mA CM OS S tandb y Po we r Sup ply Current De vice De se le cte d, Outp uts Op en, V D D = M ax., V IN > V H D o r < V LD , f = 0 (2,3) 40 60 40 60 40 60 mA Clo ck Running Po we r Sup ply Current De vice De se le cte d, Outp uts Op en, V D D = M ax., V IN > V H D o r < V LD , f = fM A X (2.3) 120 140 110 130 100 120 mA Id le Po we r Sup ply Current De vice Se le cte d , Outputs Op e n, CEN > V IH , V D D = M ax., V IN > V H D o r < V LD , f = fM A X (2,3) 40 60 40 60 40 60 mA Full Sle e p Mo d e Sup ply Current De vice Se le cte d , Outputs Op e n, CEN ≤ V IL, V D D = M ax., ZZ ≥ V H D V IN ≥ V H D o r ≤ V LD , f = fM A X (2, 3) 40 60 40 60 40 60 mA NOTES: 1. All values are maximum guaranteed values. 2. At f = f MAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC ; f=0 means no input lines are changing. 3. For I/Os V HD = VDDQ – 0.2V, VLD = 0.2V. For other inputs V HD = VDD – 0.2V, VLD = 0.2V. AC Test Load I/O (VDDQ = 2.5V) Z0 = 50Ω 6 5303 drw 04 5 Figure 1. AC Test Load 4 ∆tCD 3 (Typical, ns) 2 • • 20 30 50 Input Pulse Levels , Input Rise/Fall Times • 0 to 2.5V 2ns Input Timing Reference Levels VDDQ/2 Output Timing Reference Levels VDDQ/2 AC Test Load • • 80 100 Capacitance (pF) 5303 tb l 2 2 AC Test Conditions VDDQ/2 50Ω 1 Unit Test Conditions See Figure 1 5303 tbl 23 200 5303 drw 05 , Figure 2. Lumped Capacitive Load, Typical Derating 6.42 15 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges) 150MHz Symbol Parameter 133MHz 100MHz Min. Max. Min. Max. Min. Max. Unit tCYC Clock Cycle Time 6.7 ____ 7.5 ____ 10 ____ ns tF(1) Clock Frequency ____ 150 ____ 133 ____ 100 MHz tCH(2) Clock High Pulse Width 2.0 ____ 2.2 ____ 3.2 ____ ns tCL(2) Clock Low Pulse Width 2.0 ____ 2.2 ____ 3.2 ____ ns Output Parameters tCD Clock High to Valid Data ____ 3.8 ____ 4.2 ____ 5 ns tCDC Clock High to Data Change 1.5 ____ 1.5 ____ 1.5 ____ ns tCLZ(3,4,5) Clock High to Output Active 1.5 ____ 1.5 ____ 1.5 ____ ns tCHZ(3,4,5) Clock High to Data High-Z 1.5 3 1.5 3 1.5 3.3 ns tOE Output Enable Access Time ____ 3.8 ____ 4.2 ____ 5 ns tOLZ(3,4) Output Enable Low to Data Active 0 ____ 0 ____ 0 ____ ns tOHZ(3,4) Output Enable High to Data High-Z ____ 3.8 ____ 4.2 ____ 5 ns tSE Clock Enable Setup Time 1.5 ____ 1.7 ____ 2.0 ____ ns tSA Address Setup Time 1.5 ____ 1.7 ____ 2.0 ____ ns 1.7 ____ 2.0 ____ ns Set Up Times tSD Data In Setup Time 1.5 ____ tSW Read/Write (R/W) Setup Time 1.5 ____ 1.7 ____ 2.0 ____ ns tSADV Advance/Load (ADV/LD) Setup Time 1.5 ____ 1.7 ____ 2.0 ____ ns 1.5 ____ 1.7 ____ 2.0 ____ ns 1.7 ____ 2.0 ____ ns 0.5 ____ 0.5 ____ ns 0.5 ____ ns tSC Chip Enable/Select Setup Time tSB Byte Write Enable (BWx) Setup Time 1.5 ____ Clock Enable Hold Time 0.5 ____ 0.5 ____ Hold Times tHE tHA Address Hold Time 0.5 ____ tHD Data In Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHW Read/Write (R/W) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHADV Advance/Load (ADV/LD) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns 0.5 ____ 0.5 ____ ns 0.5 ____ 0.5 ____ ns tHC Chip Enable/Select Hold Time 0.5 ____ tHB Byte Write Enable (BWx) Hold Time 0.5 ____ NOTES: 5303 tbl 24 1. tF = 1/tCYC. 2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ. 3. Transition is measured ±200mV from steady-state. 4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested. 5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ, which is a Max. parameter (worse case at 70 deg. C, 3.135V). 6.42 16 6.42 17 A1 tSADV tHA tHW tHE tCLZ tHC Pipeline Read tSC A2 tSA tSW tSE tCD Pipeline Read Q(A1) tHADV tCH tCDC tCL Q(A 2) O1(A2) , O2(A2) 2+1) Q(A Q(A2+2) (CEN high, eliminates current L-H clock edge) Burst Pipeline Read tCD Q(A2+2) tCDC Q(A2+3) tCHZ O1(A2) Q(A 2) 5303 drw 06 (Burst Wraps around to initial state) NOTES: 1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A 2; Q (A2+1) represents the next output data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. DATAOUT OE BW1 - BW4 CE1, CE2 (2) ADDRESS R/W ADV/LD CEN CLK tCYC IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle(1,2,3,4) 6.42 18 (2) A1 tSADV tHW tHE tHB tHC Pipeline Write tSB tSC tHA A2 tSA tSW tSE . tHD Pipeline Write D(A1) tSD tHADV tCH D(A2) tCL D(A2+1) Burst Pipeline Write (CEN high, eliminates current L-H clock edge) tSD D(A2+2) tHD D(A2) 5303 drw 07 D(A2+3) (Burst Wraps around to initial state) NOTES: 1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. 5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. DATAIN OE BW1 - BW4 CE1, CE2 ADDRESS R/W ADV/LD CEN CLK tCYC IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycles(1,2,3,4,5) 6.42 19 A1 tSADV tHW tHE tCD tHB tHC Read tSB tSC tHA A2 tSA tSW tSE A3 Q(A1) tCHZ Write tHADV tCH tCLZ Read D(A2) tSD tHD A4 tCL Q(A3) tCDC Write A5 D(A4) A6 Read D(A5) A7 Q(A6) A8 Q(A7) A9 5303 drw 08 , NOTES: 1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. DATAOUT DATAIN OE BW1 - BW4 CE1, CE2(2) ADDRESS R/W ADV/LD CEN CLK tCYC IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Timing Waveform of Combined Read and Write Cycles(1,2,3) , 6.42 20 A1 tSE tSADV tHE tHW tHC tCD tCLZ tHB B(A2) tSB tSC tHA A2 tSA tSW tCH tHADV Q(A1) tCL tCHZ tCDC Q(A1) A3 D(A2) tSD tHD A4 NOTES: 1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE 2 is HIGH. 3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers in the SRAM will retain their previous state. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. DATAOUT DATAIN OE BW1 - BW4 CE1, CE2(2) ADDRESS R/W ADV/LD CEN CLK tCYC 5303 drw 09 Q(A3) A5 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Timing Waveform of CEN Operation(1,2,3,4) 6.42 21 A1 tSADV tHW tHE tSC tCLZ tCD tHC tHA A2 tSA tSW tSE Q(A1 ) tHADV tCH tCDC tCHZ tHB Q(A2) tSB A3 tCL D(A3) tSD tHD A4 Q(A4 ) A5 5303 drw 10 , NOTES: 1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE 2 is HIGH. 3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers in the SRAM will retain their previous state. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. DATAOUT DATAIN OE BW1 - BW4 CE1, CE2 (2) ADDRESS R/W ADV/LD CEN CLK tCYC IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Timing Waveform of CS Operation(1,2,3,4) IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges 100-Pin Thin Plastic Quad Flatpack (TQFP) Package Diagram Outline 6.42 22 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges 119 Ball Grid Array (BGA) Package Diagram Outline 6.42 23 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges 165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline 6.42 24 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Timing Waveform of OE Operation(1) OE tOE tOHZ tOLZ DATAOUT Valid , 5303 drw 11 NOTE: 1. A read operation is assumed to be in progress. Ordering Information IDT XXXX S XX XX Device Type Power Speed Package X Process/ Temperature Range Blank I Commercial (0° C to +70° C) Industrial (-40° C to +85° C) PF BG BQ 100 pin Plastic Thin Quad Flatpack, 100 pin 119 Ball Grid Array (BGA) 165 Fine Pitch Ball Grid Array (fBGA) 150 133 100 Clock Frequency in Megahertz IDT71V65602 256Kx36 Pipelined ZBT SRAM IDT71V65802 512Kx18 Pipelined ZBT SRAM 5303 drw 12 6.42 25 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs ZBT Commercial and Industrial Temperature Ranges Datasheet Document History 12/31/99 03/04/00 04/20/00 05/16/00 07/28/00 11/04/00 12/04/02 12/19/02 10/15/04 Created new datasheet from obsolete devices IDT71V656 and IDT71V658 Pg.1,14,15 Removed 166MHz speed grade offering; Added 150MHz speed grade offering Pg. 5,6 Add JTAG test pins to TQFP pin configuration; removed footnote Add clarification note to Recommended Operating Temperature and Absolute Max Ratings tables Pg. 7 Add note to BGA Pin configuration; corrected typo in pinout Pg. 21 Insert TQFP Package Diagram Outline Add new package offering, 13 x 15mm 165fBGA Pg. 23 Correct error in the 119 BGA Package Diagram Outline Pg. 5-8 Remove JTAG pins from TQFP, BG119 and BQ165 pinouts, refer to IDT71V656xx and IDT71V658xx device errata Pg. 7,8 Correct error in pinout, B2 on BG119 and B1 on BQ165 pinout Pg. 23 Update BG119 Package Diagram Dimensions Pg. 15 Add Izz parameter to DC Electrical Characteristics Pg. 8 Add note to pin N5 on the BQ165 pinout, reserved for JTAG TRST Pg. 1-26 Changed datasheet from Preliminary to Final Release. Pg. 5,6,15, Added I temp to datasheet. 16,25 Pg. 1,2,5,6, Removed JTAG functionality for current die revision. 7,8 Pg. 7 Corrected x36,119BGA pin configuration. Switched pins I/O0 and I/OP1. Pg. 5,6 Updated temperature Ta note. Pg. 7 Updated pin configuration 512K x 18 for the 119 BGA - reordered I/O signals on P7, N6, L6, K7, H6, G7, F6, E7, D6. . CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 26 for Tech Support: [email protected] 800-544-7726