TI1 LM311PW Quad differential comparator Datasheet

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LM111, LM211, LM311
SLCS007I – SEPTEMBER 1973 – REVISED JUNE 2015
LMx11 Quad Differential Comparators
1 Features
3 Description
•
•
•
•
•
•
The LM111, LM211, and LM311 devices are single
high-speed voltage comparators. These devices are
designed to operate from a wide range of powersupply voltages, including ±15-V supplies for
operational amplifiers and 5-V supplies for logic
systems. The output levels are compatible with most
TTL and MOS circuits. These comparators are
capable of driving lamps or relays and switching
voltages up to 50 V at 50 mA. All inputs and outputs
can be isolated from system ground. The outputs can
drive loads referenced to ground, VCC+ or VCC−. Offset
balancing and strobe capabilities are available, and
the outputs can be wire-OR connected. If the strobe
is low, the output is in the off state, regardless of the
differential input.
1
•
Fast Response Time: 165 ns
Strobe Capability
Maximum Input Bias Current: 300 nA
Maximum Input Offset Current: 70 nA
Can Operate From Single 5-V Supply
Available in Q-Temp Automotive
– High-Reliability Automotive Applications
– Configuration Control and Print Support
– Qualification to Automotive Standards
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
Device Information(1)
PACKAGE
BODY SIZE
2 Applications
LMx11D
PART NUMBER
SOIC (8)
4.90 mm × 3.91 mm
•
LMx11DK
LCCC (20)
8.89 mm × 8.89 mm
LMx11JG
CDIP (8)
9.60 mm × 6.67 mm
LMx11P
PDIP (8)
9.81 mm × 6.35 mm
LMx11PS
SOP (8)
6.20 mm × 5.30 mm
LMx11PW
TSSOP (8)
3.00 mm × 4.40 mm
Desktop PCs
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
BALANCE
BAL/STRB
IN+
+
COL OUT
IN−
−
EMIT OUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM111, LM211, LM311
SLCS007I – SEPTEMBER 1973 – REVISED JUNE 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
5
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information (8-Pin Packages) .....................
Thermal Information (20-Pin Package) .....................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 11
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
9.3 System Examples ................................................... 14
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (August 2003) to Revision I
Page
•
Updated Features with Military Disclaimer. ............................................................................................................................ 1
•
Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. No specification changes. ........................................................................... 1
2
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5 Pin Configuration and Functions
D, JG, P, PS, or PW Package
8-Pin SOIC, CDIP, PDIP, SOP or TSSOP
Top View
8
2
7
3
6
4
5
VCC+
COL OUT
BAL/STRB
BALANCE
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
NC
VCC−
NC
IN+
NC
IN−
NC
NC
COL OUT
NC
BAL/STRB
NC
NC
BALANCE
NC
1
NC
EMIT OUT
NC
VCC+
NC
EMIT OUT
IN+
IN−
VCC−
FK Package
20-Pin LCCC(1)
Top View
(1) NC = No internal connection
Pin Functions
PIN
SOIC, CDIP,
PDIP, SOP,
TSSOP
LCCC
1IN+
2
5
I
Noninverting comparator
1IN–
3
7
I
Inverting input comparator
BALANCE
5
12
I
Balance
BAL/STRB
6
15
I
Strobe
COL OUT
7
17
O
Output collector comparator
EMIT OUT
1
2
O
Output emitter comparator
VCC–
4
10
—
Negative supply
VCC+
8
20
—
Positive supply
—
No connect (No internal connection)
NAME
I/O (1)
DESCRIPTION
1
3
4
6
8
NC
—
9
11
13
14
16
18
19
(1)
I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage
MAX
VCC+ (2)
18
VCC– (2)
–18
VCC+ – VCC–
36
Differential input voltage (3)
VID
VI
Input voltage (either input)
(2) (4)
Voltage from emitter output to VCC–
Voltage from collector output to VCC–
TJ
Tstg
(1)
(2)
(3)
(4)
V
±15
V
30
V
50
LM211
50
LM211Q
50
LM311
40
Operating virtual-junction temperature
V
±30
LM111
Duration of output short circuit to ground
UNIT
V
10
s
150
°C
Case temperature for 60 s
FK package
260
°C
Lead temperature 1,6 mm (1/16 inch) from case, 10 s
J or JG package
300
°C
Lead temperature 1,6 mm (1/16 inch) from case, 60 s
D, P, PS, or PW
package
260
°C
150
°C
−65
Storage temperature range
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC–.
Differential voltages are at IN+ with respect to IN–.
The magnitude of the input voltage must never exceed the magnitude of the supply voltage or ±15 V, whichever is less.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VCC+ – VCC–
Supply voltage
VI
Input voltage (|VCC+| ≤ 15 V)
TA
Operating free-air temperature range
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UNIT
3.5
30
V
VCC– + 0.5
VCC+ – 1.5
V
LM111
–55
125
LM211
–40
85
LM211Q
–40
125
0
70
LM311
4
MAX
°C
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6.4 Thermal Information (8-Pin Packages)
LMx11
THERMAL METRIC
(1)
D (SOIC)
P (PDIP)
PS (SOP)
PW
(TSSOP)
JG (CDIP)
8 PINS
8 PINS
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
97
85
95
149
—
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
—
—
—
—
14.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information (20-Pin Package)
LMx11
THERMAL METRIC
(1)
FK (LCCC)
UNIT
20 PINS
RθJC(top)
(1)
Junction-to-case (top) thermal resistance
5.61
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Electrical Characteristics
at specified free-air temperature, VCC± = ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
LM111
LM211
LM211Q
(1)
MIN
VIO
Input offset voltage
See (3)
IIO
Input offset current
See (3)
IIB
Input bias current
1 V ≤ VO ≤ 14 V
IIL(S)
Low-level
strobe current (4)
V(strobe) = 0.3 V,
VID ≤ –10 mV
Common-mode
input-voltage
range (3)
Lower range
VICR
AVD
Large-signal
differential-voltage
amplification
IOH
High-level
(collector)
output leakage
current
VOL
Low-level
(collector-toemitter)
output voltage
VCC+ = 4.5 V,
VCC– = 0 V,
IOL = 8 mA
0.7
3
25°C
4
75
Full range
VOH = 35 V
VID = –5 mV
10
25°C
Full range
VID = –10 mV
Full range
100
250
300
–3
–14.5
–14.7
13
13.8
40
200
40
200
0.2
50
70
100
mV
nA
nA
mA
–14.5
V
V/mV
10
nA
0.5
μA
25°C
VID = –6 mV
6
13.8
25°C
VID = –10 mV
7.5
13
Full range
25°C
2
10
–3
–14.7
25°C
MAX
150
25°C
UNIT
TYP (2)
20
25°C
Full range
MIN
4
Full range
VID = 5 mV, VOH = 35 V
IOL = 50 mA
MAX
25°C
5 V ≤ VO ≤ 35 V, RL = 1 kΩ
I(strobe) = –3 mA,
VID = 5 mV
TYP (2)
Full range
Upper range
LM311
0.75
1.5
0.23
0.4
0.2
50
0.75
1.5
nA
V
0.23
0.4
ICC+
Supply current from
VCC+
VID = –10 mV,
output low
No load
25°C
5.1
6
5.1
7.5
mA
ICC–
Supply current from
VCC–
VID = 10 mV,
output high
No load
25°C
–4.1
–5
–4.1
–5
mA
(1)
(2)
(3)
(4)
Unless otherwise noted, all characteristics are measured with BALANCE and BAL/STRB open and EMIT OUT grounded. Full range for
LM111 is –55°C to 125°C, for LM211 is –40°C to 85°C, for LM211Q is –40°C to 125°C, and for LM311 is 0°C to 70°C.
All typical values are at TA = 25°C.
The offset voltages and offset currents given are the maximum values required to drive the collector output up to 14 V or down to 1 V
with a pullup resistor of 7.5 kΩ to VCC+. These parameters actually define an error band and take into account the worst-case effects of
voltage gain and input impedance.
The strobe must not be shorted to ground; it must be current driven at –3 mA to –5 mA (see Figure 18 and Figure 31).
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6.7 Switching Characteristics
VCC± = ±15 V, TA = 25°C
PARAMETER
LM111
LM211
LM211Q
LM311
TEST CONDITIONS
UNIT
TYP
Response time, low-to-high-level outputSee
(1)
Response time, high-to-low-level outputSee (1)
(1)
(2)
6
RC = 500 Ω to 5 V, CL = 5 pF, see
(2)
115
ns
165
ns
The response time specified is for a 100-mV input step with 5-mV overdrive and is the interval between the input step function and the
instant when the output crosses 1.4 V.
The package thermal impedance is calculated in accordance with MIL-STD-883.
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6.8 Typical Characteristics
Condition 1 is with BALANCE and BAL/STRB open.
Condition 2 is with BALANCE and BAL/STRB connected to VCC+.
Figure 1. Input Offset Current vs Free-Air Temperature
Condition 1 is with BALANCE and BAL/STRB open.
Condition 2 is with BALANCE and BAL/STRB connected to VCC+.
Figure 2. Input Bias Current vs Free-Air Temperature
Figure 3. Output Response for Various Input Overdrives
Figure 4. Output Response for Various Input Overdrives
Figure 5. Output Current and Dissipation vs Output Voltage
Figure 6. Positive Supply Current vs Positive Supply
Voltage
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Typical Characteristics (continued)
60
VO − Output Voltage − V
50
VCC+ = 30 V
VCC− = 0
TA = 25°C
LM111
LM211
LM311
40
30
Emitter Output
RL = 600 Ω
Collector
Output
RL = 1 kΩ
20
10
0
−1
−0.5
0
0.5
1
VID − Differential Input Voltage − mV
Figure 7. Negative Supply Current vs Negative Supply
Voltage
8
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Figure 8. Voltage Transfer Characteristics and Test Circuits
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7 Parameter Measurement Information
VCC+
VI = 50 V (LM111, LM211)
40 V (LM311)
= 30 V
VCC+ = 30 V
1 kΩ
VID
Output
Output
VID
600 Ω
VCC−
VCC−
Figure 9. Collector Output Transfer Characteristic
Test Circuit
VCC+ = 15 V
Figure 10. Emitter Output Transfer Characteristic
Test Circuit
VCC+ = 15 V
5V
500 Ω
VO
VID
VID
VO
VCC− = −15 V
RE = 2 kΩ
VCC− = −15 V
Figure 11. Test Circuit for Figure 3 and Figure 4
Figure 12. Test Circuit for Figure 14 and Figure 15
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8 Detailed Description
8.1 Overview
The LM111, LM211 and LM311 are voltage comparators that have input currents nearly a thousand times lower
than legacy standard devices. They are also designed to operate over a wider range of supply voltages: from
standard ±15V op amp supplies down to the single 5-V supply used for IC logic. Their output is compatible with
RTL, DTL and TTL as well as MOS circuits. Further, they can drive lamps or relays, switching voltages up to 50
V at currents as high as 50 mA.
Both the inputs and the outputs of the LM111, LM211 or the LM311 can be isolated from system ground, and the
output can drive loads referred to ground, the positive supply or the negative supply. Offset balancing and strobe
capability are provided and outputs can be wire ORed. The LM211 is identical to the LM111, except that its
performance is specified over a −25°C to +85°C temperature range instead of −55°C to +125°C. The LM311 has
a temperature range of 0°C to +70°C.
8.2 Functional Block Diagram
Component Count
Resistors
Diodes
EPI FET
Transistors
BAL/STRB BALANCE
450 Ω
450 Ω
20
2
1
22
VCC+
2.4
kΩ
750 Ω
2.4
kΩ
600 Ω
70 Ω
1.2 kΩ
1.2 kΩ
IN+
4 kΩ
COL OUT
IN−
400 Ω
130 Ω
60 Ω
600 Ω
450 Ω
250 Ω
200 Ω
4Ω
2 kΩ
EMIT OUT
VCC−
8.3 Feature Description
LMx11 consists of a PNP input stage to sense voltages near VCC–. It also contains balance and strobe pins for
external offset adjustment or trimming.
The input stage is followed by a very high gain stage for very fast response after a voltage difference on the input
pins have been sensed.
10
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Feature Description (continued)
This is then followed by the output stage that consists of an open collector NPN (pulldown or low-side) transistor.
Unlike most open drain comparators, this NPN output stage has an isolated emitter from VCC–, allowing this
device to set the VOL output value for collector output.
8.4 Device Functional Modes
8.4.1 Voltage Comparison
The LMx11 operates solely as a voltage comparator, comparing the differential voltage between the positive and
negative pins and outputting a logic low or high impedance (logic high with pullup) based on the input differential
polarity.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Validate and test
the design implementation to confirm system functionality.
9.1 Application Information
A typical LMx11 application compares a single signal to a reference or two signals against each other. Many
users take advantage of the open-drain output to drive the comparison logic output to a logic voltage level to an
MCU or logic device. The wide supply range and high voltage capability makes LMx11 optimal for level shifting to
a higher or lower voltage.
9.2 Typical Application
VCC+
20 kΩ
Output
Input
VCC−
Figure 13. Zero-Crossing Detector
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
PARAMETER
VIN
Input voltage range
VCC+
Positive supply voltage
VCC–
Negative supply voltage
IOUT
Output current
MIN
TYP
–15
MAX
UNIT
13
V
15
V
20
mA
–15
9.2.2 Detailed Design Procedure
When using LMx11 in a general comparator application, determine the following:
• Input voltage range
• Minimum overdrive voltage
• Output and drive current
• Response time
9.2.2.1 Input Voltage Range
When choosing the input voltage range, consider the input common mode voltage range (VICR). Operation
outside of this range can yield incorrect comparisons.
The following list describes the outcomes of some input voltage situations.
12
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•
•
•
•
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When both IN– and IN+ are both within the common-mode range:
– If IN– is higher than IN+ and the offset voltage, the output is low and the output transistor is sinking
current
– If IN– is lower than IN+ and the offset voltage, the output is high impedance and the output transistor is
not conducting
When IN– is higher than common mode and IN+ is within common mode, the output is low and the output
transistor is sinking current
When IN+ is higher than common mode and IN– is within common mode, the output is high impedance and
the output transistor is not conducting
When IN– and IN+ are both higher than common mode, the output is undefined
9.2.2.2 Minimum Overdrive Voltage
Overdrive voltage is the differential voltage produced between the positive and negative inputs of the comparator
over the offset voltage (VIO). In order to make an accurate comparison the Overdrive voltage (VOD) must be
higher than the input offset voltage (VIO). Overdrive voltage can also determine the response time of the
comparator, with the response time decreasing with increasing overdrive. Figure 14 and Figure 15 show positive
and negative response times with respect to overdrive voltage.
9.2.2.3 Output and Drive Current
Output current is determined by the pullup resistance and pullup voltage. The output current produces a output
low voltage (VOL) from the comparator, in which VOL is proportional to the output current. Use Figure 5 to
determine VOL based on the output current.
The output current can also effect the transient response.
9.2.2.4 Response Time
The load capacitance (CL), pullup resistance (RPULLUP), and equivalent collector-emitter resistance (RCE) levels
determine the transient response. Equation 1 approximates the positive response time. Equation 2 approximates
the negative response time. RCE can be determine by taking the slope of Figure 5 in the linear region at the
desired temperature, or by Equation 3.
tP @ RPULLUP ´ CL
(1)
tN @ RCE ´ CL
V
RCE = OL
IOUT
(2)
where
•
•
VOL is the low-level output voltage
IOUT is the output current
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(3)
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9.2.3 Application Curves
µ
µ
Figure 14. Output Response for Various Input Overdrives
Figure 15. Output Response for Various Input Overdrives
9.3 System Examples
Figure 16 through Figure 33 show various applications for the LM111, LM211, and LM311 comparators.
VCC+
20 kΩ
1 kΩ
Square Wave
Output
(fanout to two
Series 54 gates,
or equivalent)
10 kΩ
1200 pF
20 kΩ
39 kΩ
Figure 16. 100-kHz Free-Running Multivibrator
VCC+
3 kΩ
3 kΩ
BALANCE
BAL/
STRB
If offset balancing is not used, the BALANCE and BAL/STRB pins must be unconnected. It is also acceptable to short
pins together.
Figure 17. Offset Balancing
14
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System Examples (continued)
BAL/STRB
TTL
Strobe
2N2222
1 kΩ
Do not connect strobe pin directly to ground, because the output is turned off whenever current is pulled from the
strobe pin.
Figure 18. Strobing
5V
1 kΩ
82 kΩ
240 kΩ
Input†
Output to TTL
‡
47 kΩ
82 kΩ
†
‡
Resistor values shown are for a 0- to 30-V logic swing and a 15-V threshold.
May be added to control speed and reduce susceptibility to noise spikes
Figure 19. TTL Interface With High-Level Logic
5V
VCC+
100 kΩ
2 kΩ
4.5 kΩ
2 kΩ
100 kHz
10 pF
Output
to TTL
Output
1 kΩ
100 kΩ
0.1 µF
50 kΩ
Magnetic
Transducer
Figure 20. Detector for Magnetic Transducer
Figure 21. 100-kHz Crystal Oscillator
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System Examples (continued)
From D/A Network
VCC+
VCC+
Output
22 kΩ
Analog
Input†
BALANCE
Input
BAL/STRB
0.1 µF
TTL
Strobe
2N2222
Sample
1 kΩ
†
Figure 22. Comparator and Solenoid Driver
Typical input current is 50 pA with inputs strobed off.
Figure 23. Strobing Both Input and Output Stages
Simultaneously
VCC+
VCC+ = 5 V
500 Ω
3.9 kΩ
3 kΩ
10 kΩ
3 kΩ
Output
2N3708
BAL/
STRB
BALANCE
Output
to MOS
Input
+
1.5 µF
1 kΩ
10 kΩ
2N2222
VCC− = −10 V
Figure 24. Low-Voltage Adjustable Reference
Supply
Figure 25. Zero-Crossing Detector Driving MOS
Logic
VCC+ = 5 V
3.9 kΩ
30 kن
2N3708
1 kΩ
1 kΩ
1N914
Output
+
1N914
Input
From
TTL
2N2222
1.5 µF
2N2222
2.7 kΩ
2N2222
†
510 Ω
2.2 kΩ
Adjust to set clamp level
Figure 26. Precision Squarer
16
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Copyright © 1973–2015, Texas Instruments Incorporated
Product Folder Links: LM111 LM211 LM311
LM111, LM211, LM311
www.ti.com
SLCS007I – SEPTEMBER 1973 – REVISED JUNE 2015
System Examples (continued)
VCC+ = 5 V
5V
Opto Isolator
From
TTL
Gate
5 kΩ
1 kΩ
TTL
Output
100 Ω
1 kΩ
50 kΩ
0.01 µF
1 kΩ
Figure 27. Digital Transmission Isolator
VCC+ = 15 V
2 kΩ
Input
TL081
−
Output
10 kΩ
+
+
1.5 µF
1 MΩ
VCC− = −15 V
Figure 28. Positive-Peak Detector
VCC+ = 15 V
1 MΩ
TL081
10 kΩ
2 kΩ
+
Input
Output
−
+
15 µF
VCC− = −15 V
Figure 29. Negative-Peak Detector
Copyright © 1973–2015, Texas Instruments Incorporated
Product Folder Links: LM111 LM211 LM311
Submit Documentation Feedback
17
LM111, LM211, LM311
SLCS007I – SEPTEMBER 1973 – REVISED JUNE 2015
www.ti.com
System Examples (continued)
VCC+ = 5 V
3.9 kΩ
1N2175
2N3708
1 kΩ
Output
to TTL
2N2222
R1†
30 kΩ
†
R1 sets the comparison level. At comparison, the photodiode has less than 5 mV across it, decreasing dark current by an order of magnitude.
Figure 30. Precision Photodiode Comparator
VCC+
Inputs
BAL/STRB
‡
VCC−
TTL
Strobe
2N3708
1 kΩ
‡
Transient voltage and inductive kickback protection
Figure 31. Relay Driver With Strobe
18
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Copyright © 1973–2015, Texas Instruments Incorporated
Product Folder Links: LM111 LM211 LM311
LM111, LM211, LM311
www.ti.com
SLCS007I – SEPTEMBER 1973 – REVISED JUNE 2015
System Examples (continued)
VCC+
620 Ω
BAL/STRB
300 Ω
1
100 kΩ
Output
100 kΩ
BAL/STRB
2
10 kΩ
Input
0.1 µF
300 Ω
47 Ω
620 Ω
VCC−
Figure 32. Switching Power Amplifier
VCC+
39 kΩ
620 Ω
300 kΩ
620 Ω
BAL/STRB
1
15 kΩ
Reference
VCC−
620 Ω
0.22 µF
Outputs
V+
510 Ω
15 kΩ
510 Ω
Input
620 Ω
BAL/STRB
2
VCC−
39 kΩ
620 Ω
300 kΩ
620 Ω
Figure 33. Switching Power Amplifiers
Copyright © 1973–2015, Texas Instruments Incorporated
Product Folder Links: LM111 LM211 LM311
Submit Documentation Feedback
19
LM111, LM211, LM311
SLCS007I – SEPTEMBER 1973 – REVISED JUNE 2015
www.ti.com
10 Power Supply Recommendations
For fast response and comparison applications with noisy or AC inputs, use a bypass capacitor on the supply pin
to reject any variation on the supply voltage. This variation can affect the common-mode range of the comparator
input and create an inaccurate comparison.
11 Layout
11.1 Layout Guidelines
To create an accurate comparator application without hysteresis, maintain a stable power supply with minimized
noise and glitches, which can affect the high level input common-mode voltage range. To achieve this accuracy,
add a bypass capacitor between the supply voltage and ground. Place a bypass capacitor on the positive power
supply and negative supply (if available).
11.2 Layout Example
Ground
Bypass
Capacitor
Negative Supply or Ground
Only needed
for dual power
supplies
EMIT OUT
1IN+
1INí
VCC-
1
2
3
4
0.1PF
VCC+
7
COL OUT
6 BAL/STROB
5 BALANCE
8
Positive Supply
0.1PF
Ground
Figure 34. LMx11 Layout Example
20
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Copyright © 1973–2015, Texas Instruments Incorporated
Product Folder Links: LM111 LM211 LM311
LM111, LM211, LM311
www.ti.com
SLCS007I – SEPTEMBER 1973 – REVISED JUNE 2015
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LM111
Click here
Click here
Click here
Click here
Click here
LM211
Click here
Click here
Click here
Click here
Click here
LM311
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
Copyright © 1973–2015, Texas Instruments Incorporated
Product Folder Links: LM111 LM211 LM311
Submit Documentation Feedback
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
JM38510/10304BPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510
/10304BPA
LM111FKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
LM111FKB
LM111JG
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
LM111JG
LM111JGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
LM111JGB
LM211D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LM211
LM211DE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LM211
LM211DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LM211
LM211DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LM211
LM211DRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LM211
LM211DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LM211
LM211P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
LM211P
LM211PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
LM211P
LM211PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
L211
LM211PWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
L211
LM211PWRE4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
L211
LM211PWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
L211
LM211QD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LM211Q
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM211QDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LM211Q
LM211QDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LM211Q
LM211QDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LM211Q
LM311D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LM311
LM311DE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LM311
LM311DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LM311
LM311DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
0 to 70
LM311
LM311DRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LM311
LM311DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LM311
LM311P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
LM311P
LM311PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
LM311P
LM311PSR
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
L311
LM311PSRE4
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
L311
LM311PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
L311
LM311PWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
L311
LM311PWLE
OBSOLETE
TSSOP
PW
8
TBD
Call TI
Call TI
LM311PWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
L311
LM311PWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
L311
LM311Y
OBSOLETE
DIESALE
Y
0
TBD
Call TI
Call TI
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Jun-2014
Status
(1)
M38510/10304BPA
ACTIVE
Package Type Package Pins Package
Drawing
Qty
CDIP
JG
8
1
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
A42
N / A for Pkg Type
Op Temp (°C)
Device Marking
(4/5)
-55 to 125
JM38510
/10304BPA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM211 :
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
• Automotive: LM211-Q1
• Enhanced Product: LM211-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Nov-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM211DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
LM211DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
LM211DRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
LM211DRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
LM211PWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
LM311DR
SOIC
D
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
LM311DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
LM311DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
LM311DRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
LM311DRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
LM311PSR
SO
PS
8
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
LM311PWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Nov-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM211DR
SOIC
D
8
2500
340.5
338.1
20.6
LM211DR
SOIC
D
8
2500
367.0
367.0
35.0
LM211DRG4
SOIC
D
8
2500
340.5
338.1
20.6
LM211DRG4
SOIC
D
8
2500
367.0
367.0
35.0
LM211PWR
TSSOP
PW
8
2000
367.0
367.0
35.0
LM311DR
SOIC
D
8
2500
364.0
364.0
27.0
LM311DR
SOIC
D
8
2500
367.0
367.0
35.0
LM311DR
SOIC
D
8
2500
340.5
338.1
20.6
LM311DRG4
SOIC
D
8
2500
367.0
367.0
35.0
LM311DRG4
SOIC
D
8
2500
340.5
338.1
20.6
LM311PSR
SO
PS
8
2000
367.0
367.0
38.0
LM311PWR
TSSOP
PW
8
2000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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