DS1254 2M x 8 NV SRAM with Phantom Clock www.maxim-ic.com FEATURES § § § § § § § § § PACKAGE OUTLINE Real-time clock (RTC) keeps track of hundredths of seconds, seconds, minutes, hours, days, date, months, and years with automatic leap-year compensation valid up to the year 2100 2M x 8 NV SRAM Watch function is transparent to RAM operation Automatic data protection during power loss Unlimited write-cycle endurance Surface-mountable BGA module construction Over 10 years of data retention in the absence of power Battery monitor checks remaining capacity daily +3.3V or +5V operation Side -A- Shown (For Reference Only, Not to Scale) Component placement may vary. ORDERING INFORMATION APPLICATIONS PART Telecom Switches Routers RAID Systems DS1254WB150 DS1254YB100 DS1254WB2150 DS1254YB2100 TYPICAL OPERATING CIRCUIT PINPACKAGE TEMP RANGE BGA, 3.3V 0°C to +70°C BGA, 5V 0°C to +70°C BGA, 3.3V 0°C to +70°C BGA, 5V 0°C to +70°C TOP MARK DS1254W150 DS1254Y100 DS1254W2150 DS1254Y2100 PIN DESCRIPTION VCC A0–A20 DQ0–DQ7 CE OE WE BW GND - Supply Voltage - Address Inputs - Data I/O - Chip-Enable Input - Output-Enable Input - Write-Enable Input - Battery Warning Output (Open Drain) - Ground Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 17 REV: 082203 DS1254 DESCRIPTION The DS1254 is a fully nonvolatile static RAM (NV SRAM) (organized as 2M words by 8 bits) with builtin real-time clock. It has a self-contained lithium energy source and control circuitry that constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the DS1254 makes use of an attached DS3800 battery cap to maintain clock information and preserve stored data while protecting that data by disallowing all memory accesses. Additionally, the DS1254 has dedicated circuitry for monitoring the status of an attached DS3800 battery cap. The phantom clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap years. The phantom clock operates in either 24-hour or 12-hour format with an AM/PM indicator. Because the DS1254 has a total of 168 balls and only 35 active signals, balls are wired together into groups, thus providing redundant connections for every signal. VCC A16 A15 A11 37 A14 A10 38 A13 A9 39 A12 A8 40 GND VCC 41 Figure 1. Pin Assignment VCC 1 A7 2 A6 30 31 32 33 34 35 36 VBAT Dallas Semiconductor 29 VCC 28 A17 3 27 A18 A5 4 26 A19 GND 5 25 GND A4 6 24 A20 A3 7 23 CE A2 8 22 OE A1 9 21 WE DS1254 20 19 18 17 16 15 14 13 12 11 10 RECEPTACLES FOR DS3800 BATTERY CAP PINS 2 of 17 BW DQ7 DQ6 DQ5 DQ4 GND DQ3 DQ2 DQ1 DQ0 A0 GND DS1254 RAM READ MODE The DS1254 executes a read cycle whenever WE is inactive (high) and CE is active (low). The unique address specified by the 21 address inputs (A0–A20) defines which of the 2MB of data is to be accessed. Valid data will be available to the eight data-output drivers within tACC (access time) after the last address input is stable, providing that CE and OE access times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than address access. RAM WRITE MODE The DS1254 is in the write mode whenever WE and CE are in their active (low) state after address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE active), then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The device is fully accessible and data can be written and read only when VCC is greater than VPF. However, when VCC falls below the power-fail point, VPF (point at which write protection occurs), the internal clock registers and SRAM are blocked from any access. When VCC falls below VBAT, device power is switched from the VCC to VBAT. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. All signals must be powered down when VCC is powered down. PHANTOM CLOCK OPERATION Communication with the phantom clock is established by pattern recognition on a serial bit stream of 64 bits that must be matched by executing 64 consecutive write cycles containing the proper data on DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory. After recognition is established, the next 64 read or write cycles either extract or update data in the phantom clock, and memory access is inhibited. Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable ( CE ), output enable ( OE ), and write enable ( WE ). Initially, a read cycle to any memory location using the CE and OE control of the phantom clock starts the pattern-recognition sequence by moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CE and WE signals of the device. These 64 write cycles are used only to gain access to the phantom clock. Therefore, any address within the first 512kB of memory, (00h to 7FFFFh) is acceptable. However, the write cycles generated to gain access to the phantom clock are also writing data to a location in the memory. The preferred way to manage this requirement is to set aside just one address location in memory as a phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not 3 of 17 DS1254 advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched (this bit pattern is shown in Figure 2). With a correct match for 64-bits, the phantom clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without interrupting the pattern-recognition sequence or data-transfer sequence to the phantom clock. PHANTOM CLOCK REGISTER INFORMATION The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially accessed one bit at a time after the 64-bit pattern-recognition sequence has been completed. When updating the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These read/write registers are defined in Figure 3. Figure 2. Phantom Clock Protocol Definition NOTE: THE PATTERN RECOGNITION IN HEX IS C5, 3A, A3, 5C, C5, 3A, A3, 5C. THE ODDS OF THIS PATTERN BEING ACCIDENTALLY DUPLICATED AND CAUSING INADVERTENT ENTRY TO THE PHANTOM CLOCK IS LESS THAN 1 IN 1019. THIS PATTERN IS SENT TO THE PHANTOM CLOCK LSB TO MSB. 4 of 17 DS1254 Figure 3. Phantom Clock Register Definition 5 of 17 DS1254 AM/PM/12/24 MODE Bit 7 of the hours register is defined as the 12-hour or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). OSCILLATOR BIT Bit 5 of the day register controls the oscillator. When set to logic 1, the oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. ZERO BITS Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that will always read logic 0. When writing these locations, either a logic 1 or logic 0 is acceptable. BATTERY MONITORING The DS1254 automatically monitors the battery in an attached DS3800 battery cap on a 24-hour time interval. Such monitoring begins within tREC after VCC rises above VPF and is suspended when power failure occurs. After each 24-hour period has elapsed, the battery is connected to an internal 1MW test resistor for one second. During this one second, if the battery voltage falls below the battery-voltage trip point (~2.6V), the battery warning output BW is asserted. Once asserted, BW remains active until the attached DS3800 battery cap is replaced. However, the battery is still retested after each VCC power-up, even if it was active on power-down. If the battery voltage is found to be higher than ~2.6V during such testing, BW is de-asserted and regular testing resumes. BW has an open-drain output driver. 6 of 17 DS1254 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature -0.3V to +6.0V 0°C to +70°C -40°C to +70°C See IPC/JEDEC J-STD-020A Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device. RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70°C) PARAMETER Power-Supply Voltage (5V Operation) Power-Supply Voltage (3.3V Operation) Logic 1 Voltage (All Inputs) Logic 0 Voltage (All Inputs) SYMBOL MIN TYP MAX UNITS NOTES VCC 4.5 5.0 5.5 V 1 VCC 3.0 3.3 3.7 V 1 V 1 V 1 VIH VIL CONDITIONS VCC = 5V ±10% 2.2 VCC = 3.3V ±10% 2.0 VCC = 5V ±10% -0.3 VCC + 0.3 VCC + 0.3 0.8 VCC = 3.3V ±10% -0.3 0.6 DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±10%, TA = 0°C to +70°C.) PARAMETER Input Leakage Current I/O Leakage Current Output Current at 2.4V Output Current at 0.4V Standby Current (CE = 2.2V) Standby Current (CE = VCC - 0.5V) Operating Current, tCYC = 100ns Write Protection Voltage SYMBOL MIN IIL IIO IOH IOL -4.0 -4.0 -1.0 2.0 ICCS1 ICCS2 ICCO1 VPF TYP 5.0 3.0 4.25 MAX UNITS NOTES +4.0 +4.0 10 5.0 85 4.50 mA mA mA mA mA mA mA V 1 MAX UNITS NOTES +4.0 +4.0 mA mA mA mA mA mA mA V 3 3 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±10%, TA = 0°C to +70°C.) PARAMETER Input Leakage Current I/O Leakage Current Output Current at 2.4V Output Current at 0.4V Standby Current (CE = 2.2V) Standby Current (CE = VCC - 0.5V) Operating Current, tCYC = 100ns Write Protection Voltage SYMBOL MIN IIL IIO IOH IOL -4.0 -4.0 -1.0 2.0 ICCS1 ICCS2 ICCO1 VPF TYP 5.0 2.0 2.8 7 of 17 7 3.0 50 2.97 3 3 1 DS1254 CAPACITANCE (TA = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS Input Capacitance: A0 to A18, OE, WE, CE CIN 25 50 pF Input Capacitance: A19 to A20 CIN 5 10 pF I/O Capacitance: DQ0 to DQ7 CIO 25 50 pF COUT 5 10 pF Output Capacitance: BW NOTES AC ELECTRICAL CHARACTERISTICS ° ° (VCC = 5.0V ±10%, TA = 0 C to +70 C.) PARAMETER Read Cycle Time Address Access Time OE to Output Valid CE to Output Valid CE or OE to Output Active Output High-Z from Deselection Output Hold from Address Change Write Cycle Time WE, CE Pulse Width Address Setup Time Address Hold Time Output High-Z from WE Output Active from WE Data Setup Time Data Hold Time Read Recovery (Clock Access Only) Write Recovery (Clock Access Only) SYMBOL MIN tRC tAAC tOE tCO tCOE tOD tOH tWC tWP tAW tAH1 tAH2 tODW tOEW tDS tDH1 tDH2 tRR tWR 100 MAX 100 55 100 0 35 5 100 70 0 5 25 35 5 40 0 20 20 20 8 of 17 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 2 2 5 6 7 2 2 8 6 8 DS1254 AC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±10%, TA = 0°C to +70°C) PARAMETER Read Cycle Time Address Access Time OE to Output Valid CE to Output Valid CE or OE to Output Active Output High-Z from Deselection Output Hold from Address Change Write Cycle Time WE, CE Pulse Width Address Setup Time Address Hold Time Output High-Z from WE Output Active from WE Data Setup Time Data Hold Time Read Recovery (Clock Access Only) Write Recovery (Clock Access Only) SYMBOL MIN tRC tAAC tOE tCO tCOE tOD tOH tWC tWP tAW tAH1 tAH2 tODW tOEW tDS tDH1 tDH2 tRR tWR 150 MAX 150 75 150 0 70 5 150 100 0 5 25 70 5 60 0 20 20 20 9 of 17 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 2 2 5 6 7 2 2 8 6 8 DS1254 Figure 4. Memory Read Cycle Timing (Note 9) tRC ADDRESS tOH tACC tCO CE tOD tOE OE tCOE tCOE tOD OUTPUT DATA VALID DQ0–DQ7 Figure 5. Memory Write Cycle Timing, Write-Enable Controlled (Notes 5, 6, 8, 10, 11, 12, and 13) tWC ADDRESS tAW CE tAH1 WE tWP tODW tOEW tDS DQ0–DQ7 DATA IN STABLE 10 of 17 tDH1 DS1254 Figure 6. Memory Write Cycle Timing, Chip-Enable Controlled (Notes 5, 7, 8, 10, 11, 12, and 13) tWC ADDRESS tAW tAH2 tWP CE WE tODW tCOE tDH2 tDS DQ0–DQ7 DATA IN STABLE Figure 7. Read Cycle to Phantom Clock tRC WE = VIH tRR tCO CE tOD tOE OE tCOE DQ0 tCOE tOD OUTPUT DATA VALID 11 of 17 DS1254 Figure 8. Write Cycle to Phantom Clock tWC OE = VIH tWR tWP WE TAH2 tWP CE tDH2 tDS tDH1 DATA IN STABLE DQ0 Figure 9. Power-Up/Power-Down Waveform Timing (Note 14) VCC VPF(max) VPF(min) VBAT tPD tF tFB tREC tDR SLEWS WITH VCC CE tR , WE SLEWS WITH VCC tBPU BW POWER-UP/POWER-DOWN CHARACTERISTICS (VCC = 5V ±10%) PARAMETER CE and WE at VIH Before Power-Down VCC Fall Time: VPF(MAX) to VPF(MIN) VCC Fall Time: VPF(MIN) to VBAT VCC Rise Time: 0V to VPF(MIN) VCC Valid to End of Write Protection VCC Valid to BW Valid SYMBOL MIN tPD tF tFB tR tREC tBPU 0 300 10 150 SYMBOL MIN tDR 10 TYP MAX UNITS NOTES 125 1 ms ms ms ms ms s 3 MAX UNITS NOTES years 4 (TA = +25°C) PARAMETER Expected Data-Retention Time (Oscillator On) TYP WARNING: UNDER NO CIRCUMSTANCES ARE NEGATIVE UNDERSHOOTS, OF ANY AMPLITUDE, ALLOWED WHEN DEVICE IS IN BATTERY-BACKUP MODE. 12 of 17 DS1254 Figure 10. Battery Warning Detection (Note 3) VCC tBPU VBAT 2.6V tBTC tBTPW BATTERY TEST ACTIVE tBW BW BATTERY WARNING TIMING (VCC = 5.0V ±10%, TA = 0°C to +70°C) PARAMETER Battery Test Cycle Battery Test Pulse Width Battery Test to BW Active VCC Valid to BW Valid SYMBOL MIN TYP MAX UNITS NOTES 1 1 1 hour seconds seconds seconds 3 24 tBTC tBTPW tBW tBPU AC TEST CONDITIONS Output Load: 100pF + 1 TTL Gate Input Pulse Levels: 0V to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns 13 of 17 DS1254 NOTES: 1) Voltage referenced to ground. 2) These parameters are sampled with a 50pF load and are not 100% tested. 3) BW is an open-drain output and, as such, cannot source current. An external pullup resistor should be connected to this pin for proper operation. BW can sink 10mA. 4) The DS3800 battery cap is a one-time use part, but can be removed and replaced. By design, DS3800 removal will mechanically damage the battery cap, which eliminates the accidental use of a previously attached and possibly low-capacity battery cap. 5) tWP specified as the logical AND of CE and WE , tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 6) tAH1, tDH1 are measured from WE going high. 7) tAH2, tDH2 are measured from CE going high. 8) tDS is measured from the earlier of CE or WE going high. 9) WE is high for a read cycle. 10) OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. 11) If the CE low transition occurs simultaneously with or later than the WE low transition in a writeenable-controlled write cycle, the output buffers remain in a high-impedance state during this period. 12) If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high-impedance state during this period. 13) If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 14) In a power-down condition, the voltage on any pin cannot exceed the voltage on VCC. 14 of 17 DS1254 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) PKG A B C D E F G H I K 15 of 17 IN MM IN MM IN MM IN MM IN MM IN MM IN MM IN MM IN MM IN MM MIN MAX 1.570 39.88 1.570 39.88 0.033 0.84 1.497 38.02 0.047 1.19 0.033 0.84 0.047 1.19 0.234 5.94 0.160 4.00 0.025 0.64 1.580 40.13 1.580 40.13 0.043 1.09 1.503 38.18 0.053 1.35 0.043 1.09 0.053 1.35 0.240 6.10 0.200 5.10 0.032 0.82 DS1254 PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) DS1254 with Attached DS3800 Battery Cap PKG A IN MM B IN MM C IN MM 16 of 17 MIN MAX 1.656 42.06 1.656 42.06 — — 1.668 42.37 1.668 42.37 0.485 12.32 DS1254 PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) Recommended Land Pattern (with Overlaid Package Outline) The DS1254 BGA is a subset of the industry-standard 40mm BGA format, with all balls on a 50-mil grid. Corner balls have been removed to provide space for the electrical and mechanical interface features that facilitate attachment of the DS3800 battery cap. NOTE 0.250 0.500 0.150 NOTE: GROUND SHIELD TO ISOLATE RTC XTAL FROM EMI. Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products · Printed USA 17 of 17