ON MC33260P Greenline tm compact power factor controller: innovative circuit for cost effective solution Datasheet

MC33260
GreenLinet Compact
Power Factor Controller:
Innovative Circuit for
Cost Effective Solutions
The MC33260 is a controller for Power Factor Correction
preconverters meeting international standard requirements in
electronic ballast and off−line power conversion applications.
Designed to drive a free frequency discontinuous mode, it can also be
synchronized and in any case, it features very effective protections that
ensure a safe and reliable operation.
This circuit is also optimized to offer extremely compact and cost
effective PFC solutions. While it requires a minimum number of
external components, the MC33260 can control the follower boost
operation that is an innovative mode allowing a drastic size reduction
of both the inductor and the power switch. Ultimately, the solution
system cost is significantly lowered.
Also able to function in a traditional way (constant output voltage
regulation level), any intermediary solutions can be easily
implemented. This flexibility makes it ideal to optimally cope with a
wide range of applications.
General Features
•
•
•
•
•
•
•
•
•
•
•
Filtering
Capacitor
L1
CT
R OCP
8
7
6
5
8
1
1
8
SO−8
D SUFFIX
CASE 751
8
33260
ALYW
G
1
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
Feedback Input
1
8 VCC
Vcontrol
2
7 Gate Drive
3
6 Gnd
4
5 Synchronization
Input
Oscillator
Capacitor (CT)
Current Sense
Input
Synchronization
Input
Gnd
1
8 Vcontrol
2
7 Feedback Input
3
6 VCC
4
5 Gate Drive
MC33260D
+ C1
V CC
MC33260P
AWL
YYWWG
PDIP−8
P SUFFIX
CASE 626
MC33260P
D1
MC33260
1
2
3
4
Vcontrol
R cs
8
Oscillator
Capacitor (CT)
Current Sense
Input
Overvoltage Protection: Output Overvoltage Detection
Undervoltage Protection: Protection Against Open Loop
Effective Zero Current Detection
Accurate and Adjustable Maximum On−Time Limitation
Overcurrent Protection
ESD Protection on Each Pin
D1...D4
MARKING
DIAGRAMS
1
Standard Constant Output Voltage or “Follower Boost” Mode
Switch Mode Operation: Voltage Mode
Latching PWM for Cycle−by−Cycle On−Time Control
Constant On−Time Operation That Saves the Use of an Extra Multiplier
Totem Pole Output Gate Drive
Undervoltage Lockout with Hysteresis
Low Startup and Operating Current
Improved Regulation Block Dynamic Behavior
Synchronization Capability
Internally Trimmed Reference Current Source
Pb−Free Packages are Available
Safety Features
•
•
•
•
•
•
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LOAD
(SMPS, Lamp
Ballast,...)
M1
Ro
ORDERING INFORMATION
Sync
DIP−8 CONFIGURATION SHOWN
See detailed ordering and shipping information in the package
dimensions section on page 20 of this data sheet.
Figure 1. Typical Application
© Semiconductor Components Industries, LLC, 2005
September, 2005 − Rev. 9
1
Publication Order Number:
MC33260/D
MC33260
Vo
Current Mirror
IOSC − ch =
Io
2 x IO x IO
Iref
Io
CT
Io
0
Current
Mirror
Iref
Vref
11 V
1
FB
Io
1.5 V
15 pF
Io
97%Iref
300 k
Vreg
Vcontrol
Iref
Output_Ctrl
IovpH/IovpL
11 V
Vref
REGULATOR
+
Iref
Enable
−
OVP
r
Iuvp
r
−
11 V/8.5 V
+
+
UVP
−
Ics (205 mA)
Synchro
r
−60 mV
1
0
11 V
+
Current
Sense
Synchro
Arrangement
−
LEB
VCC
11 V
Output_Ctrl
ThStdwn
Drive
Gnd
S
R
+
R
−
R
Q
PWM
Latch
Output_Ctrl
Q
PWM Comparator
MC33260
Figure 2. Block Diagram
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2
MC33260
MAXIMUM RATINGS
Pin #
PDIP−8
Pin #
SO−8
Gate Drive Current*
Source
Sink
7
5
VCC Maximum Voltage
8
Rating
Symbol
Value
Unit
IO(Source)
IO(Sink)
−500
500
(Vcc)max
16
V
Vin
−0.3 to +10
V
PD
RqJA
600
100
mW
°C/W
Operating Junction Temperature
TJ
150
°C
Operating Ambient Temperature
TA
−40 to +105
°C
mA
6
Input Voltage
Power Dissipation and Thermal Characteristics
P Suffix, PDIP Package
Maximum Power Dissipation @ TA = 85°C
Thermal Resistance Junction−to−Air
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
ELECTRICAL CHARACTERISTICS (VCC = 13 V, TJ = 25°C for typical values, TJ = −40 to 105°C for min/max values
unless otherwise noted.)
Pin #
PDIP−8
Pin #
SO−8
Gate Drive Resistor
Source Resistor @ IDrive = 100 mA
Sink Resistor @ IDrive = 100 mA
7
5
Gate Drive Voltage Rise Time (From 3.0 V Up to 9.0 V)
(Note 1)
7
Output Voltage Falling Time (From 9.0 V Down to 3.0 V)
(Note 1)
Characteristic
Symbol
Min
Typ
Max
Unit
ROL
ROH
10
5
20
10
35
25
5
tr
−
50
−
ns
7
5
tf
−
50
−
ns
Maximum Oscillator Swing
3
1
DVT
1.4
1.5
1.6
V
Charge Current @ IFB = 100 mA
3
1
Icharge
87.5
100
112.5
mA
Charge Current @ IFB = 200 mA
3
1
Icharge
350
400
450
mA
Ratio Multiplier Gain Over Maximum Swing
@ IFB = 100 mA
3
1
Kosc
5600
6400
7200
1/(V.A)
Ratio Multiplier Gain Over Maximum Swing
@ IFB = 200 mA
3
1
Kosc
5600
6400
7200
1/(V.A)
Average Internal Oscillator Pin Capacitance Over
Oscillator Maximum Swing (CT Voltage Varying From
0 Up to 1.5 V) (Note 2)
3
1
Cint
10
15
20
pF
Discharge Time (CT = 1.0 nF)
3
1
Tdisch
−
0.5
1.0
ms
Regulation High Current Reference
1
7
IregH
192
200
208
mA
Ratio (Regulation Low Current Reference) / IregH
1
7
IregL / IregH
0.965
0.97
0.98
−
Vcontrol Impedance
1
7
ZVcontrol
−
300
−
kW
GATE DRIVE SECTION
W
OSCILLATOR SECTION
REGULATION SECTION
NOTE: IFB is the current that is drawn by the Feedback Input Pin.
1. 1.0 nF being connected between the Pin 7 and ground for PDIP−8, between Pin 5 and ground for SO−8.
2. Guaranteed by design.
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3
MC33260
ELECTRICAL CHARACTERISTICS (VCC = 13 V, TJ = 25°C for typical values, TJ = −40 to 105°C for min/max values
unless otherwise noted.)
Pin #
PDIP−8
Pin #
SO−8
Symbol
Min
Typ
Max
Unit
Feedback Pin Clamp Voltage @ IFB = 100 mA
1
7
VFB−100
1.5
2.1
2.5
V
Feedback Pin Clamp Voltage @ IFB = 200 mA
1
7
VFB−200
2.0
2.6
3.0
V
Zero Current Detection Comparator Threshold
4
2
VZCD−th
−90
−60
−30
mV
Negative Clamp Level (ICS−pin = −1.0 mA)
4
2
Cl−neg
−
−0.7
−
V
Bias Current @ Vcs = VZCD−th
4
2
Ib−cs
−0.2
−
−
mA
Propagation Delay (Vcs > VZCD−th) to Gate Drive High
7
5
TZCD
−
500
−
ns
Current Sense Pin Internal Current Source
4
2
IOCP
192
205
218
mA
τLEB
−
400
−
ns
Characteristic
REGULATION SECTION (continued)
CURRENT SENSE SECTION
Leading Edge Blanking Duration
OverCurrent Protection Propagation Delay
(Vcs < VZCD−th to Gate Drive Low)
7
5
TOCP
100
160
240
ns
Synchronization Threshold
PDIP−8
SO−8
5
−
−
3
Vsync−th
Vsync−th
0.8
0.8
1.0
1.0
1.2
1.4
V
V
Negative Clamp Level (Isync = −1.0 mA)
5
3
Cl−neg
−
−0.7
−
V
Minimum Off−Time
7
5
Toff
1.5
2.1
2.7
ms
Minimum Required Synchronization Pulse Duration
5
3
Tsync
−
−
0.5
ms
OverVoltage Protection High Current Threshold
and IregH Difference
1
7
IOVPH−IregH
8.0
13
18
mA
OverVoltage Protection Low Current Threshold
and IregH Difference
1
7
IOVPL−IregH
0
−
−
−
Ratio (IOVPH/IOVPL)
1
7
IOVPH / IOVPL
1.02
−
−
−
Propagation Delay (IFB > 110% Iref to Gate Drive Low)
7
5
TOVP
−
500
−
ns
Ratio (UnderVoltage Protection Current
Threshold) / IregH
1
7
IUVP/IregH
12
14
16
%
Propagation Delay (IFB < 12% Iref to Gate Drive Low)
7
5
TUVP
−
500
−
ns
Thermal Shutdown Threshold
7
5
Tstdwn
—
150
−
°C
Hysteresis
7
5
DTstdwn
−
30
−
°C
Startup Threshold
8
6
Vstup−th
9.7
11
12.3
V
Disable Voltage After Threshold Turn−On
8
6
Vdisable
7.4
8.5
9.6
V
8
6
ICC
−
−
0.1
4.0
0.25
8.0
SYNCHRONIZATION SECTION
OVERVOLTAGE PROTECTION SECTION
UNDERVOLTAGE PROTECTION SECTION
THERMAL SHUTDOWN SECTION
VCC UNDERVOLTAGE LOCKOUT SECTION
TOTAL DEVICE
Power Supply Current
Startup (VCC = 5 V with VCC Increasing)
Operating @ IFB = 200 mA
NOTE:
Vcs is the Current Sense Pin Voltage and IFB is the Feedback Pin Current.
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4
mA
MC33260
Vcontrol : REGULATION BLOCK OUTPUT (V)
Vcontrol : REGULATION BLOCK OUTPUT (V)
Pin Numbers are Relevant to the PDIP−8 Version
1.6
1.4
1.2
1.0
0.8
0.6
− 40°C
0.4
25°C
0.2
105°C
0
20
0
40
60
80 100 120 140 160 180 200 220 240
1.6
− 40°C
1.4
25°C
1.2
105°C
1.0
0.8
0.6
0.4
0.2
0
185
190
Ipin1: FEEDBACK CURRENT (mA)
Figure 3. Regulation Block Output versus
Feedback Current
205
210
3.5
1.335
FEEDBACK INPUT VOLTAGE (V)
MAXIMUM OSCILLATOR SWING (V)
200
Figure 4. Regulation Block Output versus
Feedback Current
1.340
1.330
1.325
1.320
1.315
1.310
1.305
3.0
2.5
2.0
1.5
− 40°C
1.0
25°C
0.5
105°C
0
1.300
−40
−20
0
20
40
60
80
0
100
20
40
JUNCTION TEMPERATURE (°C)
I osc−ch , OSCILLATOR CHARGE CURRENT (m A)
450
400
25°C
350
105°C
300
250
200
150
100
50
0
0
20
40
60
80 100 120 140 160 180 200 220 240
Figure 6. Feedback Input Voltage versus
Feedback Current
500
− 40°C
60
Ipin1: FEEDBACK CURRENT (mA)
Figure 5. Maximum Oscillator Swing versus
Temperature
I osc−ch , OSCILLATOR CHARGE CURRENT (m A)
195
Ipin1: FEEDBACK CURRENT (mA)
80 100 120 140 160 180 200 220 240
410
Ipin1 = 200 mA
405
400
395
390
385
−40
−20
0
20
40
60
80
JUNCTION TEMPERATURE (°C)
Ipin1: FEEDBACK CURRENT (mA)
Figure 7. Oscillator Charge Current versus
Feedback Current
Figure 8. Oscillator Charge Current versus
Temperature
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5
100
MC33260
104
120
Ipin1 = 100 mA
103
− 40°C
100
25°C
102
ON−TIME (μ s)
OSCILLATOR CHARGE CURRENT (μ A)
Pin Numbers are Relevant to the PDIP−8 Version
101
100
99
105°C
80
1 nF Connected to Pin 3
60
40
20
98
97
−40
0
−20
0
20
40
60
80
100
30
50
TJ, JUNCTION TEMPERATURE (°C)
REGULATION AND CS CURRENT SOURCE (μ A)
− 40°C
65
ON−TIME (μ s)
25°C
105°C
55
1 nF Connected to Pin 3
45
35
25
15
70
80
130
150
170
190
210
90
100
207
IOCP
206
205
204
203
202
IregH
201
200
199
198
197
−40
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Ipin1: FEEDBACK CURRENT (mA)
Figure 11. On−Time versus Feedback Current
Figure 12. Internal Current Sources versus
Temperature
1.07
0.150
1.06
(IovpH/Iref)
UNDERVOLTAGE RATIO (Iuvp /I ref )
(IovpH /I ref ), (I ovpL /I ref ), (I regL /I ref )
110
Figure 10. On−Time versus Feedback Current
75
60
90
Ipin1: FEEDBACK CURRENT (mA)
Figure 9. Oscillator Charge Current versus
Temperature
50
70
1.05
1.04
1.03
1.02
1.01
(IovpL/Iref)
1.00
0.99
0.98
0.97
0.96
−40
(IregL/Iref)
−20
0
20
40
60
80
100
0.148
0.146
0.144
0.142
0.140
0.138
0.136
0.134
0.132
0.130
−40
TJ, JUNCTION TEMPERATURE (°C)
−20
0
20
40
60
80
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. (IovpH/Iref), (IovpL/Iref), (IregL/Iref)
versus Temperature
Figure 14. Undervoltage Ratio versus
Temperature
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6
100
MC33260
Pin Numbers are Relevant to the PDIP−8 Version
4.5
ICC , CIRCUIT CONSUMPTION (mA)
CURRENT SENSE THRESHOLD (mV)
−54.8
−55
−55.2
−55.4
−55.6
−55.8
−56
−56.2
−56.4
−56.6
−40
−20
0
20
40
60
80
4.0
− 40°C
3.5
25°C
3.0
105°C
2.5
2.0
1.5
1.0
0.5
0
0
100
2
TJ, JUNCTION TEMPERATURE (°C)
6
8
10
12
14
16
VCC: SUPPLY VOLTAGE (V)
Figure 16. Circuit Consumption versus
Supply Voltage
Figure 15. Current Sense Threshold versus
Temperature
OSCILLATOR PIN INTERNAL CAPACITANCE (pF)
4
Vgate
20
−40°C
15
25°C
VCC = 12 V
Cgate = 1 nF
1
25°C
10
Icross−cond (50 mA/div)
105°C
5
2
0
0.2
0
0.4
0.6
0.8
1.0
1.2
1.4
Ch1
10.0 V
Ch2 10.0 mVW
M 1.00 ms
Ch1
600 mV
Vcontrol: PIN 2 VOLTAGE (V)
Figure 17. Oscillator Pin Internal Capacitance
Figure 18. Gate Drive Cross Conduction
Vgate
Vgate
−40 °C
VCC = 12 V
Cgate = 1 nF
1
105°C
VCC = 12 V
Cgate = 1 nF
1
Icross−cond (50 mA/div)
Icross−cond (50 mA/div)
2
2
Ch1
10.0 V
Ch2 10.0 mVW
M 1.00 ms
Ch1
600 mV
Ch1
Figure 19. Gate Drive Cross Conduction
10.0 V
Ch2 10.0 mVW
M 1.00 ms
Ch1
Figure 20. Gate Drive Cross Conduction
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7
600 mV
MC33260
PIN FUNCTION DESCRIPTION
Pin #
PDIP−8
Pin #
SO−8
Function
Description
1
7
Feedback Input
This pin is designed to receive a current that is proportional to the preconverter output
voltage. This information is used for both the regulation and the overvoltage and
undervoltage protections. The current drawn by this pin is internally squared to be used
as oscillator capacitor charge current.
2
8
Vcontrol
This pin makes available the regulation block output. The capacitor connected between
this pin and ground, adjusts the control bandwidth. It is typically set below 20 Hz to
obtain a nondistorted input current.
3
1
Oscillator Capacitor
(CT)
The circuit uses an on−time control mode. This on−time is controlled by comparing the
CT voltage to the Vcontrol voltage. CT is charged by the squared feedback current.
4
2
Zero Current
Detection Input
This pin is designed to receive a negative voltage signal proportional to the current
flowing through the inductor. This information is generally built using a sense resistor.
The Zero Current Detection prevents any restart as long as the Pin 4 voltage is below
(−60 mV). This pin is also used to perform the peak current limitation. The overcurrent
threshold is programmed by the resistor connected between the pin and the external
current sense resistor.
5
3
Synchronization
Input
This pin is designed to receive a synchronization signal. For instance, it enables to
synchronize the PFC preconverter to the associated SMPS. If not used, this pin must
be grounded.
6
4
Ground
7
5
Gate Drive
8
6
VCC
This pin must be connected to the preregulator ground.
The gate drive current capability is suited to drive an IGBT or a power MOSFET.
This pin is the positive supply of the IC. The circuit turns on when VCC becomes higher
than 11 V, the operating range after startup being 8.5 V up to 16 V.
Filtering
Capacitor
D1...D4
L1
D1
+ C1
2
Vcontrol
3
4
ROCP
CT
8
MC33260
1
Load
(SMPS, Lamp
Ballast,...)
VCC
M1
7
Ro
6
5
Sync
Rcs
DIP−8 CONFIGURATION SHOWN
Figure 21. Application Schematic
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MC33260
FUNCTIONAL DESCRIPTION
Pin Numbers are Relevant to the PDIP−8 Version
INTRODUCTION
OPERATION DESCRIPTION
The need of meeting the requirements of legislation on
line current harmonic content, results in an increasing
demand for cost effective solutions to comply with the
Power Factor regulations. This data sheet describes a
monolithic controller specially designed for this purpose.
Most off−line appliances use a bridge rectifier associated
to a huge bulk capacitor to derive raw dc voltage from the
utility ac line.
The MC33260 is optimized to just as well drive a free
running as a synchronized discontinuous voltage mode.
It also features valuable protections (overvoltage and
undervoltage protection, overcurrent limitation, ...) that
make the PFC preregulator very safe and reliable while
requiring very few external components. In particular, it is
able to safely face any uncontrolled direct charges of the
output capacitor from the mains which occur when the
output voltage is lower than the input voltage (startup,
overload, ...).
In addition to the low count of elements, the circuit can
control an innovative mode named “Follower Boost” that
permits to significantly reduce the size of the preconverter
inductor and power MOSFET. With this technique, the
output regulation level is not forced to a constant value, but
can vary according to the a.c. line amplitude and to the
power. The gap between the output voltage and the ac line
is then lowered, what allows the preconverter inductor and
power MOSFET size reduction. Finally, this method brings
a significant cost reduction.
A description of the functional blocks is given below.
Rectifiers
AC
Line
Converter
+
Bulk
Storage
Capacitor
Load
Figure 22. Typical Circuit Without PFC
This technique results in a high harmonic content and in
poor power factor ratios. In effect, the simple rectification
technique draws power from the mains when the
instantaneous ac voltage exceeds the capacitor voltage. This
occurs near the line voltage peak and results in a high charge
current spike. Consequently, a poor power factor (in the
range of 0.5 − 0.7) is generated, resulting in an apparent input
power that is much higher than the real power.
REGULATION SECTION
Connecting a resistor between the output voltage to be
regulated and the Pin 1, a feedback current is obtained.
Typically, this current is built by connecting a resistor
between the output voltage and the Pin 1. Its value is then
given by the following equation:
Vpk
Rectified DC
0
I
Line Sag
0
AC Line Current
Figure 23. Line Waveforms Without PFC
Active solutions are the most popular way to meet the
legislation requirements. They consist of inserting a PFC
pre−regulator between the rectifier bridge and the bulk
capacitor. This interface is, in fact, a step−up SMPS that
outputs a constant voltage while drawing a sinusoidal
current from the line.
Regulation Block Output
1.5 V
Load
+
pin1
Ro
Converter
Bulk Storage
Capacitor
MC33260
High Frequency
Bypass Capacitor
AC
Line
PFC Preconverter
Vo * V
where:
Ro is the feedback resistor,
Vo is the output voltage,
Vpin1 is the Pin 1 clamp value.
The feedback current is compared to the reference current
so that the regulation block outputs a signal following the
characteristic depicted in Figure 25. According to the power
and the input voltage, the output voltage regulation level
varies between two values (Vo)regL and (Vo)regH
corresponding to the IregL and IregH levels.
AC Line Voltage
Rectifiers
pin1
+
Io
IregL
(97%Iref)
IregH
(Iref)
Figure 25. Regulation Characteristic
Figure 24. PFC Preconverter
The feedback resistor must be chosen so that the feedback
current should equal the internal current source IregH when
the output voltage exceeds the chosen upper regulation
voltage [(Vo)regH].
The MC33260 was developed to control an active solution
with the goal of increasing its robustness while lowering its
global cost.
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9
MC33260
Pin Numbers are Relevant to the PDIP−8 Version
Consequently:
Ro +
ǒ V oǓ
where:
Vo is the output voltage,
Ro is the feedback resistor,
Vpin1 is the Pin 1 clamp voltage.
In practice, Vpin1 that is in the range of 2.5 V, is very small
compared to Vo. The equation can then be simplified by
neglecting Vpin1:
*V
regH
pin1
I
regH
In practice, Vpin1 is small compared to (Vo)regH and this
equation can be simplified as follows (IregH being also
replaced by its typical value 200 mA):
ǒV oǓ
Ro [ 5
regH
(kW)
I
The regulation block output is connected to the Pin 2
through a 300 kW resistor. The Pin 2 voltage (Vcontrol) is
compared to the oscillator sawtooth for PWM control.
An external capacitor must be connected between Pin 2
and ground, for external loop compensation. The bandwidth
is typically set below 20 Hz so that the regulation block
output should be relatively constant over a given ac line
cycle. This integration that results in a constant on−time over
the ac line period, prevents the mains frequency output
ripple from distorting the ac line current.
C
0
C
1
0
t on +
15 pF
The oscillator charge current is dependent on the feedback
current (Io). In effect
+2
I2
o
I
ǒtonǓmax +
ref
where:
Icharge is the oscillator charge current,
Io is the feedback current (drawn by Pin 1),
Iref is the internal reference current (200 mA).
So, the oscillator charge current is linked to the output
voltage level as follows:
+
ref
+C )C
T
int
ǒVo * Vpin1Ǔ
R2
o
I
V
pin3
I
control
ch
R2
o
I
ref
C
V
pin3
2 V2
o
control
One can notice that the on−time depends on Vo
(preconverter output voltage) and that the on−time is
maximum when Vcontrol is maximum (1.5 V typically).
At a given Vo, the maximum on−time is then expressed by
the following equation:
Figure 26. Oscillator
charge
I
where:
ton is the on−time,
Cpin3 is the total oscillator capacitor (sum of the
internal and external capacitor),
Icharge is the oscillator charge current (Pin 3 current),
Vcontrol is the Pin 2 voltage (regulation block output).
Consequently, replacing Icharge by the expression given in
the Oscillator Section:
Output_Ctrl
3
I
pin3
t on +
CT
2
R2
o
The MC33260 operates in voltage mode: the regulation
block output (Vcontrol − Pin 2 voltage) is compared to the
oscillator sawtooth so that the gate drive signal (Pin 7) is
high until the oscillator ramp exceeds Vcontrol.
The on−time is then given by the following equation:
Icharge = 2 Io Io / Iref
charge
V2
o
PWM LATCH SECTION
The oscillator consists of three phases:
• Charge Phase: The oscillator capacitor voltage grows
up linearly from its bottom value (ground) until it
exceeds Vcontrol (regulation block output voltage). At
that moment, the PWM latch output gets low and the
oscillator discharge sequence is set.
• Discharge Phase: The oscillator capacitor is abruptly
discharged down to its valley value (0 V).
• Waiting Phase: At the end of the discharge sequence,
the oscillator voltage is maintained in a low state until
the PWM latch is set again.
I
2
It must be noticed that the oscillator terminal (Pin 3) has
an internal capacitance (Cint) that varies versus the Pin 3
voltage. Over the oscillator swing, its average value
typically equals 15 pF (min 10 pF, max 20 pF).
The total oscillator capacitor is then the sum of the internal
and external capacitors.
OSCILLATOR SECTION
1
charge
[
C
pin3
R2
o
I
ref
2
ǒVcontrolǓ
max
V2
o
This equation can be simplified replacing
NJ[(Vcontrol)2max * Iref]Nj by Kosc
Refer to Electrical Characteristics, Oscillator Section.
Then:
2
C
ǒtonǓ max + pin3
K osc
ref
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10
R2
o
V2
o
MC33260
Pin Numbers are Relevant to the PDIP−8 Version
Zero Current Detection
This equation shows that the maximum on−time is inversely
proportional to the squared output voltage. This property is
used for follower boost operation (refer to Follower Boost
section).
The Zero Current Detection function guarantees that the
MOSFET cannot turn on as long as the inductor current
hasn’t reached zero (discontinuous mode).
The Pin 4 voltage is simply compared to the (−60 mV)
threshold so that as long as Vcs is lower than this threshold,
the circuit gate drive signal is kept in low state.
Consequently, no power MOSFET turn on is possible until
the inductor current is measured as smaller than (60 mV/Rcs)
that is, the inductor current nearly equals zero.
CURRENT SENSE BLOCK
The inductor current is converted into a voltage by
inserting a ground referenced resistor (Rcs) in series with the
input diodes bridge (and the input filtering capacitor).
Therefore a negative voltage proportional to the inductor
current is built:
V cs + −ǒR cs
I
Ǔ
Iocp (205 mA)
L
D1...D4
where:
IL is the inductor current,
Rcs is the current sense resistor,
Vcs is the measured Rcs voltage.
1
0
+
−
ROCP
Inductor Current Power Switch Drive
Rcs
VOCP
S
Output_Ctrl
−60 mV
4
PWM
Latch
Output_Ctrl
R
Q
R
LEB
To Output Buffer
(Output_Ctrl Low <=> Gate Drive in Low State)
Figure 28. Current Sense Block
Time
Overcurrent Protection
Rcs Voltage
During the power switch conduction (i.e. when the Gate
Drive Pin voltage is high), a current source is applied to the
Pin 4. A voltage drop VOCP is then generated across the
resistor ROCP that is connected between the sense resistor
and the Current Sense Pin (refer to Figure 28). So, instead of
Vcs, the sum (Vcs + VOCP) is compared to (−60 mV) and the
maximum permissible current is the solution of the
following equation:
−ǒR cs
Pin 4 Voltage
VOCP
Ipk maxǓ ) V
OCP
+ −60 mV
where:
Ipkmax is maximum allowed current,
Rcs is the sensing resistor.
The overcurrent threshold is then:
−60 mV
Zero Current Detection
Ipk max +
VOCP = ROCP IOCP
An overcurrent is detected if Vpin4 crosses the threshold (−60 mV)
during the Power Switch on state
ǒROCP
I
Ǔ ) 60
OCP
R cs
10 −3
where:
ROCP is the resistor connected between the pin and the
sensing resistor (Rcs),
IOCP is the current supplied by the Current Sense Pin
when the gate drive signal is high (power switch
conduction phase). IOCP equals 205 mA typically.
Practically, the VOCP offset is high compared to 60 mV
and the precedent equation can be simplified. The maximum
current is then given by the following equation:
Figure 27. Current Sensing
The negative signal Vcs is applied to the current sense
through a resistor ROCP. The pin is internally protected by a
negative clamp (−0.7 V) that prevents substrate injection.
As long as the Pin 4 voltage is lower than (−60 mV), the
Current Sense comparator resets the PWM latch to force the
gate drive signal low state. In that condition, the power
MOSFET cannot be on.
During the on−time, the Pin 4 information is used for the
overcurrent limitation while it serves the zero current
detection during the off time.
Ipk max [
R
(kW)
OCP
R cs(W)
0.205 (A)
Consequently, the ROCP resistor can program the OCP level
whatever the Rcs value is. This gives a high freedom in the
choice of Rcs. In particular, the inrush resistor can be utilized.
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11
MC33260
Pin Numbers are Relevant to the PDIP−8 Version
VCC
Th−Stdwn
Synchronization
Arrangement
5
S
OVP, UVP
Current Sense
Comparator
Output
Buffer
Q
7
PWM
Latch
−
ZCD & OCP
R
+
Q
&
Output_Ctrl
−60 mV
+
−
PWM Latch
Comparator
Vcontrol (Vpin2 − Regulation Output)
Oscillator Sawtooth
Figure 29. PWM Latch
A LEB (Leading Edge Blanking) has been implemented.
This circuitry disconnects the Current Sense comparator
from Pin 4 and disables it during the 400 first ns of the power
switch conduction. This prevents the block from reacting on
the current spikes that generally occur at power switch turn
on. Consequently, proper operation does not require any
filtering capacitor on Pin 4.
Practically, Vpin1 that is in the range of 2.5 V, can be
neglected. The equation can then be simplified:
PROTECTIONS
where IovpL is the internal low OVP current threshold.
Consequently, Vpin1 being neglected:
V
V
V
Refer to Current Sense Block.
The feedback current (Io) is compared to a threshold
current (IovpH). If it exceeds this value, the gate drive signal
is maintained low until this current gets lower than a second
level (IovpL).
Io
IregL IregH IovpL IovpH
ǒ
+V
pin1
ǒ
) Ro
+ R o(MW)
I
I
ovpL
Ǔ
ovpL
(mA) (V)
pin1
) ǒR o(MW)
Iuvp(mA)Ǔ (V)
Practically (Vpin1 being neglected),
So, the OVP upper threshold is:
) Ro
ovpL
V uvp [ V
Figure 30. Internal Current Thresholds
pin1
ovpL
This function detects when the feedback current is lower
than 14% of Iref. In this case, the PWM latch is reset and the
power switch is kept off.
This protection is useful to:
• Protect the preregulator from working in too low
mains conditions.
• To detect the feedback current absence (in case of a
nonproper connection for instance).
The UVP threshold is:
Vcontrol
+V
(mA) (V)
ovpH
UVP (Undervoltage Protection)
Gate
Drive
Enable
ovpH
I
The OVP hysteresis prevents erratic behavior.
IovpL is guaranteed to be higher than IregH (refer to
parameters specification). This ensures that the OVP
function doesn’t interfere with the regulation one.
OVP (Overvoltage Protection)
V
+ R o(MW)
On the other hand, the OVP low threshold is:
OCP (Overcurrent Protection)
Iuvp
ovpH
I
Ǔ
V uvp + R o(MW)
I uvp(mA) (V)
ovpH
Maximum On−Time Limitation
where:
Ro is the feedback resistor that is connected between
Pin 1 and the output voltage,
IovpH is the internal upper OVP current threshold,
Vpin1 is the Pin 1 clamp voltage.
As explained in PWM Latch, the maximum on−time is
accurately controlled.
Pin Protection
All the pins are ESD protected.
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MC33260
Pin Numbers are Relevant to the PDIP−8 Version
In particular, a 11 V Zener diode is internally connected
between the terminal and ground on the following pins:
Feedback, Vcontrol, Oscillator, Current Sense, and
Synchronization.
Sync
+
5
S1
1V
−
Q1
Rsync
UVLO
Q1 High <=>
Synchronization Mode
R2
2 ms
&
PWM
Latch
Set
S2
Q2
1V
R2
Output_Ctrl
Figure 31. Synchronization Arrangement
SYNCHRONIZATION BLOCK
OUTPUT SECTION
The MC33260 features two modes of operation:
• Free Running Discontinuous Mode: The power switch
is turned on as soon as there is no current left in the
inductor (Zero Current Detection). This mode is
simply obtained by grounding the synchronization
terminal (Pin 5).
• Synchronization Mode: This mode is set as soon as a
signal crossing the 1.0 V threshold, is applied to the
Pin 5. In this case, operation in free running can only
be recovered after a new circuit startup. In this mode,
the power switch cannot turn on before the two
following conditions are fulfilled.
− Still, the zero current must have been detected.
− The precedent turn on must have been followed by
(at least) one synchronization raising edge
crossing the 1.0 V threshold.
In other words, the synchronization acts to prolong the
power switch off time.
Consequently, a proper synchronized operation requires
that the current cycle (on−time + inductor demagnetization)
is shorter than the synchronization period. Practically, the
inductor must be chosen accordingly. Otherwise, the system
will keep working in free running discontinuous mode.
Figure 36 illustrates this behavior.
It must be noticed that whatever the mode is, a 2.0 ms
minimum off−time is forced. This delay limits the switching
frequency in light load conditions.
The output stage contains a totem pole optimized to
minimize the cross conduction current during high speed
operation. The gate drive is kept in a sinking mode whenever
the Undervoltage Lockout is active. The rise and fall times
have been controlled to typically equal 50 ns while loaded
by 1.0 nF.
REFERENCE SECTION
An internal reference current source (Iref) is trimmed to be
±4% accurate over the temperature range (the typical value
is 200 mA). Iref is the reference used for the regulation
(IregH = Iref).
UNDERVOLTAGE LOCKOUT SECTION
An Undervoltage Lockout comparator has been
implemented to guarantee that the integrated circuit is
operating only if its supply voltage (VCC) is high enough to
enable a proper working. The UVLO comparator monitors
the Pin 8 voltage and when it exceeds 11 V, the device gets
active. To prevent erratic operation as the threshold is
crossed, 2.5 V of hysteresis is provided.
The circuit off state consumption is very low: in the range
of 100 mA @ VCC = 5.0 V. This consumption varies versus
VCC as the circuit presents a resistive load in this mode.
THERMAL SHUTDOWN
An internal thermal circuitry is provided to disable the
circuit gate drive and then to prevent it from oscillating, if
the junction temperature exceeds 150°C typically.
The output stage is again enabled when the temperature
drops below 120°C typically (30°C hysteresis).
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MC33260
Pin Numbers are Relevant to the PDIP−8 Version
FOLLOWER BOOST
of the follower boost: it allows the use of smaller, lighter and
cheaper inductors compared to traditional systems.
Finally, this technique utilization brings a drastic system
cost reduction by lowering the size and then the cost of both
the inductor and the power switch.
Traditional PFC preconverters provide the load with a fixed
and regulated voltage that generally equals 230 V or 400 V
according to the mains type (U.S., European, or universal).
In the “Follower Boost” operation, the preconverter
output regulation level is not fixed but varies linearly versus
the ac line amplitude at a given input power.
IL
traditional preconverter
follower boost preconverter
Ipk
Traditional Output
Vo (Follower Boost)
time
Vin
Vin
Vac
Vin
Vout
Vin
IL
IL
Load
the power switch is on
the power switch is off
Figure 33. Off−Time Duration Increase
Figure 32. Follower Boost Characteristics
This technique aims at reducing the gap between the
output and the input voltages to minimize the boost
efficiency degradation.
Follower Boost Implementation
In the MC33260, the on−time is differently controlled
according to the feedback current level. Two areas can be
defined:
• When the feedback current is higher than IregL (refer
to regulation section), the regulation block output
(Vcontrol) is modulated to force the output voltage to a
desired value.
• On the other hand, when the feedback current is lower
than IregL, the regulation block output and therefore,
the on−time are maximum. As explained in PWM
Latch Section, the on−time is then inversely
proportional to the output voltage square. The
Follower Boost is active in these conditions in which
the on−time is simply limited by the output voltage
level. Note: In this equation, the Feedback Pin voltage
(Vpin1) is neglected compared to the output voltage
(refer to the PWM Latch Section).
Follower Boost Benefits
The boost presents two phases:
• The on−time during which the power switch is on. The
inductor current grows up linearly according to a slope
(Vin/Lp), where Vin is the instantaneous input voltage
and Lp the inductor value.
• The off−time during which the power switch is off.
The inductor current decreases linearly according the
slope (Vo − Vin)/Lp, where Vo is the output voltage.
This sequence that terminates when the current equals
zero, has a duration that is inversely proportional to the
gap between the output and input voltages.
Consequently, the off−time duration becomes longer
in follower boost.
Consequently, for a given peak inductor current, the
longer the off time, the smaller power switch duty cycle and
then its conduction dissipation. This is the first benefit of this
technique: the MOSFET on−time losses are reduced.
The increase of the off time duration also results in a
switching frequency diminution (for a given inductor
value). Given that in practise, the boost inductor is selected
big enough to limit the switching frequency down to an
acceptable level, one can immediately see the second benefit
t on + ǒt onǓ max +
pin3
R2
o
K osc
V2
o
C
where:
Cpin3 is the total oscillator capacitor (sum of the
internal and external capacitors − Cint + CT),
Kosc is the ratio (oscillator swing over oscillator gain),
Vo is the output voltage,
Ro is the feedback resistor.
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MC33260
Pin Numbers are Relevant to the PDIP−8 Version
On the other hand, the boost topology has its own rule that
dictates the on−time necessary to deliver the required power:
t on +
4
Lp
P
Regulation Block is Active
Vo
(Pin)min
in
V2
pk
Pin
where:
Vpk is the peak ac line voltage,
Lp is the inductor value,
Pin is the input power.
Combining the two equations, one can obtain the
Follower Boost equation:
Vo +
Ro
2
Vo = Vpk
Ǹ
C
K osc
pin3
Lp
P
V
in
(Pin)max
non usable area
pk
Vac
Consequently, a linear dependency links the output
voltage to the ac line amplitude at a given input power.
VacLL
Vac
VacHL
Figure 35. Follower Boost Output Voltage
Input Power
Output Voltage
The Regulation Block is Active
Mode Selection
(Vac)max
Vac
The operation mode is simply selected by adjusting the
oscillator capacitor value. As shown in Figure 35, the output
voltage first has an increasing linear characteristic versus the
ac line magnitude and then is clamped down to the
regulation value. In the traditional mode, the linear area
must be rejected. This is achieved by dimensioning the
oscillator capacitor so that the boost can deliver the
maximum power while the output voltage equals its
regulation level and this, whatever the given input voltage.
Practically, that means that whatever the power and input
voltage conditions are, the follower boost would generate
output voltages values higher than the regulation level, if
there was no regulation block.
In other words, if (Vo)regL is the low output regulation
level:
Output Voltage
Input Power
Pin
(Vac)min
Vo
ton = k/Vo2
ton
on−time
Figure 34. Follower Boost Characteristics
The behavior of the output voltage is depicted in
Figures 34 and 35. In particular, Figure 35 illustrates how
the output voltage converges to a stable equilibrium level.
First, at a given ac line voltage, the on−time is dictated by the
power demand. Then, the follower boost characteristic
makes correspond one output voltage level to this on−time.
Combining these two laws, it appears that the power level
forces the output voltage.
One can notice that the system is fully stable:
• If an output voltage increase makes it move away from
its equilibrium value, the on−time will immediately
diminish according to the follower boost law. This will
result in a delivered power decrease. Consequently,
the supplied power being too low, the output voltage
will decrease back,
• In the same way, if the output voltage decreases, more
power will be transferred and then the output voltage
will increase back.
ǒV oǓ
regL
v
Ǹ
Ro
2
C )C
T
int
K osc
V
ǒPinǓ max
Lp
pk
Consequently,
4
K osc
C w −C )
T
int
ǒPinǓ max
Lp
R2
o
ǒV oǓ
2
regL
V2
pk
Using IregL (regulation block current reference), this
equation can be simplified as follows:
4
C w −C )
T
int
K osc
Lp
ǒPinǓ max
I2
regL
V2
pk
In the Follower Boost case, the oscillator capacitor must
be chosen so that the wished characteristics are obtained.
Consequently, the simple choice of the oscillator
capacitor enables the mode selection.
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MC33260
Synchronization
Signal
Zero Current
Detection
2 ms
Delay
2 ms
2 ms
2 ms
2 ms
Vcontrol
Oscillator
Circuit
Output
205 mA
Ics
Inductor
Current
1
2
case no. 1: the turn on is delayed by the Zero Current Detection
cases no. 2 and no. 3: the turn on is delayed by the synchronization signal
case no. 4: the turn on is delayed by the minimum off−time (2 ms)
Figure 36. Typical Waveforms
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3
4
MC33260
MAIN DESIGN EQUATIONS (Note 3)
rms Input Current (Iac)
I ac +
η (preconverter efficiency) is generally in the
range of 90 − 95%.
Po
h Vac
Maximum Inductor Peak Current ((Ipk)max):
2 Ǹ2 (P o) max
(I ) max +
pk
h V
acLL
(Ipk)max is the maximum inductor current.
Output Voltage Peak to Peak 100Hz (120Hz) Ripple ((DVo)pk−pk):
fac is the ac line frequency (50 or 60Hz).
Po
(DVo ) pk–pk +
2p
Inductor Value (Lp):
2
Lp +
ǒ
t
Vo
Vo
Ǹ2
f ac
Co
Ǔ
*V
acLL
V
acLL
(I
Vo
t is the maximum switching period.
(t = 40 ms) for universal mains operation and
(t = 20 ms) for narrow range are generally
used.
2
V
acLL
) max
pk
Maximum Power MOSFET Conduction Losses ((pon)max):
(Pon ) max [ 1
3
(Rds)on
(I
pk
ƪ
1*
) max 2
1.2
V
acLL
Vo
ƫ
Maximum Average Diode Current (Id):
The Average Diode Current depends on the
power and on the output voltage.
(P ) max
(I d) max + o
(Vo) min
Current Sense Resistor Losses (pRcs):
pR cs + 1
6
(Rds)on
(I
pk
This formula indicates the required dissipation
capability for Rcs (current sense resistor).
) 2 max
Over Current Protection Resistor (ROCP):
R cs (I pk) max
R
[
OCP
0.205
Oscillator External Capacitor Value (CT):
−Traditional Operation
2 K osc
C w*C )
T
int
− Follower Boost:
Vo +
Ro
2
Feedback Resistor (Ro):
Ro +
Ǹ
Lp
(kW)
(P ) max
in
I2
regL
V 2ac
C T ) C int
K osc
Lp
(Rds)on is the MOSFET drain source on−time
resistor.
In Follower Boost, the ratio (VacLL/Vo) is
higher. The on−time MOSFET losses are then
reduced.
P
in
The overcurrent threshold is adjusted by ROCP
at a given Rcs.
Rcs can be a preconverter inrush resistor.
The Follower Boost characteristic is adjusted
by the CT choice.
The Traditional Mode is also selected by CT.
Cint is the oscillator pin internal capacitor.
Vpk
(Vo ) reg * VFB
V
[ o
200
I
regH
(MW)
3. The preconverter design requires the following characteristics specification:
− (Vo)reg: desired output voltage regulation level
− (DVo)pk−pk: admissible output peak to peak ripple voltage
− Po: desired output power
− Vac: ac rms operating line voltage
− VacLL: minimum ac rms operating line voltage
− VFB: Feedback Pin voltage
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17
The output voltage regulation level is adjusted
by Ro.
MC33260
L1
320 mH
D5
MUR460E
1N4007
D1
D2
90 to
270 Vac
EMI
Filter
D3
R1
1 MW
0.25 W
Q1
MTP4N50E
+
C1
330 nF
500 Vdc
D4
80 W Load
(SMPS, Lamp
Ballast,...)
C2
47 mF
450 V
R2
1 MW
0.25 W
R4
R3
15 kW/0.25 W
1 W/2 W
R5
22 W/0.25 W
Feedback
Input
Io
Iref
Iref
Vprot
Vreg
Vcontrol
C3
680 nF
Io
Io
Feedback
Block
1.5 V
Vreg
Regulation
Block
Io
(− − −)
Iuvp IovpL IovpH
Io
300 k
97%.Iref
UVP, OVP
Iref
Vref
Iref
MC33260
REGULATOR
−
Enable
+
11 V/8.5 V
VCC
Vprot
ThStdwn
Output
Buffer
PWM Comp
Oscillator
I osc–ch +
Gnd
+
2x|0x|0
I ref
R
−
Iocp (205 mA)
CT
C4
330 pF
0
1
1
0
−60 mV
15 pF
Q
PWM
Latch
Current
Sense
Block
S
Output
Q
+
Synchronization
Block
−
LEB
Output
Drive
Synchro
L1: Coilcraft N2881 − A (primary: 62 turns of # 22 AWG − Secondary: 5 turns of # 22 AWG Core: Coilcraft PT2510, EE 25
L1: Gap: 0.072″ total for a primary inductance (Lp) of 320 mH)
Figure 37. 80 W Wide Mains Power Factor Corrector
POWER FACTOR CONTROLLER TEST DATA*
AC Line Input
Current Harmonic Distortion (% Ifund)
Vrms
(V)
Pin
(W)
PF
(−)
Ifund
(mA)
THD
H2
H3
H5
H7
DC Output
H9
Vo
(V)
DVo
(V)
Io
(mA)
Po
(W)
η
(%)
90
88.2
0.991
990
8.1
0.07
5.9
4.3
1.5
1.7
181
31.2
440
79.6
90.2
110
86.3
0.996
782
7.0
0.05
2.7
5.7
1.1
0.8
222
26.4
360
79.9
92.6
135
85.2
0.995
642
8.2
0.03
1.5
6.8
1.1
1.5
265
20.8
300
79.5
93.3
180
87.0
0.994
480
9.5
0.16
4.0
6.5
3.1
4.0
360
16.0
225
81.0
93.1
220
84.7
0.982
385
15
0.5
8.4
7.8
5.3
1.9
379
14.0
210
79.6
94.4
240
85.3
0.975
359
16.5
0.7
9.0
7.8
7.4
3.8
384
14.0
210
80.6
94.5
260
84.0
0.967
330
18.8
0.7
11.0
7.0
9.0
4.0
392
13.2
205
80.4
95.7
*Measurements performed using Voltech PM1200 ac power analysis.
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MC33260
Rstup
D1...D4
r
+
15 V
8
MC33260
1
2
3
4
Cpin8
VCC
+
7
6
5
PDIP−8 CONFIGURATION SHOWN
Figure 38. Circuit Supply Voltage
MC33260 VCC SUPPLY VOLTAGE
When the PFC preconverter is loaded by an SMPS, the
MC33260 should preferably be supplied by the SMPS itself.
In this configuration, the SMPS starts first and the PFC gets
active when the MC33260 VCC supplied by the power
supply, exceeds the device startup level. With this
configuration, the PFC preconverter doesn’t require any
auxiliary winding and finally a simple coil can be used.
In some applications, the arrangement shown in Figure 38
must be implemented to supply the circuit. A startup resistor
is connected between the rectified voltage (or one−half
wave) to charge the MC33260 VCC up to its startup
threshold (11 V typically). The MC33260 turns on and the
VCC capacitor (Cpin8) starts to be charged by the PFC
transformer auxiliary winding. A resistor, r (in the range of
22 W) and a 15 V Zener should be added to protect the circuit
from excessive voltages.
PCB LAYOUT
The connections of the oscillator and Vcontrol capacitors
should be as short as possible.
Preconverter Output
2
3
4
8
MC33260
1
+
+
+
+
VCC
+
7
6
+
+
5
SMPS Driver
DIP−8 CONFIGURATION SHOWN
Figure 39. Preconverter Loaded by a Flyback SMPS: MC33260 VCC Supply
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19
MC33260
ORDERING INFORMATION
Package
Shipping †
PDIP−8
50 Units / Rail
PDIP−8
(Pb−Free)
50 Units / Rail
SOIC−8
98 Units / Rail
MC33260DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC33260DR2
SOIC−8
2500 Units / Tape & Reel
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
Device
MC33260P
MC33260PG
MC33260D
MC33260DR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
PACKAGE DIMENSIONS
PDIP−8
P SUFFIX
PLASTIC PACKAGE
CASE 626−05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
−B−
1
4
F
−A−
NOTE 2
L
C
J
−T−
N
SEATING
PLANE
D
H
M
K
G
0.13 (0.005)
M
T A
M
B
M
http://onsemi.com
20
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
−−−
10_
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
−−−
10_
0.030
0.040
MC33260
PACKAGE DIMENSIONS
SOIC−8
CASE 751−07
ISSUE AG
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
21
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8 _
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
MC33260
The product described herein (MC33260), may be covered by one or more of the following U.S. patents: 5,073,850; 6,177,782.
There may be other patents pending.
GreenLine is a trademark of Motorola, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
Literature Distribution Center for ON Semiconductor
USA/Canada
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Phone: 81−3−5773−3850
Email: [email protected]
http://onsemi.com
22
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
MC33260/D