HA-5195 DUCT NT E PRO T E CEME at L A O L P E OBS R C ent er NDED OMME ical Support .com/tsc C E R NO hn Data November 19, 2004 ersil ecSheet ww.int t our T contac TERSIL or w IN 1- 888 ® FN2914.6 150MHz, Fast Settling Operational Amplifier Features The HA-5195 is a operational amplifier featuring a combination of speed, precision, and bandwidth. Employing monolithic bipolar construction coupled with Dielectric Isolation, this device is capable of delivering 200V/µs slew rate with a settling time of 70ns (0.1%, 5V output step). This truly differential amplifier is designed to operate at gains ≥ 5 without the need for external compensation. Other outstanding features are 150MHz gain bandwidth product and 6.5MHz full power bandwidth. In addition to these dynamic characteristics, this amplifier also has excellent input characteristics such as 3mV offset voltage and 6.0nV/√Hz input voltage noise at 1kHz. • Very High Slew Rate . . . . . . . . . . . . . . . . . . . . . . 200V/µs • Fast Settling Time (0.1%). . . . . . . . . . . . . . . . . . . . . 70ns With 200V/µs slew rate and 70ns settling time, the HA-5195 is an ideal output amplifier for accurate, high speed D/A converters or the main components in high speed sample/hold circuits. The 5195 is also ideally suited for a variety of pulse and wideband video amplifiers. Please refer to Application Notes AN525 and AN526 for some of these application designs. • Wide Gain-Bandwidth (AV ≥ 5). . . . . . . . . . . . . . . 150MHz • Full Power Bandwidth. . . . . . . . . . . . . . . . . . . . . . 6.5MHz • Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 3mV • Input Noise Voltage . . . . . . . . . . . . . . . . . . . . . . 6nV/√Hz • Bipolar D.I. Construction Applications • Fast, Precise D/A Converters • High Speed Sample-Hold Circuits • Pulse and Video Amplifiers • Wideband Amplifiers Pinout HA-5195 (CERDIP) TOP VIEW At temperatures above 75oC a heat sink is required for the HA-5195 (see Note 2 and Application Note AN556). Part Number Information PART NUMBER HA1-5195-5 TEMP. RANGE (oC) 0 to 75 PACKAGE 14 Ld CERDIP 1 PKG. DWG. # F14.3 NC 1 14 NC NC 2 13 NC NC 3 12 NC -IN 4 - 11 V+ +IN 5 + 10 OUT V- 6 9 NC NC 7 8 NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright Harris Corporation 1998. Copyright Intersil Americas Inc. 2002, 2004. All Rights Reserved HA-5195 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA (Peak) Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . . . 75 20 Maximum Junction Temperature (Hermetic Package, Note 1) . .175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Heat sinking may be required, especially at TA ≥ 75oC. 2. θJA is measured with the component mounted on an evaluation PC board in free air. VSUPPLY = ±15V, Unless Otherwise Specified Electrical Specifications PARAMETER TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage 25 - 3 6 mV Full - - 10 mV Average Offset Voltage Drift Full - 20 - µV/oC Bias Current 25 - 5 15 µA Full - - 20 µA 25 - 1 4 µA Full - - 6 µA 25 - 10 - kΩ Offset Current Input Resistance Input Capacitance 25 - 1 - pF Common Mode Range Full ±5 - - V Input Noise Current f = 1kHz, RG = 0Ω 25 - 5 - pA/√Hz Input Noise Voltage f = 1kHz, RG = 0Ω 25 - 6 - nV/√Hz 25 10 30 - kV/V TRANSFER CHARACTERISTICS Large Signal Voltage Gain (Note 3) Common Mode Rejection Ratio Full 5 - - kV/V ∆VCM = ±5V Full 74 95 - dB 25 5 - - V/V VOUT = 90mV, AV = 10 25 150 - - MHz Full ±5 ±8 - V Minimum Stable Gain Gain-Bandwidth-Product OUTPUT CHARACTERISTICS Output Voltage Swing (Note 3) 25 ±25 ±30 - mA 25 - 30 - Ω 25 5 6.5 - MHz Rise Time 25 - 13 18 ns Overshoot 25 - 8 - % Output Current (Note 3) Output Resistance Open Loop Full Power Bandwidth (Notes 3, 4) TRANSIENT RESPONSE (Note 5) Slew Rate Settling Time (Note 5) 25 160 200 - V/µs 5V Step to 0.1% 25 70 - - ns 5V Step to 0.01% 25 - 100 - ns 2.5V Step to 0.1% 25 - 50 - ns 2.5V Step to 0.01% 25 - 80 - ns Full - 19 28 mA POWER SUPPLY CHARACTERISTICS Supply Current 2 FN2914.6 November 19, 2004 HA-5195 VSUPPLY = ±15V, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS Full 70 90 - dB ∆VS = ±10V to ±20V Power Supply Rejection Ratio NOTES: 3. RL = 200Ω, CL < 10pF, VOUT = ±5V. Slew Rate 4. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = ----------------------------- . 2πV PEAK 5. Refer to Test Circuits section of the data sheet. Test Circuits and Waveforms IN + OUT 1.6kΩ 200Ω NOTES: 6. AV = 5. 400Ω 7. CL < 10pF. FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT +5V 90% VOUT VOUT 10% -5V +1V VIN VIN -1V Vertical Scale: VIN = 2.0V/Div., VOUT = 4.0/Div. Horizontal Scale: 100ns/Div. Vertical Scale: VIN = 50mV/Div., VOUT = 100mV/Div. Horizontal Scale: 100ns/Div LARGE SIGNAL RESPONSE SMALL SIGNAL RESPONSE V+ 0.001µF NOTES: IN 8. AV = -5. 400Ω 1µF + 0.001µF OUT PROBE MONITOR 1kΩ V- SETTLE POINT 1µF 2kΩ 9. Load Capacitance should be less than 10pF. 10. It is recommended that resistors be carbon composition and that feedback and summing network ratios be matched to 0.1%. 11. Settle Point (Summing Node) capacitance should be less than 10pF. For optimum settling time results, it is recommended that the test circuit be constructed directly onto the device pins. A Tektronix 568 Sampling Oscilloscope with S-3A sampling heads is recommended as a settle point monitor. 5kΩ FIGURE 2. SETTLING TIME TEST CIRCUIT 3 FN2914.6 November 19, 2004 HA-5195 Schematic Diagram V+ R1 R2 R3 R4 QP4 QP24 QP23 R28 QN56 QP6 QP3 R6 QP5 C1 QN22 R7 R8 R29 QP20 QN21 R9 QP19 QP32 QP35 QN39 QN42 QN1 QN49 QN2 C3 R24 QN50 R25 QN53 QP33 D34 +IN D51 -IN R26 QP36 D37 QP44 C2 R32 R27 OUT D52 QP7 D38 R33 QP8 QN40 D41 QP54 QN43 R10 QN18 R11 R12 QP55 QN9 QN10 QN45 QP16 QN46 QN17 R13 QP15 R14 QN14 QN11 QN12 QN47 QN13 QN48 R15 R16 R17 R18 R30 R31 V- Application Information Power Supply Decoupling Output Short Circuit Although not absolutely necessary, it is recommended that all power supply lines be decoupled with 0.01µF ceramic capacitors to ground. Decoupling capacitors should be located as near to the amplifier terminals as possible. HA-5195 does not have output short circuit protection. Short circuits to ground can be tolerated for approximately 10 seconds. Short circuits to either supply will result in immediate destruction of the device. Stability Considerations Heavy Capacitive Loads HA-5195 is stable at gains > 5. Gains < 5 are covered below. Feedback resistors should be of carbon composition located as near to the input terminals as possible. When driving heavy capacitive loads (>100pF) a small resistor (100Ω) should be connected in series with the output and inside the feedback loop. Wiring Considerations Video pulse circuits should be built on a ground plane. Minimum point to point connections directly to the amplifier terminals should be used. When ground planes cannot be used, good single point grounding techniques should be applied. 4 FN2914.6 November 19, 2004 HA-5195 Typical Applications IN 11pF (NOTE) C1 (Also see Application Notes AN525 and AN526) IN + OUT - OUT - 200Ω 200Ω RF RF 750Ω (NOTE) 1kΩ (NOTE) OUTPUT OUTPUT INPUT INPUT Vertical Scale: 2V/Div. Horizontal Scale: 100ns/Div. NOTE: + 1kΩ (NOTE) Vertical Scale: 2V/Div. Horizontal Scale: 100ns/Div Values were determined experimentally for optimum speed and settling time. RF and C1 should be optimized for each particular application to ensure best overall frequency response. FIGURE 3. SUGGESTED COMPENSATION FOR NONINVERTING UNITY GAIN AMPLIFIER 1kΩ OUTPUT 1kΩ IN - OUT + 200Ω INPUT Vertical Scale: 2V/Div. Horizontal Scale: 50ns/Div. FIGURE 4. SUGGESTED COMPENSATION FOR INVERTING UNITY GAIN AMPLIFIER V+ IN + 200Ω - + 120Ω 1.6kΩ 75Ω 50Ω 1µF 1µF HA-5195 - HA-5033 50Ω 200Ω 1µF 1µF 400Ω 5kΩ V1kΩ FIGURE 5. VIDEO PULSE AMPLIFIER/75Ω COAXIAL DRIVER 5 FIGURE 6. VIDEO PULSE AMPLIFIER COAXIAL LINE DRIVER FN2914.6 November 19, 2004 HA-5195 VS = ±15V, TA = 25oC, Unless Otherwise Specified 1.6 BIAS CURRENT 1.2 3 0.8 2 OFFSET VOLTAGE 0.4 1 0 -40 40 80 120 0 80 GAIN 60 40 20 135 0 180 225 -20 0 160 1K 10K 100M 1.2 NORMALIZED PARAMETERS REFERRED TO VALUES AT 25oC OUTPUT VOLTAGE SWING (VP-P) 10M FIGURE 8. OPEN LOOP FREQUENCY RESPONSE 18 16 14 12 10 8 6 10K 1M 100K 10M 1.1 SLEW RATE 1.0 BANDWIDTH 0.9 0.8 0.7 100M -80 -40 0 40 80 FIGURE 9. OUTPUT VOLTAGE SWING vs FREQUENCY 1000 INPUT NOISE VOLTAGE (nV/√Hz) 1000 1.1 BANDWIDTH 1.0 SLEW RATE 0.9 200 LOAD CAPACITANCE (pF) FIGURE 11. NORMALIZED AC PARAMETERS vs LOAD CAPACITANCE 6 160 FIGURE 10. NORMALIZED AC PARAMETERS vs TEMPERATURE 1.2 100 120 TEMPERATURE (oC) FREQUENCY (Hz) NORMALIZED VALUE REFERRED TO LOAD CAPACITANCE EQUAL TO 10pF 1M 100K FREQUENCY (Hz) FIGURE 7. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs TEMPERATURE 0.8 10 90 PHASE TEMPERATURE (oC) 4 1K 45 250 100 100 INPUT NOISE CURRENT 10 10 INPUT NOISE VOLTAGE 1 1 10 100 1K 10K INPUT NOISE CURRENT (pA/√Hz) 0 -80 OPEN LOOP VOLTAGE GAIN (dB) 4 OFFSET VOLTAGE (mV) INPUT BIAS CURRENT (µA) 100 2.0 5 PHASE (DEGREES) Typical Performance Curves 1 100K FREQUENCY (Hz) FIGURE 12. INPUT NOISE VOLTAGE AND NOISE CURRENT vs FREQUENCY FN2914.6 November 19, 2004 HA-5195 VS = ±15V, TA = 25oC, Unless Otherwise Specified (Continued) 12 OUTPUT VOLTAGE STEP (V) OUTPUT VOLTAGE SWING (V) Typical Performance Curves 10 8 6 4 5 0.5mV 5mV 0.5mV 0 -2.5 -5 2 0 200 400 800 600 1K 1.2K 0 10 20 30 LOAD RESISTANCE (Ω) POWER SUPPLY REJECTION RATIO (dB) 100 80 60 40 20 1K 10K 60 50 70 80 90 100 110 FIGURE 14. SETTLING TIME FOR VARIOUS OUTPUT STEP VOLTAGES 120 0 100 40 SETTLING TIME (ns) FIGURE 13. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE COMMON MODE REJECTION RATIO (dB) 5mV 2.5 100K 1M 120 100 POSITIVE SUPPLY 80 60 NEGATIVE SUPPLY 40 20 0 100 1K FREQUENCY (Hz) FIGURE 15. COMMON MODE REJECTION RATIO vs FREQUENCY 10K FREQUENCY (Hz) 100K 1M FIGURE 16. POWER SUPPLY REJECTION RATIO vs FREQUENCY 24 POWER SUPPLY CURRENT (mA) VSUPPLY = ±15V 20 VSUPPLY = ±10V 16 12 8 4 0 -80 -40 0 40 80 120 160 TEMPERATURE (oC) FIGURE 17. POWER SUPPLY CURRENT vs TEMPERATURE 7 FN2914.6 November 19, 2004 HA-5195 Die Characteristics DIE DIMENSIONS: SUBSTRATE POTENTIAL (Powered Up): 54 mils x 88 mils x 19 mils 1360µm x 2240µm x 483µm VTRANSISTOR COUNT: METALLIZATION: 49 Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ PROCESS: Bipolar Dielectric Isolation PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ Metallization Mask Layout HA-5195 -IN V+ OUTPUT +IN 8 V- FN2914.6 November 19, 2004 HA-5195 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.785 - 19.94 5 E 0.220 0.310 5.59 7.87 5 eA e ccc M C A-B S eA/2 c aaa M C A - B S D S D S NOTES - b2 b MAX 0.014 α A A MIN b A L MILLIMETERS MAX A Q SEATING PLANE MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. α 90o aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. N 14 14 5. This dimension allows for off-center lid, meniscus, and glass overrun. 8 Rev. 0 4/94 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN2914.6 November 19, 2004