Cypress CY7C1314BV18 18-mbit qdrâ® ii sram two-word burst architecture Datasheet

CY7C1312BV18
CY7C1314BV18
18-Mbit QDR® II SRAM Two-Word Burst
Architecture
18-Mbit QDR® II SRAM Two-Word Burst Architecture
Features
Functional Description
■
Separate independent read and write data ports
❐ Supports concurrent transactions
■
250 MHz clock for high bandwidth
■
Two-word burst on all accesses
■
Double data rate (DDR) interfaces on both read and write ports
(data transferred at 500 MHz) at 250 MHz
■
Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■
Single multiplexed address input bus latches address inputs
for both read and write ports
■
Separate port selects for depth expansion
■
Synchronous internally self timed writes
■
Available in x18, and x36 configurations
■
Full data coherency, providing most current data
■
Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
■
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
Variable drive HSTL output buffers
■
JTAG 1149.1 compatible test access port
■
Delay lock loop (DLL) for accurate data placement
The CY7C1312BV18, and CY7C1314BV18 are 1.8 V
Synchronous Pipelined SRAMs, equipped with QDR® II
architecture. QDR II architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has data outputs to support read operations and the
write port has data inputs to support write operations. QDR II
architecture has separate data inputs and data outputs to
completely eliminate the need to “turn around” the data bus
required with common I/O devices. Access to each port is
accomplished through a common address bus. The read
address is latched on the rising edge of the K clock and the write
address is latched on the rising edge of the K clock. Accesses to
the QDR II read and write ports are completely independent of
one another. To maximize data throughput, both read and write
ports are provided with DDR interfaces. Each address location
is associated with two 18-bit words (CY7C1312BV18), or 36-bit
words (CY7C1314BV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turn arounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self timed write circuitry.
Configurations
CY7C1312BV18 – 1 M × 18
CY7C1314BV18 – 512 K × 36
Selection Guide
Description
Maximum operating frequency
Maximum operating current
250 MHz
200 MHz
167 MHz
Unit
250
200
167
MHz
x18
800
675
600
mA
x36
900
750
650
Cypress Semiconductor Corporation
Document #: 38-05619 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 2, 2011
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CY7C1312BV18
CY7C1314BV18
Logic Block Diagram (CY7C1312BV18)
K
CLK
Gen.
DOFF
19
Address
Register
Read Add. Decode
K
Write
Reg
512 K × 18 Array
Address
Register
Write
Reg
512 K × 18 Array
A(18:0)
19
18
Write Add. Decode
D[17:0]
A(18:0)
RPS
Control
Logic
C
Read Data Reg.
C
CQ
36
VREF
WPS
BWS[1:0]
18
Control
Logic
18
Reg.
Reg. 18
Reg.
18
CQ
18
Q[17:0]
Logic Block Diagram (CY7C1314BV18)
K
CLK
Gen.
DOFF
18
Address
Register
Read Add. Decode
K
Write
Reg
256 K × 36 Array
Address
Register
Write
Reg
256 K × 36 Array
A(17:0)
18
36
Write Add. Decode
D[35:0]
A(17:0)
RPS
Control
Logic
C
Read Data Reg.
C
CQ
72
VREF
WPS
BWS[3:0]
36
Control
Logic
Document #: 38-05619 Rev. *J
36
Reg.
Reg. 36
Reg.
36
CQ
36
Q[35:0]
Page 2 of 29
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CY7C1312BV18
CY7C1314BV18
Contents
Pin Configuration ............................................................. 4
165-ball FBGA (13 × 15 × 1.4 mm) Pinout .................. 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 7
Read Operations ......................................................... 7
Write Operations ......................................................... 7
Byte Write Operations ................................................. 7
Single Clock Mode ...................................................... 7
Concurrent Transactions ............................................. 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 8
Echo Clocks ................................................................ 8
DLL .............................................................................. 8
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ................................................. 9
Write Cycle Descriptions ............................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port—Test Clock ................................... 11
Test Mode Select (TMS) ........................................... 11
Test Data-In (TDI) ..................................................... 11
Test Data-Out (TDO) ................................................. 11
Performing a TAP Reset ........................................... 11
TAP Registers ........................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Electrical Characteristics ...................................... 14
TAP AC Switching Characteristics ............................... 15
Document #: 38-05619 Rev. *J
TAP Timing and Test Conditions .................................. 15
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Instruction Codes ........................................................... 16
Boundary Scan Order .................................................... 17
Power-up Sequence in QDR II SRAM ........................... 18
Power-up Sequence .................................................. 18
DLL Constraints ......................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Neutron Soft Error Immunity ......................................... 19
Electrical Characteristics ............................................... 19
DC Electrical Characteristics ..................................... 19
AC Electrical Characteristics ..................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagram ............................................................ 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC Solutions ......................................................... 29
Page 3 of 29
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CY7C1312BV18
CY7C1314BV18
Pin Configuration
The pin configuration for CY7C1312BV18, and CY7C1314BV18 follow. [1]
165-ball FBGA (13 × 15 × 1.4 mm) Pinout
Table 1. CY7C1312BV18 (1 M × 18)
1
A
CQ
2
3
NC/144 M NC/36 M
4
5
6
7
8
9
10
11
WPS
BWS1
K
NC/288
M
RPS
A
NC/72 M
CQ
B
NC
Q9
D9
A
NC
K
BWS0
A
NC
NC
Q8
C
NC
NC
D10
VSS
A
A
A
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
A
A
A
VSS
NC
NC
D1
P
NC
NC
Q17
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
4
5
6
7
8
9
10
11
WPS
BWS2
K
BWS1
RPS
Table 2. CY7C1314BV18 (512 K × 36)
1
2
3
A
CQ
NC/288 M NC/72 M
NC/36 M NC/144 M
CQ
B
Q27
Q18
D18
A
BWS3
K
BWS0
A
D17
Q17
Q8
C
D27
Q28
D19
VSS
A
A
A
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
A
A
A
VSS
Q10
D9
D1
P
Q35
D35
Q26
A
A
C
A
A
Q9
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Note
1. NC/36 M, NC/72 M, NC/144 M, and NC/288 M are not connected to the die and can be tied to any voltage level.
Document #: 38-05619 Rev. *J
Page 4 of 29
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CY7C1312BV18
CY7C1314BV18
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
InputSynchronous
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1312BV18 - D[17:0]
CY7C1314BV18 - D[35:0]
WPS
InputSynchronous
Write Port Select  Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
BWS0,
BWS1,
BWS2,
BWS3
InputSynchronous
Byte Write Select 0, 1, 2 and 3  Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1312BV18 BWS0 controls D[8:0], BWS1 controls D[17:9].
CY7C1314BV18BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3 controls
D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
InputSynchronous
Address Inputs. Sampled on the rising edge of the K (Read address) and K (Write address) clocks during
active read and write operations. These address inputs are multiplexed for both read and write operations.
Internally, the device is organized as 1 M × 18 (2 arrays each of 512 K × 18) for CY7C1312BV18 and 512
K × 36 (2 arrays each of 256 K × 36) for CY7C1314BV18. Therefore, only 19 address inputs are needed
to access the entire memory array of CY7C1312BV18 and 18 address inputs for CY7C1314BV18. These
inputs are ignored when the appropriate port is deselected.
Q[x:0]
OutputsSynchronous
Data Output Signals. These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of both the C and C clocks during read operations, or K and K when in single
clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated.
CY7C1312BV18  Q[17:0]
CY7C1314BV18  Q[35:0]
RPS
InputSynchronous
Read Port Select  Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tri-stated following the next rising edge of
the C clock. Each read access consists of a burst of two sequential transfers.
C
Input Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 8 for further details.
C
Input Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 8 for further details.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
CQ
Echo Clock
CQ Referenced with Respect to C. This is a free - running clock and is synchronized to the Input clock
for output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks is shown in the Switching Characteristics on page 22.
CQ
Echo Clock
CQ Referenced with Respect to C. This is a free - running clock and is synchronized to the Input clock
for output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks is shown in the Switching Characteristics on page 22.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
Document #: 38-05619 Rev. *J
Page 5 of 29
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CY7C1312BV18
CY7C1314BV18
Pin Definitions
Pin Name
(continued)
I/O
Pin Description
DOFF
Input
DLL Turn Off  Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing
in the DLL turned off operation differs from those listed in this data sheet.
TDO
Output
TDO for JTAG.
TCK
Input
TCK Pin for JTAG.
TDI
Input
TDI Pin for JTAG.
TMS
Input
TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/36M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/72M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M N/A
Not Connected to the Die. Can be tied to any voltage level.
VREF
InputReference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, Outputs, and AC
measurement points.
VDD
Power Supply Power Supply Inputs to the Core of the Device.
VSS
Ground
VDDQ
Power Supply Power Supply Inputs for the Outputs of the Device.
Ground for the Device.
Document #: 38-05619 Rev. *J
Page 6 of 29
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CY7C1312BV18
CY7C1314BV18
Functional Overview
The CY7C1312BV18, and CY7C1314BV18 are synchronous
pipelined Burst SRAMs equipped with a read port and a write
port. The read port is dedicated to read operations and the write
port is dedicated to write operations. Data flows into the SRAM
through the write port and flows out through the read port. These
devices multiplex the address inputs to minimize the number of
address pins required. By having separate read and write ports,
the QDR II completely eliminates the need to turn around the
data bus and avoids any possible data contention, thereby
simplifying system design. Each access consists of two 18-bit
data transfers in the case of CY7C1312BV18, and two 36-bit
data transfers in the case of CY7C1314BV18 in one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input timing is
referenced from the rising edge of the input clocks (K and K) and
all output timing is referenced to the rising edge of the output
clocks (C and C, or K and K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the output clocks (C and C, or K and K when in
single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C1312BV18 is described in the following sections. The
same basic descriptions apply to CY7C1314BV18.
Read Operations
The CY7C1312BV18 is organized internally as two arrays of
512K x 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address is latched on the rising edge of the K clock. The address
presented to the address inputs is stored in the read address
register. Following the next K clock rise the corresponding lowest
order 18-bit word of data is driven onto the Q[17:0] using C as the
output timing reference. On the subsequent rising edge of C, the
next 18-bit data word is driven onto the Q[17:0]. The requested
data is valid 0.45 ns from the rising edge of the output clock (C
and C or K and K when in single clock mode).
Synchronous internal circuitry automatically tri-states the outputs
following the next rising edge of the output clocks (C/C). This
allows for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise, the data presented to D[17:0] is latched and stored into the
Document #: 38-05619 Rev. *J
lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
presented to D[17:0] is stored into the write data register, provided
BWS[1:0] are both asserted active. The 36-bits of data are then
written into the memory array at the specified location. When
deselected, the write port ignores all inputs after completion of
pending write operations.
Byte Write Operations
Byte write operations are supported by the CY7C1312BV18.
A write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each 18-bit data word. Asserting
the appropriate Byte Write Select input during the data portion of
a write latches the data being presented and writes it into the
device. Deasserting the Byte Write Select input during the data
portion of a write allows the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify read,
modify, or write operations to a byte write operation.
Single Clock Mode
The CY7C1312BV18 can be used with a single clock that
controls both the input and output registers. In this mode, the
device recognizes only a single pair of input clocks (K and K) that
control both the input and output registers. This operation is
identical to the operation if the device had zero skew between
the K/K and C/C clocks. All timing parameters remain the same
in this mode. To use this mode of operation, the user must tie C
and C HIGH at power on. This function is a strap option and not
alterable during device operation.
Concurrent Transactions
The read and write ports on the CY7C1312BV18 operate
independently of one another. As each port latches the address
inputs on different clock edges, the user can read or write to any
location, regardless of the transaction on the other port. The user
can start reads and writes in the same clock cycle. If the ports
access the same location at the same time, the SRAM delivers
the most recent information associated with the specified
address location. This includes forwarding data from a write
cycle that was initiated on the previous K clock rise.
Depth Expansion
The CY7C1312BV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed prior to the device being deselected.
Page 7 of 29
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CY7C1312BV18
CY7C1314BV18
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175  and 350 , with VDDQ = 1.5 V. The
output impedance is adjusted every 1024 cycles upon power-up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR II to simplify data capture
on high-speed systems. Two echo clocks are generated by the
QDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free-running clocks and are
synchronized to the output clock (C/C) of the QDR II. In single
clock mode, CQ is generated with respect to K and CQ is
generated with respect to K. The timing for the echo clocks is
shown in the Switching Characteristics on page 22.
DLL
These chips use a DLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power-up, when the DOFF is tied HIGH, the DLL is locked after
1024 cycles of stable clock. The DLL can also be reset by
slowing or stopping the input clock K and K for a minimum of
30 ns. However, it is not necessary to reset the DLL to lock to the
desired frequency. The DLL automatically locks 1024 clock
cycles after a stable clock is presented. The DLL may be
disabled by applying ground to the DOFF pin. For information
refer to the application note, DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+ – AN5062.
Application Example
Figure 1 shows two QDR II used in an application.
Figure 1. Application Example
SRAM #1
Vt
R
D
A
R
P
S
#
W
P
S
#
B
W
S
#
ZQ
CQ/CQ#
Q
C C# K K#
DATA IN
DATA OUT
Address
RPS#
BUS
WPS#
MASTER
BWS#
(CPU CLKIN/CLKIN#
or
Source K
ASIC)
Source K#
R = 250ohms
SRAM #2
R
P
S
#
D
A
R
W
P
S
#
B
W
S
#
ZQ R = 250ohms
CQ/CQ#
Q
C C# K K#
Vt
Vt
Delayed K
Delayed K#
R
Document #: 38-05619 Rev. *J
R = 50ohms Vt = Vddq/2
Page 8 of 29
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CY7C1312BV18
CY7C1314BV18
Truth Table
The truth table for CY7C1312BV18, and CY7C1314BV18 follows. [2, 3, 4, 5, 6, 7]
Operation
K
RPS WPS
DQ
DQ
Write cycle:
Load address on the rising edge of K;
input write data on K and K rising edges.
L-H
X
L
D(A + 0) at K(t) 
Read Cycle:
Load address on the rising edge of K;
wait one and a half cycle; read data on C and C rising edges.
L-H
L
X
Q(A + 0) at C(t + 1)  Q(A + 1) at C(t + 2) 
NOP: No operation
L-H
H
H
D=X
Q = High Z
D=X
Q = High Z
Stopped
X
X
Previous state
Previous state
Standby: Clock stopped
D(A + 1) at K(t) 
Write Cycle Descriptions
The write cycle description table for CY7C1312BV18 follows. [2, 8]
BWS0
BWS1
K
K
L
L
L–H
–
L
L
–
L
H
L–H
L
H
–
H
L
L–H
H
L
–
H
H
L–H
H
H
–
Comments
During the data portion of a write sequence
Both bytes (D[17:0]) are written into the device.
L-H During the data portion of a write sequence
Both bytes (D[17:0]) are written into the device.
–
During the data portion of a write sequence
Only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L–H During the data portion of a write sequence
Only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
–
During the data portion of a write sequence
Only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L–H During the data portion of a write sequence
Only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = “Do not Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions
of a write cycle, as long as the setup and hold requirements are achieved.
Document #: 38-05619 Rev. *J
Page 9 of 29
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CY7C1312BV18
CY7C1314BV18
Write Cycle Descriptions
The write cycle description table for CY7C1314BV18 follows. [9, 10]
BWS0
BWS1
BWS2
BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L
H
H
H
L–H
L
H
H
H
–
H
L
H
H
L–H
H
L
H
H
–
H
H
L
H
L–H
H
H
L
H
–
H
H
H
L
L–H
H
H
H
L
–
H
H
H
H
L–H
H
H
H
H
–
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Notes
9. X = “Do not Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
10. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions
of a write cycle, as long as the setup and hold requirements are achieved.
Document #: 38-05619 Rev. *J
Page 10 of 29
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CY7C1312BV18
CY7C1314BV18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-1900. The TAP operates using JEDEC
standard 1.8 V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull-up resistor. TDO
must be left unconnected. Upon power-up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 13. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in on page 14. Upon power-up, the
instruction register is loaded with the IDCODE instruction. It is
also loaded with the IDCODE instruction if the controller is placed
in a reset state, as described in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The Boundary Scan Order on page 17 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Test Data-Out (TDO)
Identification (ID) Register
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 16).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 16.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power-up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document #: 38-05619 Rev. *J
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 16. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Page 11 of 29
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CY7C1312BV18
CY7C1314BV18
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power-up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a high Z state until the next command is supplied during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
high Z condition.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is pre-set LOW to enable the
output when the device is powered-up, and also when the TAP
controller is in the Test-Logic-Reset state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
Document #: 38-05619 Rev. *J
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 12 of 29
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CY7C1312BV18
CY7C1314BV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [11]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
SELECT
DR-SCAN
1
1
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-IR
UPDATE-DR
1
1
0
PAUSE-DR
0
0
0
1
0
Note
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05619 Rev. *J
Page 13 of 29
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CY7C1312BV18
CY7C1314BV18
TAP Controller Block Diagram
0
Bypass Register
2
Selection
Circuitry
TDI
1
0
Selection
Circuitry
Instruction Register
31
30
29
.
.
2
1
0
1
0
TDO
Identification Register
106
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics
Over the Operating Range [12, 13, 14]
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH voltage
IOH =2.0 mA
1.4
–
V
VOH2
Output HIGH voltage
IOH =100 A
1.6
–
V
VOL1
Output LOW voltage
IOL = 2.0 mA
–
0.4
V
VOL2
Output LOW voltage
IOL = 100 A
–
0.2
V
VIH
Input HIGH voltage
VIL
Input LOW voltage
IX
Input and output load current
0.65 VDD VDD + 0.3
GND  VI  VDD
V
–0.3
0.35 VDD
V
–5
5
A
Notes
12. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
13. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2).
14. All Voltage referenced to Ground.
Document #: 38-05619 Rev. *J
Page 14 of 29
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CY7C1312BV18
CY7C1314BV18
TAP AC Switching Characteristics
Over the Operating Range [15, 16]
Parameter
Description
Min
Max
Unit
50
–
ns
TCK clock frequency
–
20
MHz
TCK clock HIGH
20
–
ns
TCK clock LOW
20
–
ns
tTCYC
TCK clock cycle time
tTF
tTH
tTL
Setup Times
tTMSS
TMS setup to TCK clock rise
5
–
ns
tTDIS
TDI setup to TCK clock rise
5
–
ns
tCS
Capture setup to TCK rise
5
–
ns
Hold Times
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
Output Times
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions. [16]
Figure 2. TAP Timing and Test Conditions
0.9 V
All input pulses
1.8 V
50 
0.9 V
TDO
0V
Z0 = 50 
(a)
CL = 20 pF
tTH
GND
tTL
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Notes
15. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
16. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document #: 38-05619 Rev. *J
Page 15 of 29
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CY7C1312BV18
CY7C1314BV18
Identification Register Definitions
Value
Instruction Field
Description
CY7C1312BV18
CY7C1314BV18
000
000
Cypress Device ID (28:12)
11010011010010101
11010011010100101
Cypress JEDEC ID (11:1)
00000110100
00000110100
Allows unique identification of
SRAM vendor.
ID Register Presence (0)
1
1
Indicates the presence of an
ID register.
Revision Number (31:29)
Version number.
Defines the type of SRAM.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
107
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the
register between TDI and TDO. This operation does not affect
SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan
register between TDI and TDO. Forces all SRAM output drivers to
a High Z state.
RESERVED
011
Do not use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input and output ring contents. Places the boundary
scan register between TDI and TDO. Does not affect the SRAM
operation.
RESERVED
101
Do not use: This instruction is reserved for future use.
RESERVED
110
Do not use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation
does not affect SRAM operation.
Document #: 38-05619 Rev. *J
Page 16 of 29
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CY7C1312BV18
CY7C1314BV18
Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
1
6P
27
11H
54
7B
81
3G
28
10G
55
6B
82
2G
2
6N
29
9G
56
6A
83
1J
3
7P
30
11F
57
5B
84
2J
4
7N
31
11G
58
5A
85
3K
5
7R
32
9F
59
4A
86
3J
6
8R
33
10F
60
5C
87
2K
7
8P
34
11E
61
4B
88
1K
8
9R
35
10E
62
3A
89
2L
9
11P
36
10D
63
1H
90
3L
10
10P
37
9E
64
1A
91
1M
11
10N
38
10C
65
2B
92
1L
12
9P
39
11D
66
3B
93
3N
13
10M
40
9C
67
1C
94
3M
14
11N
41
9D
68
1B
95
1N
15
9M
42
11B
69
3D
96
2M
16
9N
43
11C
70
3C
97
3P
17
11L
44
9B
71
1D
98
2N
18
11M
45
10B
72
2C
99
2P
19
9L
46
11A
73
3E
100
1P
20
10L
47
Internal
74
2D
101
3R
21
11K
48
9A
75
2E
102
4R
22
10K
49
8B
76
1E
103
4P
23
9J
50
7C
77
2F
104
5P
24
9K
51
6C
78
3F
105
5N
25
10J
52
8A
79
1G
106
5R
26
11J
53
7A
80
1F
Document #: 38-05619 Rev. *J
Page 17 of 29
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CY7C1312BV18
CY7C1314BV18
Power-up Sequence in QDR II SRAM
QDR II SRAMs must be powered-up and initialized in a
predefined manner to prevent undefined operations.
DLL Constraints
■
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
■
The DLL functions at frequencies down to 120 MHz.
■
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide1024 cycles stable clock
to relock to the desired clock frequency.
Power-up Sequence
■
■
Apply power and drive DOFF either HIGH or LOW (all other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ.
❐ Apply VDDQ before VREF or at the same time as VREF.
❐ Drive DOFF HIGH.
Provide stable DOFF (HIGH), power and clock (K, K) for 1024
cycles to lock the DLL.
~
~
Figure 3. Power-up Waveforms
K
K
~
~
Unstable Clock
> 1024 Stable clock
Start Normal
Operation
Clock Start (Clock Starts after V DD / V DDQ Stable)
VDD / VDDQ
DOFF
Document #: 38-05619 Rev. *J
V DD / V DDQ Stable (< +/- 0.1V DC per 50ns )
Fix High (or tie to VDDQ)
Page 18 of 29
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CY7C1312BV18
CY7C1314BV18
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Neutron Soft Error Immunity
Storage temperature ................................ –65 °C to +150 °C
Description
Test
Conditions
Typ
Max*
Unit
LSBU
Logical
single-bit
upsets
25 °C
320
368
FIT/
Mb
LMBU
Logical
multi-bit
upsets
25 °C
0
0.01
FIT/
Mb
Single event
latch-up
85 °C
0
0.1
FIT/
Dev
Ambient temperature with power applied . –55 °C to +125 °C
Parameter
Supply voltage on VDD relative to GND ........–0.5 V to +2.9 V
Supply voltage on VDDQ relative to GND....... –0.5 V to +VDD
DC applied to outputs in high Z ........ –0.5 V to VDDQ + 0.3 V
DC input voltage [17] ............................ –0.5 V to VDD + 0.3 V
Current into outputs (LOW) ......................................... 20 mA
SEL
Static discharge voltage (MIL-STD-883, M. 3015).. > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature (TA)
VDD [18]
VDDQ [18]
0 °C to +70 °C
1.8 ± 0.1 V
1.4 V to
VDD
–40 °C to +85 °C
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to
Application Note, Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates – AN54908.
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range [19]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VDD
Power supply voltage
1.7
1.8
1.9
V
VDDQ
I/O supply voltage
1.4
1.5
VDD
V
VOH
Output HIGH voltage
Note 20
VDDQ/2 – 0.12
–
VDDQ/2 + 0.12
V
VOL
Output LOW voltage
Note 21
VDDQ/2 – 0.12
–
VDDQ/2 + 0.12
V
VOH(LOW)
Output HIGH voltage
IOH =0.1 mA, nominal impedance
VDDQ – 0.2
–
VDDQ
V
VOL(LOW)
Output LOW voltage
IOL = 0.1 mA, nominal impedance
VSS
–
0.2
V
VIH
Input HIGH voltage
VREF + 0.1
–
VDDQ + 0.3
V
VIL
Input LOW voltage
–0.3
–
VREF – 0.1
V
IX
Input leakage current
GND  VI  VDDQ
5
–
5
A
IOZ
Output leakage current
GND  VI  VDDQ, output disabled
5
–
5
A
0.68
0.75
0.95
V
VREF
Input reference voltage
[22]
Typical Value = 0.75 V
Notes
17. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2).
18. Power-up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
19. All Voltage referenced to Ground.
20. Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 ohms  RQ  350 ohms.
21. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms  RQ  350 ohms.
22. VREF (min) = 0.68 V or 0.46 VDDQ, whichever is larger, VREF (max) = 0.95 V or 0.54 VDDQ, whichever is smaller.
Document #: 38-05619 Rev. *J
Page 19 of 29
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CY7C1312BV18
CY7C1314BV18
Electrical Characteristics
(continued)
DC Electrical Characteristics
Over the Operating Range [19]
Parameter
IDD [23]
ISB1
Description
VDD operating supply
Automatic power-down
current
Test Conditions
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
Max VDD,
both ports deselected,
VIN  VIH or VIN  VIL
f = fMAX = 1/tCYC,
inputs static
Min
Typ
Max
Unit
250 MHz (x18)
–
–
800
mA
(x36)
–
–
900
200 MHz (x18)
–
–
675
(x36)
–
–
750
167 MHz (x18)
–
–
600
(x36)
–
–
650
250 MHz (x18)
–
–
400
mA
(x36)
–
–
450
200 MHz (x18)
–
–
380
(x36)
–
–
400
167 MHz (x18)
–
–
360
(x36)
–
–
370
Min
Typ
Max
Unit
AC Electrical Characteristics
Over the Operating Range [24]
Parameter
Description
Test Conditions
VIH
Input HIGH voltage
VREF + 0.2
–
–
V
VIL
Input LOW voltage
–
–
VREF – 0.2
V
Notes
23. The operation current is calculated with 50% read cycle and 50% write cycle.
24. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2).
Document #: 38-05619 Rev. *J
Page 20 of 29
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CY7C1312BV18
CY7C1314BV18
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
CIN
Description
Test Conditions
Max
Unit
5
pF
Clock input capacitance
6
pF
Output capacitance
7
pF
165 FBGA
Package
Unit
18.7
°C/W
4.5
°C/W
TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V
Input capacitance
CCLK
CO
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
Figure 4. AC Test Loads and Waveforms
VREF = 0.75 V
VREF
0.75 V
VREF
OUTPUT
Z0 = 50 
Device
Under
Test
ZQ
RL = 50
R = 50 
All input pulses
OUTPUT
Device
Under
VREF = 0.75 V Test ZQ
RQ =
250 
(a)
0.75 V
Including
JIG and
scope
[25]
1.25 V
0.75 V
5 pF
0.25 V
Slew Rate = 2 V/ns
RQ =
250 
(b)
Note
25. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input
pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.
Document #: 38-05619 Rev. *J
Page 21 of 29
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CY7C1312BV18
CY7C1314BV18
Switching Characteristics
Over the Operating Range [26, 27]
Cypress Consortium
Parameter Parameter
Description
VDD(Typical) to the first access [28]
tPOWER
tCYC
tKHKH
K clock and C clock cycle time
250 MHz
200 MHz
167 MHz
Min Max Min Max Min Max
Unit
1
–
1
–
1
–
ms
4.0
8.4
5.0
8.4
6.0
8.4
ns
tKH
tKHKL
Input clock (K/K and C/C) HIGH
1.6
–
2.0
–
2.4
–
ns
tKL
tKLKH
Input clock (K/K and C/C) LOW
1.6
–
2.0
–
2.4
–
ns
tKHKH
tKHKH
K clock rise to K clock rise and C to C rise
(rising edge to rising edge)
1.8
–
2.2
–
2.7
–
ns
tKHCH
tKHCH
K/K clock rise to C/C clock rise (rising edge to rising edge)
0
1.8
0
2.2
0
2.7
ns
Setup Times
tSA
tAVKH
Address setup to K clock rise
0.35
–
0.4
–
0.5
–
ns
tSC
tIVKH
Control setup to K clock rise (RPS, WPS)
0.35
–
0.4
–
0.5
–
ns
tSCDDR
tIVKH
DDR control setup to clock (K/K) rise
(BWS0, BWS1, BWS3, BWS4)
0.35
–
0.4
–
0.5
–
ns
tSD
tDVKH
D[X:0] setup to clock (K/K) rise
0.35
–
0.4
–
0.5
–
ns
Hold Times
tHA
tKHAX
Address hold after K clock rise
0.35
–
0.4
–
0.5
–
ns
tHC
tKHIX
Control hold after K clock rise (RPS, WPS)
0.35
–
0.4
–
0.5
–
ns
tHCDDR
tKHIX
DDR control hold after clock (K/K) rise
(BWS0, BWS1, BWS3, BWS4)
0.35
–
0.4
–
0.5
–
ns
tHD
tKHDX
D[X:0] hold after clock (K/K) rise
0.35
–
0.4
–
0.5
–
ns
Output Times
tCO
tCHQV
C/C clock rise (or K/K in single clock mode) to data valid
tDOH
tCHQX
Data output hold after output C/C clock rise
(active to active)
tCCQO
tCHCQV
C/C clock rise to echo clock valid
tCQOH
tCHCQX
Echo clock hold after C/C clock rise
tCQD
tCQHQV
Echo clock high to data valid
tCQDOH
tCQHQX
Echo clock high to data invalid
tCHZ
tCHQZ
Clock (C/C) rise to high Z (active to high Z) [29, 30]
tCLZ
tCHQX1
Clock (C/C) rise to low Z
[29, 30]
–
0.45
–
0.45
–
0.50
ns
–0.45
–
–0.45
–
–0.50
–
ns
–
0.45
–
0.45
–
0.50
ns
–0.45
–
–0.45
–
–0.50
–
ns
–
0.30
–
0.35
–
0.40
ns
–0.30
–
–0.35
–
–0.40
–
ns
–
0.45
–
0.45
–
0.50
ns
–0.45
–
–0.45
–
–0.50
–
ns
DLL Timing
tKC Var
tKC Var
Clock phase jitter
–
0.20
–
0.20
–
0.20
ns
tKC lock
tKC lock
DLL lock time (K, C)
1024
–
1024
–
1024
–
Cycles
tKC Reset
tKC Reset
K static to DLL reset
30
–
30
–
30
–
ns
Notes
26. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input
pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.
27. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
28. This part has a voltage regulator internally; tPOWER is the time that the power is supplied above VDD minimum initially before a read or write operation is initiated.
29. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±100 mV from steady state voltage.
30. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Document #: 38-05619 Rev. *J
Page 22 of 29
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CY7C1312BV18
CY7C1314BV18
Switching Waveforms
Figure 5. Read/Write/Deselect Sequence [31, 32, 33]
READ
WRITE
READ
WRITE
READ
WRITE
NOP
WRITE
NOP
1
2
3
4
5
6
7
8
9
10
K
tKH
tKL
tKHKH
tCYC
K
RPS
tSC
t HC
WPS
A
D
A1
A2
tSA tHA
tSA tHA
D11
D30
A0
D10
A3
A4
A5
D31
D50
D51
tSD
Q00
t CLZ
C
tKL
tKH
tKHCH
D60
D61
tSD tHD
tHD
Q
tKHCH
A6
Q01
tDOH
tCO
Q20
Q21
Q41
Q40
tCQDOH
t CHZ
tCQD
t CYC
tKHKH
C
tCQOH
tCCQO
CQ
tCQOH
tCCQO
CQ
DON’T CARE
UNDEFINED
Notes
31. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
32. Outputs are disabled (High Z) one clock cycle after a NOP.
33. In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document #: 38-05619 Rev. *J
Page 23 of 29
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CY7C1312BV18
CY7C1314BV18
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices
Speed
(MHz)
Package
Diagram
Ordering Code
Package Type
Operating
Range
250
CY7C1314BV18-250BZXC
200
CY7C1312BV18-200BZXC
51-85180 165-ball Fine Pitch Ball Grid Array (13 × 15 × 1.4 mm) Pb-free Commercial
CY7C1312BV18-200BZI
51-85180 165-ball Fine Pitch Ball Grid Array (13 × 15 × 1.4 mm)
Industrial
CY7C1312BV18-167BZI
51-85180 165-ball Fine Pitch Ball Grid Array (13 × 15 × 1.4 mm)
Industrial
167
51-85180 165-ball Fine Pitch Ball Grid Array (13 × 15 × 1.4 mm) Pb-free Commercial
Ordering Code Definitions
CY 7C 13XX B V18 - XXX
XXX X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Package Type: XXX = BZ or BZX
BZ = 165-ball FPBGA
BZX = 165-ball FPBGA (Pb-free)
Speed: 250 MHz / 200 MHz / 167 MHz
V18 = 1.8 V VDD
Process Technology: 90 nm errata affected
Part Identifier: 13XX = 1312 or 1314
Marketing Code: 7C = SRAMs
Company ID: CY = Cypress
Document #: 38-05619 Rev. *J
Page 24 of 29
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CY7C1312BV18
CY7C1314BV18
Package Diagram
Figure 6. 165-ball FPBGA (13 × 15 × 1.4 mm)
51-85180 *C
Document #: 38-05619 Rev. *J
Page 25 of 29
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CY7C1312BV18
CY7C1314BV18
Acronyms
Acronym
Description
DDR
double data rate
FPBGA
fine-pitch ball grid array
HSTL
high-speed transceiver logic
JEDEC
joint electron device engineering council
JTAG
joint test action group
ODT
on-die termination
PLL
phase-locked loop
QDR
quad data rate
TAP
test access port
TCK
test clock
TDO
test data out
TDI
test data in
TMS
test mode select
Document Conventions
Units of Measure
Symbol
Unit of Measure
ns
nano seconds
V
Volts
µA
micro Amperes
mA
milli Amperes
mm
milli meter
MHz
Mega Hertz
pF
pico Farad
°C
degree Celcius
W
Watts
Document #: 38-05619 Rev. *J
Page 26 of 29
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CY7C1312BV18
CY7C1314BV18
Document History Page
Document Title: CY7C1312BV18/CY7C1314BV18, 18-Mbit QDR® II SRAM Two-Word Burst Architecture
Document Number: 38-05619
Revision
ECN
Orig. of Submission Description of Change
Change
Date
**
252474
SYT
See ECN
New datasheet
*A
325581
SYT
See ECN
Removed CY7C1910BV18 from the title
Included 300 MHz Speed Bin
Added Industrial Temperature Grade
Replaced TBDs for IDD and ISB1 specifications
Replaced the TBDs on the Thermal Characteristics Table to JA = 28.51 C/W and
JC = 5.91 C/W
Replaced TBDs in the Capacitance Table for the 165 FBGA Package
Changed the package diagram from BB165E (15 × 17 × 1.4 mm) to BB165D
(13 × 15 × 1.4 mm)
Added Pb-Free Product Information
Updated the Ordering Information by Shading and Unshading MPNs as per availability
*B
413997
NXR
See ECN
Converted from Preliminary to Final
Added CY7C1910BV18 part number to the title
Removed 300 MHz Speed Bin
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Changed C/C Pin Description in the features section and Pin Description
Corrected Typo in Identification Register Definitions for CY7C1910BV18 on page# 16
Added power-up sequence details and waveforms
Added foot notes #15, 16, and 17 on page# 18
Replaced Three state with Tri-state
Changed the description of IX from Input Load Current to Input Leakage Current on
page# 13
Modified the IDD and ISB values
Modified test condition in Footnote #20 on page# 19 from VDDQ < VDD to
VDDQ < VDD
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*C
423334
NXR
See ECN
Changed the IEEE Standard # 1149.1-1900 to 1149.1-2001
Changed the Minimum Value of tSC and tHC from 0.5ns to 0.35ns for 250 MHz and
0.6 ns to 0.4 ns for 200 MHz speed bins
Changed the description of tSA from K Clock Rise to Clock (K/K) Rise
Changed the description of tSC and tHC from Clock (K and K) Rise to K Clock Rise
*D
472384
NXR
See ECN
Modified the ZQ Definition from Alternately, this pin is connected directly to VDD to
Alternately, this pin is connected directly to VDDQ
Changed the IEEE Standard # from 1149.1-2001 to 1149.1-1900
Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND
Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH
from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in Tap Switching Characteristics.
Modified power-up waveform
Changed the Maximum rating of Ambient Temperature with Power Applied from
–10 C to +85 C to –55 C to +125 C
Added additional notes in the AC parameter section
Modified AC Switching Waveform
Corrected the typo In the Tap Switching Characteristics.
Updated the Ordering Information Table
Document #: 38-05619 Rev. *J
Page 27 of 29
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CY7C1312BV18
CY7C1314BV18
Document History Page (continued)
Document Title: CY7C1312BV18/CY7C1314BV18, 18-Mbit QDR® II SRAM Two-Word Burst Architecture
Document Number: 38-05619
*E
1274723
VKN
See ECN
Corrected typo in the JTAG ID code for CY7C1910BV18
*F
2511674
VKN/
PYRS
06/03/08
Updated Logic Block diagrams
Updated IDD/ISB specs
Added footnote# 19 related to IDD
Updated power-up sequence waveform and its description
Changed DLL minimum operating frequency from 80 MHz to 120 MHz
Changed JA spec from 28.51 to 18.7
Changed JC spec from 5.91 to 4.5
Changed tCYC maximum spec to 8.4 ns for all speed bins
Modified footnotes 21 and 28
*G
2755901
VKN
08/25/09
Removed x8 and x9 part number details
Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available and modified
the disclaimer for the Ordering information.
Updated Package Diagram.
*H
2998771
NJY
08/02/10
Template update.
Package diagram update: 51-85180 – *B to *C
*I
3088678
NJY
11/25/2010
Updated Ordering Information.
Added Units of Measure.
*J
3158296
NJY
02/02/2011
Updated Ordering Information.
Document #: 38-05619 Rev. *J
Page 28 of 29
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CY7C1312BV18
CY7C1314BV18
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05619 Rev. *J
Revised February 2, 2011
Page 29 of 29
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC, and Samsung. All product and company names mentioned in this document are
the trademarks of their respective holders.
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