CSD17553Q5A www.ti.com SLPS373 – MAY 2012 30V, N-Channel NexFET™ Power MOSFETs Check for Samples: CSD17553Q5A FEATURES 1 • • • • • • • PRODUCT SUMMARY Ultralow Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm × 6-mm Plastic Package VDS Drain to Source Voltage Qg Gate Charge Total (4.5V) Qgd Gate Charge Gate to Drain RDS(on) Drain to Source On Resistance VGS(th) Threshold Voltage • DESCRIPTION The NexFET power MOSFET has been designed to minimize losses in power conversion applications. Top View 1 8 D S 2 7 D S 3 G 4 6 D 5 D 4.7 nC 3.5 mΩ VGS = 10V 2.7 mΩ 1.5 V ORDERING INFORMATION Point of load Synchronous Buck in Networking, Telecom and Computing Systems Optimized for Control and Synchronous FET Applications S V nC VGS = 4.5V Device Package Media CSD17553Q5A SON 5-mm × 6-mm Plastic Package 13-Inch Reel APPLICATIONS • 30 17.5 Qty Ship 2500 Tape and Reel ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise stated VALUE UNIT VDS Drain to Source Voltage 30 V VGS Gate to Source Voltage +/-20 V Continuous Drain Current, TC = 25°C 100 A Continuous Drain Current, TA = 25°C(1) 23.5 A IDM Pulsed Drain Current, TA = 25°C(2) 151 A PD Power Dissipation(1) 3.1 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, Single Pulse ID = 45A, L = 0.1mH, RG = 25Ω 101 mJ ID (1) Typical RθJA = 40.5°C/W on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB. (2) Pulse duration ≤300μs, duty cycle ≤2% D P0093-01 Text 4 Spacing RDS(on) vs VGS Text 4 Spacing GATE CHARGE 10 TC = 25°C Id = 20A TC = 125ºC Id = 20A 10 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance - mΩ 12 8 6 4 2 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage - V 18 20 G001 ID = 20A VDS = 15V 8 6 4 2 0 0 5 10 15 20 25 30 Qg - Gate Charge - nC (nC) 35 40 G001 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated CSD17553Q5A SLPS373 – MAY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250μA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 24V IGSS Gate to Source Leakage Current VDS = 0V, VGS = 20V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = 250μA RDS(on) Drain to Source On Resistance gfs Transconductance 30 1 V 1 μA 100 nA 1.5 1.9 3.5 4 mΩ VGS = 10V, ID = 20A 2.7 3.1 mΩ VDS = 15V, ID = 20A 106 VGS = 4.5V, ID = 20A V S Dynamic Characteristics Ciss Input Capacitance VGS = 0V, VDS = 15V, f = 1MHz 2710 3252 pF Coss Output Capacitance 635 762 pF Crss Reverse Transfer Capacitance 48 60 pF RG Series Gate Resistance 0.7 0.9 Ω Qg Gate Charge Total (4.5V) 17.5 21.5 nC Qgd Gate Charge Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) VDS = 15V, ID = 20A 4.7 nC 5.8 nC 4.1 nC 19.6 nC Turn On Delay Time 9.7 ns tr Rise Time 17 ns td(off) Turn Off Delay Time 14.8 ns tf Fall Time 5.2 ns VDS = 15V, VGS = 0V VDS = 15V, VGS = 4.5V, IDS = 20A, RG = 0.75Ω Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time IDS = 20A, VGS = 0V 0.8 VDS= 14V, IF = 20A, di/dt = 300A/μs 1 V 23.8 nC 23.1 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER RθJC Thermal Resistance Junction to Case (1) RθJA Thermal Resistance Junction to Ambient (1) (2) (1) (2) 2 MIN TYP MAX UNIT 1.3 °C/W 50.6 °C/W RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Copyright © 2012, Texas Instruments Incorporated CSD17553Q5A www.ti.com GATE SLPS373 – MAY 2012 GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50.6°C/W when mounted on 1 inch2 (6.45-cm2) of 2oz. (0.071-mm thick) Cu. Source Max RθJA = 122.4°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance Copyright © 2012, Texas Instruments Incorporated 3 CSD17553Q5A SLPS373 – MAY 2012 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 200 IDS - Drain-to-Source Current - A IDS - Drain-to-Source Current - A 120 100 80 60 40 VGS =10V VGS =4V VGS =2.5V 20 0 0 1 2 3 4 VDS - Drain-to-Source Voltage - V 160 140 120 100 80 60 TC = 125°C TC = 25°C TC = −55°C 40 20 0 5 VDS = 5V 180 0 1 2 3 VGS - Gate-to-Source Voltage - V G001 Figure 2. Saturation Characteristics TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 3.5 8 C − Capacitance − nF VGS - Gate-to-Source Voltage (V) 4 ID = 20A VDS = 15V 6 4 2 3 2.5 2 1.5 1 0.5 0 0 5 10 15 20 25 30 Qg - Gate Charge - nC (nC) 35 0 40 0 5 10 15 20 25 VDS - Drain-to-Source Voltage - V G001 Figure 4. Gate Charge 30 G001 Figure 5. Capacitance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 2 12 RDS(on) - On-State Resistance - mΩ ID = 250uA VGS(th) - Threshold Voltage - V G001 Figure 3. Transfer Characteristics 10 1.6 1.2 0.8 0.4 0 −75 −25 25 75 125 TC - Case Temperature - ºC Figure 6. Threshold Voltage vs. Temperature 4 4 175 G001 TC = 25°C Id = 20A TC = 125ºC Id = 20A 10 8 6 4 2 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage - V 18 20 G001 Figure 7. On-State Resistance vs. Gate-to-Source Voltage Copyright © 2012, Texas Instruments Incorporated CSD17553Q5A www.ti.com SLPS373 – MAY 2012 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1.8 1.6 100 VGS = 4.5V VGS = 6V VGS = 10V ID =20A ISD − Source-to-Drain Current - A Normalized On-State Resistance 2 1.4 1.2 1 0.8 0.6 0.4 −75 −25 25 75 125 TC - Case Temperature - ºC 175 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage - V G001 Figure 8. Normalized On-State Resistance vs. Temperature 1 G001 Figure 9. Typical Diode Forward Voltage TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING − IAV - Peak Avalanche Current- A 200 TC = 25ºC TC = 125ºC 100 10 1 0.001 Figure 10. Maximum Safe Operating Area 0.01 0.1 TAV - Time in Avalanche - mS 1 2 G001 Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING − IDS - Drain- to- Source Current - A 120.0 100.0 80.0 60.0 40.0 20.0 0.0 −50 −25 0 25 50 75 100 125 TC - Case Temperature - ºC 150 175 G001 Figure 12. Maximum Drain Current vs. Temperature Copyright © 2012, Texas Instruments Incorporated 5 CSD17553Q5A SLPS373 – MAY 2012 www.ti.com MECHANICAL DATA Q5A Package Dimensions L E2 H K 7 D2 3 4 b 4 5 5 6 3 6 e D1 7 2 2 8 8 1 1 q L1 Top View Bottom View Side View c A q E1 E Front View M0135-01 DIM 6 MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.34 D1 4.80 4.90 5.00 D2 3.61 3.81 4.02 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 e 1.17 1.27 1.37 H 0.41 0.56 0.71 K 1.10 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 θ 0° 12° Copyright © 2012, Texas Instruments Incorporated CSD17553Q5A www.ti.com SLPS373 – MAY 2012 Figure 13. Recommended PCB Pattern DIM F1 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 F8 F4 F10 M0139-01 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 Q5A Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket Copyright © 2012, Texas Instruments Incorporated 7 PACKAGE OPTION ADDENDUM www.ti.com 22-Jun-2012 PACKAGING INFORMATION Orderable Device CSD17553Q5A Status (1) ACTIVE Package Type Package Drawing SON DQJ Pins Package Qty 8 2500 Eco Plan (2) Pb-Free (RoHS Exempt) Lead/ Ball Finish CU SN MSL Peak Temp (3) Samples (Requires Login) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. 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