ATMEL ATR0603 Gps front-end ic Datasheet

Features
•
•
•
•
•
•
•
•
•
Very Low Power Design
Single IF Architecture
Excellent Noise Performance
1-bit ADC on Chip
Small QFN Package (4 mm × 4 mm, 24 Pins)
Highly Integrated, Few External Components
Advanced BiCMOS Technology (UHF6s)
Supply Switch for External Circuitry (e.g., TCXO)
Non-ESD-sensitive Device
GPS Front-end
IC
1. Description
The ATR0603 is a single-IF GPS front-end IC, designed to meet the requirements of
mobile and automotive applications. Excellent RF performance combined with high
bandwidth and a low noise figure enables high-quality GPS solutions, and its very low
power consumption is a perfect match for portable devices. Featuring a fully integrated balanced frequency synthesizer, only a few external components are required.
The gain of the IF amplifier can be set to three different levels in order to meet the
requirements for various applications. Several types of external oscillators can be connected to the robust TCXO interface. The startup logic allows significant power saving
due to very low power-down current and the ability to disable the external TCXO or
even other external components. CMOS output drivers deliver a 1-bit data signal and
a 16.367667-MHz clock signal to the baseband interface.
Figure 1-1.
ATR0603
Preliminary
Block Diagram
PU
BP
NBP
BPI
NBPI
AMP1
AMP2
Startup
logic
VCC
GND
ATR0603
VDIG
RF
SIG
A
D
NRF
XSUP
VCO
PLL
XIN
SC
XREF
4950B–GPS–11/06
2. Pin Configuration
Pinning QFN24 (4 mm × 4 mm)
VDIG
SC
SIG
PU
VCC
AMP2
Figure 2-1.
24 23 22 21 20 19
GND
GND
XREF
XIN
GND
XSUP
1
2
3
4
5
6
Paddle
GND
18
17
16
15
14
13
AMP1
NBPI
BPI
NBP
BP
VCC
VCC
MO
GND
NRF
RF
TEST
7 8 9 10 11 12
Table 2-1.
Type(1)
Pin
Symbol
Paddle
GND
S
Common ground
1
GND
S
Ground
2
GND
S
Ground
3
XREF
A_I
TCXO interface ground
4
XIN
A_I
TCXO interface signal
5
GND
S
6
XSUP
XS
7
VCC
S
8
MO
A_O
9
GND
S
10
NRF
A_I
Complementary RF input
Function
Ground
External circuitry supply switch
Analog supply
Test buffer output (fIF)
Ground
11
RF
A_I
RF input
12
TEST
D_I
Enable test buffer
13
VCC
S
14
BP
A_O
IF filter interface (mixer output, open collector)
15
NBP
A_O
IF filter interface (complementary mixer output, open collector)
16
BPI
A_I
IF filter interface (IF input)
17
NBPI
A_I
IF filter interface (complementary IF input)
18
AMP1
D_I
IF gain control bit #1
19
AMP2
D_I
20
VCC
S
Analog supply
IF gain control bit #2
Analog supply
21
PU
D_I
Power-up signal input
22
SIG
D_O
Data output
23
SC
D_O
Sample clock
VDIG
S
Digital supply
24
Notes:
2
Pin Description
1. Type: A_I = Analog input, A_O = Analog output, D_I = Digital input, D_O = Digital output, S = Supply, XS = External
supply
ATR0603 [Preliminary]
4950B–GPS–11/06
ATR0603 [Preliminary]
3. Functional Description
3.1
General Description
The ATR0603 GPS receiver IC has been especially designed for GPS applications in both
mobile phone and automotive applications. From this system point of view, it incorporates highest isolation between GPS and cellular bands, as well as very low power consumption.
The L1 input signal (fRF) is a direct sequence spread spectrum (DSSS) signal with a center frequency of: fRF = 1575.42 MHz.
The digital modulation scheme is bi-phase shift keying (BPSK) with a chip rate of 1.023 Mbps.
As the input signal power at the antenna is approximately –140 dBm, the desired signal is below
the thermal noise floor.
3.2
Startup Logic
The startup logic ensures reliable operation within the recommended operating conditions. The
external power control signal PU is passed through a Schmitt trigger input to eliminate voltage
ripple and prevent undesired behavior during startup and shutdown.
This block includes a switch to supply external circuits, for example, the TCXO. This switch is
controlled by the power control signal PU.
3.3
TCXO Interface
This receiver is designed for use with an external TCXO. The TCXO output signal is fed to a balanced input buffer.
The recommended reference frequency is: fTCXO = 16.367667 MHz.
Connecting the supply pin of the TCXO to the XSUP pin of ATR0603 allows for a power down of
the TCXO when the ATR0603 is shut off (see Section 3.2).
3.4
VCO/PLL
The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no
external components are required. The VCO combines very good phase noise behavior and
excellent spurious suppression. The relation between the reference frequency (fTCXO) and the
VCO center frequency (fVCO) is given by:
fVCO = fTCXO × 90 = 16.367667 MHz × 90 = 1473.09003 MHz.
3.5
RF Mixer/Image Filter
Combined with the antenna, an external LNA provides a first bandpass filtering of the signal. For
the LNA, Atmel®’s ATR0610 is recommended, due to its low noise figure, high linearity and low
power consumption. The output of the LNA drives a SAW filter, which provides image rejection
for the mixer and the required isolation of all GSM bands. The output of the SAW filter is fed into
a highly linear mixer with high conversion gain and excellent noise performance.
The IF frequency (fIF) is given by:
fIF = fRF – fVCO = 1575.42 MHz – 1473.09003 MHz = 102.32997 MHz.
3
4950B–GPS–11/06
3.6
IF Filter
The mixer directly drives an external LC bandpass filter via open collector outputs. In order to
provide highest selectivity and conversion gain, it is recommended to design the external filter,
according to the application proposal in chapter 10, as a 2-pole filter with a quality factor Q > 25.
3.7
IF Amplifier
The output of the IF filter drives an IF amplifier which is combined with additional low-pass filtering. The gain of this amplifier can be set to three different levels in order to optimally charge the
input of the following analog-to-digital converter for each application.
The gain is internally set to high gain mode but can be adjusted by using external pull-down
resistors at pin 18 (AMP1) and pin 19 (AMP2). If high gain mode is desired, pins 18 and 19 have
to be left floating (see Section 8. ”Electrical Characteristics” ).
3.8
A/D Converter
The analog-to-digital converter stage has a total resolution of 1 bit. It comprises a sub-sampling
unit, clocked by the reference frequency (fTCXO). The frequency spectrum of the digital output
signal (fOUT), present at the data output SIG, is then given by: fOUT = ⏐ fIF – fTCXO × n⏐ . The
selected sub-sampling factor (n = 6) leads to the designated digital output signal, with a center
frequency given by:
fOUT = ⏐ fIF – fTCXO × 6⏐ = ⏐ 102.32997 MHz – 16.367667 MHz × 6⏐ = 4.123968 MHz.
3.9
Clock and Data Driver
CMOS output drivers provide the output bit as well as the system clock to the baseband IC. The
amplitude of this signal strongly depends on the value for the digital supply voltage (see Section
8. ”Electrical Characteristics” on page 7).
4
ATR0603 [Preliminary]
4950B–GPS–11/06
ATR0603 [Preliminary]
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Value
Unit
Analog supply voltage
VCC
–0.3 to +3.7
V
Digital supply voltage
VDIG
–0.3 to +3.7
V
Vin
–0.3 to +3.7
V
Max. supply voltage difference: ∆(VDIG – VCC)
V∆DIG
0.5
V
Max. supply voltage difference: ∆(VPU – VCC)
Input voltage
V∆PU
0.5
V
Operating temperature
Top
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Symbol
Value
Unit
Rth
45
K/W
Symbol
Value
Unit
Analog supply voltage
VCC
2.6 to 3.6
V
Digital supply voltage
VDIG
1.6 to 3.6
V
Temperature range
Temp
–40 to +85
°C
5. Thermal Resistance
Parameters
Thermal Resistance
6. Operating Range
Parameters
Input frequency
Reference frequency
fRF
1575.42
MHz
fTCXO
16.3 to 16.4
MHz
7. ESD Characteristics
Parameters
Symbol
Used Norm
Value
Unit
ESD level HBM (Human Body Model)
VHBM
ESD-STM5.1-2001
JESD22-A114D 2006
AEC-Q100-002-Ref-D
4000
V
ESD level MM (Machine Model)
VMM
EIA/JESD22 A115 A
300
V
ESD level CDM (Charged Device Model)
VCDM
ESD-STM.5.3.1-1999
1000
V
5
4950B–GPS–11/06
8. Electrical Characteristics
Temperature = +25°C
Minimum/maximum limits are at +25°C ambient temperature, unless otherwise specified.
No.
1
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Common
1.1
Analog supply current
VCC = 3.6V,
VDIG = 1.6V,
VPU = 1.6V
7, 13,
20
IS
10.5
mA
A
1.2
Analog supply current
VCC = 2.6V,
VDIG = 1.6V,
VPU = 1.6V
7, 13,
20
IS
9
mA
A
1.3
Mixer core current
VCC = 3.6V,
VDIG = 1.6V,
VPU = 1.6V
14, 15,
16, 17
IBP
1.5
mA
A
1.4
Mixer core current
VCC = 2.6V,
VDIG = 1.6V,
VPU = 1.6V
14, 15,
16, 17
IBP
1.4
mA
A
1.5
VCC = 3.6V,
Digital supply current(1) VDIG = 3.3V,
VPU = 1.6V
24
IDIG
1.4
mA
A
1.6
VCC = 2.6V,
Digital supply current(1) VDIG = 1.6V,
VPU = 1.6V
24
IDIG
1.0
mA
A
1.7
Supply current in
power-down mode
7, 13,
14, 15,
16, 17,
20, 24
IPD
µA
A
1.8
Noise figure (SSB)
2
VPU = VPU,off
5
NFtot
8
dB
C
Mixer
2.1
Output frequency
fTCXO = 16.367667 MHz
14, 15
fIF
102.32997
MHz
A
2.2
Input impedance
(balanced)
fRF = 1575.42 MHz
10, 11
Z11
10 – j80
Ω
C
2.3
Conversion gain
Recommended IF filter
8
GMIX
20
dB
B
8
NFMIX
6.8
dB
C
18, 19
GIF0
28
dB
D
AMP1 = X ,
AMP2 = low
18, 19
GIF1
42
dB
D
2.4
3
3.1
Noise figure (SSB)
IF Amplifier
IF gain0
AMP1 = AMP2 = low
(2)
3.2
IF gain1
3.3
IF gain2
AMP1 = low, AMP2 = X
18, 19
GIF2
42
dB
D
3.4
IF gain3
AMP1 = AMP2 = X
18, 19
GIF3
56
dB
D
*) Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1. Capacitive load (CL = 10 pF) at pins 22, 23
2. X represents a pin left floating (internal pull up)
6
ATR0603 [Preliminary]
4950B–GPS–11/06
ATR0603 [Preliminary]
8. Electrical Characteristics (Continued)
Temperature = +25°C
Minimum/maximum limits are at +25°C ambient temperature, unless otherwise specified.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
16.367667
MHz
A
0.5
Vpp
D
4
Clock and Data Driver
4.1
Clock driver frequency
fTCXO = 16.367667 MHz
23
fCLK
4.2
Clock input level
fTCXO = 16.367667 MHz
3, 4
VTCXO
4.3
Clock output level, high Cload,max = 10 pF
23
VCLK,high
0.9 × VDIG
V
B
0.1
4.4
Clock output level, low
Cload.max = 10 pF
23
VCLK,low
0.1 × VDIG
V
B
4.5
Data output level, high
Cload,max = 10 pF
22
VData,high
0.9 × VDIG
V
B
4.6
Data output level, low
Cload,max = 10 pF
22
VData,low
0.1 × VDIG
V
B
5
Startup Logic
5.1
Voltage level power-on
21
VPU,on
5.2
Voltage level power-off
21
VPU,off
5.3
Voltage level at XSUP
6
VXSUP
Ixsup = 2 mA,
VPU = VPU,on
1.4
0.8
(VCC – 0.1)
V
A
V
A
V
A
*) Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1. Capacitive load (CL = 10 pF) at pins 22, 23
2. X represents a pin left floating (internal pull up)
9. Output Interface
Figure 9-1.
Data Output SIG Is Valid with Rising Edge of Sample Clock SC
SIG
SC
T = 1/16.367667 MHz
7
4950B–GPS–11/06
10. Application Circuit
Figure 10-1. Application Example
VCC
68Ω
PU
220 nH
220 nH
21
14
15
16
17
18
PU
BP
NBP
BPI
NBPI
AMP1
19
AMP2
Startup
logic
GND
ATR0603
10 nF
1.3 pF
11
7
VCC
13
VCC
20
VDIG
24
SIG
22
100 nF
A
5.6 nH
1.5 pF
ATR0610
SAW
B4060
1.3 pF
10
100 nF
RF
4.7 nH
100 nF
VCC
PU
LNA section (opt.)
VCC
220 nH
4.3 pF
4.3 pF
47 pF
220 nH
VDIG
VCC
10 nF
Data out
D
NRF
6
XSUP
4
XIN
VCO
PLL
TCXO
SC
23
Sample clock
3
XREF
TEST
12
Note:
8
MO
8
See also the recommended IF filter layout, shown in Figure 10-2 on page 9.
ATR0603 [Preliminary]
4950B–GPS–11/06
ATR0603 [Preliminary]
Figure 10-2. Recommended IF Filter: Layout versus Schematic
Lc
NBP
BPI
Cb
BP
Ca
14
15
16
NBPI
14 15 16 17
17
Ld
Ca
Cb
B
Lc
Le
Ld
A
Note:
Le
Lf
Lf
VCC
Mutual inductance between the four inductors Lc to Lf plays an important role in the IF filter characteristics. In any design, the layout arrangement shown in Figure 10-2 should be followed as
closely as possible. Measurements: A = 2.8 mm; B = 1.4 mm
Lc to Lf: Wire-wound SMD inductors, size 0603 (see Table 11-1 on page 11)
Table 10-1.
Specifications of Recommended TCXO (Rakon; IT5325BE 16.367667 MHz)
Parameter
Comment
Nominal frequency
Nominal frequency referenced to 25°C
Frequency deviation
Within operating temperature range
Temperature range
Operating temperature range
Output waveform
DC-coupled clipped sine wave
Output voltage (peak to peak) At minimum supply voltage
Current
At maximum supply voltage
Output load capacitance
Tolerable load capacitance
Min.
Nominal
Max.
16.367667
–40
±2.5
ppm
85
°C
0.8
9
Unit
MHz
V
1.5
mA
11
pF
9
4950B–GPS–11/06
11. Demonstration Board
Figure 11-1. Schematic of Demonstration Board (Without LNA Section)
C34
+
+
C35
J5
VCC
2
3
VDIG
VCC1
R1
7
C1
VCC3
VCC4
13
20
C7
J1
L4
1
2
3
L3
L2
L1
1
2
3
C3
C4
14
15
16
17
21
BP
NBP
BPI
NBPI
PU
VCC2
24
C23
J4
R2
Startup
logic
C2
12
TEST
MO
8
C35
P2
C12
FI1
P1
6
IN
11
RF
2
OUT
A
L7
5
NIN
NOUT
C31
10
1
22
AMP1
18
AMP2
19
SC
23
1
2
J3
1
C18
XO2
SIG
D
4
3
10
NRF
6
XSUP
3
XIN
4
XREF
VCO/PLL
1473.09003 MHz
2
1
2
J2
ATR0603 [Preliminary]
4950B–GPS–11/06
ATR0603 [Preliminary]
Table 11-1.
Bill of Materials for the Demonstration Board (Without LNA Section)
Qty
Value
2
Parts
Tolerance
Voltage
Material
J2, J3
3
Manufacturer
Manufacturer
Order Code
Molex®
90120-0762
J1, J4, J5
Molex
90120-0763
1
0
R2
Vishay®
CRCW0402000Z
2
1p3
C12, C18
Taiyo Yuden®
EVK105CH1R3BW
2
4p3 ±0p1
C3, C4
0.1 pF
16V
0.1 pF
C0G
Murata
®
®
1
5n6 2% Multilayer
L7
2%
2
10µ
C5, C34
20%
16V
1
10n
C1
5%
16V
1
68
R1
5%
4
100n
C2, C7,
C23, C31
20%
16V
1
100p
C35
5%
25V
1
142-0711-821
P1
4
220n 2%
L1, L2, L3,
L4
2%
C0G
GRM1555C1H4R3GZ01B
Würth Elektronik
744784056G
Vishay
293D106X0016B2
Vishay
VJ0402Y103JXJ
Vishay
CRCW0402680J
Y5V
Vishay
VJ0402V104MXJ
C0G
Vishay
VJ0402A101JXXA.
Johnson
Components™
142-0711-821
X7R
Coilcraft®
alternatively
Würth Elektronik
0603CS-R22XGB
744761222G
1
ATR0603-PFQW
IC1
Atmel
ATR0603
1
B4060
FI1
Epcos®
B39162-B4060-U810
1
IT5325BE
16.367667 MHz
XO2
Rakon
IT5325BE Ref. no. 34365
1
R125426
P2
Radiall®
125426
2.0 ppm
Figure 11-2. Photo of Evaluation Board (Including LNA Section)
11
4950B–GPS–11/06
12. Recommended Footprint (QFN24 - 4 mm × 4 mm)
Figure 12-1. Recommended Footprint
0.30
0.4 × 0.4 (16 ×)
solder stop opening
∅ 0.25 (9 ×)
2.6 × 2.6
metal pad
Pads 0.8 × 0.28 (24 ×)
solder stop overlap 0.05
0.50
All dimensions in mm
Scale 10 : 1
12
ATR0603 [Preliminary]
4950B–GPS–11/06
ATR0603 [Preliminary]
13. Ordering Information
Extended Type Number
Package
Remarks
ATR0603-PFQW
QFN24 - 4 mm × 4 mm
Taped and reeled
14. Package Information
Package: QFN_ 4 x 4_24L
Exposed pad 2.6 x 2.6
Dimensions in mm
Bottom
Not indicated tolerances ±0.05
2.6±0.15
24
Top
19
24
1
18
1
6
13
6
Pin1 identification
4
Z
0.2
0.5 nom.
0.4±0.1
technical drawings
according to DIN
specifications
Drawing-No.: 6.543-5123.01-4
Issue: 1; 28.11.05
7
2.5
0.9±0.1
Z 10:1
12
0.23±0.07
13
4950B–GPS–11/06
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4950B–GPS–11/06