SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 D Zero Reading for 0-V Input D Precision Null Detection With True Polarity DW OR N PACKAGE (TOP VIEW) at Zero VCC − REF ANLG COMMON INT OUT AUTO ZERO BUFF OUT Cref − Cref + IN − IN + VCC + D5 B1 B2 D 1-pA Typical Input Current D True Differential Input D Multiplexed Binary-Coded-Decimal (BCD) D D D D D D Output Low Rollover Error: ± 1 Count Max Control Signals Allow Interfacing With UARTs or Microprocessors Autoranging Capability With Over- and Under-Range Signals TTL-Compatible Outputs Second Source to Teledyne TSC7135, Intersil ICL7135, Maxim ICL7135, and Siliconix Si7135 CMOS Technology 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 UNDER RANGE OVER RANGE STROBE RUN/HOLD DGTL GND POLARITY CLK BUSY D1 D2 D3 D4 B8 B4 DESCRIPTION The ICL7135C and TLC7135C converters are manufactured with Texas Instruments highly efficient CMOS technology. These 4 1/2-digit, dual-slope-integrating, analog-to-digital converters (ADCs) are designed to provide interfaces to both a microprocessor and a visual display. The digit-drive outputs D1 through D4 and multiplexed binary-coded-decimal outputs B1, B2, B4, and B8 provide an interface for LED or LCD decoder/drivers as well as microprocessors. The ICL7135C and TLC7135C offer 50-ppm (one part in 20,000) resolution with a maximum linearity error of one count. The zero error is less than 10 µV and zero drift is less than 0.5 µV/°C. Source-impedance errors are minimized by low input current (less than 10 pA). Rollover error is limited to ± 1 count. The BUSY, STROBE, RUN/HOLD, OVER RANGE, and UNDER RANGE control signals support microprocessor-based measurement systems. The control signals also can support remote data acquisition systems with data transfer through universal asynchronous receiver transmitters (UARTs). The ICL7135C and TLC7135C are characterized for operation from 0°C to 70°C. AVAILABLE OPTIONS PACKAGE TA PLASTIC DIP (N) 0°C to 70°C SMALL OUTLINE (DW) ICL7135CN TLC7135CN TLC7135CDW Caution. These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam during storage or handlilng to prevent electrostatic damage to the MOS gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999−2003, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 FUNCTIONAL BLOCK DIAGRAM DIGITAL SECTION POLARITY From Analog Section 23 20 Polarity Flip-Flop Latch 19 18 17 Zero Cross Detect CLK RUN/HOLD OVER RANGE UNDER RANGE STROBE BUSY DGTL GND 22 Latch Control Logic 12 D1 (LSD) D2 D3 Digit Drive Output D4 D5 (MSD) Counters Latch Multiplexer 25 27 28 13 Latch 26 14 21 24 15 16 Latch B1 (LSB) B2 B4 Binary Coded Decimal Output B8 (MSB) ANALOG SECTION RINT Cref 8 Cref + Cref − 7 BUFF OUT CAZ 5 6 Buffer − Input High − A/Z INT IN + 10 DE(−) DE(+) Z/I A/Z A/Z DE(+) ANLG COMMON IN − 2 DE(−) 3 9 INT Input Low A/Z, DE( ±), Z/I POST OFFICE BOX 655303 Comparator + + 2 4 INT OUT + REF CINT Integrator − A/Z AUTO ZERO • DALLAS, TEXAS 75265 To Digital Section SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT Supply voltage (VCC+ with respect to VCC −) 15 V Analog input voltage (IN − or IN +) Reference voltage range VCC − to VCC+ VCC − to VCC+ Clock input voltage range 0 V to VCC+ Operating free-air temperature range, TA 0°C to 70°C Storage temperature range, Tstg −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package 260°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX Supply voltage, VCC+ 4 5 6 V Supply voltage, VCC− −3 −5 −8 V Reference voltage, Vref UNIT 1 High-level input voltage, CLK, RUN/HOLD, VIH V 2.8 V Low-level input voltage, CLK, RUN/HOLD, VIL 0.8 Differential input voltage, VID VCC − +1 1.2 Maximum operating frequency, fclock (see Note 1) Operating free-air temperature range, TA NOTE 1: Clock frequency range extends down to 0 Hz. V VCC+ − 0.5 2 V MHz 0 °C 70 ELECTRICAL CHARACTERISTICS VCC + = 5 V, VCC − = 5 V, Vref = 1 V, fclock = 120 kHz, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS D1-D5, B1,B2,B4,B8 IO = − 1 mA IO = − 10 µA MIN TYP MAX 2.4 5 4.9 5 UNIT VOH High-level output voltage VOL VON(PP) Low-level output voltage αVO IIH Zero-reading temperature coefficient of output voltage VID = 0, VI = 5 V, 0°C ≤ TA ≤ 70°C 0.5 2 High-level input current 0°C ≤ TA ≤ 70°C 0.1 10 µA IIL Low-level input current VI = 0 V, 0°C ≤ TA ≤ 70°C −0.02 −0.1 mA Input leakage current, IN − and IN + VID = 0 TA = 25°C 0°C ≤ TA ≤ 70°C 1 II Positive supply current fclock = 0 TA = 25°C 0°C ≤ TA ≤ 70°C 1 ICC + Negative supply current fclock = 0 TA = 25°C 0°C ≤ TA ≤ 70°C −0.8 ICC − Other outputs Peak-to-peak output noise voltage (see Note 1) IO = 1.6 mA VID = 0, Full scale = 2 V 0.4 V V µV 15 µV/°C 10 250 pA 2 3 mA −2 −3 mA Cpd Power dissipation capacitance See Note 2 40 pF NOTES: 1. This is the peak-to-peak value that is not exceeded 95% of the time. 2. Factor-relating clock frequency to increase in supply current. At VCC+ = 5 V, ICC+ = ICC+(fclock = 0) + Cpd × 5 V × fclock POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 OPERATING CHARACTERISTICS VCC + = 5 V, VCC − = 5 V, Vref = 1 V, fclock = 120 kHz, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS αFS EL Full-scale temperature coefficient (see Note 1) Linearity error VID = 2 V, 0°C ≤ TA ≤ 70°C −2 V ≤ VID ≤ 2 V ED EFS Differential linearity error (see Note 2) −2 V ≤ VID ≤ 2 V ± Full-scale symmetry error (rollover error) (see Note 3) VID = ± 2 V Display reading with 0-V input VID = 0, Display reading in ratiometric operation VID = Vref, TA = 25°C 0°C ≤ TA ≤ 70°C MIN TYP MAX 5 0.5 LSB 0.5 −0.0000 1 ± 0.0000 0.0000 0.9998 0.9999 1.0000 0.9995 0.9999 1.0005 NOTES: 1. This parameter is measured with an external reference having a temperature coefficient of less than 0.01 ppm/°C. 2. The magnitude of the difference between the worst case step of adjacent counts and the ideal step. 3. Rollover error is the difference between the absolute values of the conversion for 2 V and − 2 V. TIMING DIAGRAMS End of Conversion BUSY† B1 −B8 D5 D4 D3 D2 D1 D5 STROBE† 200 Counts D5 200 Counts 201 Counts D4 200 Counts D3 200 Counts D2 200 Counts D1 200 Counts † Delay between BUSY going low and the first STROBE pulse is dependent upon the analog input. Figure 1 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ppm/°C count 0.01 0°C ≤ TA ≤ 70°C UNIT count Digital Reading Digital Reading SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 Digital Scan for OVER-RANGE D5 D4 D3 D2 D1 1000 Counts Figure 2 Integrator Output AUTO ZERO 10,001 Counts Signal Int 10,000 Counts De-Integrate 20,001 Counts Max Full Measurement Cycle 40,002 Counts BUSY OVER RANGE When Applicable UNDER RANGE When Applicable Figure 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 STROBE AUTO ZERO Digit Scan for OVER RANGE Signal Integrate Deintegrate† D5† D4 D3 D2 D1 † First D5 of AUTO ZERO and deintegrate is one count longer. Figure 4 PRINCIPLES OF OPERATION A measurement cycle for the ICL7135C and TLC7135C consists of the following four phases. 1. Auto-Zero Phase. The internal IN + and IN− inputs are disconnected from the terminals and internally connected to ANLG COMMON. The reference capacitor is charged to the reference voltage. The system is configured in a closed loop and the auto-zero capacitor is charged to compensate for offset voltages in the buffer amplifier, integrator, and comparator. The auto-zero accuracy is limited only by the system noise, and the overall offset, as referred to the input, is less than 10 µV. 2. Signal Integrate Phase. The auto-zero loop is opened and the internal IN + and IN − inputs are connected to the external terminals. The differential voltage between these inputs is integrated for a fixed period of time. When the input signal has no return with respect to the converter power supply, IN− can be tied to ANLG COMMON to establish the correct common-mode voltage. Upon completion of this phase, the polarity of the input signal is recorded. 3. Deintegrate Phase. The reference is used to perform the deintegrate task. The internal IN− is internally connected to ANLG COMMON and IN+ is connected across the previously charged reference capacitor. The recorded polarity of the input signal ensures that the capacitor is connected with the correct polarity so that the integrator output polarity returns to zero. The time required for the output to return to zero is proportional to the amplitude of the input signal. The return time is displayed as a digital reading and is determined by the equation 10,000 × (VID/Vref). The maximum or full-scale conversion occurs when VID is two times Vref. 4. Zero Integrator Phase. The internal IN− is connected to ANLG COMMON. The system is configured in a closed loop to cause the integrator output to return to zero. Typically, this phase requires 100 to 200 clock pulses. However, after an over-range conversion, 6200 pulses are required. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 DESCRIPTION OF ANALOG CIRCUITS Input Signal Range The common mode range of the input amplifier extends from 1 V above the negative supply to 1 V below the positive supply. Within this range, the common-mode rejection ratio (CMRR) is typically 86 dB. Both differential and common-mode voltages cause the integrator output to swing. Therefore, care must be exercised to ensure that the integrator output does not become saturated. Analog Common Analog common (ANLG COMMON) is connected to the internal IN− during the auto-zero, deintegrate, and zero integrator phases. When IN− is connected to a voltage that is different from analog common during the signal integrate phase, the resulting common-mode voltage is rejected by the amplifier. However, in most applications, IN− is set at a known fixed voltage (i.e., power supply common for instance). In this application, analog common should be tied to the same point, thus removing the common-mode voltage from the converter. Removing the common-mode voltage in this manner slightly increases conversion accuracy. Reference The reference voltage is positive with respect to analog common. The accuracy of the conversion result is dependent upon the quality of the reference. Therefore, to obtain a high accuracy conversion, a high quality reference should be used. DESCRIPTION OF DIGITAL CIRCUITS RUN/HOLD Input When RUN/HOLD is high or open, the device continuously performs measurement cycles every 40,002 clock pulses. When this input is taken low, the integrated circuit continues to perform the ongoing measurement cycle and then hold the conversion reading for as long as the terminal is held low. When the terminal is held low after completion of a measurement cycle, a short positive pulse (greater than 300 ns) initiates a new measurement cycle. When this positive pulse occurs before the completion of a measurement cycle, it will not be recognized. The first STROBE pulse, which occurs 101 counts after the end of a measurement cycle, is an indication of the completion of a measurement cycle. Thus, the positive pulse could be used to trigger the start of a new measurement after the first STROBE pulse. STROBE Input Negative going pulses from this input transfer the BCD conversion data to external latches, UARTs, or microprocessors. At the end of the measurement cycle, STROBE goes high and remains high for 201 counts. The most significant digit (MSD) BCD bits are placed on the BCD terminals. After the first 101 counts, halfway through the duration of output D1−D5 going high, the STROBE terminal goes low for 1/2 clock pulse width. The placement of the STROBE pulse at the midpoint of the D5 high pulse allows the information to be latched into an external device on either a low-level or an edge. Such placement of the STROBE pulse also ensures that the BCD bits for the second MSD are not yet competing for the BCD lines and latching of the correct bits is ensured. The above process is repeated for the second MSD and the D4 output. Similarly, the process is repeated through the least significant digit (LSD). Subsequently, inputs D5 through D1 and the BCD lines continue scanning without the inclusion of STROBE pulses. This subsequent continuous scanning causes the conversion results to be continuously displayed. Such subsequent scanning does not occur when an over-range condition occurs. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 BUSY Output The BUSY output goes high at the beginning of the signal integrate phase. BUSY remains high until the first clock pulse after zero crossing or at the end of the measurement cycle when an over-range condition occurs. It is possible to use the BUSY terminal to serially transmit the conversion result. Serial transmission can be accomplished by ANDing the BUSY and CLOCK signals and transmitting the ANDed output. The transmitted output consists of 10,001 clock pulses, which occur during the signal integrate phase, and the number of clock pulses that occur during the deintegrate phase. The conversion result can be obtained by subtracting 10,001 from the total number of clock pulses. OVER-RANGE Output When an over-range condition occurs, this terminal goes high after the BUSY signal goes low at the end of the measurement cycle. As previously noted, the BUSY signal remains high until the end of the measurement cycle when an over-range condition occurs. The OVER RANGE output goes high at the end of BUSY and goes low at the beginning of the deintegrate phase in the next measurement cycle. UNDER-RANGE Output At the end of the BUSY signal, this terminal goes high when the conversion result is less than or equal to 9% (count of 1800) of the full-scale range. The UNDER-RANGE output is brought low at the beginning of the signal integrate phase of the next measurement cycle. POLARITY Output The POLARITY output is high for a positive input signal and updates at the beginning of each deintegrate phase. The polarity output is valid for all inputs including ± 0 and OVER RANGE signals. Digit-Drive (D1, D2, D4 and D5) Outputs Each digit-drive output (D1 through D5) sequentially goes high for 200 clock pulses. This sequential process is continuous unless an over-range occurs. When an over-range occurs, all of the digit-drive outputs are blanked from the end of the strobe sequence until the beginning of the deintegrate phase (when the sequential digit-drive activation begins again). The blanking activity during an over-range condition can cause the display to flash and indicate the over-range condition. BCD Outputs The BCD bits (B1, B2, B4 and B8) for a given digit are sequentially activated on these outputs. Simultaneously, the appropriate digit-drive line for the given digit is activated. System Aspects Integrating Resistor The value of the integrating resistor (RINT) is determined by the full-scale input voltage and the output current of the integrating amplifier. The integrating amplifier can supply 20 µA of current with negligible nonlinearity. The equation for determining the value of this resistor is: R INT + Full Scale Voltage I INT Integrating amplifier current, IINT, from 5 to 40 µA yields good results. However, the nominal and recommended current is 20 µA. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 Integrating Capacitor The product of the integrating resistor and capacitor should be selected to give the maximum voltage swing without causing the integrating amplifier output to saturate and get too close to the power supply voltages. When the amplifier output is within 0.3 V of either supply, saturation occurs. With ± 5-V supplies and ANLG COMMON connected to ground, the designer should design for a ± 3.5-V to ± 4-V integrating amplifier swing. A nominal capacitor value is 0.47 µF. The equation for determining the value of the integrating capacitor (CINT) is: C INT + 10, 000 Clock Period I INT Integrator Output Voltage Swing where IINT is nominally 20 µA. Capacitors with large tolerances and high dielectric absorption can induce conversion inaccuracies. A capacitor that is too small could cause the integrating amplifier to saturate. High dielectric absorption causes the effective capacitor value to be different during the signal integrate and deintegrate phases. Polypropylene capacitors have very low dielectric absorption. Polystyrene and polycarbonate capacitors have higher dielectric absorption, but also work well. Auto-Zero and Reference Capacitor Large capacitors tend to reduce noise in the system. Dielectric absorption is unimportant except during power up or overload recovery. Typical values are 1 µF. Reference Voltage For high-accuracy absolute measurements, a high quality reference should be used. Rollover Resistor and Diode The ICL7135C and TLC7135C have a small rollover error; however, it can be corrected. The correction is to connect the cathode of any silicon diode to INT OUT and the anode to a resistor. The other end of the resistor is connected to ANLG COMMON or ground. For the recommended operating conditions, the resistor value is 100 kΩ. This value may be changed to correct any rollover error that has not been corrected. In many noncritical applications the resistor and diode are not needed. Maximum Clock Frequency For most dual-slope A/D converters, the maximum conversion rate is limited by the frequency response of the comparator. In this circuit, the comparator follows the integrator ramp with a 3-µs delay. Therefore, with a 160-kHz clock frequency (6-µs period), half of the first reference integrate clock period is lost in delay. Hence, the meter reading changes from 0 to 1 with a 50-µV input, 1 to 2 with a 150-µV input, 2 to 3 with a 250-µV input, etc. This transition at midpoint is desirable; however, when the clock frequency is increased appreciably above 160 kHz, the instrument flashes 1 on noise peaks even when the input is shorted. The above transition points assume a 2-V input range is equivalent to 20,000 clock cycles. When the input signal is always of one polarity, comparator delay need not be a limitation. Clock rates of 1 MHz are possible since nonlinearity and noise do not increase substantially with frequency. For a fixed clock frequency, the extra count or counts caused by comparator delay are a constant and can be subtracted out digitally. For signals with both polarities, the clock frequency can be extended above 160 kHz without error by using a low value resistor in series with the integrating capacitor. This resistor causes the integrator to jump slightly towards the zero-crossing level at the beginning of the deintegrate phase, and thus compensates for the comparator delay. This series resistor should be 10 Ω to 50 Ω. This approach allows clock frequencies up to 480 kHz. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 Minimum Clock Frequency The minimum clock frequency limitations result from capacitor leakage from the auto-zero and reference capacitors. Measurement cycles as high as 10 µs are not influenced by leakage error. Rejection of 50-Hz or 60-Hz Pickup To maximize the rejection of 50-Hz or 60-Hz pickup, the clock frequency should be chosen so that an integral multiple of 50-Hz or 60-Hz periods occur during the signal integrate phase. To achieve rejection of these signals, some clock frequencies that can be used are: 50 Hz: 250, 166.66, 125, 100 kHz, etc. 60 Hz: 300, 200, 150, 120, 100, 40, 33.33 kHz, etc. Zero-Crossing Flip-Flop This flip-flop interrogates the comparator’s zero-crossing status. The interrogation is performed after the previous clock cycle and the positive half of the ongoing clock cycle has occurred, so any comparator transients that result from the clock pulses do not affect the detection of a zero-crossing. This procedure delays the zero-crossing detection by one clock cycle. To eliminate the inaccuracy, which is caused by this delay, the counter is disabled for one clock cycle at the beginning of the deintegrate phase. Therefore, when the zero-crossing is detected one clock cycle later than the zero-crossing actually occurs, the correct number of counts is displayed. Noise The peak-to-peak noise around zero is approximately 15 µV (peak-to-peak value not exceeded 95% of the time). Near full scale, this value increases to approximately 30 µV. Much of the noise originates in the auto-zero loop, and is proportional to the ratio of the input signal to the reference. Analog and Digital Grounds For high-accuracy applications, ground loops must be avoided. Return currents from digital circuits must not be sent to the analog ground line. Power Supplies The ICL7135C and TLC7135C are designed to work with ± 5-V power supplies. However, 5-V operation is possible when the input signal does not vary more than ± 1.5 V from midsupply. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 27-Apr-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TLC7135CDW ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7135C TLC7135CDWG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7135C TLC7135CDWR ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7135C TLC7135CDWRG4 ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7135C TLC7135CN LIFEBUY PDIP N 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type ICL7135CN TLC7135CN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 27-Apr-2016 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC7135CDWR Package Package Pins Type Drawing SOIC DW 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 32.4 Pack Materials-Page 1 11.35 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 18.67 3.1 16.0 32.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC7135CDWR SOIC DW 28 1000 367.0 367.0 55.0 Pack Materials-Page 2 MECHANICAL DATA MPDI008 – OCTOBER 1994 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 24 PIN SHOWN A 24 13 0.560 (14,22) 0.520 (13,21) 1 12 0.060 (1,52) TYP 0.200 (5,08) MAX 0.610 (15,49) 0.590 (14,99) 0.020 (0,51) MIN Seating Plane 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.125 (3,18) MIN 0.010 (0,25) M PINS ** 0°– 15° 0.010 (0,25) NOM 24 28 32 40 48 52 A MAX 1.270 (32,26) 1.450 (36,83) 1.650 (41,91) 2.090 (53,09) 2.450 (62,23) 2.650 (67,31) A MIN 1.230 (31,24) 1.410 (35,81) 1.610 (40,89) 2.040 (51,82) 2.390 (60,71) 2.590 (65,79) DIM 4040053 / B 04/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MS-011 Falls within JEDEC MS-015 (32 pin only) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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