ON NCV7383DB0R2G Flexray bus driver Datasheet

NCV7383
FlexRay] Bus Driver
NCV7383 is a single−channel FlexRay bus driver compliant with
the FlexRay Electrical Physical Layer Specification Rev. 3.0.1,
capable of communicating at speeds of up to 10 Mbit/s. It provides
differential transmit and receive capability between a wired FlexRay
communication medium on one side and a protocol controller and
a host on the other side.
NCV7383 mode control functionality is optimized for nodes
without the need of extended power management provided by
transceivers with permanent connection to the car battery as is on
NCV7381. NCV7383 is primarily intended for nodes switched off by
ignition.
It offers excellent Electromagnetic compatibility (EMC) and
Electrostatic discharge (ESD) performance.
KEY FEATURES
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MARKING
DIAGRAM
14
14
NV73
83−0
ALYWG
1
TSSOP−14
CASE 948G
1
General
• Compliant with FlexRay Electrical Physical Layer Specification Rev 3.0.1
• FlexRay Transmitter and Receiver in Normal−Power Modes for
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Communication up to 10 Mbit/s
Support of 60 ns Bit Time
FlexRay Low−Power Mode Receiver for Remote Wakeup Detection
Excellent Electromagnetic Susceptibility (EMS) Level Over Full
Frequency Range. Very Low Electromagnetic Emissions (EME)
Bus Pins Protected Against >10 kV System ESD Pulses
Safe Behavior Under Missing Supply or No Supply Conditions
Interface Pins for a Protocol Controller and a Host (TxD, RxD,
TxEN, STBN, BGE, ERRN, CSN, SCK, SDO)
Supply Pins VCC, VIO with Independent Voltage Ramp Up:
♦ VCC Supply Parametrical Range from 4.75 V to 5.25 V
♦ VIO Supply Parametrical Range from 2.3 V to 5.25 V
TxEN Timeout and BGE Feedback
Two Error Indication Modes
♦ Track mode − Error Signaling on ERRN Pin
♦ Latched mode − Status Register accessible via SPI
Compatible with 14 V and 28 V Systems
Operating Ambient Temperature −40°C to +125°C (TAMB_Class1)
Junction Temperature Monitoring
TSSOP−14 Package
These are Pb−Free Devices
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
VIO
1
VCC
BP
TxD
TxEN
BM
RxD
GND
BGE
ERRN
STBN
CSN
SCK
SDO
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 20 of this data sheet.
FlexRay Functional Classes
• Bus Driver − Bus Guardian Interface
• Bus Driver Logic Level Adaptation
• Bus Driver Remote Wakeup
Quality
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
© Semiconductor Components Industries, LLC, 2013
September, 2013 − Rev. 0
1
Publication Order Number:
NCV7383/D
NCV7383
BLOCK DIAGRAM
VIO
VCC
Voltage
Monitoring
Thermal Shutdown
TxD
CC
Module
TxEN
BP
Transmitter
RxD
BM
BGE
Module
BGE
STBN
Host
Module
ERRN
CONTROL
Bus Error
Detection
LOGIC
Normal mode/
Low−power mode
Receiver
CSN
SPI
Module
SCK
Wakeup
Detection
SDO
NCV7383
GND
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin
Number
Pin
Name
Pin Type
Pin Function
1
VIO
supply
Supply voltage for digital pins level adaptation
2
TxD
digital input, internal PD
Data to be transmitted
3
TxEN
digital input, internal PU
Transmitter enable input; when High, transmitter disabled
4
RxD
digital output
Receive data output
5
BGE
digital input, internal PD
Bus guardian enable input; when Low, transmitter disabled
6
STBN
digital input, internal PD
Mode control input
7
SCK
digital input, internal PU
SPI clock input
8
SDO
digital output
SPI data output
9
CSN
digital input, internal PU or PD
Chip select input, active Low
10
ERRN
digital output
Bus Driver error condition indication
11
GND
ground
Ground connection
12
BM
high−voltage analog input/output
Bus line minus
13
BP
high−voltage analog input/output
Bus line plus
14
VCC
supply
Bus driver core supply voltage; 5V nominal
Notes:
PU means Pull−up
PD means Pull−down
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NCV7383
APPLICATION INFORMATION
ECU
OUT
CVIO
OUT
IN
VIO reg.
VBAT
IN
VCC reg.
CVCC
FlexRay
Communication
Controller
TxEN
RxD
Bus guardian
BGE
STBN
SCK
Host
14
2
13
3
12
4
5
11
10
6
9
7
8
VCC
BP
CMC
BP
BM
BM
GND
RBUS2
TxD
1
RBUS1
VIO
NCV7383
MCU + CC + BG
ERRN
CBUS
CSN
SDO
SPI
GND
Figure 2. Application Diagram
Table 2. RECOMMENDED EXTERNAL COMPONENTS FOR THE APPLICATION DIAGRAM
Component
Function
Min
Typ
Max
Unit
Note
CVCC
Decoupling capacitor on VCC supply line, ceramic
100
nF
CVIO
Decoupling capacitor on VIO supply line, ceramic
100
nF
RBUS1
Bus termination resistor
47.5
W
(Note 1)
RBUS2
Bus termination resistor
47.5
W
(Note 1)
CBUS
Common−mode stabilizing capacitor, ceramic
4.7
nF
(Note 2)
CMC
Common−mode choke
100
mH
1. Tolerance ±1%, type 0805. The value RBUS1+RBUS2 should match the nominal cable impedance.
2. Tolerance ±20%, type 0805
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NCV7383
FUNCTIONAL DESCRIPTION
Operating Modes
The operating mode selected is a function of the host
signal STBN, the state of the supply voltages and the wakeup
detection. As long as both supplies (VCC and VIO) remain
above their respective under−voltage detection levels, the
logical control by STBN pin shown in Figure 3 applies.
Influence of the power−supplies and of the wakeup
detection on the operating modes is described in subsequent
paragraphs.
NCV7383 can switch between two operating modes
depicted in Figure 3. In Normal mode, the chip
interconnects a FlexRay communication controller with the
bus medium for full−speed communication. This mode is
also referred to as normal−power mode.
In Standby mode, the communication is suspended and
the power consumption is substantially reduced. A wakeup
on the bus can be detected and signaled to the host. The
Standby mode is referred to as low−power mode.
Unsupplied
Power cons.: Low
uVCC < uVCC_PORL
uVCC > uVCC_PORH
Standby mode
Transmitter: off
Receiver: wakeup−detection
RxD: Wakeup flag
SPI: ready
Normal mode
STBN = L
VCC or VIOUV detected
STBN = H (no UV) or
recovery from all UVs (STBN = H)
Power cons.: low
Transmitter: on
Receiver: on
RxD: Bus state
SPI: ready
Power cons.: normal
Figure 3. State Diagram
Normal
Mode
Standby
Mode
Normal
Mode
Error Flag
Wake Flag
Error Flag
STBN
ERRN
dBDModeChange
dBDModeChange
Figure 4. Timing Diagram of Operating Modes Control by the STBN Pin
Power Supplies and Power Supply Monitoring
digital signal levels. Both supplies should be properly
decoupled by filtering capacitors − see Figure 2 and Table 2.
VIO supply voltage can be applied prior to VCC during
Power−up event, however the NCV7383 is not considered
NCV7383 is supplied by two pins. VCC is the main 5 V
supply powering NCV7383 and the FlexRay bus driver core.
VIO supply serves to adapt the logical levels of NCV7383 to
the host and/or the FlexRay communication controller
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NCV7383
supplied until VCC supply voltage is above uVCC_PORH
threshold (VCC > uVCC_PORH ) − See Table 3.
Both supplies are monitored by under−voltage detectors
with individual thresholds and filtering times both for
under−voltage detection and recovery − see Table 15.
This will reduce the power dissipation and decrease the
junction temperature.
The transmitter is enabled as soon as the Thermal
Shutdown flag is cleared. This requires the junction
temperature falling below the Thermal Shutdown level and
TxEN pin being set to High in Normal mode.
Junction Temperature Monitoring
In order to protect the NCV7383 from being damaged in
case of thermal event, a junction temperature monitoring is
implemented. High ambient temperature together with the
device high power dissipation can lead to junction
temperature reaching a critical temperature. Under certain
failure conditions (e.g. bus pin shorted to the supply voltage
during the transmitter active state), the device power
dissipation can be rapidly increased even though the
absolute short current is limited. If the junction temperature
is higher than TJSD (typically 165°C) in Normal mode,
Thermal Shutdown flag is set and the transmitter is disabled.
Logic Level Adaptation
Level shift input VIO is used to apply a reference voltage
uVDIG = uVIO to all digital inputs and outputs in order to
adapt the logical levels of NCV7383 to the host and/or the
FlexRay communication controller digital signal levels.
Internal Flags
The NCV7383 control logic uses a number of internal
flags (i.e. one−bit memories) reflecting important
conditions or events. Table 3 summarizes the individual
flags and the conditions that lead to a set or reset of the flags.
Table 3. INTERNAL FLAGS
Flag
Set Condition
Reset Condition
Comment
Remote
Wakeup
VCC Under−voltage flag is not set
and
Remote Wakeup is detected in Standby
mode
Normal mode is entered
Mode
Normal mode is entered
Normal mode is left
Transmitter
Ready
All of the following terms are valid:
The bus driver is in Normal mode
TxEN Timeout flag is not set
BGE is High
Thermal Shutdown flag is not set
Any of the following terms is valid:
The bus driver is not in Normal mode
TxEN Timeout flag is set
BGE is Low
Thermal Shutdown flag is set
Power−on
VCC power supply level becomes sufficient
for the operation of the control logic
Normal mode is entered
Bus Error
Transmitter is enabled
and
Data on bus are different from TxD signal
(sampled after each TXD edge)
(Transmitter is enabled
and
Data on bus are identical to TxD signal)
or
TxEN is set High or Normal mode is left
The bus error flag has no
influence on the bus driver
function
Thermal
Shutdown
Junction temperature is higher than Tjsd
(typ. 165°C) in a Normal mode
Junction temperature is below Tjsd in
a Normal mode and TxEN is High
or
Normal mode is left
The transmitter is disabled
as long as the thermal
shutdown flag is set
TxEN Timeout
TxEN is Low for longer than dBDTxActiveMax (typ. 1.5 ms) in a Normal mode
TxEN is High
or
Normal mode is left
The transmitter is disabled
as long as the timeout flag
is set
VCC
Under−voltage
VCC is below the under−voltage threshold
for longer than dBDUVVCC
VCC is above the under−voltage threshold
for longer than dBDRVCC
Standby mode is forced
as long as the VCC UV
flag is set
VIO
Under−voltage
VIO is below the under−voltage threshold
for longer than dUVIO
VIO is above the under−voltage threshold
for longer than dBDRVIO
or
Remote Wakeup flag becomes set
Standby mode is forced
as long as the VIO UV flag
is set
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RxD and ERRN are set
Low if Remote Wakeup
flag is set and STBN is
Low
NCV7383
Table 3. INTERNAL FLAGS
Flag
Set Condition
Reset Condition
Comment
SPI Error
SPI error is detected:
Number of SCK falling edges
while CSN is Low is different from 16
or
SCK is not Low at CSN falling or rising
edge
CSN falling edge is detected
or
Track mode is entered
The status bits update is
discarded if SPI Error is
detected
Error
Any of the following flags is set:
All of the following Flags (Track mode)
or Status bits (Latched mode) are reset:
ERRN is set Low if Error
flag is set and STBN is
High
•
•
•
•
•
•
Bus error
•
•
•
•
•
•
Thermal Shutdown
TxEN Timeout
VCC Under−voltage
VIO Under−voltage
SPI Error
Bus error
Thermal Shutdown
TxEN Timeout
VCC Under−voltage
VIO Under−voltage
SPI Error
Internal Error Flag
pin if STBN pin is High and the particular flags are
accessible via SPI interface.
After Power−up the Error signaling is switched to the
Latched mode by default (internal Pull−Up on CSN pin).
When VIO is not in under−voltage Error indication Track
mode can be selected by host request (setting CSN pin Low
for longer than dERRNModeChange while SCK is set High
− see Figure 5), or simply by leaving CSN pin permanently
connected to GND and SCK pin permanently connected to
VIO. As soon as Error Indication Track mode is selected,
CSN pin internal Pull−Up is switched to Pull−Down
providing the CSN pin input current is reduced.
There are two Error Signaling modes:
• Track mode − the common Error flag is reset when all
of the Error related flags are reset − Error flag is
directly visible on ERRN pin if STBN pin is High.
Minimum ERRN pin indication time is
dBDERRNSTABLE .
• Latched mode − the common Error flag is reset when
all of the related Status Bits are reset (requires
successful status Register read−out while all these flags
are reset). The common Error flag is visible on ERRN
Error indication
Latched Mode
CSN
(Internal Pull−Up)
Error indication
Track Mode
(Internal Pull−Up)
Error indication
Latched Mode
(Internal Pull−Down)
(Internal Pull−Up)
dERRNModeChange
SCK
Don’t care
Don’t care
Figure 5. Timing Diagram of Error Indication Mode Control.
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NCV7383
ERRN Pin signaling
The polarity of the indication is reversed − ERRN pin is
pulled Low when the “Error” flag or “Wake” flag (depends
on STBN pin state) is set. The signaling on pin ERRN is
functional in both operating modes.
Provided VIO supply is present together with VCC, the
digital output ERRN indicates the state of the internal
“Error” flag when the Normal mode is commanded by
STBN and the state of the internal “Wake” flag when the
Standby mode is commanded by STBN.
Table 4. SIGNALING ON ERRN PIN
STBN
Description
High
Detected error signaling
Low
Detected Wakeup event signaling
Error Flag
Wake Flag
ERRN
not set
x
High
set
x
Low
x
not set
High
x
set
Low
Failure Conditions Handling
The individual status bits are channeled to SDO pin at the
rising edge on SCK pin. The NCV7383 SPI supports baud
rates from 10 kbit/s to 2 Mbit/s. The status register consist
of 16 main bits and 16 additional bits providing information
about the analog and digital part version. The read−out
always starts with bit S0.
One SPI frame consists of exactly sixteen bits transferred
from the NCV7383 to the host through output pin SDO. The
number of SCK falling edges is checked on every SPI frame.
If the number is different from 16, the SPI frame is
considered as incorrect, SPI frame error flag is set and the
status register bits S4−S10 are not reset when the read−out
is finished. As soon as the CSN is set to High and no
violation was detected in the SPI frame, the read−out is
considered as finished. At the same time, the status register
bits S4 to S10 are reset provided the corresponding flags are
reset − see Table 5.
Additionally, the total number of bits shifted to SDO
during the read−out can be extended to 32, considering the
SPI frame incorrect. This provides ability to obtain the
additional status register bits identifying the production
masks version. Such SPI frame sets the SPI frame error flag
and the status register bits S4−S10 are not reset when the
read−out is finished.
SPI interface is fully functional only if Latched Error
Indication mode is selected and VIO supply is not in
undervoltage.
SPI interface is disabled in Power−Off mode (VCC <
uVCC_PORL ) even if VIO supply voltage is not in
undervoltage.
Safe behavior of the NCV7383 is guaranteed in order not
to disturb the rest of the FlexRay network in case the
NCV7383 is under following fault conditions:
• Undervoltage on VIO and/or VCC − Standby mode is
entered and transmitter is disabled
• BP or BM is shorted to GND or to Supply voltage −
The absolute bus pins output current is limited
• BP and BM are shorted together − The absolute bus
pins output current is limited
• GND pin is unconnected while all digital inputs are
High − Absolute BP and BM leakage current and input
current of the digital input pins are limited.
• TxEN is Low for longer than dBDTxActiveMax (typ.
1.5 ms) when the NCV7383 is in a Normal mode
−the transmitter is disabled
• Junction temperature exceeds the Thermal Shutdown
Temperature (TJSD, typ. 165°C) when the NCV7383 is
in a Normal mode − the transmitter is disabled
SPI Interface and Status Register
A full set of internal bits referred to as status register can
be read through the Serial Peripheral Interface (SPI). The
status register content is described in Table 5 while an
example of the read−out waveform is shown in Figure 6.
As long as the CSN chip select is High, the SCK clock
input is not relevant and the SDO output is kept in
High−Impedance state. The signal on the SCK input is taken
into account only when CSN chip select input is set to Low.
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NCV7383
tCSN_SCK
tSCK_per
tSCK_CSN
tCSN_High
tSCK_High tSCK_Low
CSN
SCK
SDO
S0
S14
tCSN_SDO
tSCK_SDO
S15
tCSN_SDO
Figure 6. Definition of SPI Timing Parameters
Table 5. STATUS REGISTER
Bit Number
Status Bit Content
S0
Remote wakeup flag
S1
Mode flag
S2
Transmitter ready flag
S3
BGE Feedback
S4
Power−on status
S5
Bus error status
S6
Thermal shutdown status
S7
TxEN Timeout status
S8
VCC Under−voltage status
S9
VIO Under−voltage status
S10
SPI Error status
S11
Note
Reset After Finished Read−out
reflects directly the corresponding flag
no
Normal mode: BGE pin logical state
(Note 3)
Other modes: Low
−
the status bit is set if the corresponding
flag was set previously (the respective
High level of the flag is latched in its status counter−part)
yes, if the corresponding flag is reset and the SPI frame was correct
(no SPI error)
not used; always Low
−
−
S12
not used; always High
−
−
S13
not used; always Low
−
−
S14
not used; always High
−
−
S15
Parity
Exclusive−OR of Status bits S0−S14
−
Fixed values identifying the production
masks version. Cannot be read out without detection of an SPI Error
−
S16−S23
Version of the NCV7383 analog
part
S24−S31
Version of the NCV7383 digital
part
3. The BGE pin state is latched during Status bit S2 read−out, at the SCK pin falling edge.
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NCV7383
Mode Changes Caused by Internal Flags
Rev. 3.0.1. The transmitter part translates logical signals on
digital inputs TxEN, BGE and TxD into appropriate bus
levels on pins BP and BM. A transmission cannot be started
with Data_1. In case the TxEN is set Low for longer than
dBDTxActiveMax in Normal mode, the TxEN Timeout flag
is set and the transmitter is disabled. The receiver part
monitors bus pins BP and BM and signals the detected levels
on digital output RxD. The different bus levels are defined
in Figure 7. The function of the bus driver and the related
digital pins in different operating modes is detailed in
Tables 6 and 7.
• The transmitter can only be enabled if the activation of
the transmitter is initiated in Normal mode.
• The Normal mode receiver function is enabled by
entering the Normal mode.
• The Low power receiver function is enabled by
entering the Standby mode.
Changes of some internal flags described in Table 3 can
force an operating mode transition complementing or
overruling the operating mode control by the digital input
STBN which is shown in Figure 3:
• Setting the VIO or VCC under−voltage flag causes a
transition to the Standby mode
• Reset of the Under−voltage flag (i.e. recovery from
under−voltage) re−enables the control of the chip by
digital input STBN.
• Setting of the Wake flag causes the reset of all
under−voltage flags. The NCV7383 stays in the
Standby mode.
FlexRay Bus Driver
NCV7383 contains a fully−featured FlexRay bus driver
compliant with Electrical Physical Layer Specification
uBus
BP
VCC/2
BM
Idle_LP
Idle
Data_0
Data_1
Figure 7. FlexRay Bus Signals
Table 6. TRANSMITTER FUNCTION AND TRANSMITTER−RELATED PINS
Operating Mode
BGE
TxEN
TxD
Transmitted Bus Signal
Standby
x
x
x
Idle_LP
0
x
x
Idle
1
1
x
Idle
1
0
0
Data_0
1
0
1
Data_1
Normal
Table 7. RECEIVER FUNCTION AND RECEIVER−RELATED PINS
Operating Mode
Standby
Normal
Signal on Bus
Wake flag
RxD
x
not set
High
x
set
Low
Idle
x
High
Data_0
x
Low
Data_1
x
High
Bus Guardian Interface
Bus Driver Remote Wakeup Detection
The interface consists of the BGE digital input signal
allowing a Bus Guardian unit to disable the transmitter.
During the Standby mode and under the presence of VCC
voltage, a low−power receiver constantly monitors the
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NCV7383
Data_1 symbols − referred to as “alternative wakeup
pattern” − is depicted in Figure 9.
A remote wake−up is detected even if a transition from
Normal mode to Standby mode takes place while a valid
wakeup pattern is being received (if the wakeup pattern
starts in Normal mode and ends in Standby mode).
activity on bus pins BP and BM. A valid remote wake−up is
detected when either a wakeup pattern or a dedicated
wakeup frame is received.
A wakeup pattern is composed of two Data_0 symbols
separated by Data_1 or Idle symbols. The basic wakeup
pattern composed of Data_0 and Idle symbols is shown in
Figure 8; the wakeup pattern composed of Data_0 and
uBus
<dWUTimeout
>dWUIdleDetect
>dWU0Detect
Data_0
Idle(_LP)
Data_0
>dWUIdleDetect
0
uData0_LP
Idle(_LP)
Idle(_LP)
Remote wakeup
detected
>dWU0Detect
Figure 8. Valid Remote Wakeup Pattern
<dWUTimeout
>dWUIdleDetect
>dWU0Detect
Data_1
Data_0
>dWUIdleDetect
0
uData0_LP
Idle(_LP)
Data_0
Data _1
Remote wakeup
detected
>dWU0Detect
uBus
Figure 9. Valid Alternative Remote Wakeup Pattern
A remote wakeup will be also detected if NCV7383 receives a full FlexRay frame at 10 Mbit/s with the following payload data:
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
The wakeup pattern, the alternative wakeup pattern and the wakeup frame lead to identical wakeup treatment and signaling.
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NCV7383
ABSOLUTE MAXIMUM RATINGS
Table 8. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Unit
uVCC−MAX
5V Supply voltage
−0.3
5.5
V
uVIO−MAX
Supply voltage for VIO voltage level adaptation
−0.3
5.5
V
uDigInMAX
DC voltage at digital inputs (STBN, TxD, TxEN, BGE, SCSN, SCLK)
−0.3
5.5
V
DC voltage at digital Outputs (RxD, ERRN, SDO)
−0.3
VIO+0.3
V
Digital output pins input current (VIO = 0 V)
−10
10
mA
uBMMAX
DC voltage at pin BM
−50
50
V
uBPMAX
DC voltage at pin BP
−50
50
V
TJ_MAX
Junction temperature
−40
175
°C
Storage Temperature Range
−55
150
°C
uESDIEC
System HBM on pins BP and BM
(as per IEC 61000−4−2; 150 pF/330 W)
−10
+10
kV
uESDEXT
Component HBM on pins BP, BM
(as per EIA−JESD22−A114−B; 100 pF/1500 W)
−8
+8
kV
uESDINT
Component HBM on all other pins
(as per EIA−JESD22−A114−B; 100 pF/1500 W)
−4
+4
kV
uVTRAN
Voltage transients, pins BP and BM
According to ISO7637−2, Class C (Note 4)
−100
−
V
test pulses 2a
−
+75
V
test pulses 3a
−150
−
V
test pulses 3b
−
+100
V
uDigOutMAX
iDigOutIN−MAX
TSTG
test pulses 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. Test is carried out according to setup in FlexRay Physical Layer EMC Measurement Specification, Version 3.0. This specification is referring
to ISO7637. Test for higher voltages is planned.
OPERATING RANGES
Table 9. NCV7383: OPERATING RANGES
Symbol
Parameter
Min
Max
Unit
uVCC−OP
Supply voltage 5 V
4.75
5.25
V
uVIO−OP
Supply voltage for VIO voltage level adaptation
2.3
5.25
V
uDigIOOP
DC voltage at digital pins (TxD, TxEN, RxD, BGE, STBN, ERRN, SCSN,
SCLK, SDO)
0
VIO
V
uBMOP
DC voltage at pin BM
−50
50
V
uBPOP
DC voltage at pin BP
−50
50
V
TAMB
Ambient temperature (Note 5)
−40
125
°C
TJ_OP
Junction temperature
−40
150
°C
5. The specified range corresponds to TAMB_Class1
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NCV7383
THERMAL CHARACTERISTICS
Table 10. PACKAGE THERMAL RESISTANCE
Symbol
Rating
Value
Unit
RqJA_1
Thermal Resistance Junction−to−Air, JEDEC 1S0P PCB
153
K/W
RqJA_2
Thermal Resistance Junction−to−Air, JEDEC 2S2P PCB
104
K/W
ELECTRICAL CHARACTERISTICS
The characteristics defined in this section are guaranteed within the operating ranges listed in Table 9, unless stated otherwise. Positive
currents flow into the respective pin.
Table 11. CURRENT CONSUMPTION
Symbol
iVCC−NORM−IDLE
Parameter
Conditions
Current consumption from VCC
iVCC−NORM−ACTIVE
iVCC−LP
iVIO−NORM
Current consumption from VIO
iVIO−LP
iTot−LP
Total current consumption − Sum from all
supply pins
Min
Typ
Max
Unit
Normal mode − bus signals Idle
15
mA
Normal mode − bus signals Data_0/1
RBUS = No load
37
mA
Normal mode − bus signals Data_0/1
RBUS = 40−55 W
72
mA
Standby mode, TJ ≤ 85°C (Note 6)
30
mA
Normal mode
1
mA
Standby mode, TJ ≤ 85°C (Note 6)
6
mA
Standby mode
53
mA
Standby mode, TJ < 85°C (Note 6)
37
mA
Standby mode, TJ < 25°C (Note 6)
24
mA
Max
Unit
600
2000
mV
0
25
mV
60
ns
60
ns
4
ns
6
18.75
ns
6
18.75
ns
3
ns
6. Values based on design and characterization, not tested in production
Table 12. TRANSMISSION PARAMETERS
Symbol
Parameter
Conditions
uBDTxactive
Differential voltage |uBP−uBM| when sending symbol
“Data_0” or “Data_1”
(Functional class Bus driver increased voltage
amplitude transmitter)
uBDTxIdle
Differential voltage |uBP−uBM| when driving signal
“Idle”
dBDTx10
Transmitter delay, negative edge
dBDTx01
Transmitter delay, positive edge
dBDTxAsym
RBUS = 40−55 W;
CBUS = 100 pF
Parameters defined in
Figure 10.
Min
Test setup as per Figure 14
with RBUS = 40 W;
CBUS =100 pF
Sum of TxD signal rise and
fall time (20%−80% VIO) of
up to 9 ns
Transmitter delay mismatch,
|dBDTx10−dBDTx01| (Note 8)
dBusTx10
Fall time of the differential bus voltage from 80% to
20%
dBusTx01
Rise time of the differential bus voltage from 20% to
80%
dBusTxDif
Differential bus voltage fall and rise time mismatch
|dBusTx10−dBusTx01|
Parameters defined in
Figure 10.
Typ
7. Values based on design and characterization, not tested in production
8. Guaranteed for ±300mV and ±150 mV level of uBus
9. Not tested in production. Limits based on bus driver simulations. For more information see FlexRay Communication System − Electrical
Physical Layer Specification, Version 3.0.1.
http://onsemi.com
12
NCV7383
Table 12. TRANSMISSION PARAMETERS
Symbol
dTxENLOW
Parameter
Time span of bus activity
dBDTxia
Transmitter delay idle −> active
dBDTxai
Transmitter delay active −> idle
Conditions
Min
Test setup as per Figure 14
with RBUS = 40 W; CBUS =
100 pF
550
Typ
Parameters defined in
Figure 11.
Max
Unit
650
ns
75
ns
75
ns
50
ns
dBDTxDM
Idle−active transmitter delay mismatch
| dBDTxia − dBDTxai |
dBusTxia
Transition time idle >active
30
ns
dBusTxai
Transition time active > idle
30
ns
75
ns
75
ns
dBDBGEia
BGE delay idle −> active (Note 7)
dBDBGEai
BGE delay active > idle (Note 7)
dBDTxActiveMax
RBUS = 40 W;
CBUS = 100 pF
Maximum length of transmitter activation
650
2600
ms
iBPBMShortMax
iBMBPShortMax
Absolute maximum output current when BP shorted
to BM − no time limit
RShortCircuit ≤ 1 W
60
mA
iBPGNDShortMax
iBMGNDShortMax
Absolute maximum output current when shorted to
GND − no time limit
RShortCircuit ≤ 1 W
60
mA
iBP−5VShortMax
iBM−5VShortMax
Absolute maximum output current when shorted to
−5 V − no time limit
RShortCircuit ≤ 1 W
60
mA
iBPBAT27ShortMax
iBMBAT27ShortMax
Absolute maximum output current when shorted to
27 V − no time limit
RShortCircuit ≤ 1 W
60
mA
iBPBAT48ShortMax
iBMBAT48ShortMax
Absolute maximum output current when shorted to
48 V − no time limit
RShortCircuit ≤ 1 W
72
mA
500
W
RBDTransmitter
Bus interface equivalent output impedance
Bus driver simulation model parameter (Note 9)
31
105
7. Values based on design and characterization, not tested in production
8. Guaranteed for ±300mV and ±150 mV level of uBus
9. Not tested in production. Limits based on bus driver simulations. For more information see FlexRay Communication System − Electrical
Physical Layer Specification, Version 3.0.1.
http://onsemi.com
13
NCV7383
uTxD
100% VIO
100...4400ns
50% VIO
0% VIO
dBDTx10
dBDTx01
uBus
uBDTxActive
100%
80%
300 mV
−300 mV
20%
−uBDTxActive
0%
dBusTx01
dBusTx10
TxD signal is constant for 100..4400 ns before the first edge.
All parameters values are valid even if the test is performed with opposite polarity.
Figure 10. Transmission Parameters (TxEN is Low and BGE is High)
uTxEN
dTxENLOW
100% VIO
50% VIO
0% VIO
dBDTxia
dBDTxai
uBus
−30 mV
−300 mV
−uBDTx
dBusTxia
dBusTxai
Figure 11. Transmission Parameters for Transitions between Idle and Active (TxD is Low)
http://onsemi.com
14
NCV7383
Table 13. RECEPTION PARAMETERS
Symbol
Parameter
Conditions
Min
Max
Unit
−300
−150
mV
Receiver threshold for detecting Data_1
Activity detected
previously.
|uBP−uBM| ≤ 3 V
150
300
mV
Mismatch of receiver thresholds
(uBP+uBM)/2 = 2.5 V
−30
30
mV
Low power receiver threshold for detecting Data_0
uVCC = 5 V.
−400
−100
mV
uCM
Common mode voltage range (with respect to
GND) that does not disturb the receiver function
and reception level parameters
uBP = (uBP+uBM)/2
(Note10)
−10
15
V
uBias
Bus bias voltage during bus state Idle in Normal
mode
uData0
Receiver threshold for detecting Data_0
uData1
|uData1|−|uData0|
uData0_LP
Bus bias voltage during bus state Idle in Standby
mode
RBUS= 40 − 55 W;
CBUS= 100 pF
(Note 11)
Typ
1800
2500
3150
mV
−100
0
100
mV
40
kW
RCM1, RCM2
Receiver common mode resistance
(Note 11)
C_BP, C_BM
Input capacitance on BP and BM pin (Note 13)
f = 5 MHz
20
pF
C_BusDIF
Bus differential input capacitance (Note 13)
f = 5 MHz
5
pF
iBPLEAK
iBMLEAK
Absolute leakage current when driver is off
uBP = uBM = 5 V
All other pins = 0 V
5
mA
iBPLEAKGND
iBMLEAKGND
Absolute leakage current, in case of loss of GND
uBP = uBM = 0 V
All other pins = 16 V
1600
mA
uBusRxData
Test signal parameters for reception of Data_0 and
Data_1 symbols
400
3000
mV
60
4330
ns
60
4330
ns
dBusRx10
22.5
ns
dBusRx01
22.5
ns
75
ns
75
ns
5
ns
400
3000
mV
590
610
ns
dBusIdle
590
610
ns
dBusRxia
18
22
ns
dBusRx0BD
dBusRx1BD
dBDRx10
Receiver delay, negative edge (Note 12)
dBDRx01
Receiver delay, positive edge (Note 12)
dBDRxAsym
uBusRx
Receiver delay mismatch
|dBDRx10− dBDRx01| (Note 12)
Test signal parameters for bus activity detection
dBusActive
Test signal and
parameters defined in
Figures 12 and 13.
RxD pin loaded with
25 pF capacitor.
dBusRxai
10
18
22
ns
Bus driver filter−time for idle detection
50
200
ns
Bus driver filter−time for activity detection
100
250
ns
dBDRxai
Bus driver idle reaction time
100
275
ns
dBDRxia
Bus driver activity reaction time
100
325
ns
300
ns
dBDIdleDetection
dBDActivityDetection
dBDTxRxai
Idle−Loop delay
10. Tested on a receiving bus driver. Sending bus driver has a ground offset voltage in the range of [−12.5 V to +12.5 V] and sends a 50/50
pattern.
11. Bus driver is connected to GND and uVCC = 5 V.
12. Guaranteed for ±300 mV and ±150 mV level of uBus
13. Values based on design and characterization, not tested in production
http://onsemi.com
15
NCV7383
dBusRx10
uBus
dBusRx01
uBusRxData
300 mV
150 mV
−150 mV
−300 mV
−uBusRxData
dBusRx0BD
uRxD
100% VIO
dBusRx1BD
dBDRx10
dBDRx01
50% VIO
0% VIO
Figure 12. Reception Parameters
dBusRxia
uBus
dBusRxai
−30 mV
−150 mV
−300 mV
−uBusRx
dBusActive
uRxD
dBDRxia
dBusIdle
dBDRxai
100% VIO
50% VIO
0% VIO
Figure 13. Parameters of Bus Activity Detection
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16
NCV7383
Table 14. REMOTE WAKE−UP DETECTION PARAMETERS
Symbol
Max
Unit
Wake−up detection time for Data_0 symbol
1
4
ms
dWUIdleDetect
Wake−up detection time for Idle/Data_1
1
4
ms
dWUTimeout
Total Wake−up detection time (Note 15)
50
140
ms
dWUInterrupt
Acceptance timeout for interruptions
0.13
1
ms
50
ms
Max
Unit
dWU0Detect
dBDWakeup
Reactionremote
Parameter
Conditions
(Note 14)
Min
Typ
Reaction time after remote wakeup event (Note 15)
14. The minimum value is only guaranteed, when the phase that is interrupted was continuously present for at least 870ns.
15. Values based on design and characterization, not tested in production
Table 15. POWER SUPPLY MONITORING PARAMETERS
Symbol
Parameter
Conditions
Min
Typ
uBDUVVCC
VCC under−voltage threshold
4
4.5
V
uUVIO
VIO under−voltage threshold
2
2.3
V
uUV_HYST
Hysteresis of the under−voltage detectors
20
100
200
mV
dBDUVVCC
VCC Undervoltage detection time (Note 16)
35
60
100
ms
dBDUVVIO
VIO Undervoltage detection time (Note 16)
35
60
100
ms
dBDRVCC
VCC Undervoltage recovery time (Note 16)
35
60
100
ms
dBDRVIO
30
VIO Undervoltage recovery time (Note 16)
14
48
ms
uVCC_PORH
VCC threshold for power on event
3.0
3.9
V
uVCC_PORL
VCC threshold for power off event
2.95
3.85
V
16. Values based on design and characterization, not tested in production
Table 16. TEMPERATURE MONITORING PARAMETERS
Symbol
TJSD
Parameter
Conditions
Thermal shut−down level
Min
Typ
Max
Unit
150
165
185
°C
Min
Typ
Max
Unit
50
ms
50
ms
Table 17. HOST INTERFACE TIMING PARAMETERS
Symbol
dBDModeChange
dReactionTimeERRN
dBDERRNSTABLE
dERRNModeChange
Parameter
Conditions
STBN level filtering time for operating mode
transition (Note 17)
14
Reaction time on ERRN pin
Error signaling time
Track mode
1
10
ms
Error signaling mode change request detection
time
Latched mode
VIO UV flag not set
95
330
ms
Max
Unit
17. Values based on design and characterization, not tested in production
Table 18. SPI INTERFACE TIMING CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
dCSN_SCK
First SPI clock edge after CSN active
250
dSCK_CSN
Last SPI clock edge before CSN inactive
250
dCSN_SDO
SDO output stable after CSN active
150
ns
SDO output High−Z after CSN inactive
150
ns
dSCK_per
ns
ns
SPI clock period
0.5
dSCK_High
Duration of SPI clock High level
250
ns
dSCK_Low
Duration of SPI clock Low level
250
ns
dSCK_SDO
SDO output stable after an SPI clock rising edge
dCSN_High
SPI Inter−frame space (CSN inactive)
150
250
http://onsemi.com
17
100
ms
ns
ns
NCV7383
DIGITAL INPUT SIGNALS
Table 19. DIGITAL INPUT SIGNALS VOLTAGE THRESHOLDS (Pins STBN, BGE, TxEN, CSN, SCK)
Symbol
Parameter
uVDIG−IN−LOW
Low level input voltage
uVDIG−IN−HIGH
High level input voltage
Conditions
uVDIG = uVIO
Min
Typ
Max
Unit
−0.3
0.3*VIO
V
0.7*VIO
5.5
V
Table 20. TxD PIN PARAMETERS
Max
Unit
uBDLogic_0
Symbol
Low level input voltage
Parameter
Conditions
−0.3
0.4*VIO
V
uBDLogic_1
High level input voltage
0.6*VIO
5.5
V
RPD_TxD
Pull−down resistance
iTxDIL
Low level input current
uTXD = 0 V
Input capacitance on TxD pin
uTXD = 100 mV, f = 5 MHz
(Note 18)
C_BDTxD
Min
Typ
5
11
20
kW
−1
0
1
uA
10
pF
18. Values based on design and characterization, not tested in production
Table 21. TxEN PIN PARAMETERS
Symbol
RPU_TxEN
iTxENIH
iTxENLEAK
Parameter
Conditions
Pull−up resistance
Min
Typ
Max
Unit
50
110
200
kW
High level input current
uTXEN = VIO
−1
0
1
mA
Input leakage current
uTxEN = 5.25V, VIO = 0 V
−1
0
1
mA
Min
Typ
Max
Unit
50
110
200
kW
−1
0
1
mA
Min
Typ
Max
Unit
500
kW
Table 22. STBN PIN PARAMETERS
Symbol
Parameter
RPD_STBN
Pull−down resistance
iSTBNIL
Low level input current
Conditions
uSTBN = 0 V
Table 23. BGE PIN PARAMETERS
Symbol
Parameter
RPD_BGE
Pull−down resistance
iBGEIL
Low level input current
Conditions
150
uBGE = 0 V
−1
0
1
mA
Min
Typ
Max
Unit
110
200
kW
Table 24. CSN PIN PARAMETERS
Symbol
RPU_CSN
iCSNIH
Parameter
Conditions
Pull−up resistance
Latched mode
50
High level input current
Latched mode, uCSN = VIO
−1
0
1
mA
RPD_CSN
Pull−down resistance
Track mode
50
110
200
kW
iCSNIL
Low level input current
Track mode, uCSN = 0V
−1
0
1
mA
Input leakage current
uCSN = 5.25V, VIO = 0V
−1
0
1
mA
Min
Typ
Max
Unit
50
110
200
kW
iCSNLEAK
Table 25. SCK PIN PARAMETERS
Symbol
RPU_SCK
iSCKIH
iSCKLEAK
Parameter
Conditions
Pull−up resistance
High level input current,
uSCK = VIO
−1
0
1
mA
Input leakage current
uSCK = 5.25V, VIO = 0 V
−1
0
1
mA
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18
NCV7383
DIGITAL OUTPUT SIGNALS
Table 26. DIGITAL OUTPUT SIGNALS VOLTAGE LIMITS (Pins RxD, ERRN and SDO)
Symbol
uVDIG−OUT−LOW
uVDIG−OUT−HIGH
Parameter
Conditions
Low level output voltage
Min
Max
Unit
0
0.2*VIO
V
0.8*VIO
VIO
V
iRxDOL = 3 mA,
iERRNOL = 0.7 mA,
iSDOOL = 1 mA
(Note 19)
High level output voltage
iRxDOH = −3 mA,
iERRNOH = −0.7 mA,
iSDOOH = −1 mA
(Note 19)
Typ
uVDIG−OUT−UV
Output voltage on a digital output
when VIO in undervoltage (Note 20)
RLOAD = 100 kW to GND,
VCC supplied
500
mV
uVDIG−OUT−OFF
Output voltage on a digital output
when unsupplied
RLOAD = 100 kW to GND
500
mV
Max
Unit
6.5
ns
6.5
ns
13
ns
5
ns
19. uVDIG = uVIO. No undervoltage on VIO and VCC supplied.
20. RxD and ERRN outputs forced Low, SDO output switched to High Impedance state
Table 27. RxD PIN PARAMETERS
Symbol
Parameter
Conditions
dBDRxDR15
RxD signal rise time (20%−80% VIO)
dBDRxDF15
RxD signal fall time (20%−80% VIO)
Min
Typ
RxD pin loaded with 15 pF
capacitor (Note 21)
dBDRxDR15 +
dBDRxDF15
Sum of rise and fall time
(20%−80% VIO)
|dBDRxDR15 −
dBDRxDF15|
Difference of rise and fall time
dBDRxDR25
RxD signal rise time (20%−80% VIO)
8.5
ns
dBDRxDF25
RxD signal fall time (20%−80% VIO)
8.5
ns
16.5
ns
5
ns
16.5
ns
5
ns
RxD pin loaded with 25 pF
capacitor
dBDRxDR25 +
dBDRxDF25
Sum of rise and fall time
(20%−80% VIO)
|dBDRxDR25 −
dBDRxDF25|
Difference of rise and fall time
dBDRxDR10_MS +
dBDRxDF10_MS
RXD signal sum of rise and fall time
at TP4_CC (20%−80% VIO)
|dBDRxDR10_MS
− dBDRxDF10_MS|
RxD signal difference of rise and fall
time at TP4_CC (20%−80% VIO)
RxD pin loaded with 10 pF at the
end of a 50 W, 1 ns microstripline
(Note 22)
21. Values based on design and characterization, not tested in production
22. Simulation result. Simulation performed within TJ_OP range, according to FlexRay Electrical Physical Layer Specification, Version 3.0.1
5 VDC
100 nF
100 nF
VIO
VCC
BP
RBUS
NCV7383
RxD
BM
25 pF
GND
Figure 14. Test Setup for Dynamic Characteristics
http://onsemi.com
19
CBUS
NCV7383
5 VDC
3.3 VDC
+
100 nF
22 mF
+
100 nF
22 mF
VIO
VCC
330 pF
BP
RBUS
56 W
NCV7383
RxD
15 pF
ISO 7637−2
pulse generator
BM
330 pF
GND
Figure 15. Test Setup for Transients Test Pulses
ORDERING INFORMATION
Device
Description
Temperature Range
Package
Shipping†
NCV7383DB0R2G
Clamp 15 FlexRay Transceiver
−40°C to +125°C
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
20
NCV7383
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
FlexRay is a trademark of the FlexRay Consortium.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NCV7383/D