Intersil HM3-6514-9 1024 x 4 cmos ram Datasheet

HM-6514
1024 x 4 CMOS RAM
March 1997
Features
Description
• Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max
The HM-6514 is a 1024 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. The device utilizes
synchronous circuitry to achieve high performance and low
power operation.
• Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
On-chip latches are provided for addresses allowing efficient
interfacing with microprocessor systems. The data output
can be forced to a high impedance state for use in expanded
memory arrays.
• TTL Compatible Input/Output
• Common Data Input/Output
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Pin Package for High Density
Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors. The
HM-6514 is a fully static RAM and may be maintained in any
state for an indefinite period of time.
Data retention supply voltage and supply current are guaranteed over temperature.
• On-Chip Address Register
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
Ordering Information
120ns
200ns
HM3-6514S-9
HM3-6514B-9
HM3-6514-9
-40oC to +85oC
PDIP
HM1-6514S-9
HM1-6514B-9
HM1-6514-9
-40oC to +85oC
CERDIP
24502BVA
-
8102402VA
8102404VA
-
-
-
-
300ns
TEMPERATURE RANGE
-
-
8102406VA
-40oC to +85oC
-
PACKAGE
PKG. NO.
E18.3
F18.3
JAN#
F18.3
SMD#
F18.3
CLCC
J18.B
-55oC to +125oC
HM4-6514-B
J18.B
Pinouts
3
16 A8
A3
4
15 A9
A0
5
14 DQ0
A1
6
13 DQ1
A2
7
12 DQ2
E
8
11 DQ3
GND
9
10 W
Address Input
E
Chip Enable
W
Write Enable
D
Data Input
Q
Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-1
A7
A4
A
2
1
18
17
A4
3
16 A8
A3
4
15 A9
A0
5
14 DQ0
A1
6
13 DQ1
A2
7
12 DQ2
8
9
10
11
DQ3
17 A7
VCC
2
DESCRIPTION
W
A5
PIN
A6
18 VCC
GND
1
E
A6
HM-6514 (CLCC)
TOP VIEW
A5
HM-6514 (PDIP, CERDIP)
TOP VIEW
File Number
2995.1
HM-6514
Functional Diagram
LSB A9
A8
A7
A6
A5
A4
A
LATCHED
ADDRESS
REGISTER
6
A
GATED
ROW
DECODER
64 x 64
MATRIX
64
6
L
G
16 16 16 16
L
LSB A2
A1
A0
A3
A
LATCHED
ADDRESS
REGISTER
GATED
COLUMN
I/O SELECT
4
A
4
G
4
1 OF 4
E
W
DQ
6-2
HM-6514
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical)
θJA
θJC
CERDIP Package . . . . . . . . . . . . . . . . 75oC/W
15oC/W
PDIP Package . . . . . . . . . . . . . . . . . . . 75oC/W
N/A
CLCC Package . . . . . . . . . . . . . . . . . . 90oC/W
33oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Ranges:
HM-6514S-9, HM-6514B-9, HM-6514-9 . . . . . . . . -40oC to +85oC
HM-6514B-8, HM-6514-8 . . . . . . . . . . . . . . . . . . -55oC to +125oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
VCC = 5V ±10%; TA = -40oC to +85oC (HM-6514S-9, HM-6514B-9, HM-6514-9)
TA = -55oC to +125oC (HM-6514B-8, HM-6514-8)
LIMITS
SYMBOL
ICCSB
PARAMETER
Standby Supply Current
MIN
MAX
UNITS
TEST CONDITIONS
HM-6514-9
-
25
µA
IO = 0mA, E = VCC -0.3V, VCC = 5.5V
HM-6514-8
-
50
µA
ICCOP
Operating Supply Current (Note 1)
-
7
mA
E = 1MHz, IO = 0mA, VI = GND,
VCC = 5.5V
ICCDR
Data Retention Supply
Current
HM-6514-9
-
15
µA
IO = 0mA, VCC = 2.0V, E = VCC
HM-6514-8
-
25
µA
Data Retention Supply Voltage
2.0
-
V
Input Leakage Current
-1.0
+1.0
µA
VI = VCC or GND, VCC = 5.5V
IIOZ
Input/Output Leakage Current
-1.0
+1.0
µA
VIO = VCC or GND, VCC = 5.5V
VIL
Input Low Voltage
-0.3
0.8
V
VCC = 4.5V
VIH
Input High Voltage
VCC -2.0
VCC +0.3
V
VCC = 5.5V
VOL
Output Low Voltage
-
0.4
V
IO = 2.0mA, VCC = 4.5V
VOH1
Output High Voltage
2.4
-
V
IO = -1.0mA, VCC = 4.5V
VOH2
Output High Voltage (Note 2)
VCC -0.4
-
V
IO = -100µA, VCC = 4.5V
VCCDR
II
Capacitance
SYMBOL
CI
CIO
TA = +25oC
PARAMETER
MAX
UNITS
Input Capacitance (Note 2)
8
pF
Input/Output Capacitance (Note 2)
10
pF
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
6-3
TEST CONDITIONS
f = 1MHz, All measurements are
referenced to device GND
HM-6514
AC Electrical Specifications
VCC = 5V ±10%; TA = -40oC to +85oC (HM-6514S-9, HM-6514B-9, HM-6514-9)
TA = -55oC to +125oC (HM-6514B-8, HM-6514-8)
LIMITS
SYMBOL
PARAMETER
HM-6514S-9
HM-6514B-9
HM-6514-9
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
TEST
CONDITIONS
(1) TELQV
Chip Enable Access Time
-
120
-
220
-
300
ns
(Notes 1, 3)
(2) TAVQV
Address Access Time
-
120
-
220
-
320
ns
(Notes 1, 3, 4)
(3) TELQX
Chip Enable Output Enable
Time
5
-
5
-
5
-
ns
(Notes 2, 3)
(4) TEHQZ
Chip Enable Output Disable
Time
-
50
-
80
-
100
ns
(Notes 2, 3)
(5) TELEH
Chip Enable Pulse Negative
Width
120
-
200
-
300
-
ns
(Notes 1, 3)
(6) TEHEL
Chip Enable Pulse Positive
Width
50
-
90
-
120
-
ns
(Notes 1, 3)
(7) TAVEL
Address Setup Time
0
-
20
-
20
-
ns
(Notes 1, 3)
(8) TELAX
Address Hold Time
40
-
50
-
50
-
ns
(Notes 1, 3)
(9) TWLWH
Write Enable Pulse Width
120
-
200
-
300
-
ns
(Notes 1, 3)
(10) TWLEH
Chip Enable Write Pulse
Setup Time
120
-
200
-
300
-
ns
(Notes 1, 3)
(11) TELWH
Chip Enable Write Pulse Hold
Time
120
-
200
-
300
-
ns
(Notes 1, 3)
(12) TDVWH
Data Setup Time
50
-
120
-
200
-
ns
(Notes 1, 3)
(13) TWHDX
Data Hold Time
0
-
0
-
0
-
ns
(Notes 1, 3)
(14) TWLDV
Write Data Delay Time
70
-
80
-
100
-
ns
(Notes 1, 3)
(15) TWLEL
Early Output High-Z Time
0
-
0
-
0
-
ns
(Notes 1, 3)
(16) TEHWH
Late Output High-Z Time
0
-
0
-
0
-
ns
(Notes 1, 3)
(17) TELEL
Read or Write Cycle Time
170
-
290
-
420
-
-
(Notes 1, 3)
NOTES:
1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. VCC = 4.5V and 5.5V.
4. TAVQV = TELQV + TAVEL.
6-4
HM-6514
Timing Waveforms
(2) TAVQV
(17) TELEL
(8)
TELAX
(7)
TAVEL
A
(7) TAVEL
VALID ADD
NEXT ADD
(2) TAVQY
(6)
TEHEL
(6)
TEHEL
(5) TELEH
E
(1) TELQV
DQ
(4) TEHQZ
(3) TELQX
HIGH Z
HIGH Z
VALID DATA OUT
W
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 1. READ CYCLE
TRUTH TABLE
INPUTS
TIME
REFERENCE
E
W
A
DATA I/O
DQ
-1
H
X
X
Z
Memory Disabled
H
V
Z
Cycle Begins, Addresses are Latched
0
FUNCTION
1
L
H
X
X
Output Enabled
2
L
H
X
V
Output Valid
H
X
V
Read Accomplished
X
X
Z
Prepare for Next Cycle (Same as -1)
H
V
Z
Cycle Ends, Next Cycle Begins (Same as 0)
3
4
5
H
The address information is latched in the on-chip registers
on the falling edge of E (T = 0). Minimum address set up and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes
enabled, but data is not valid until during time (T = 2). W
must remain high throughout the read cycle. After the output
data has been read, E may return high (T = 3). This will disable the output buffer and all inputs, and ready the RAM for
the next memory cycle (T = 4).
6-5
HM-6514
Timing Waveforms (Continued)
TELAX
TAVEL
A
TEVAL
VALID ADD
NEXT ADD
TELEL
TEHEL
TELEH
TEHEL
E
TWLEH
TELWL
TWHEH
TWLWH
W
TWLDV
HIGH Z
HIGH Z
VALID DATA INPUT
DQ
TWHDZ
TDVWH
TELWH
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 2. WRITE CYCLE
TRUTH TABLE
INPUTS
TIME
REFERENCE
E
W
A
DQ
-1
H
X
X
Z
Memory Disabled
X
V
Z
Cycle Begins, Addresses are Latched
L
X
Z
Write Period Begins
X
V
Data In is Written
H
X
Z
Write Completed
X
X
Z
Prepare for Next Cycle (Same as -1)
X
V
Z
Cycle Ends, Next Cycle Begins (Same as 0)
0
1
L
2
L
3
4
H
5
The write cycle is initiated by the falling edge of E (T = 0),
which latches the address information in the on-chip registers. There are two basic types of write cycles, which differ in
the control of the common data-in/data-out bus.
Case 1: E falls before W falls
The output buffers may become enabled (reading) if E falls
before W falls. W is used to disable (three-state) the outputs
so input data can be applied. TWLDV must be met to allow
the W signal time to disable the outputs before applying
input data. Also, at the end of the cycle the outputs may
become active if W rises before E. The RAM outputs and all
inputs will three-state after E rises (TEHQZ). In this type of
write cycle TWLEL and TEHWH may be ignored.
Case 2: E falls equal to or after W falls, and E rises before
or equal to W rising
FUNCTION
This E and W control timing will guarantee that the data outputs will stay disabled throughout the cycle, thus, simplifying
the data input timing. TWLEL and TEHWH must be met, but
TWLDV becomes meaningless and can be ignored. In this
cycle TDVWH and TWHDX become TDVEH and TEHDX. In
other words, reference data setup and hold times to the E
rising edge.
IF
OBSERVE
IGNORE
Case 1
E falls before W
TWLDV
TWLEL
Case 2
E falls after W and
E rises before W
TWLEL
TEHWH
TWLDV
TWHDX
If a series of consecutive write cycles are to be performed,
W may be held low until all desired locations have been written (an extension of Case 2).
6-6
HM-6514
Test Load Circuit
DUT
(NOTE 1) CL
IOH
+
-
1.5V
IOL
EQUIVALENT CIRCUIT
NOTE:
1. Test head capacitance.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
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6-7
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