LINER LTC2271 16-bit, 20msps serial low noise dual adc Datasheet

LTC2271
16-Bit, 20Msps
Serial Low Noise Dual ADC
FEATURES
DESCRIPTION
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The LTC®2271 is a 2-channel, simultaneous sampling
16-bit A/D converter designed for digitizing high frequency,
wide dynamic range signals. It is perfect for demanding
communications applications with AC performance that
includes 84.1dB SNR and 99dB spurious free dynamic
range (SFDR).
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2-Channel Simultaneous Sampling ADC
Serial LVDS Outputs: 1, 2 or 4 Bits per Channel
84.1dB SNR (46μVRMS Input Referred Noise)
99dB SFDR
Low Power: 185mW Total
92mW per Channel
Single 1.8V Supply
Selectable Input Ranges: 1VP-P to 2.1VP-P
200MHz Full-Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Conﬁguration
Pin Compatible With
LTC2190: 16-Bit, 25Msps, 104mW
52-Lead (7mm × 8mm) QFN Package
APPLICATIONS
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DC specs include ±1LSB INL (typ), ±0.2LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.44LSBRMS.
To minimize the number of data lines the digital outputs
are serial LVDS. Each channel outputs one bit, two bits or
four bits at a time. The LVDS drivers have optional internal
termination and adjustable output levels to ensure clean
signal integrity.
The ENC+ and ENC– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An internal clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
Low Power Instrumentation
Software-Deﬁned Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Integral Non-Linearity (INL)
1.8V
VDD
1.8V
2.0
OVDD
1.5
CH2
ANALOG
INPUT
ENCODE
INPUT
S/H
16-BIT
ADC CORE
S/H
16-BIT
ADC CORE
DATA
SERIALIZER
PLL
GND
OGND
2271 TA01
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
DATA CLOCK OUT
FRAME
1.0
SERIALIZED
LVDS
OUTPUTS
INL ERROR (LSB)
CH1
ANALOG
INPUT
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0
16384
32768
49152
OUTPUT CODE
65536
2271 TA02
2271f
1
LTC2271
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
OUT1B–
OUT1B+
OUT1A–
OUT1A+
GND
SDO
GND
VREF
GND
SENSE
VDD
TOP VIEW
VDD
Supply Voltages
VDD, OVDD................................................ –0.3V to 2V
Analog Input Voltage
AIN+, AIN–, PAR/SER, SENSE
(Note 3) ....................................–0.3V to (VDD + 0.2V)
Digital Input Voltage
ENC+, ENC–, CS, SDI, SCK (Note 4) ...... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2271C ................................................ 0°C to 70°C
LTC2271I.............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
52 51 50 49 48 47 46 45 44 43 42 41
VCM1 1
40 OUT1C+
GND 2
39 OUT1C–
AIN1+ 3
38 OUT1D+
AIN1– 4
37 OUT1D–
GND 5
36 DCO+
REFH 6
35 DCO–
REFL 7
34 OVDD
53
GND
REFH 8
33 OGND
REFL 9
32 FR+
PAR/SER 10
31 FR–
AIN2+ 11
30 OUT2A+
AIN2– 12
29 OUT2A–
GND 13
28 OUT2B+
VCM2 14
27 OUT2B–
OUT2C+
OUT2C–
OUT2D+
OUT2D–
GND
SDI
SCK
CS
ENC–
ENC+
VDD
VDD
15 16 17 18 19 20 21 22 23 24 25 26
UKG PACKAGE
52-LEAD (7mm s 8mm) PLASTIC QFN
TJMAX = 150°C, θJA = 29°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2271CUKG#PBF
LTC2271CUKG#TRPBF
LTC2271UKG
52-Lead (7mm × 8mm) Plastic QFN
0°C to 70°C
LTC2271IUKG#PBF
LTC2271IUKG#TRPBF
LTC2271UKG
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based ﬁnish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/
2271f
2
LTC2271
CONVERTER CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
l
16
Integral Linearity Error
Differential Analog Input (Note 6)
l
–2.6
±1
2.6
LSB
Differential Linearity Error
Differential Analog Input
l
–0.8
±0.2
0.8
LSB
Offset Error
(Note 7)
l
–7
±1.3
7
mV
Gain Error
Internal Reference
External Reference
–1.6
±1.2
–0.3
1
%FS
%FS
l
Bits
Offset Drift
Full-Scale Drift
Internal Reference
External Reference
±10
μV/°C
±30
±10
ppm/°C
ppm/°C
Gain Matching
l
–0.2
±0.06
0.2
%FS
Offset Matching
l
–10
±1.5
10
mV
Transition Noise
1.44
LSBRMS
ANALOG INPUT The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise
speciﬁcations are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Input Range (AIN+ – AIN–)
1.7V < VDD < 1.9V
l
Differential Analog Input (Note 8)
l
0.65
VCM
VCM + 200mV
V
l
0.625
1.250
1.300
V
VIN(CM)
Analog Input Common Mode (AIN+ + AIN–)/2
VSENSE
External Voltage Reference Applied to SENSE External Reference Mode
MIN
TYP
MAX
1 to 2.1
UNITS
VP-P
IINCM
Analog Input Common Mode Current
Per Pin, 20Msps
IIN1
Analog Input Leakage Current (No Encode)
0 < AIN+, AIN– < VDD
l
–1
1
μA
IIN2
PAR/SER Input Leakage Current
0 < PAR/SER < VDD
l
–1
1
μA
0.625V < SENSE < 1.3V
l
–2
2
μA
IIN3
SENSE Input Leakage Current
tAP
Sample-and-Hold Acquisition Delay Time
tJITTER
Sample-and-Hold Acquisition Delay Jitter
CMRR
Analog Input Common Mode Rejection Ratio
BW–3B
Full-Power Bandwidth
32
0
Single-Ended Encode
Differential Encode
Figure 5 Test Circuit
μA
ns
85
100
fsRMS
fsRMS
80
dB
200
MHz
2271f
3
LTC2271
DYNAMIC ACCURACY
The l denotes the speciﬁcations which apply over the full operating temperature range,
otherwise speciﬁcations are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
1.4MHz Input
5MHz Input
30MHz Input
70MHz Input
SFDR
Spurious Free Dynamic Range, 2nd Harmonic
Spurious Free Dynamic Range, 3rd Harmonic
Spurious Free Dynamic Range, 4th Harmonic or Higher
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
MIN
1.4MHz Input
5MHz Input
30MHz Input
70MHz Input
1.4MHz Input
5MHz Input
30MHz Input
70MHz Input
1.4MHz Input
5MHz Input
30MHz Input
70MHz Input
1.4MHz Input
5MHz Input
30MHz Input
70MHz Input
Crosstalk
l
82.3
l
88
l
88
l
93
l
81.8
10MHz Input
TYP
MAX
UNITS
84.1
84.1
83.8
82.7
dBFS
dBFS
dBFS
dBFS
99
98
98
90
dBFS
dBFS
dBFS
dBFS
99
98
98
96
dBFS
dBFS
dBFS
dBFS
110
110
105
100
dBFS
dBFS
dBFS
dBFS
83.9
83.9
83.7
82.0
dBFS
dBFS
dBFS
dBFS
–110
dBc
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full
operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VCM Output Voltage
IOUT = 0
l
MIN
TYP
MAX
0.5 • VDD – 25mV
0.5 • VDD
0.5 • VDD + 25mV
VCM Output Temperature Drift
UNITS
±25
VCM Output Resistance
–600μA < IOUT < 1mA
VREF Output Voltage
IOUT = 0
ppm/°C
4
l
1.230
Ω
1.250
VREF Output Temperature Drift
1.270
V
±25
VREF Output Resistance
–400μA < IOUT < 1mA
VREF Line Regulation
1.7V < VDD < 1.9V
V
ppm/°C
7
Ω
0.6
mV/V
DIGITAL INPUTS AND OUTPUTS The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC+, ENC–)
Differential Encode Mode (ENC– Not Tied to GND)
VID
Differential Input Voltage
(Note 8)
l
0.2
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
1.1
1.6
V
V
l
0.2
3.6
V
V
1.2
VIN
Input Voltage Range
ENC+, ENC– to GND (Note 8)
RIN
Input Resistance
See Figure 10
10
kΩ
CIN
Input Capacitance
(Note 8)
3.5
pF
2271f
4
LTC2271
DIGITAL INPUTS AND OUTPUTS The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Single-Ended Encode Mode (ENC– Tied to GND)
VIH
High Level Input Voltage
VDD =1.8V
l
1.2
V
VIL
Low Level Input Voltage
VDD =1.8V
l
VIN
Input Voltage Range
ENC+ to GND
l
RIN
Input Resistance
See Figure 11
30
kΩ
CIN
Input Capacitance
(Note 8)
3.5
pF
0
0.6
V
3.6
V
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH
High Level Input Voltage
VDD =1.8V
l
VIL
Low Level Input Voltage
VDD =1.8V
l
IIN
Input Current
VIN = 0V to 3.6V
l
CIN
Input Capacitance
(Note 8)
1.3
V
–10
0.6
V
10
μA
3
pF
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
ROL
Logic Low Output Resistance to GND
VDD =1.8V, SDO = 0V
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT
Output Capacitance
(Note 8)
200
l
–10
Ω
10
3
μA
pF
DIGITAL DATA OUTPUTS
VOD
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
247
125
350
175
454
250
VOS
Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
1.125
1.125
1.250
1.250
1.375
1.375
RTERM
On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100
mV
mV
V
V
Ω
POWER REQUIREMENTS The l denotes the speciﬁcations which apply over the full operating temperature
range, otherwise speciﬁcations are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
VDD
Analog Supply Voltage
(Note 10)
l
1.7
1.8
1.9
UNITS
OVDD
Output Supply Voltage
(Note 10)
l
1.7
1.8
1.9
V
IVDD
Analog Supply Current
Sine Wave Input
l
93.3
103
mA
IOVDD
Digital Supply Current
1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
4-Lane Mode, 1.75mA Mode
4-Lane Mode, 3.5mA Mode
l
l
l
l
l
l
9.4
17.5
13.4
25.5
21.9
42
10.7
19.6
15.5
29
25
47
mA
mA
mA
mA
mA
mA
PDISS
Power Dissipation
1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
4-Lane Mode, 1.75mA Mode
4-Lane Mode, 3.5mA Mode
l
l
l
l
l
l
185
199
192
214
207
244
205
221
214
238
231
270
mW
mW
mW
mW
mW
mW
PSLEEP
Sleep Mode Power
1
mW
PNAP
Nap Mode Power
50
mW
PDIFFCLK
Power Increase with Diffential Encode Mode Enabled
(No Increase for Sleep Mode)
20
mW
V
2271f
5
LTC2271
TIMING CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature
range, otherwise speciﬁcations are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
fS
Sampling Frequency
(Note 10)
tENCL
MIN
l
5
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
23.5
2
tENCH
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
23.5
2
tAP
Sample-and-Hold
Acquistion Delay Time
SYMBOL
PARAMETER
TYP
MAX
20
MHz
25
25
100
100
ns
ns
25
25
100
100
ns
ns
0
CONDITIONS
MIN
TYP
UNITS
ns
MAX
UNITS
Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND On Each Output)
tSER
Serial Data Bit Period
4-Lane Output Mode
2-Lane Output Mode
1-Lane Output Mode
1/(4 • fS)
1/(8 • fS)
1/(16 • fS)
Sec
tFRAME
FR to DCO Delay
(Note 8)
l
0.35 • tSER
0.5 • tSER
0.65 • tSER
Sec
tDATA
Data to DCO Delay
(Note 8)
l
0.35 • tSER
0.5 • tSER
0.65 • tSER
Sec
tPD
Propagation Delay
(Note 8)
l
tr
Output Rise Time
Data, DCO, FR, 20% to 80%
0.17
ns
tf
Output Fall Time
Data, DCO, FR, 20% to 80%
0.17
ns
DCO Cycle-Cycle Jitter
tSER = 3.1ns
0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER
60
Pipeline Latency
7
Sec
psP-P
7
Cycles
SPI Port Timing (Note 8)
l
l
40
250
ns
ns
CS-to-SCK Setup Time
l
5
ns
SCK-to-CS Setup Time
l
5
ns
tDS
SDI Setup Time
l
5
ns
tDH
SDI Hold Time
l
5
ns
tDO
SCK Falling to SDO
Valid
tSCK
SCK Period
tS
tH
Write Mode
Readback Mode,
CSDO = 20pF, RPULLUP = 2k
Readback Mode,
CSDO = 20pF, RPULLUP = 2k
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 20MHz, 2-lane output mode,
differential ENC+/ENC– = 2VP-P sine wave, input range = 2.1VP-P with
differential drive, unless otherwise noted.
l
125
ns
Note 6: Integral nonlinearity is deﬁned as the deviation of a code from a
best ﬁt straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5LSB when the
output code ﬂickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = OVDD=1.8V, fSAMPLE = 20MHz, 2-lane output mode, ENC+
= single-ended 1.8V square wave, ENC– = 0V, input range = 2.1VP-P with
differential drive, unless otherwise noted. The supply current and power
dissipation speciﬁcations are totals for the entire IC, not per channel.
Note 10: Recommended operating conditions.
2271f
6
LTC2271
TIMING DIAGRAMS
4-Lane Output Mode
tAP
ANALOG
INPUT
N
N+1
tENCL
tENCH
ENC–
ENC+
tDATA
DCO–
tSER
DCO+
tSER
tFRAME
FR+
FR–
tPD
OUT#A–
OUT#A+
tSER
D15
D13
D11
D9
D15
D13
D11
D9
D15
D14
D12
D10
D8
D14
D12
D10
D8
D14
D7
D5
D3
D1
D7
D5
D3
D1
D7
D6
D4
D2
D0
D6
D4
D2
D0
D6
OUT#B–
OUT#B+
OUT#C–
OUT#C+
OUT#D–
OUT#D+
SAMPLE N–7
SAMPLE N–6
SAMPLE N–5
2271 TD01
2-Lane Output Mode
tAP
ANALOG
INPUT
N+1
N
tENCL
tENCH
ENC–
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
tDATA
tSER
FR+
tPD
OUT#A–
OUT#A+
tSER
D7
D5
D3
D1
D15
D13
D11
D9
D7
D5
D3
D1
D15
D13
D11
D6
D4
D2
D0
D14
D12
D10
D8
D6
D4
D2
D0
D14
D12
D10
OUT#B–
OUT#B+
SAMPLE N–7
SAMPLE N–6
OUT#C+, OUT#C–, OUT#D+, OUT#D– ARE DISABLED
SAMPLE N–5
2271 TD02
2271f
7
LTC2271
TIMING DIAGRAMS
1-Lane Output Mode
tAP
ANALOG
INPUT
N+1
N
tENCH
ENC–
tENCL
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
tDATA
tSER
FR+
tPD
OUT#A–
OUT#A+
D3
D2
D1
tSER
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
219210 TD03
SAMPLE N–7
SAMPLE N–6
SAMPLE N–5
OUT#B+, OUT#B–, OUT#C+, OUT#C–, OUT#D+, OUT#D– ARE DISABLED
SPI Port Timing (Readback Mode)
tDS
tS
tDH
tSCK
tH
CS
SCK
tDO
SDI
R/W
A6
A5
A4
A3
A2
A1
A0
SDO
XX
D7
HIGH IMPEDANCE
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
XX
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
R/W
SDO
HIGH IMPEDANCE
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
219210 TD04
2271f
8
LTC2271
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Non-Linearity (INL)
2.0
1.0
1.5
0.8
0
–20
0.6
1.0
0.5
0.0
–0.5
AMPLITUDE (dBFS)
0.4
DNL ERROR (LSB)
INL ERROR (LSB)
64k Point FFT, fIN = 1.4MHz, –1dBFS,
20Msps
Differential Non-Linearity (DNL)
0.2
0.0
–0.2
–0.4
–1.0
–40
–60
–80
–100
–0.6
–1.5
–120
–0.8
–2.0
–1.0
65536
–140
0
16384
32768
49152
OUTPUT CODE
2271 G01
0
–20
–20
–20
–40
–40
–40
–60
–80
–120
–120
–140
–140
10
0
2
4
6
FREQUENCY (MHz)
8
2271 G04
10
40000
–20
–20
35000
–40
–40
30000
25000
–60
COUNT
–80
15000
–100
10000
–120
4
6
FREQUENCY (MHz)
8
10
2271 G07
–140
0
2
4
6
FREQUENCY (MHz)
8
10
0
N+4
2
N+3
0
5000
N+2
–140
20000
N
AMPLITUDE (dBFS)
0
–120
10
Shorted Input Histogram
0
–100
8
2271 G06
64k Point 2-Tone FFT, fIN = 14.8,
15.2MHz, –7dBFS, 20Msps
–80
4
6
FREQUENCY (MHz)
2
2271 G05
64k Point FFT, fIN = 70.3MHz,
–1dBFS, 20Msps
–60
0
N+1
8
N-1
4
6
FREQUENCY (MHz)
N-2
2
N+6
–140
N+5
–120
–80
–100
–100
0
10
–60
N-3
–100
AMPLITUDE (dBFS)
0
–80
8
64k Point FFT, fIN = 30.3MHz,
–1dBFS, 20Msps
0
–60
4
6
FREQUENCY (MHz)
2
2271 G03
64k Point FFT, fIN = 10.1MHz,
–1dBFS, 20Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
2271 G02
64k Point FFT, fIN = 5.1MHz,
–1dBFS, 20Msps
AMPLITUDE (dBFS)
65536
N-4
32768
49152
OUTPUT CODE
N-5
16384
N-6
0
OUTPUT CODE
2271 G08
2271 G09
2271f
9
LTC2271
TYPICAL PERFORMANCE CHARACTERISTICS
2nd, 3rd Harmonic vs Input
Frequency, –1dBFS, 20Msps,
2.1V Range
SNR vs Input Frequency, –1dBFS,
20Msps, 2.1V Range
105
84
100
100
SINGLE-ENDED
ENCODE
82
DIFFERENTIAL
ENCODE
81
80
79
95
3RD
90
85
20
40
60
80 100 120
INPUT FREQUENCY (MHz)
2ND
80
75
70
0
2ND AND 3RD HARMONIC (dBFS)
105
2ND AND 3RD HARMONIC (dBFS)
85
83
SNR (dBFS)
2nd, 3rd Harmonic vs Input
Frequency, –1dBFS, 20Msps,
1.05V Range
140
0
20
40
60
80 100 120
INPUT FREQUENCY (MHz)
95
2ND
90
85
80
75
70
140
3RD
0
20
40
60
80 100 120
INPUT FREQUENCY (MHz)
2271 G11
2271 G10
2271 G12
IVDD vs Sample Rate, 5MHz,
–1dBFS Sine Wave Input on
Each Channel
SFDR vs Input Level, fIN = 5MHz,
20Msps, 2.1V Range
130
IOVDD vs Sample Rate, 5MHz,
–1dBFS Sine Wave Input on
Each Channel
100
45
4 LANE, 3.5mA
dBFS
120
40
95
35
90
80
dBc
70
IOVDD (mA)
100
IVDD (mA)
SFDR (dBc AND dBFS)
110
90
85
60
50
40
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
80
0
5
0
10
15
SAMPLE RATE (Msps)
2271 G13
30
4 LANE, 1.75mA
20
1 LANE, 3.5mA
15
2 LANE, 1.75mA
10
1 LANE, 1.75mA
5
20
2 LANE, 3.5mA
25
0
5
10
15
SAMPLE RATE (Msps)
2271 G14
85
20
2271 G15
SFDR vs Analog Input Common
Mode, fIN = 9.7MHz, 20Msps,
2.1V Range
SNR vs SENSE,
fIN = 5MHz, –1dBFS
SNR, SFDR vs Sample Rate,
fIN = 5MHz, –1dBFS
110
100
VDD 1.9V
84
VDD 1.7V
95
SFDR (dBFS)
82
81
80
79
SNR, SFDR (dBFS)
83
SNR (dBFS)
140
90
SFDR
100
90
85
SNR
78
77
0.6
0.7
0.8
0.9
1
1.1
SENSE PIN (V)
1.2
1.3
2271 G16
80
80
0.6
0.7
0.9
1
1.1
0.8
INPUT COMMON MODE (V)
1.2
2271 G17
0
5
10
15
SAMPLE RATE (Msps)
20
2271 G18
2271f
10
LTC2271
PIN FUNCTIONS
VCM1 (Pin 1): Common Mode Bias Output, Nominally Equal
to VDD/2. VCM1 should be used to bias the common mode
of the analog inputs of channel 1. Bypass to ground with
a 1μF ceramic capacitor.
GND (Pins 2, 5, 13, 22, 45, 47, 49, Exposed Pad Pin 53):
ADC Power Ground. The exposed pad must be soldered
to the PCB ground.
AIN1+ (Pin 3): Channel 1 Positive Differential Analog
Input.
AIN1– (Pin 4): Channel 1 Negative Differential Analog
Input.
REFH (Pins 6, 8): ADC High Reference. See the Reference
section in the Applications Information for recommended
bypassing circuits for REFH and REFL.
REFL (Pins 7, 9): ADC Low Reference. See the Reference
section in the Applications Information for recommended
bypassing circuits for REFH and REFL.
PAR/SER (Pin 10): Programming Mode Selection Pin.
Connect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the VDD of the part and not be driven
by a logic signal.
AIN2+ (Pin 11): Channel 2 Positive Differential Analog
Input.
AIN2– (Pin 12): Channel 2 Negative Differential Analog
Input.
VCM2 (Pin 14): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM2 should be used to bias the common
mode of the analog inputs of channel 2. Bypass to ground
with a 1μF ceramic capacitor.
VDD (Pins 15, 16, 51, 52): Analog Power Supply, 1.7V
to 1.9V. Bypass to ground with 0.1μF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
ENC+ (Pin 17): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 18): Encode Complement Input. Conversion
starts on the falling edge. Tie to GND for single-ended
encode mode.
CS (Pin 19): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = VDD), CS along with SCK selects 1-,
2- or 4-lane output mode (see Table 3). CS can be driven
with 1.8V to 3.3V logic.
SCK (Pin 20): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = VDD), SCK along with CS
selects 1-, 2- or 4-lane output mode (see Table 3). SCK
can be driven with 1.8V to 3.3V logic.
SDI (Pin 21): In Serial Programming Mode, (PAR/SER =
0V), SDI is the Serial Interface Data Input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In the parallel programming pode (PAR/SER
= VDD), SDI can be used to power down the part. SDI can
be driven with 1.8V to 3.3V logic.
OGND (Pin 33): Output Driver Ground. This pin must be
shorted to the ground plane by a very low inductance path.
Use multiple vias close to the pin.
OVDD (Pin 34): Output Driver Supply. Bypass to ground
with a 0.1μF ceramic capacitor.
SDO (Pin 46): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V to 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
parallel programming mode (PAR/SER = VDD), SDO selects
3.5mA or 1.75mA LVDS output currents. When used as an
input, SDO can be driven with 1.8V to 3.3V logic through
a 1k series resistor.
VREF (Pin 48): Reference Voltage Output. Bypass to ground
with a 2.2μF ceramic capacitor. The reference output is
nominally 1.25V.
2271f
11
LTC2271
PIN FUNCTIONS
SENSE (Pin 50): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1.05V
input range. Connecting SENSE to ground selects the
internal reference and a ±0.525V input range. An external
reference between 0.625V and 1.3V applied to SENSE
selects an input range of ±0.84 • VSENSE.
OUT2D–/OUT2D+, OUT2C–/OUT2C+, OUT2B–/OUT2B+,
OUT2A–/OUT2A+ (Pins 23/24, 25/26, 27/28, 29/30): Serial
Data Outputs for Channel 2. In 1-lane output mode only
OUT2A–/OUT2A+ are used. In 2-Lane output mode only
OUT2A–/OUT2A+ and OUT2B–/OUT2B+ are used.
LVDS Outputs
DCO–/DCO+ (Pins 35/36): Data Clock Outputs.
The following pins are differential LVDS outputs. The
output current level is programmable. There is an optional
internal 100Ω termination resistor between the pins of
each LVDS output pair.
OUT1D–/OUT1D+, OUT1C–/OUT1C+, OUT1B–/OUT1B+,
OUT1A–/OUT1A+ (Pins 37/38, 39/40, 41/42, 43/44): Serial
Data Outputs for Channel 1. In 1-lane output mode only
OUT1A–/OUT1A+ are used. In 2-lane output mode only
OUT1A–/OUT1A+ and OUT1B–/OUT1B+ are used.
FR–/FR+ (Pins 31/32): Frame Start Outputs.
FUNCTIONAL BLOCK DIAGRAM
ENC+
1.8V
VDD
ENC–
1.8V
OVDD
PLL
CH1
ANALOG
INPUT
16-BIT
ADC CORE
S/H
DATA
SERIALIZER
CH2
ANALOG
INPUT
16-BIT
ADC CORE
S/H
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
DATA CLOCK OUT
FRAME
OGND
VREF
1.25V
REFERENCE
2.2μF
RANGE
SELECT
REF BUF
REFH
REFL
SENSE
VDD/2
DIFF REF
AMP
MODE
CONTROL
REGISTERS
2271 F01
REFH 2.2μF REFL
VCM1
1μF
1μF
VCM2
1μF
PAR/SER CS SCK SDI SDO
1μF
Figure 1. Functional Block Diagram
2271f
12
LTC2271
APPLICATIONS INFORMATION
CONVERTER OPERATION
The LTC2271 is a low power, 2-channel, 16-bit, 20Msps
A/D converter that is powered by a single 1.8V supply. The
analog inputs must be driven differentially. The encode
input can be driven differentially or single ended for lower
power consumption. To minimize the number of data lines
the digital outputs are serial LVDS. Each channel outputs
one bit at a time (1-lane mode), two bits at a time (2-lane
mode) or four bits at a time (4-lane mode). Many additional
features can be chosen by programming the mode control
registers through a serial SPI port.
ANALOG INPUT
The analog inputs are differential CMOS sample-andhold circuits (Figure 2). The inputs should be driven
differentially around a common mode voltage set by the
VCM1 or VCM2 output pins, which are nominally VDD/2.
For the 2.1V input range, the inputs should swing from
VCM – 525mV to VCM + 525mV. There should be 180°
phase difference between the inputs.
The two channels are simultaneously sampled by a shared
encode circuit (Figure 2).
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC lowpass ﬁlter right at
the analog inputs. This lowpass ﬁlter isolates the drive
circuitry from the A/D sample-and-hold switching, and
also limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC ﬁlter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with VCM, setting the A/D input at its optimal
DC level. At higher input frequencies a transmission line
balun transformer (Figures 4 to 5) has better balance,
resulting in lower A/D distortion.
LTC2271
VDD
RON
24Ω
10Ω
CSAMPLE
17pF
AIN+
CPARASITIC
1.8pF
VDD
RON
24Ω
10Ω
AIN–
CSAMPLE
17pF
CPARASITIC
1.8pF
VDD
1.2V
10k
ENC+
ENC–
10k
1.2V
2271 F02
Figure 2. Equivalent Input Circuit. Only One of Two Analog Channels Is Shown
2271f
13
LTC2271
APPLICATIONS INFORMATION
50Ω
50Ω
VCM
VCM
1μF
1μF
0.1μF
ANALOG
INPUT
0.1μF
T1
1:1
25Ω
25Ω
LTC2271
0.1μF
AIN+
ANALOG
INPUT
AIN+
T2
T1
25Ω
LTC2271
0.1μF
1.8pF
12pF
25Ω
0.1μF
25Ω
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
2271 F03
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 1MHz to 40MHz
50Ω
VCM
VCM
12Ω
HIGH SPEED
DIFFERENTIAL
0.1μF
AMPLIFIER
T1
AIN+
T2
25Ω
LTC2271
0.1μF
2271 F05
Figure 5. Recommended Front-End Circuit for Input Frequencies
Above 80MHz
1μF
ANALOG
INPUT
AIN–
AIN–
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
0.1μF
25Ω
ANALOG
INPUT
200Ω
1μF
200Ω
25Ω
AIN+
+
LTC2271
12pF
8.2pF
0.1μF
25Ω
12Ω
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
0.1μF
–
AIN–
25Ω
AIN–
12pF
2271 F04
Figure 4. Recommended Front-End Circuit for Input Frequencies
from 5MHz to 80MHz
2271 F06
Figure 6. Front-End Circuit Using a High Speed
Differential Ampliﬁer
Ampliﬁer Circuits
Figure 6 shows the analog input being driven by a high
speed differential ampliﬁer. The output of the ampliﬁer is
AC coupled to the A/D so the ampliﬁer’s output common
mode voltage can be optimally set to minimize distortion.
If DC coupling is necessary use a differential ampliﬁer
with an output common mode set by the LTC2271 VCM
pin (Figure 7).
VCM
1μF
25Ω
ANALOG
INPUT
+
CM
–
AIN+
25pF
–
LTC2271
+
25Ω
AIN–
25pF
2271 F07
Figure 7. DC-Coupled Ampliﬁer
2271f
14
LTC2271
APPLICATIONS INFORMATION
Reference
The LTC2271 has an internal 1.25V voltage reference. For
a 2.1V input range using the internal reference, connect
SENSE to VDD. For a 1.05V input range using the internal
reference, connect SENSE to ground. For a 2.1V input
range with an external reference, apply a 1.25V reference
voltage to SENSE (Figure 9).
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.68 • VSENSE.
The VREF, REFH and REFL pins should be bypassed as
shown in Figure 8. A low inductance 2.2μF interdigitated
capacitor is recommended for the bypass between REFH
and REFL. This type of capacitor is available at a low cost
from multiple suppliers.
Figure 8c and 8d show the recommended circuit board
layout for the REFH/REFL bypass capacitors. Note that in
Figure 8c, every pin of the interdigitated capacitor (C1)
is connected since the pins are not internally connected
in some vendors’ capacitors. In Figure 8d the REFH and
REFL pins are connected by short jumpers in an internal
layer. To minimize the inductance of these jumpers they
can be placed in a small hole in the GND plane on the
second board layer.
REFH
C3
1μF
LTC2271
REFL
C1
2.2μF
REFH
C2
1μF
REFL
2271 F08b
Alternatively, C1 can be replaced by a standard 2.2μF
capacitor between REFH and REFL. The capacitors should
be as close to the pins as possible (not on the back side
of the circuit board).
CAPACITORS ARE 0402 PACKAGE SIZE
Figure 8b. Alternative REFH/REFL Bypass Circuit
LTC2271
VREF
1.25V
5Ω
1.25V BANDGAP
REFERENCE
2.2μF
2271 F08c
0.625V
TIE TO VDD FOR 2.1V RANGE;
TIE TO GND FOR 1.05V RANGE;
3"/(&t7SENSE FOR
0.625V < VSENSE < 1.300V
Figure 8c. Recommended Layout for the REFH/REFL Bypass
Circuit in Figure 8a
RANGE
DETECT
AND
CONTROL
SENSE
BUFFER
INTERNAL ADC
HIGH REFERENCE
C2
1μF
–
+
+
–
REFH
REFL
C1
C3
1μF
–
+
+
–
REFH
2271 F08d
0.84x
DIFF AMP
Figure 8d. Recommended Layout for the REFH/REFL Bypass
Circuit in Figure 8b
REFL
C1: 2.2μF LOW INDUCTANCE
INTERDIGITATED CAPACITOR
TDK CLLE1AX7S0G225M
MURATA LLA219C70G225M
AVX W2L14Z225M
OR EQUIVALENT
VREF
INTERNAL ADC
LOW REFERENCE
2.2μF
LTC2271
2271 F08a
1.25V
EXTERNAL
REFERENCE
SENSE
1μF
2271 F09
Figure 8a. Reference Circuit
Figure 9. Using an External 1.25V Reference
2271f
15
LTC2271
APPLICATIONS INFORMATION
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalent resistance. The encode inputs can be taken above
VDD (up to 3.6V), and the common mode range is from 1.1V
to 1.6V. In the differential encode mode, ENC– should stay
at least 200mV above ground to avoid falsely triggering the
single-ended encode mode. For good jitter performance
ENC+ should have fast rise and fall times.
The single-ended encode mode should be used with
CMOS encode inputs. To select this mode, ENC– is connected to ground and ENC+ is driven with a square wave
LTC2271
VDD
encode input. ENC+ can be taken above VDD (up to 3.6V)
so 1.8V to 3.3V CMOS logic levels can be used. The ENC+
threshold is 0.9V. For good jitter performance ENC+ should
have fast rise and fall times. If the encode signal is turned
off or drops below approximately 500kHz, the A/D enters
nap mode.
0.1μF
ENC+
T1
50Ω
100Ω
0.1μF
50Ω
ENC–
0.1μF
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
2271 F12
Figure 12. Sinusoidal Encode Drive
0.1μF
PECL OR
LVDS
CLOCK
ENC+
LTC2271
0.1μF
ENC–
DIFFERENTIAL
COMPARATOR
VDD
LTC2271
2271 F13
Figure 13. PECL or LVDS Encode Drive
15k
ENC+
Clock PLL and Duty Cycle Stabilizer
ENC–
30k
2271 F10
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
LTC2271
1.8V TO 3.3V
0V
ENC+
ENC–
30k
The encode clock is multiplied by an internal phase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25μs to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
CMOS LOGIC
BUFFER
2271 F11
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
2271f
16
LTC2271
APPLICATIONS INFORMATION
DIGITAL OUTPUTS
Optional LVDS Driver Internal Termination
The digital outputs of the LTC2271 are serialized LVDS
signals. Each channel outputs one bit at a time (1-lane
mode), two bits at a time (2-lane mode) or four bits at a
time (4-lane mode). Please refer to the Timing Diagrams
for details. In 4-lane mode the clock duty cycle stabilizer
must be enabled.
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A2. The internal termination helps absorb any reﬂections
caused by imperfect termination at the receiver. When
the internal termination is enabled, the output driver
current is doubled to maintain the same output voltage
swing. Internal termination can only be selected in serial
programming mode.
The output data should be latched on the rising and falling
edges of the data clock out (DCO). A data frame output
(FR) can be used to determine when the data from a new
conversion result begins.
The minimum sample rate for all serialization modes is
5Msps.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD which is isolated from
the A/D core power.
Table 1. Maximum Sampling Frequency for All Serialization
Modes
MAXIMUM
SAMPLING
SERIALIZATION FREQUENCY,
DCO
FR
SERIAL
MODE
fS (MHz)
FREQUENCY FREQUENCY DATA RATE
4-Lane
20
2 • fS
fS
4 • fS
2-Lane
20
4 • fS
fS
8 • fS
1-Lane
20
8 • fS
fS
16 • fS
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
Table 2. Output Codes vs Input Voltage
AIN+-AIN–
(2V RANGE)
D15-D0
(OFFSET BINARY)
D15-D0
(2’ s COMPLEMENT)
>1.000000V
+0.999970V
+0.999939V
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1110
0111 1111 1111 1111
0111 1111 1111 1111
0111 1111 1111 1110
+0.000030V
+0.000000V
–0.000030V
–0.000061V
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1110
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
–0.999939V
–1.000000V
<–1.000000V
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
1000 0000 0000 0001
1000 0000 0000 0000
1000 0000 0000 0000
Digital Output Randomizer
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by control register A2 in the
serial programming mode. Available current levels are
1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
In the parallel programming mode the SDO pin can select
either 3.5mA or 1.75mA.
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off-chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
2271f
17
LTC2271
APPLICATIONS INFORMATION
The digital output is randomized by applying an exclusive
OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied—an
exclusive OR operation is applied between the LSB and all
other bits. The FR and DCO outputs are not affected. The
output randomizer is enabled by serially programming
mode control register A1.
Digital Output Test Pattern
To allow in-circuit testing of the digital interface to the
A/D, there is a test mode that forces the A/D data outputs
(D15-D0) of both channels to known values. The digital
output test patterns are enabled by serially programming
mode control registers A2, A3 and A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement and randomizer.
Output Disable
The digital outputs may be disabled by serially programming mode control register A2. The current drive for all
digital outputs including DCO and FR are disabled to save
power or enable in-circuit testing. When disabled the common mode of each output pair becomes high impedance,
but the differential impedance may remain low.
leaves nap mode. Nap mode is enabled by mode control
register A1 in the serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2271 can be programmed
by either a parallel interface or a simple serial interface.
The serial interface has more ﬂexibility and can program
all available modes. The parallel interface is more limited
and can only program some of the more commonly used
modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK, SDI and SDO pins are binary
logic inputs that set certain operating modes. These pins
can be tied to VDD or ground, or driven by 1.8V, 2.5V or
3.3V CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table 3 shows the
modes set by CS, SCK, SDI and SDO.
Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN
CS/SCK
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire device is powered down,
resulting in 1mW power consumption. Sleep mode is
enabled by mode control register A1 (serial programming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF ,
REFH and REFL. For the suggested values in Figure 8, the
A/D will stabilize after 2ms.
In nap mode any combination of A/D channels can be
powered down while the internal reference circuits and the
PLL stay active, allowing faster wake up than from sleep
mode. Recovering from nap mode requires at least 100
clock cycles. If the application demands very accurate DC
settling then an additional 50μs should be allowed so the
on-chip references can settle from the slight temperature
shift caused by the change in supply current as the A/D
DESCRIPTION
2-Lane/4-Lane/1-Lane Selection Bits
00 = 2-Lane Output Mode
01 = 4-Lane Output Mode
10 = 1-Lane Output Mode
11 = Not Used
SDI
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
SDO
LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the ﬁrst 16 rising edges of
SCK. Any SCK rising edges after the ﬁrst 16 are ignored.
The data transfer ends when CS is taken high again.
2271f
18
LTC2271
APPLICATIONS INFORMATION
The ﬁrst bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The ﬁnal eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a read back command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and read back is not needed,
then SDO can be left ﬂoating and no pull-up resistor is
needed.
Table 4 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The ﬁrst serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset SPI
write command is complete, bit D7 is automatically set
back to zero.
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
RESET
Bit 7
X
RESET
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers are Reset to 00h. The ADC is Momentarily Placed in Sleep Mode.
This Bit is Automatically Set Back to Zero at the end of the SPI write command. The Reset register is write-only.
Data read back from the Reset register will be random.
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
DCSOFF
RAND
TWOSCOMP
SLEEP
NAP_2
X
X
NAP_1
Bit 7
DCSOFF
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This is not recommended.
Bit 6
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 5
TWOSCOMP
Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Bits 4, 3, 0
SLEEP:NAP_2:NAP_1 Sleep/Nap Mode Control Bits
000 = Normal Operation
0X1 = Channel 1 in Nap Mode
01X = Channel 2 in Nap Mode
1XX = Sleep Mode. Both Channels are Disabled.
Note: Any Combination of Channels Can Be Placed in Nap Mode
Bits 1, 2
Unused, Don’t Care Bits
2271f
19
LTC2271
APPLICATIONS INFORMATION
REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h)
D7
ILVDS2
D6
D5
D4
D3
D2
D1
D0
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTTEST
OUTMODE1
OUTMODE0
Bits 7-5
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 4
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 2× the Current Set by ILVDS2:ILVDS0
Bit 3
OUTOFF
Output Disable Bit
0 = Digital Outputs are Enabled
1 = Digital Outputs are Disabled
Bit 2
OUTTEST
Digital Output Test Pattern Control Bit
0 = Digital Output Test Pattern Off
1 = Digital Output Test Pattern On
Bits 1-0
OUTMODE1:OUTMODE0
00 = 2-Lane Output Mode
01 = 4-Lane Output Mode
10 = 1-Lane Output Mode
11 = Not Used
Digital Output Mode Control Bits
REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)
D7
D6
D5
D4
D3
D2
D1
D0
TP15
TP14
TP13
TP12
TP11
TP10
TP9
TP8
Bits 7-0
TP15:TP8
Test Pattern Data Bits (MSB)
TP15:TP8 Set the Test Pattern for Data Bit 15 (MSB) Through Data Bit 8.
REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)
D7
D6
D5
D4
D3
D2
D1
D0
TP7
TP6
TP5
TP4
TP3
TP2
TP1
TP0
Bits 7-0
TP7:TP0
Test Pattern Data Bits (LSB)
TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).
2271f
20
LTC2271
APPLICATIONS INFORMATION
GROUNDING AND BYPASSING
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground ﬁll and
grounded vias should be used as barriers to isolate these
signals from each other.
The LTC2271 require a printed circuit board with a clean
unbroken ground plane. A multilayer board with an internal ground plane in the ﬁrst layer beneath the ADC is
recommended. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
HEAT TRANSFER
Most of the heat generated by the LTC2271 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad must
be soldered to a large grounded pad on the PC board. This
pad should be connected to the internal ground planes by
an array of vias.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass
capacitors must be located as close to the pins as possible.
Size 0402 ceramic capacitors are recommended. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
Of particular importance is the capacitor between REFH
and REFL. This capacitor should be on the same side of
the circuit board as the A/D, and as close to the device
as possible.
TYPICAL APPLICATIONS
C4
2.2μF
SDO
42
43
41
OUT1B–
OUT1B+
OUT1A–
44
OUT1A+
45
GND
46
SDO
47
GND
48
VREF
49
GND
50
SENSE
VDD
FR+
PAR/SER
FR–
34
32
31
29
GND
OUT2B+
28
OUT2B
DIGITAL
OUTPUTS
C16 0.1μF
27
26
25
VCM2
OUT2C+
OUT2A–
OUT2C–
AIN2–
OUT2D+
30
OUT2D–
OUT2A+
–
OVDD
33
AIN2+
24
CN1: 2.2μF LOW INDUCTANCE
INTERDIGITATED CAPACITOR
TDK CLLE1AX7S0G225M
MURATA LLA219C70G225M
AVX W2L14Z225M
OR EQUIVALENT
REFL
GND
C37
1μF
OGND
23
14
REFH
SDI
13
OVDD
LTC2271
22
AIN2–
REFL
SCK
12
35
21
11
REFH
CS
PAR/SER
AIN2+
36
DCO–
20
9
10
GND
ENC
8
37
DCO+
19
7
OUT1D–
–
6
AIN1–
ENC
+
–
–
+
CN1 +
–
–
+
38
18
5
AIN1+
+
C2
1μF
AIN1–
39
OUT1D+
VDD
C3
1μF
4
GND
17
AIN1+
40
OUT1C–
VDD
3
OUT1C+
VCM1
16
2
15
1
VDD
52
C5
0.1μF
C29
1μF
51
SENSE
VDD
VDD
C7
0.1μF
ENCODE
INPUT
SPI
PORT
2271 TA02
2271f
21
LTC2271
TYPICAL APPLICATIONS
Top Side
Inner Layer 2
Inner Layer 3
Inner Layer 4
Inner Layer 5
Bottom Side
2271f
22
LTC2271
PACKAGE DESCRIPTION
UKG Package
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC DWG # 05-08-1729 Rev Ø)
7.50 p0.05
6.10 p0.05
5.50 REF
(2 SIDES)
0.70 p0.05
6.45 p0.05
6.50 REF 7.10 p0.05 8.50 p0.05
(2 SIDES)
5.41 p0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 p 0.10
(2 SIDES)
0.75 p 0.05
0.00 – 0.05
R = 0.115
TYP
5.50 REF
(2 SIDES)
51
52
0.40 p 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45oC
CHAMFER
6.45 p0.10
8.00 p 0.10
(2 SIDES)
6.50 REF
(2 SIDES)
5.41 p0.10
R = 0.10
TYP
TOP VIEW
0.200 REF
0.00 – 0.05
0.75 p 0.05
(UKG52) QFN REV Ø 0306
0.25 p 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
SIDE VIEW
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
2271f
23
LTC2271
TYPICAL APPLICATION
Integral Non-Linearity (INL)
1.8V
1.8V
2.0
OVDD
VDD
1.5
S/H
16-BIT
ADC CORE
CH2
ANALOG
INPUT
S/H
16-BIT
ADC CORE
ENCODE
INPUT
DATA
SERIALIZER
PLL
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
DATA CLOCK OUT
FRAME
1.0
SERIALIZED
LVDS
OUTPUTS
OGND
GND
INL ERROR (LSB)
CH1
ANALOG
INPUT
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0
2271 TA05
16384
32768
49152
OUTPUT CODE
65536
2271 TA06
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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45mW, 77dB SNR, 90dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs,
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LTC2188
16-Bit 20Msps, 1.8V Dual ADC, Ultralow Power 38mW/Ch, 77dB SNR, 90dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs,
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LTC2190
16-Bit 25Msps, 1.8V Dual ADC, Ultralow Power 52mW/Ch, 77dB SNR, 90dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52
LTC2202/LTC2203
16-Bit 10Msps/25Msps 3.3V ADCs
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LTC6946-X
Ultralow Noise and Spurious Integer-N
Synthesizer with Integrated VCO
3.7MHz to 5.7GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor, –157dBc/
Hz Wideband Output Phase Noise Floor
LTC6945
Ultralow Noise and Spurious 0.35GHz to 6GHz 3.5GHz to 6GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor, –157dBc/Hz
Integer-N Synthesizer
Wideband Output Phase Noise Floor
ADCs
PLLs
Signal Chain Receivers
LTM9002
14-Bit, Dual Channel IF/Baseband μModule
Receiver
Dual ADC, Dual Ampliﬁers, Anti-Alias Filters and a Dual Trim DAC in
15mm × 11.25mm LGA
LTM9004
14-Bit, Direct Conversion μModule Receiver
I/Q Demodulator, Baseband Ampliﬁers, Lowpass Filters Up to 20MHz, Dual 14-Bit
125Msps ADC in 22mm × 15mm LGA
RF Mixers/Demodulators
LTC5569
300MHz to 4GHz Dual Active Downconverting
Mixer
High IIP3: 26.8dBm, 2dB Conversion Gain, Low Power: 3.3V/600mW, Integrated RF
Transformer for compact Footprint
LTC5584
30MHz to 1.4GHz Wideband I/Q Demodulator
I/Q Demodulation Bandwidth >530MHz, 31dBm IIP3, IIP2 Adjustable to >80dBm,
DC Offset Adjustable to Zero, 45dB Image Rejection
LTC5585
700MHz to 3GHz Wideband I/Q Demodulator
I/Q Demodulation Bandwidth >530MHz, 25.7dBm IIP3, IIP2 Adjustable to >80dBm,
DC Offset Adjustable to Zero, 43dB Image Rejection
2271f
24 Linear Technology Corporation
LT 1012 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2012

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