Freescale MPC5602BEMLQR Mpc5604b/c microcontroller data sheet Datasheet

Document Number: MPC5604BC
Rev. 4, 08/2009
MPC5604B/C
MPC5604B/C
Microcontroller Data Sheet
•
Features:
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Single issue, 32-bit CPU core complex (e200z0)
— Compliant with the Power Architecture™
embedded category
— Includes an instruction set enhancement
allowing variable length encoding (VLE) for
code size footprint reduction. With the optional
encoding of mixed 16-bit and 32-bit
instructions, it is possible to achieve significant
code size footprint reduction.
Up to 512 Kbytes on-chip flash supported with the
flash controller
Up to 48 Kbytes on-chip SRAM
Memory protection unit (MPU) with 8 region
descriptors and 32-byte region granularity
Interrupt controller (INTC) with 148 interrupt
vectors, including 16 external interrupt sources and
18 external interrupt/wakeup sources
Frequency modulated phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus
masters
Boot assist module (BAM) supports internal flash
programming via a serial link (CAN or SCI)
Timer supports input/output channels providing a
range of 16-bit input capture, output compare, and
pulse width modulation functions (eMIOS-lite)
10-bit analog-to-digital converter (ADC)
3 serial peripheral interface (DSPI) modules
Up to 4 serial communication interface (LINFlex)
modules
QFN12
##_mm_x_##mm
SOT-343R
##_mm_x_##mm
PKG-TBD
## mm x ## mm
208 MAPBGA
(17 x 17 x 1.7 mm)
32-bit MCU family built on the Power Architecture™ for
automotive body electronics applications
•
MAPBGA–225
15 mm x 15 mm
•
•
•
•
•
•
100 LQFP
(14 x 14 x 1.4 mm)
Up to 6 enhanced full CAN (FlexCAN) modules
with configurable buffers
1 inter IC communication interface (I2C) module
Up to 123 configurable general purpose pins
supporting input and output operations (package
dependent)
Real Time Counter (RTC) with clock source from
128 kHz or 16 MHz internal RC oscillator
supporting autonomous wakeup with 1 ms
resolution with max timeout of 2 seconds
Up to 6 periodic interrupt timers (PIT) with 32-bit
counter resolution
1 System Module Timer (STM)
Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class Two Plus standard
Device/board boundary Scan testing supported with
per Joint Test Action Group (JTAG) of IEEE (IEEE
1149.1)
On-chip voltage regulator (VREG) for regulation of
input supply for all internal levels
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
TBD
144 LQFP
(20 x 20 x 1.4 mm)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Freescale Semiconductor
Data Sheet: Advance Information
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Device blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.2 Device block summary . . . . . . . . . . . . . . . . . . . . . . . . . .6
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .11
4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.3.1 NVUSRO[PAD3V5V] field description . . . . . . . .11
4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description
12
4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .12
4.5 Recommended operating conditions . . . . . . . . . . . . . .13
4.6 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .15
4.6.1 Package thermal characteristics . . . . . . . . . . . .15
4.6.2 Power considerations. . . . . . . . . . . . . . . . . . . . .15
4.7 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .16
4.7.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.7.2 I/O input DC characteristics . . . . . . . . . . . . . . . .17
4.7.3 I/O output DC characteristics. . . . . . . . . . . . . . .17
4.7.4 Output pin transition times . . . . . . . . . . . . . . . . .20
4.7.5 I/O pad current specification . . . . . . . . . . . . . . .21
4.8 nRSTIN electrical characteristics . . . . . . . . . . . . . . . . .23
4.9 Power management electrical characteristics. . . . . . . .25
4.9.1 Voltage regulator electrical characteristics . . . .25
4.9.2 Voltage monitor electrical characteristics. . . . . .27
4.10 Low voltage domain power consumption . . . . . . . . . . .28
4.11 Flash memory electrical characteristics . . . . . . . . . . . .29
4.11.1 Program/Erase characteristics . . . . . . . . . . . . . 29
4.11.2 Flash power supply DC characteristics . . . . . . 31
4.11.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 31
4.12 Electromagnetic compatibility (EMC) characteristics. . 32
4.12.1 Designing hardened software to avoid noise
problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.12.2 Electromagnetic interference (EMI) . . . . . . . . . 32
4.12.3 Absolute maximum ratings (electrical sensitivity)33
4.13 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.14 Slow external crystal oscillator (32 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.15 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 39
4.16 Fast internal RC oscillator (16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.17 Slow internal RC oscillator (128 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 42
4.18.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 44
4.18.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . 50
4.18.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 51
4.18.5 ADC electrical characteristics . . . . . . . . . . . . . 52
5 Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 60
6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Appendix A
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
MPC5604B/C Microcontroller Data Sheet, Rev. 4
2
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Table of Contents
1
General description
1.1
Introduction
The MPC5604B/C is a family of next generation microcontrollers built on the Power Architecture™ embedded category. This
document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the device1.
The MPC5604B/C family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers.
It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics
applications within the vehicle. The advanced and cost-efficient host processor core of the MPC5604B/C automotive controller
family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding)
APU, providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized
for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices
and is supported with software drivers, operating systems and configuration code to assist with users implementations.
Table 1. MPC5604B/C device comparison1
Device
Feature
MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560
2BxLL 2BxLQ 2CxLL 3BxLL 3BxLQ 3CxLL 4BxLL 4BxLQ 4BxMG 4CxLL
CPU
e200z0h
Execution
speed2
Static - 64 MHz
Code Flash
256 KB
384 KB
Data Flash
64 KB (4 × 16 KB)
RAM
24 KB
32 KB
28 KB
MPU
ADC
512 KB
40 KB
32 KB
48 KB
8-entry
28 ch,
10-bit
36 ch,
10-bit
28 ch, 10-bit
36 ch,
10-bit
CTU
28 ch,
10-bit
28 ch,
10-bit
36 ch,
10-bit
36 ch,
10-bit
28 ch,
10-bit
Yes
28 ch,
16-bit
56 ch,
16-bit
• PWM + MC
+ IC/OC4
5 ch
10 ch
5 ch
5 ch
10 ch
5 ch
5 ch
10 ch
10 ch
5 ch
• PWM +
IC/OC4
20 ch
40 ch
20 ch
20 ch
40 ch
20 ch
20 ch
40 ch
40 ch
20 ch
• IC/OC4
3 ch
6 ch
3 ch
3 ch
6 ch
3 ch
3 ch
6 ch
6 ch
3 ch
Total timer
I/O3
eMIOS
SCI (LINFlex)
3
28 ch, 16-bit
4
56ch,
16-bit
4
SPI (DSPI)
CAN
(FlexCAN)
28 ch, 16-bit
4
56 ch, 16-bit
4
28 ch,
16-bit
4
3
2
6
3
6
3
3
6
6
1.For a correct use of the datasheet, it’s recommended of referring to the errata sheet.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
General description
Table 1. MPC5604B/C device comparison1 (continued)
Device
Feature
MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560
2BxLL 2BxLQ 2CxLL 3BxLL 3BxLQ 3CxLL 4BxLL 4BxLQ 4BxMG 4CxLL
I2C
1
32 kHz
oscillator
GPIO5
Yes
79
123
79
Debug
Package
1
2
3
4
5
6
79
123
79
79
123
JTAG
100
LQFP
144
LQFP
100
LQFP
100
LQFP
144
LQFP
100
LQFP
100
LQFP
144
LQFP
123
79
Nexus2+
JTAG
208 MA
PBGA6
100
LQFP
Feature set dependent on selected peripheral multiplexing—table shows example implementation
Based on 105 °C ambient operating temperature
Refer to eMIOS section of device reference manual for information on the channel configuration and functions
IC - Input Capture; OC - Output Compare; PWM - Pulse Width Modulation; MC - Modulus counter
I/O count based on multiplexing with peripherals
208 MAPBGA available only as development package for Nexus2+
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
4
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
General description
2
Device blocks
2.1
Block diagram
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Device blocks
Figure 1 shows a top-level block diagram of the MPC5604B/C device series.
Figure 1. MPC5604B/C series block diagram
TCU
RAM
48 KB
Code Flash DataFlash
512 KB
64 KB
SRAM
Controller
Flash
Controller
JTAG
Instructions
Nexus Port
e200z0h
Nexus
(Master)
Data
NMI
Nexus 2+
(Master)
SIUL
Voltage
Regulator
Interrupt requests
from peripheral
blocks
NMI
INTC
Clocks
MPU
64-bit 2 x 3 Crossbar Switch
JTAG Port
(Slave)
(Slave)
(Slave)
MPU
Registers
CMU
FMPLL
RTC
STM
SWT
RGM
PIT
ECSM
CGM
MEM
PCU
BAM
SSCM
Peripheral Bridge
Interrupt
Request
SIUL
Reset Control
36 Ch.
ADC
CTU
2x
eMIOS
4x
LINFlex
3x
DSPI
6x
FlexCAN
I2C
External
Interrupt
Request
IMUX
GPIO &
Pad Control
I/O
...
...
...
...
...
Legend:
ADC
BAM
CAN
CGM
CMU
CTU
DSPI
eMIOS
FMPLL
I2C
IMUX
INTC
JTAG
LINFlex
Analog-to-Digital Converter
Boot Assist Module
Controller Area Network (FlexCAN)
Clock Generation Module
Clock Monitor Unit
Cross Triggering Unit
Deserial Serial Peripheral Interface
Enhanced Modular Input Output System
Frequency-Modulated Phase-Locked Loop
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
JTAG controller
Serial Communication Interface (LIN support)
MEM
MPU
Nexus
NMI
PCU
PIT
RGM
RTC
SIUL
SRAM
SSCM
STM
SWT
TCU
Mode Entry Module
Memory Protection Unit
NexuS Development Interface (NDI) Level
Non-Maskable Interrupt
Power Control Unit
Periodic Interrupt Timer
Reset Generation Module
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Test Control Unit
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
5
2.2
Device block summary
Table 2 summarizes the functions of all blocks present in the MPC5604B/C series of microcontrollers. Please note that the
presence and number of blocks varies by device and package.
Table 2. MPC5604B/C series block summary
Block
Function
Crossbar (XBAR) switch
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to digital-converter
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock generation module (CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Clock monitor unit (CMU)
Monitors clock source (internal and external) integrity
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices
(DSPI)
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol
FMPLL (frequency-modulated
phase-locked loop)
Generates high-speed system clocks and supports programmable frequency
modulation
Internal multiplexer (IMUX) SIU
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of
data exchange between devices
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINflex controller
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Memory protection unit (MPU)
Provides hardware access control for all memory references generated in a
device
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control unit,
reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Non-Maskable Interrupt (NMI)
Handles external events that must produce an immediate response, such as
power down detection
Nexus development interface
(NDI)
Provides real-time development support capabilities in compliance with the
IEEE-ISTO 5001-2003 standard
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
6
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Device blocks
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Device blocks
Table 2. MPC5604B/C series block summary (continued)
Block
Function
Periodic interrupt timer (PIT)
Produces periodic interrupts and triggers
Power control unit (PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Real-time counter (RTC)
A free running counter used for time keeping applications, the RTC can be
configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode)
Reset generation module (RGM)
Centralizes reset sources and manages the device reset sequence of the device
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
System integration unit (SIU)
Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status configuration
module (SSCM)
Provides system configuration and status data (such as memory size and status,
device mode and security status), device identification data, debug status port
enable and selection, and bus and peripheral abort enable/disable
System timer module (STM)
Provides a set of output compare events to support AUTOSAR and operating
system tasks
System watchdog timer (SWT)
Provides protection from runaway code
Test control unit (TCU)
An extension of the JTAG controller module, the TCU provides the means to test
chip functionality and connectivity while remaining transparent to system logic
when not in test mode.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
7
3
Package pinouts
The available LQFP pinouts and the 208 MAPBGA ballmap are provided in the following figures. For pin signal descriptions,
please refer to the device reference manual.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144 LQFP
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PA[11] / GPIO[11] / E0UC[11] / SCL
PA[10] / GPIO[10] / E0UC[10] / SDA
PA[9] / GPIO[9] / E0UC[9] / FAB
PA[8] / GPIO[8] / E0UC[8] / LIN3RX / EIRQ[3] / ABS[0]
PA[7] / GPIO[7] / E0UC[7] / LIN3TX / EIRQ[2]
PE[13] / GPIO[77] / SOUT2 / E1UC[20]
PF[14] / GPIO[94] / CAN1TX / CAN4TX / E1UC[27]
PF[15] / GPIO[95] / CAN1RX / CAN4RX / EIRQ[13]
VDD_HV
VSS_HV
PG[0] / GPIO[96] / CAN5TX / E1UC[23]
PG[1] / GPIO[97] / CAN5RX / E1UC[24] / EIRQ[14]
PH[3] / GPIO[115] / E1UC[5] / CS0_1
PH[2] / GPIO[114] / E1UC[4] / SCK1
PH[1] / GPIO[113] / E1UC[3] / SOUT1
PH[0] / GPIO[112] / E1UC[2] / SIN1
PG[12] / GPIO[108] / E0UC[26]
PG[13] / GPIO[109] / E0UC[27]
PA[3] / GPIO[3] / E0UC[3] / EIRQ[0]
PB[15] / GPIO[31] / CS4_0 / E0UC[7] / ANX[3]
PD[15] / GPIO[63] / CS2_1 / ANS[7] / E0UC[27]
PB[14] / GPIO[30] / CS3_0 / E0UC[6] / ANX[2]
PD[14] / GPIO[62] / CS1_1 / ANS[6] / E0UC[26]
PB[13] / GPIO[29] / CS2_0 / E0UC[5] / ANX[1]
PD[13] / GPIO[61] / CS0_1 / ANS[5] / E0UC[25]
PB[12] / GPIO[28] / CS1_0 / E0UC[4] / ANX[0]
PD[12] / GPIO[60] / CS5_0 / ANS[4] / E0UC[24]
PB[11] / GPIO[27] / E0UC[3] / ANS[3] / CS0_0
PD[11] / GPIO[59] / ANP[15]
PD[10] / GPIO[58] / ANP[14]
PD[9] / GPIO[57] / ANP[13]
PB[7] / GPIO[23] / ANP[3]
PB[6] / GPIO[22] / ANP[2]
PB[5] / GPIO[21] / ANP[1]
VDD_HV_ADC
VSS_HV_ADC
WKUP[12] / LIN1RX / GPIO[39] / PC[7]
GPIO[90] / PF[10]
WKUP[15] / GPIO[91] / PF[11]
WKUP[10] / SCK_0 / CS0_0 / GPIO[15] / PA[15]
WKUP[16] / E1UC[26] / GPIO[93] / PF[13]
EIRQ[4] / CS0_0 / SCK_0 / GPIO[14] / PA[14]
WKUP[9] / E0UC[4] / GPIO[4] / PA[4]
SOUT_0 / GPIO[13] / PA[13]
SIN_0 / GPIO[12] / PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
OSC32K_EXTAL / ANS[1] / GPIO[25] / PB[9]
OSC32K_XTAL / ANS[0] / GPIO[24] / PB[8]
WKUP[8] / ANS[2] / GPIO[26] / PB[10]
CS3_1 / ANS[8] / E0UC[10] / GPIO[80] / PF[0]
CS4_1 / ANS[9] / E0UC[11] / GPIO[81] / PF[1]
CS0_2 / ANS[10] / E0UC[12] / GPIO[82] / PF[2]
CS1_2 / AN1[11] / E0UC[13] / GPIO[83] / PF[3]
CS2_2 / ANS[12] / E0UC[14] / GPIO[84] / PF[4]
CS3_2 / ANS[13] / E0UC[22] / GPIO[85] / PF[5]
ANS[14] / E0UC[23] / GPIO[86] / PF[6]
ANS[15] / GPIO[87] / PF[7]
ANP[4] / GPIO[48] / PD[0]
ANP[5] / GPIO[49] / PD[1]
ANP[6] / GPIO[50] / PD[2]
ANP[7] / GPIO[51] / PD[3]
ANP[8] / GPIO[52] / PD[4]
ANP[9] / GPIO[53] / PD[5]
ANP[10] / GPIO[54] / PD[6]
ANP[11] / GPIO[55] / PD[7]
ANP[12] / GPIO[56] / PD[8]
ANP[0] / GPIO[20] / PB[4]
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
WKUP[11] / SCL / LIN0RX / GPIO[19] / PB[3]
WKUP[13] / LIN2RX / GPIO[41] / PC[9]
EIRQ[8] / SCK2 / E0UC[14] / GPIO[46] / PC[14]
CS0_2 / E0UC[15] / GPIO[47] / PC[15]
WKUP[18] / E1UC[14] / GPIO[101] / PG[5]
E1UC[13] / GPIO[100] / PG[4]
WKUP[17] / E1UC[12] / GPIO[99] / PG[3]
E1UC[11] / GPIO[98] / PG[2]
WKUP[3] / E0UC[2] / GPIO[2] / PA[2]
WKUP[6] / CAN5RX / E0UC[16] / GPIO[64] / PE[0]
WKUP[2] / NMI / E0UC[1] / GPIO[1] / PA[1]
CAN5TX / E0UC[17] / GPIO[65] / PE[1]
CAN3TX / E0UC[22] / CAN2TX / GPIO[72] / PE[8]
WKUP[7] / E0UC[23] / CAN3RX / CAN2RX / GPIO[73] / PE[9]
EIRQ[10] / CS3_1 / LIN3TX / GPIO[74] / PE[10]
WKUP[19] / CLKOUT / E0UC[0] / GPIO[0] / PA[0]
WKUP[14] / CS4_1 / LIN3RX / GPIO[75] / PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
SCK_2 / E1UC[18] / GPIO[105] / PG[9]
EIRQ[15] / CS0_2 / E1UC[17] / GPIO[104] / PG[8]
WKUP[5] / CAN4RX / CAN1RX / GPIO[43] / PC[11]
MA[1] / CAN4TX / CAN1TX / GPIO[42] / PC[10]
E1UC[16] / GPIO[103] / PG[7]
E1UC[15] / GPIO[102] / PG[6]
CAN0TX / GPIO[16] / PB[0]
WKUP[4] / CAN0RX / GPIO[17] / PB[1]
CS5_0 / CAN3RX / CAN2RX / GPIO[89] / PF[9]
CS4_0 / CAN3TX / CAN2TX / GPIO[88] / PF[8]
E1UC[25] / GPIO[92] / PF[12]
LIN1TX / GPIO[38] / PC[6]
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PB[2] / GPIO[18] / LIN0TX / SDA
PC[8] / GPIO[40] / LIN2TX
PC[13] / GPIO[45] / E0UC[13] / SOUT_2
PC[12] / GPIO[44] / E0UC[12] / SIN_2
PE[7] / GPIO[71] / E0UC[23] / CS2_0 / MA[0]
PE[6] / GPIO[70] / E0UC[22] / CS3_0 / MA[1]
PH[8] / GPIO[120] / E1UC[10] / CS2_2 / MA[0]
PH[7] / GPIO[119] / E1UC[9] / CS3_2 / MA[1]
PH[6] / GPIO[118] / E1UC[8] MA[2]
PH[5] / GPIO[117] / E1UC[7]
PH[4] / GPIO[116] / E1UC[6]
PE[5] / GPIO[69] / E0UC[21] / CS0_1 / MA[2]
PE[4] / GPIO[68] / E0UC[20] / SCK_1 / EIRQ[9]
PC[4] / GPIO[36] / SIN_1 / CAN3RX
PC[5] / GPIO[37] / SOUT_1 / CAN3TX / EIRQ[7]
PE[3] / GPIO[67] / E0UC[19] / SOUT_1
PE[2] / GPIO[66] / E0UC[18] / SIN_1
PH[9] / GPIO[121] / TCK
PC[0] / GPIO[32] / TDI
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1] / GPIO[33] / TDO
PH[10] / GPIO[122] / TMS
PA[6] / GPIO[6] / E0UC[6] / EIRQ[1]
PA[5] / GPIO[5] / E0UC[5]
PC[2] / GPIO[34] / SCK_1 / CAN4TX / EIRQ[5]
PC[3] / GPIO[35] / CS0_1 / MA[0] / CAN1RX / CAN4RX / EIRQ[6]
PG[11] / GPIO[107] / E0UC[25]
PG[10] / GPIO[106] / E0UC[24]
PE[15] / GPIO[79] / CS0_2 / E1UC[22]
PE[14] / GPIO[78] / SCK_2 / E1UC[21] / EIRQ[12]
PG[15] / GPIO[111] / E1UC[1]
PG[14] / GPIO[110] / E1UC[0]
PE[12] / GPIO[76] / SIN_2 / E1UC[19] / EIRQ[11]
Figure 2. LQFP 144-pin configuration (top view)
Note:
Availability of port pin alternate functions depends on product selection.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
8
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Package pinouts
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Package pinouts
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PB[2] / GPIO[18] / LIN0TX / SDA
PC[8] / GPIO[40] / LIN2TX
PC[13] / GPIO[45] / E0UC[13] / SOUT_2
PC[12] / GPIO[44] / E0UC[12] / SIN_2
PE[7] / GPIO[71] / E0UC[23] / CS2_0 / MA[0]
PE[6] / GPIO[70] / E0UC[22] / CS3_0 / MA[1]
PE[5] / GPIO[69] / E0UC[21] / CS0_1 / MA[2]
PE[4] / GPIO[68] / E0UC[20] / SCK_1 / EIRQ[9]
PC[4] / GPIO[36] / SIN1 / CAN3RX
PC[5] / GPIO[37] / SOUT_1 / CAN3TX / EIRQ[7]
PE[3] / GPIO[67] / E0UC[19] / SOUT_1
PE[2] / GPIO[66] / E0UC[18] / SIN_1
PH[9] / GPIO[121] / TCK
PC[0] / GPIO[32] / TDI
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1] / GPIO[33] / TDO
PH[10] / GPIO[122] / TMS
PA[6] / GPIO[6] / E0UC[6] / EIRQ[1]
PA[5] / GPIO[5] / E0UC[5]
PC[2] / GPIO[34] / SCK1 / CAN4TX / EIRQ[5]
PC[3] / GPIO[35] / CS0_1 / MA[0] / CAN1RX / CAN4RX / EIRQ[6]
PE[12] / GPIO[76] / SIN_2 / EIRQ[11]
Figure 3. LQFP 100-pin configuration (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100 LQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA[11] / GPIO[11] / E0UC[11] / SCL
PA[10] / GPIO[10] / E0UC[10] / SDA
PA[9] / GPIO[9] / E0UC[9] / FAB
PA[8] / GPIO[8] / E0UC[8] / LIN3RX / EIRQ[3] / ABS[0]
PA[7] / GPIO[7] / E0UC[7] / LIN3TX / EIRQ [2]
VDD_HV
VSS_HV
PA[3] / GPIO[3] / E0UC[3] / EIRQ[0]
PB[15] / GPIO[31] / CS4_0 / E0UC[7] / ANX[3]
PD[15] / GPIO[63] / CS2_1 / ANS[7] / E0UC[27]
PB[14] / GPIO[30] / CS3_ 0 / E0UC[6] / ANX[2]
PD[14] / GPIO[62] / CS1_1 / ANS[6] / E0UC[26]
PB[13] / GPIO[29] / CS2_0 / E0UC[5] / ANX[1]
PD[13] / GPIO[61] / CS0_1 / ANS[5] / E0UC[25]
PB[12] / GPIO[28] / CS1_0 / E0UC[4] / ANX[0]
PD[12] / GPIO[60] / CS5_0 / ANS[4] / E0UC[24]
PB[11] / GPIO[27] / E0UC[3] / ANS[3] / CS0_0
PD[11] / GPIO[59] / ANP[15]
PD[10] / GPIO[58] / ANP[14]
PD[9] / GPIO[57] / ANP[13]
PB[7] / GPIO[23] / ANP[3]
PB[6] / GPIO[22] / ANP[2]
PB[5] / GPIO[21] / ANP[1]
VDD_HV_ADC
VSS_HV_ADC
WKUP[12] / LIN1RX / GPIO[39] / PC[7]
WKUP[10] / SCK0 / CS0_0 / GPIO[15] / PA[15]
EIRQ[4] / CS0_0 / SCK0 / GPIO[14] / PA[14]
WKUP[9] / E0UC[4] / GPIO[4] / PA[4]
SOUT_0 / GPIO[13] / PA[13]
SIN_0 / GPIO[12] / PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
OSC32K_EXTAL / ANS[1] / GPIO[25] / PB[9]
OSC32K_XTAL / ANS[0] / GPIO[24] / PB[8]
WKUP[8] / ANS[2] / GPIO[26] / PB[10]
ANP[4] / GPIO[48] / PD[0]
ANP[5] / GPIO[49] / PD[1]
ANP[6] / GPIO[50] / PD[2]
ANP[7] / GPIO[51] / PD[3]
ANP[8] / GPIO[52] / PD[4]
ANP[9] / GPIO[53] / PD[5]
ANP[10] / GPIO[54] / PD[6]
ANP[11] / GPIO[55] / PD[7]
ANP[12] / GPIO[56] / PD[8]
ANP[0] / GPIO[20] / PB[4]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
WKUP[11] / SCL / LIN0RX / GPIO[19] / PB[3]
WKUP[13] / LIN2RX / GPIO[41] / PC[9]
EIRQ[8] / SCK2 / E0UC[14] / GPIO[46] / PC[14]
CS0_2 / E0UC[15] / GPIO[47] / PC[15]
WKUP[3] / E0UC[2] / GPIO[2] / PA[2]
WKUP[6] / CAN5RX / E0UC[16] / GPIO[64] / PE[0]
WKUP[2] / NMI / E0UC[1] / GPIO[1] / PA[1]
CAN5TX / E0UC[17] / GPIO[65] / PE[1]
CAN3TX / E0UC[22] /CAN2TX / GPIO[72] / PE[8]
WKUP[7] / CAN3RX / E0UC[23] /CAN2RX / GPIO[73] / PE[9]
EIRQ[10] / CS3_1 / LIN3TX / GPIO[74] / PE[10]
WKUP[19] / CLKOUT / E0UC[0] / GPIO[0] / PA[0]
WKUP[14] / CS4_1 / LIN3RX / GPIO[75] / PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
WKUP[5] / CAN4RX / CAN1RX / GPIO[43] / PC[11]
MA[1] / CAN4TX / CAN1TX / GPIO[42] / PC[10]
CAN0TX / GPIO[16] / PB[0]
WKUP[4] / CAN0RX / GPIO[17] / PB[1]
LIN1TX / GPIO[38] / PC[6]
Note:
Availability of port pin alternate functions depends on product selection.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
PC[8]
PC[13]
NC
NC
PH[8]
PH[4]
PC[5]
PC[0]
NC
NC
PC[2]
NC
PE[15]
NC
NC
NC
A
B
PC[9]
PB[2]
NC
PC[12]
PE[6]
PH[5]
PC[4]
PH[9]
PH[10]
NC
PC[3]
PG[11]
PG[15]
PG[14]
PA[11]
PA[10]
B
C
PC[14]
VDD_HV
PB[3]
PE[7]
PH[7]
PE[5]
PE[3]
VSS_LV
PC[1]
NC
PA[5]
NC
PE[14]
PE[12]
PA[9]
PA[8]
C
D
NC
NC
PC[15]
NC
PH[6]
PE[4]
PE[2]
VDD_LV
VDD_HV
NC
PA[6]
NC
PG[10]
PF[14]
PE[13]
PA[7]
D
E
PG[4]
PG[5]
PG[3]
PG[2]
PG[1]
PG[0]
PF[15]
VDD_HV
E
F
PE[0]
PA[2]
PA[1]
PE[1]
PH[0]
PH[1]
PH[3]
PH[2]
F
G
PE[9]
PE[8]
PE[10]
PA[0]
VSS_HV VSS_HV VSS_HV VSS_HV
VDD_HV
NC
NC
MSEO
G
H
VSS_HV
PE[11]
VDD_HV
NC
VSS_HV VSS_HV VSS_HV VSS_HV
MDO3
MDO2
MDO0
MDO1
H
J
RESET
VSS_LV
NC
NC
VSS_HV VSS_HV VSS_HV VSS_HV
NC
NC
NC
NC
J
K
EVTI
NC
VDD_BV
VDD_LV
VSS_HV VSS_HV VSS_HV VSS_HV
NC
PG[12]
PA[3]
PG[13]
K
L
PG[9]
PG[8]
NC
EVTO
PB[15]
PD[15]
PD[14]
PB[14]
L
M
PG[7]
PG[6]
PC[10]
PC[11]
PB[13]
PD[13]
PD[12]
PB[12]
M
N
PB[1]
PF[9]
PB[0]
NC
NC
PA[4]
VSS_LV
EXTAL
VDD_HV
PF[0]
PF[4]
NC
PB[11]
PD[10]
PD[9]
PD[11]
N
P
PF[8]
NC
PC[7]
NC
NC
PA[14]
VDD_LV
XTAL
PB[10]
PF[1]
PF[5]
PD[0]
PD[3]
VDD_HV
_ADC
PB[6]
PB[7]
P
R
PF[12]
PC[6]
PF[10]
PF[11]
VDD_HV
PA[15]
PA[13]
NC
OSC32K
_XTAL
PF[3]
PF[7]
PD[2]
PD[4]
PD[7]
VSS_HV
_ADC
PB[5]
R
T
NC
NC
NC
MCKO
NC
PF[13]
PA[12]
NC
OSC32K
_EXTAL
PF[2]
PF[6]
PD[1]
PD[5]
PD[6]
PD[8]
PB[4]
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Note: 208 MAPBGA available only as development package for Nexus 2+.
NC
= Not connected
Figure 4. 208 MAPBGA configuration
4
Electrical characteristics
4.1
Introduction
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by
the internal pull-up and pull-down, which is provided by the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
10
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
CAUTION
All of the following figures are indicative and must be confirmed during either silicon validation, silicon characterization or
silicon reliability trial.
4.2
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in Table 3 are used and the parameters are tagged accordingly in the tables where
appropriate.
Table 3. Parameter classifications
Classification tag
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
4.3
NVUSRO register
Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are
controlled via bit values in the Non-Volatile User Options Register (NVUSRO) register.
4.3.1
NVUSRO[PAD3V5V] field description
Table 4 shows how NVUSRO[PAD3V5V] controls the device configuration.
Table 4. PAD3V5V field description1
Value2
1
2
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
See the device reference manual for more information on the NVUSRO register.
'1' is delivery value. It is part of shadow Flash, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V bit value.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
11
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
4.3.2
NVUSRO[OSCILLATOR_MARGIN] field description
Table 5 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
Table 5. OSCILLATOR_MARGIN field description1
Value2
1
2
Description
0
Low consumption configuration (4 MHz/8 MHz)
1
High margin configuration (4 MHz/16 MHz)
See the device reference manual for more information on the NVUSRO register.
'1' is delivery value. It is part of shadow Flash, thus programmable by customer.
The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value.
4.4
Absolute maximum ratings
Table 6. Absolute maximum ratings
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
0
V
VDD
SR Voltage on VDD_HV pins with respect to
ground (VSS)
—
−0.3
6.0
V
VSS_LV
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground
(VSS)
—
VDD_BV
SR Voltage on VDD_BV pin (regulator
supply) with respect to ground (VSS)
—
Relative to VDD
VSS_ADC SR Voltage on VSS_HV_ADC (ADC
reference) pin with respect to ground
(VSS)
—
VDD_ADC SR Voltage on VDD_HV_ADC pin (ADC
reference) with respect to ground (VSS)
—
VIN
SR Voltage on any GPIO pin with respect to
ground (VSS)
VSS−0.1 VSS+0.1
−0.3
5.5
−0.3
VDD+0.3
VSS−0.1 VSS+0.1
−0.3
5.5
V
V
V
V
VDD −0.3 VDD+0.3
Relative to VDD
—
−0.3
5.5
V
VDD −0.3 VDD+0.3
Relative to VDD
IINJPAD
SR Injected input current on any pin during
overload condition
—
−10
10
IINJSUM
SR Absolute sum of all injected input
currents during overload condition
—
−50
50
—
70
—
64
—
—
150
mA
—
−55
150
°C
IAVGSEG SR Sum of all the static I/O current within a VDD = 5.0 V ± 10%, PAD3V5V = 0
supply segment
VDD = 3.3 V ± 10%, PAD3V5V = 1
ICORELV SR Low voltage static current sink through
VDD_BV
TSTORAGE SR Storage temperature
mA
mA
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
12
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. During overload conditions (VIN > VDD or
VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the
recommended values.
4.5
Recommended operating conditions
Table 7. Recommended operating conditions (3.3 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
0
V
VDD1
SR Voltage on VDD_HV pins with respect
to ground (VSS)
—
3.0
3.6
V
VSS_LV2
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground
(VSS)
—
VDD_BV3
SR Voltage on VDD_BV pin (regulator
supply) with respect to ground (VSS)
—
Relative to VDD
VSS_ADC
SR Voltage on VSS_HV_ADC (ADC
reference) pin with respect to ground
(VSS)
—
VDD_ADC4
SR Voltage on VDD_HV_ADC pin (ADC
reference) with respect to ground
(VSS)
—
VIN
SR Voltage on any GPIO pin with respect
to ground (VSS)
Relative to VDD
—
Relative to VDD
VSS−0.1 VSS+0.1
3.0
3.6
V
V
VDD−0.1 VDD+0.1
VSS−0.1 VSS+0.1
3.05
3.6
V
V
VDD−0.1 VDD+0.1
VSS−0.1
—
—
VDD+0.1
V
IINJPAD
SR Injected input current on any pin
during overload condition
—
−5
5
IINJSUM
SR Absolute sum of all injected input
currents during overload condition
—
−50
50
SR VDD slope to ensure correct power up6
—
—
0.25
V/µs
—
3
—
V/s
−40
125
°C
−40
150
TVDD
TA
SR Ambient temperature under bias
TJ
SR Junction temperature under bias
fCPU < 64 MHz
—
mA
1
100 nF capacitance needs to be provided between each VDD/VSS pair
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
3
100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
4
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
2
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
13
5
Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL,
device is reset.
6
Guaranteed by device validation
Table 8. Recommended operating conditions (5.0 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
0
V
VDD1
SR Voltage on VDD_HV pins with respect to
ground (VSS)
—
4.5
5.5
V
3.0
5.5
VSS_LV3
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground
(VSS)
VDD_BV4
SR Voltage on VDD_BV pin (regulator
supply) with respect to ground (VSS)
Voltage drop2
—
—
Voltage
drop(2)
Relative to VDD
VSS_ADC
SR Voltage on VSS_HV_ADC (ADC
reference) pin with respect to ground
(VSS
—
VDD_ADC5
SR Voltage on VDD_HV_ADC pin (ADC
reference) with respect to ground (VSS)
—
Voltage drop(2)
Relative to VDD
VIN
SR Voltage on any GPIO pin with respect to
ground (VSS)
—
Relative to VDD
VSS−0.1 VSS+0.1
4.5
5.5
3.0
5.5
V
V
VDD−0.1 VDD+0.1
VSS−0.1 VSS+0.1
4.5
5.5
3.0
5.5
V
V
VDD−0.1 VDD+0.1
VSS−0.1
—
—
VDD+0.1
V
IINJPAD
SR Injected input current on any pin during
overload condition
—
−5
5
IINJSUM
SR Absolute sum of all injected input
currents during overload condition
—
−50
50
SR VDD slope to ensure correct power up6
—
—
0.25
V/µs
—
3
—
V/s
−40
85
°C
−40
110
−40
105
−40
130
−40
125
−40
150
TVDD
TA C-Grade Part
SR Ambient temperature under bias
TJ C-Grade Part
SR Junction temperature under bias
TA V-Grade Part
SR Ambient temperature under bias
TJ V-Grade Part
SR Junction temperature under bias
TA M-Grade Part
SR Ambient temperature under bias
TJ M-Grade Part
SR Junction temperature under bias
fCPU < 64 MHz
—
fCPU < 64 MHz
—
fCPU < 60 MHz
—
mA
1
100 nF capacitance needs to be provided between each VDD/VSS pair.
Full device operation is guaranteed by design when the voltage drops below 4.5V down to 3.6V. However, certain analog
electrical characteristics will not be guaranteed to stay within the stated limits.
3 330 nF capacitance needs to be provided between each V
DD_LV/VSS_LV supply pair.
2
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
4
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
5
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
6
Guaranteed by device validation
NOTE
RAM data retention is guaranteed with VDD_LV not below 1.08 V.
4.6
Thermal characteristics
4.6.1
Package thermal characteristics
Table 9. LQFP thermal characteristics1
Symbol
RθJA CC
C
D
Conditions2
Parameter
Thermal resistance,
junction-to-ambient natural
convection4
Single-layer board—1s
Four-layer board—2s2p
Pin
count
Value3
Unit
Min
Typ
Max
100
—
—
64
144
—
—
64
100
—
—
50.8
144
—
—
49.4
°C/W
1
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C.
3 All values need to be confirmed during device validation.
4 Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA.
2
Table 10. 208 MAPBGA thermal characteristics1
Symbol
C
Parameter
Conditions
RθJA CC — Thermal resistance, junction-to-ambient natural Single-layer board—1s
convection2
Four-layer board—2s2p
1
2
Value
Unit
TBD
°C/W
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA.
4.6.2
Power considerations
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1:
TJ = TA + (PD x RθJA)
Eqn. 1
Where:
TA is the ambient temperature in °C.
RθJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PI/O (PD = PINT + PI/O).
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
15
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Electrical characteristics
PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power.
PI/O represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device
is configured to continuously drive external modules and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
PD = K / (TJ + 273 °C)
Eqn. 2
K = PD x (TA + 273 °C) + RθJA x PD2
Eqn. 3
Therefore, solving equations 1 and 2:
Where:
K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations 1 and 2
iteratively for any value of TA.
4.7
4.7.1
I/O pad electrical characteristics
I/O pad types
The device provides four main I/O pad types depending on the associated alternate functions:
•
•
•
•
Slow pads—These pads are the most common pads, providing a good compromise between transition time and low
electromagnetic emission.
Medium pads—These pads provide transition fast enough for the serial communication channels with controlled
current to reduce electromagnetic emission.
Fast pads—These pads provide maximum speed. There are used for improved Nexus debugging capability.
Input only pads—These pads are associated to ADC channels and 32 kHz slow external crystal oscillator providing
low input leakage.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
4.7.2
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Electrical characteristics
I/O input DC characteristics
Table 11 provides input DC electrical characteristics as described in Figure 5.
Figure 5. I/O input DC electrical characteristics definition
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
Table 11. I/O input DC electrical characteristics
Symbol
C
Value2
Conditions1
Parameter
Unit
Min
Typ
Max
VIH
SR P Input high level CMOS (Schmitt
Trigger)
—
0.65VDD
—
VDD+0.4
VIL
SR P Input low level CMOS (Schmitt
Trigger)
—
−0.4
—
0.35VDD
—
0.1VDD
—
—
TA = −40 °C
—
2
—
TA = 25 °C
—
2
—
D
TA = 105 °C
—
12
500
P
TA = 125 °C
—
70
1000
—
—
—
40
ns
—
1000
—
—
ns
VHYS CC C Input hysteresis CMOS (Schmitt
Trigger)
ILKG CC P Digital input leakage
P
WFI
No injection
on adjacent
pin
SR P Digital input filtered pulse
WNFI SR P Digital input not filtered pulse
1
2
4.7.3
V
nA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
•
•
Table 12 provides weak pull figures. Both pull-up and pull-down resistances are supported.
Table 13 provides output driver characteristics for I/O pads when in SLOW configuration.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
17
•
•
Table 14 provides output driver characteristics for I/O pads when in MEDIUM configuration.
Table 15 provides output driver characteristics for I/O pads when in FAST configuration.
Table 12. I/O pull-up/pull-down DC electrical characteristics
Symbol
C
|IWPU| CC P Weak pull-up current
absolute value
C
2
Typ
Max
10
—
150
10
—
250
VIN = VIL, VDD = 3.3 V ± 10% PAD3V5V = 1
10
—
150
VIN = VIH, VDD = 5.0 V ± 10% PAD3V5V = 0
10
—
150
PAD3V5V = 1
10
—
250
VIN = VIH, VDD = 3.3 V ± 10% PAD3V5V = 1
10
—
150
PAD3V5V =
|IWPD| CC P Weak pull-down current
absolute value
C
P
Unit
Min
VIN = VIL, VDD = 5.0 V ± 10% PAD3V5V = 0
P
1
Value
Conditions1
Parameter
12
µA
µA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 13. SLOW configuration output buffer electrical characteristics
Symbol C
Parameter
Typ
Max
Push Pull IOH = −2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
0.8VDD
—
—
C
IOH = −2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
0.8VDD
—
—
C
IOH = −1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
VDD−0.8
—
—
—
—
0.1VDD
VOL CC P Output low level
SLOW configuration
2
Unit
Min
VOH CC P Output high level
SLOW configuration
1
Value
Conditions1
Push Pull IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
C
IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V =
1(2)
—
—
0.1VDD
C
IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
V
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
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from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
Table 14. MEDIUM configuration output buffer electrical characteristics
Symbol C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
Push Pull IOH = −3.8 mA,
VOH CC C Output high level
MEDIUM configuration
VDD = 5.0 V ± 10%, PAD3V5V = 0
0.8VDD
—
—
P
IOH = −2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
0.8VDD
—
—
C
IOH = −1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
0.8VDD
—
—
C
IOH = −1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
VDD−0.8
—
—
C
IOH = −100 µA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
0.8VDD
—
—
VOL CC C Output low level
Push Pull IOL = 3.8 mA,
MEDIUM configuration
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
0.2VDD
P
IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
C
IOL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
—
—
0.1VDD
C
IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
C
IOH = 100 µA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
0.1VDD
1
2
V
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
19
Table 15. FAST configuration output buffer electrical characteristics
Symbol C
Typ
Max
IOH = −14mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
0.8VDD
—
—
C
IOH = −7mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
0.8VDD
—
—
C
IOH = −11mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
VDD−0.8
—
—
IOL = 14mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
C
IOL = 7mA,
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
—
—
0.1VDD
C
IOL = 11mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
VOL CC P Output low level
FAST configuration
2
Unit
Min
VOH CC P Output high level
FAST configuration
1
Value
Conditions1
Parameter
Push
Pull
Push
Pull
V
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
4.7.4
Output pin transition times
Table 16. Output pin transition times
Symbol
C
Ttr CC D Output transition time output pin3
SLOW configuration
T
CL = 25 pF
CL = 50 pF
D
CL = 100 pF
D
CL = 25 pF
T
CL = 50 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF
D
Ttr CC D Output transition time output
MEDIUM configuration
T
Value2
Conditions1
Parameter
pin(3)
CL = 25 pF
CL = 50 pF
D
CL = 100 pF
D
CL = 25 pF
T
CL = 50 pF
D
CL = 100 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
Unit
Min
Typ
Max
—
—
50
—
—
100
—
—
125
—
—
50
—
—
100
—
—
125
—
—
10
—
—
20
—
—
40
—
—
12
—
—
25
—
—
40
ns
ns
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
Table 16. Output pin transition times (continued)
Symbol
C
Value2
1
Parameter
Conditions
Ttr CC D Output transition time output pin(3) CL = 25 pF
FAST configuration
CL = 50 pF
Unit
VDD = 5.0 V ± 10%,
PAD3V5V = 0
CL = 100 pF
CL = 25 pF
CL = 50 pF
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF
Min
Typ
Max
—
—
4
—
—
6
—
—
12
—
—
4
—
—
7
—
—
12
ns
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 C includes device and package capacitances (C
L
PKG < 5 pF).
1
2
4.7.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as
described in Table 17.
Table 18 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG
maximum value.
In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain
below the IDYNSEG maximum value.
Table 17. I/O supply segment
Supply segment
Package
1
208 MAPBGA1
1
2
3
4
Equivalent to 144 LQFP segment pad distribution
144 LQFP
pin20–pin49
pin51–pin99
100 LQFP
pin16–pin35
pin37–pin69
pin100–pin122 pin 123–pin19
pin70–pin83
pin 84–pin15
5
6
MCKO
MDOn/MSEO
—
—
—
—
208 MAPBGA available only as development package for Nexus2+
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
21
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Electrical characteristics
Table 18. I/O consumption
Symbol
IDYNSEG
ISWTSLW,3
ISWTMED(3)
ISWTFST(3)
IRMSSLW
C
Max
—
—
110
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
65
CC D Dynamic I/O current
for SLOW
configuration
CL = 25 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
20
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
16
CC D Dynamic I/O current CL = 25 pF
for MEDIUM
configuration
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
29
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
17
CC D Dynamic I/O current CL = 25 pF
for FAST
configuration
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
110
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
50
CC D Root medium square CL = 25 pF, 2 MHz
I/O current for SLOW
CL = 25 pF, 4 MHz
configuration
CL = 100 pF, 2 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
2.3
—
—
3.2
—
—
6.6
—
—
1.6
—
—
2.3
—
—
4.7
—
—
6.6
—
—
13.4
—
—
18.3
—
—
5
—
—
8.5
—
—
11
—
—
22
—
—
33
—
—
56
—
—
14
—
—
20
CL = 100 pF, 40 MHz
—
—
35
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
70
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
65
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 2 MHz
CC D Root medium square CL = 25 pF, 13 MHz VDD = 5.0 V ± 10%,
I/O current for
PAD3V5V = 0
CL = 25 pF, 40 MHz
MEDIUM
configuration
CL = 100 pF, 13 MHz
CL = 25 pF, 13 MHz
CL = 25 pF, 40 MHz
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 13 MHz
CC D Root medium square CL = 25 pF, 40 MHz VDD = 5.0 V ± 10%,
I/O current for FAST
PAD3V5V = 0
CL = 25 pF, 64 MHz
configuration
CL = 100 pF, 40 MHz
CL = 25 pF, 40 MHz
CL = 25 pF, 64 MHz
IAVGSEG
Typ
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 25 pF, 4 MHz
IRMSFST
Unit
Min
SR D Sum of all the
dynamic and static
I/O current within a
supply segment
CL = 25 pF, 2 MHz
IRMSMED
Value2
Conditions1
Parameter
SR D Sum of all the static
I/O current within a
supply segment
VDD = 3.3 V ± 10%,
PAD3V5V = 1
mA
mA
mA
mA
mA
mA
mA
mA
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
22
Freescale Semiconductor
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from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
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from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3
Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
1
2
4.8
nRSTIN electrical characteristics
The device implements a dedicated bidirectional RESET pin.
Figure 6. Start-up reset requirements
VDD
VDDMIN
nRSTIN
VIH
VIL
device reset forced by nRSTIN
device start-up phase
Figure 7. Noise filtering on reset signal
VRSTIN
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
23
Table 19. Reset electrical characteristics
Symbol
C
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
VIH
SR P Input High Level CMOS
(Schmitt Trigger)
—
0.65VDD
—
VDD+0.4
V
VIL
SR P Input low Level CMOS
(Schmitt Trigger)
—
−0.4
—
0.35VDD
V
VHYS
CC C Input hysteresis CMOS
(Schmitt Trigger)
—
0.1VDD
—
—
V
VOL
CC P Output low level
Push Pull, IOL = 2mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
V
Push Pull, IOL = 1mA,
VDD = 5.0 V ± 10%, PAD3V5V = 13
—
—
0.1VDD
Push Pull, IOL = 1mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
CL = 25pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
10
CL = 50pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
20
CL = 100pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
40
CL = 25pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
12
CL = 50pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
25
CL = 100pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
40
WFRST SR P nRSTIN input filtered
pulse
—
—
—
40
ns
WNFRST SR P nRSTIN input not filtered
pulse
—
1000
—
—
ns
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
—
150
µA
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
—
150
VDD = 5.0 V ± 10%, PAD3V5V = 15
10
—
250
Ttr
CC D Output transition time
output pin4
MEDIUM configuration
|IWPU| CC P Weak pull-up current
absolute value
ns
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3
This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
the device reference manual).
4
CL includes device and package capacitance (CPKG < 5 pF).
5 The configuration PAD3V5 = 1 when V
DD = 5 V is only transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
1
2
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
24
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Electrical characteristics
4.9
Power management electrical characteristics
4.9.1
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage
ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved:
•
•
•
HV—High voltage external power supply for voltage regulator module. This must be provided externally through VDD
power pin.
BV—High voltage external power supply for internal ballast module. This must be provided externally through
VDD_BV power pin. Voltage values should be aligned with VDD.
LV—Low voltage internal power supply for core, FMPLL and flash digital logic. This is generated by the internal
voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure
noise isolation between critical LV modules within the device:
— LV_COR—Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding.
— LV_CFLA—Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_DFLA—Low voltage supply for data flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_PLL—Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
Figure 8. Voltage regulator capacitance connection
CREG2 (LV_COR/LV_CFLA)
GND
VDD
VSS_LV
VDD_BV
Voltage Regulator
I
VSS_LVn
VDD_BV
CREG1 (LV_COR/LV_DFLA)
VDD_LVn
CDEC1 (Ballast decoupling)
VREF
VDD_LV
VDD_LV
DEVICE
VSS_LV
GND
VSS_LV
DEVICE
GND
VSS
VDD_LV
VDD
GND
CREG3 (LV_COR/LV_PLL)
CDEC2 (supply/IO decoupling)
The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable
low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins.
Care should also be taken to limit the serial inductance of the board to less than 5 nH.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
25
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Electrical characteristics
Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see
Section 4.5, “Recommended operating conditions).
Table 20. Voltage regulator electrical characteristics
Symbol
C
Parameter
Typ
Max
SR — Internal voltage regulator external
capacitance
—
200
—
330
nF
RREG
SR — Stability capacitor equivalent serial
resistance
—
—
—
0.2
Ω
CDEC1
SR — Decoupling capacitance3 ballast
VDD_BV/VSS_LV pair
400
4704
—
nF
CDEC2
SR — Decoupling capacitance regulator
supply
VDD/VSS pair
10
100
—
nF
VMREG
CC P Main regulator output voltage
Before trimming
—
1.32
—
V
After trimming
—
1.28
—
—
—
150
mA
mA
IMREGINT
SR — Main regulator current provided to
VDD_LV domain
—
CC D Main regulator module current
consumption
IMREG = 200 mA
—
—
2
IMREG = 0 mA
—
—
1
VLPREG
CC P Low power regulator output voltage
After trimming
—
1.23
—
V
ILPREG
SR — Low power regulator current provided
to VDD_LV domain
—
—
15
mA
—
—
600
µA
ILPREG = 0 mA;
TA = 55 °C
—
5
TBD
Post trimming
—
1.23
—
V
—
—
5
mA
IULPREG = 5 mA;
TA = 55 °C
—
—
100
µA
IULPREG = 0 mA;
TA = 55 °C
—
2
TBD
CC D Main LVDs and reference current
consumption (low power and main
regulator switched off)
TA = 55 °C
—
17
—
µA
CC D Main LVD current consumption
(switch-off during standby)
TA = 55 °C
—
2
TBD
µA
—
—
4005
mA
ILPREGINT
VULPREG
CC P Ultra low power regulator output
voltage
IULPREG
SR — Ultra low power regulator current
provided to VDD_LV domain
IULPREGINT
CC D Ultra low power regulator module
current consumption
IVREGREF
IVREDLVD12
IDD_BV
—
CC D Low power regulator module current ILPREG = 15 mA;
consumption
TA = 55 °C
—
2
Unit
Min
CREGn
IMREG
1
Value2
Conditions1
CC D In-rush current on VDD_BV during
power-up
—
—
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
3
This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage.
A typical value is in the range of 470 nF.
4
External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV
in operating range.
5
In-rush current is seen only for short time during power-up and on standby exit (max 20µs, depending on external
capacitances to be load)
4.9.2
Voltage monitor electrical characteristics
The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well as four low voltage
detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied:
•
•
•
•
•
POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state
LVDHV3 monitors VDD to ensure device reset below minimum functional supply
LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range
LVDLVCOR monitors power domain No. 1
LVDLVBKP monitors power domain No. 0
NOTE
When enabled, power domain No. 2 is monitored through LVD_DIGBKP.
Figure 9. Low voltage monitor vs reset
VDD
VLVDHVxH
VLVDHVxL
RESET
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
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Electrical characteristics
Table 21. Low voltage monitor electrical characteristics
Symbol
C
VPORUP
SR P Supply for functional POR module
VPORH
CC P Power-on reset threshold
Value2
Conditions1
Parameter
Unit
Min
Typ
Max
1.0
—
5.5
1.5
—
2.6
TA = 25 °C,
after trimming
VLVDHV3H
CC T LVDHV3 low voltage detector high threshold
—
—
2.95
VLVDHV3L
CC P LVDHV3 low voltage detector low threshold
2.7
—
2.9
VLVDHV5H
CC T LVDHV5 low voltage detector high threshold
—
—
4.5
VLVDHV5L
CC P LVDHV5 low voltage detector low threshold
3.8
—
4.4
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold
1.07
—
1.11
VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold
1.07
—
1.11
1
2
4.10
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
Low voltage domain power consumption
Table 22 provides DC electrical characteristics for significant application modes. These values are indicative values; actual
consumption depends on the application.
Table 22. Low voltage power domain electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
IDDMAX2
CC D RUN mode maximum
average current
—
—
115
1403
mA
IDDRUN4
CC T RUN mode typical average
current5
P
—
—
60
80
mA
—
—
TBD
TBD
—
—
8
TBD
mA
µA
IDDHALT
IDDSTOP
IDDSTDBY2
CC P HALT mode
current6
CC P STOP mode
current7
—
180
D
Slow internal RC oscillator TA = 25 °C
(128 kHz) running
TA = 55 °C
7008
—
500
—
D
TA = 85 °C
—
1
—
D
TA = 105 °C
—
2
—
P
TA = 125 °C
—
4.5
TBD(8)
CC P STANDBY2 mode current9 Slow internal RC oscillator TA = 25 °C
(128 kHz) running
D
TA = 55 °C
—
30
100
—
TBD
—
D
TA = 85 °C
—
—
D
TA = 105 °C
—
—
P
TA = 125 °C
—
TBD
mA
µA
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
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Electrical characteristics
Table 22. Low voltage power domain electrical characteristics (continued)
Symbol
IDDSTDBY1
C
Value
Conditions1
Parameter
Unit
Min
Typ
Max
Slow internal RC oscillator TA = 25 °C
(128 kHz) running
TA = 55 °C
—
20
60
—
TBD
—
D
TA = 85 °C
—
—
D
TA = 105 °C
—
—
D
TA = 125 °C
—
CC T STANDBY1 mode
current10
D
280
µA
TBD
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
Running consumption is given on voltage regulator supply (VDDREG). It does not include consumption linked to I/Os
toggling. This value is highly dependent on the application. The given value is thought to be a worst case value with
all peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to be
noticed that this value can be significantly reduced by application: switch-off not used peripherals (default), reduce
peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when
possible.
3 Higher current may be sinked by device during power-up and standby exit. please refer to in rush current on Table 20.
4 RUN current measured with typical application with accesses on both flash and RAM.
5 Only for the “P” classification: Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPi as Master,
PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic
SW/WDG timer reset enabled.
6 Data Flash Power Down. Code Flash in Low Power. RC-osc128kHz & RC-OSC 16MHz on. 10MHz XTAL clock.
FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex:
instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON
(16 channels on PA[0]-PA[11] and PC[12]-PC[15]) with PWM 20KHz, instance: 1 clock gated. DSPI: instance: 0
(clocked but no communication). RTC/API ON.PIT ON. STM ON. ADC ON but not conversion except 2 analogue
watchdog
7 Only for the “P” classification: No clock, RC 16MHz off, RC128kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All
possible peripherals off and clock gated. Flash in power down mode.
8 When going from RUN to STOP mode and the core consumption is > 6 mA , it is normal operation for the main
regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction
temperatures exceeding 125 °C and under these circumstances , it is possible for the current to initially exceed the
maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to
the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA.
9
Only for the “P” classification: ULPreg on, HP/LPVreg off, 32kB RAM on, device configured for minimum
consumption, all possible modules switched-off.
10
ULPreg on, HP/LPVreg off, 8kB RAM on, device configured for minimum consumption, all possible modules
switched-off.
1
2
4.11
4.11.1
Flash memory electrical characteristics
Program/Erase characteristics
Table 23 shows the program and erase characteristics.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
29
Table 23. Program and erase specifications
Value
Symbol
C
Parameter
Unit
Min
Typ1
Initial
max2
Max3
Tdwprogram CC C Double word (64 bits) program time4
—
22
TBD
500
µs
T16Kpperase
16 KB block pre-program and erase time
—
300
500
5000
ms
T32Kpperase
32 KB block pre-program and erase time
—
400
600
5000
ms
T128Kpperase
128 KB block pre-program and erase time
—
800
1300
7500
ms
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3
The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4 Actual hardware programming times. This does not include software overhead.
Table 24. Flash module life
Value
Symbol
C
Parameter
2
Unit
Min
Typ
—
P/E
CC C Number of program/erase cycles per
block for 16 Kbyte blocks over the
operating temperature range (TJ)
—
100,000
P/E
CC C Number of program/erase cycles per
block for 32 Kbyte blocks over the
operating temperature range (TJ)
—
10,000
100,0001 cycles
P/E
CC C Number of program/erase cycles per
block for 128 Kbyte blocks over the
operating temperature range (TJ)
—
1,000
100,000(1) cycles
Retention CC C Minimum data retention at 85 °C
average ambient temperature2
1
Conditions
cycles
Blocks with 0–1,000 P/E
cycles
20
—
years
Blocks with 10,000 P/E
cycles
10
—
years
Blocks with 100,000 P/E
cycles
1–5
—
years
To be confirmed
Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results.
Some units will experience single bit corrections throughout the life of the product with no impact to product
reliability.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
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from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
Table 25. Flash read access timing
Symbol
4.11.2
Conditions1
Parameter
Max
Unit
2 wait states
64
MHz
C
1 wait state
40
C
0 wait states
20
CC P Maximum frequency for Flash reading
fREAD
1
C
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
Flash power supply DC characteristics
Table 26 shows the power supply DC characteristics on external supply.
Table 26. Flash power supply DC electrical characteristics
Symbol
C
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
IFREAD CC D Sum of the current consumption on VDDHV Flash module read
fCPU = 64 MHz3
and VDDBV on read access
—
—
33
mA
IFMOD
CC D Sum of the current consumption on VDDHV Program/Erase on-going
and VDDBV on matrix modification
while reading Flash registers
(program/erase)
fCPU = 64 MHz(3)
—
—
33
mA
IFLPW
CC D Sum of the current consumption on VDDHV
and VDDBV during Flash low-power mode
—
—
900
µA
IFPWD
CC D Sum of the current consumption on VDDHV
and VDDBV during Flash powe-down mode
—
—
150
µA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 f
CPU 64 MHz can be achieved only at up to 105 °C
1
2
4.11.3
Start-up/Switch-off timings
Table 27. Start-up time/Switch-off time
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
TFLARSTEXIT
CC T Delay for Flash module to exit reset mode
—
—
—
125
TFLALPEXIT
CC T Delay for Flash module to exit low-power
mode
—
—
—
0.5
TFLAPDEXIT
CC T Delay for Flash module to exit power-down
mode
—
—
—
30
TFLALPENTRY CC T Delay for Flash module to enter low-power
mode
—
—
—
0.5
TFLAPDENTRY CC T Delay for Flash module to enter power-down
mode
—
—
—
1.5
µs
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
31
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
1
4.12
Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.12.1
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified
MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in
particular.
Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC
level requested for his application.
Software recommendations − The software flowchart must include the management of runaway conditions such as:
— Corrupted program counter
— Unexpected reset
— Critical data corruption (control registers...)
Prequalification trials − Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the
software can be hardened to prevent unrecoverable errors occurring.
•
•
4.12.2
Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC 61967-1
standard, which specifies the general conditions for EMI measurements.
Table 28. EMI radiated emission measurement1,2
Value
Symbol
C
Parameter
Conditions
Unit
Min
—
fCPU
Max
S — Scan range
R
—
0.15
0
S — Operating frequency
R
—
—
64
—
MHz
—
—
1.28
—
V
—
—
18
dBµ
V
—
—
143
dBµ
V
VDD_L S — LV operating
R
voltages
V
SEMI
Typ
C T Peak level
C
No PLL frequency
VDD = 5 V, TA = 25 °C,
modulation
LQFP144 package
Test conforming to IEC 61967-2,
± 2% PLL
fOSC = 8 MHz/fCPU = 64 MHz
frequency
modulation
1000 MHz
1
EMI testing and I/O port waveforms per IEC 61967-1, -2, -4
For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your
local marketing representative.
3 All values need to be confirmed during device validation
2
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
4.12.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine
its performance in terms of electrical sensitivity.
4.12.3.1
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This
test conforms to the AEC-Q100-002/-003/-011 standard.
Table 29. ESD absolute maximum ratings1 2
Symbol
C
Ratings
Conditions
Class
Max value
Unit
V
VESD(HBM) CC T Electrostatic discharge voltage
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
H1C
2000
VESD(MM) CC T Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
VESD(CDM) CC T Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
500
750 (corners)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
4.12.3.2
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 30. Latch-up results
Symbol
LU
4.13
CC
C
Parameter
T Static latch-up class
Conditions
TA = 125 °C
conforming to JESD 78
Class
II level A
Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure 10 describes a simple model of the internal oscillator driver and
provides an example of a connection for an oscillator or a resonator.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
33
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Electrical characteristics
Table 31 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations.
Figure 10. Crystal oscillator and resonator connection scheme
EXTAL
C1
Crystal
EXTAL
XTAL
C2
DEVICE
VDD
I
R
EXTAL
XTAL
Resonator
DEVICE
XTAL
DEVICE
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
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from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
Table 31. Crystal description
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Load on
xtalin/xtalout
C1 = C2
(pF)1
Shunt
capacitance
between
xtalout
and xtalin
C02 (pF)
Nominal
frequency
(MHz)
NDK crystal
reference
Crystal
equivalent
series
resistance
ESR Ω
4
NX8045GB
300
2.68
591.0
21
2.93
8
NX5032GA
300
2.46
160.7
17
3.01
10
150
2.93
86.6
15
2.91
12
120
3.11
56.5
15
2.93
16
120
3.90
25.3
10
3.00
1
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing
includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
2 The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,
package, etc.).
Figure 11. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
S_MTRANS bit (ME_GS register)
‘1’
‘0’
VXTAL
1/fFXOSC
VFXOSC
90%
VFXOSCOP
10%
TFXOSCSU
valid internal clock
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
35
Table 32. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Symbol
C
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
fFXOSC
SR — Fast external crystal
oscillator frequency
—
4.0
—
16.0
MHz
gmFXOSC
CC C Fast external crystal
oscillator
transconductance
VDD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 0
2.2
—
8.2
mA/V
CC P
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 0
2.0
—
7.4
CC C
VDD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 1
2.7
—
9.7
CC C
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 1
2.5
—
9.2
CC T Oscillation amplitude at
EXTAL
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
1.3
—
—
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
1.3
—
—
—
—
0.95
VFXOSC
VFXOSCOP CC P Oscillation operating point
V
V
IFXOSC,3
CC T Fast external crystal
oscillator consumption
—
—
2
3
mA
TFXOSCSU
CC T Fast external crystal
oscillator start-up time
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
—
—
6
ms
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
—
—
1.8
VIH
SR P Input high level CMOS
(Schmitt Trigger)
Oscillator bypass mode
0.65VDD
—
VDD+0.4
V
VIL
SR P Input low level CMOS
(Schmitt Trigger)
Oscillator bypass mode
−0.4
—
0.35VDD
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 Stated values take into account only analog module consumption but not the digital contributor (clock tree and
enabled peripherals)
1
2
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
36
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from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
4.14
Slow external crystal oscillator (32 kHz) electrical characteristics
The device provides a low power oscillator/resonator driver.
Figure 12. Crystal oscillator and resonator connection scheme
OSC32K_EXTAL
OSC32K_EXTAL
Crystal
Resonator
C1
OSC32K_XTAL
OSC32K_XTAL
C2
DEVICE
DEVICE
NOTE
OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.
Figure 13. Equivalent circuit of a quartz crystal
C0
C1
Crystal
Cm
C2
Rm
C1
Lm
C2
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
37
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
Table 33. Crystal motional characteristics1
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
Lm
Motional inductance
—
—
11.796
—
KH
Cm
Motional capacitance
—
—
2
—
fF
—
18
—
28
pF
AC coupled @ C0 = 2.85 pF4
—
—
65
kW
(4)
—
—
50
AC coupled @ C0 = 7.0 pF(4)
—
—
35
(4)
—
—
30
C1/C2 Load capacitance at OSC32K_XTAL and
OSC32K_EXTAL with respect to ground2
Rm3
Motional resistance
AC coupled @ C0 = 4.9 pF
AC coupled @ C0 = 9.0 pF
1
The crystal used is Epson Toyocom MC306.
This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to
ground. It includes all the parasitics due to board traces, crystal and package.
3 Maximum ESR (R ) of the crystal is 50 kΩ
m
4 C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins
2
Figure 14. Slow external crystal oscillator (32 kHz) electrical characteristics
OSCON bit (OSC_CTL register)
1
0
VOSC32K_XTAL
1/fSXOSC
VSXOSC
90%
10%
TSXOSCSU
valid internal clock
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
38
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Electrical characteristics
Table 34. Slow external crystal oscillator (32 kHz) electrical characteristics
Symbol
C
fSXOSC
SR — Slow external crystal oscillator
frequency
gmSXOSC
CC — Slow external crystal oscillator
transconductance
VSXOSC
Value2
Conditions1
Parameter
Unit
Min
Typ
Max
32
32.768
40
—
VDD = 3.3 V ± 10%,
PAD3V5V = 1
TBD
VDD = 5.0 V ± 10%
PAD3V5V = 0
TBD
VDD = 3.3 V ± 10%,
PAD3V5V = 1
TBD
VDD = 5.0 V ± 10%,
PAD3V5V = 0
TBD
CC T Oscillation amplitude
—
ISXOSCBIAS CC T Oscillation bias current
—
2.1
—
kHz
mA/V
—
V
TBD
µA
ISXOSC
CC T Slow external crystal oscillator
consumption
—
—
—
8
µA
TSXOSCSU
CC T Slow external crystal oscillator
start-up time
—
—
—
23
s
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal
1
2
4.15
FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main
oscillator driver.
Table 35. FMPLL electrical characteristics
Symbol
C
Parameter
Unit
Min
Typ
Max
fPLLIN
SR — FMPLL reference clock3
—
4
—
64
MHz
ΔPLLIN
SR — FMPLL reference clock duty
cycle(3)
—
40
—
60
%
—
16
—
64
MHz
fPLLOUT CC P FMPLL output clock frequency
fCPU
SR — System clock frequency
—
—
—
644
MHz
fFREE
CC P Free-running frequency
—
20
—
150
MHz
tLOCK
CC P FMPLL lock time
40
100
µs
ΔtLTJIT CC — FMPLL long term jitter
IPLL
1
Value2
Conditions1
CC C FMPLL consumption
Stable oscillator (fPLLIN = 16 MHz)
fPLLIN = 16 MHz (resonator),
fPLLCLK @ 64 MHz, 4000 cycles
—
—
10
ns
TA = 25 °C
—
—
4
mA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
39
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from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
2
All values need to be confirmed during device validation.
PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN.
4
fCPU 64 MHz can be achieved only at up to 105 °C
3
4.16
Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up of the device.
Table 36. Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol
fFIRC
C
Parameter
CC P Fast internal RC oscillator high TA = 25 °C, trimmed
frequency
SR —
—
IFIRCRUN3, CC T Fast internal RC oscillator high TA = 25 °C, trimmed
frequency current in running
mode
IFIRCPWD
Typ
Max
—
16
—
12
—
200
µA
—
TBD
10
µA
—
TBD
TBD
sysclk = off
—
500
—
sysclk = 2 MHz
—
600
—
sysclk = 4 MHz
—
700
—
sysclk = 8 MHz
—
900
—
sysclk = 16 MHz
—
1250
—
VDD = 5.0 V ± 10%
—
1.1
2.0
VDD = 3.3 V ± 10%
—
1.2
TBD
—
TA = 125 °C VDD = 5.0 V ± 10%
—
—
2.0
—
VDD = 3.3 V ± 10%
—
—
TBD
+1
CC D Fast internal RC oscillator high TA = 25 °C
frequency current in power
—
TA = 55 °C
down mode
CC C Fast internal RC oscillator
start-up time
—
TA = 55 °C
TA = 25 °C
−1
—
ΔFIRCTRIM CC C Fast internal RC oscillator
trimming step
TA = 25 °C
—
1.6
−5
—
ΔFIRCVAR
MHz
20
CC C Fast internal RC oscillator
precision after software
trimming of fFIRC
ΔFIRCPRE
1
Unit
Min
—
IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 °C
frequency and system clock
current in stop mode
TFIRCSU
Value2
Conditions1
CC C Fast internal RC oscillator
variation in temperature and
supply with respect to fFIRC at
TA = 55 °C in high-frequency
configuration
—
µA
µs
%
%
+5
%
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
2
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from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
All values need to be confirmed during device validation.
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
3
4.17
Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the RTC module.
Table 37. Slow internal RC oscillator (128 kHz) electrical characteristics
Symbol
C
Parameter
Value2
1
Conditions
Unit
Min
Typ
Max
—
128
—
100
—
150
—
—
5
µA
CC P Slow internal RC oscillator low
frequency
SR —
TA = 25 °C, trimmed
ISIRC3,
CC C Slow internal RC oscillator low
frequency current
TA = 25 °C, trimmed
TSIRCSU
CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V ± 10%
time
—
8
12
µs
ΔSIRCPRE
CC C Slow internal RC oscillator precision TA = 25 °C
after software trimming of fSIRC
−2
—
+2
%
ΔSIRCTRIM
CC C Slow internal RC oscillator trimming
step
—
2.7
—
ΔSIRCVAR
CC C Slow internal RC oscillator variation High frequency configuration
in temperature and supply with
respect to fSIRC at TA = 55 °C in high
frequency configuration
−10
—
+10
fSIRC
—
—
kHz
%
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
All values need to be confirmed during device validation.
3 This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
1
2
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
41
4.18
On-chip peripherals
4.18.1
Current consumption
Table 38. On-chip peripherals current consumption1
Value
Symbol
C
Parameter
Conditions
Unit
Min
IDD_BV(CAN)
IDD_BV(eMIOS)
CC T CAN (FlexCAN) supply 500 Kbps
current on VDD_BV
125 Kbps
CC T eMIOS supply current
on VDD_BV
Typ
Max
Total (static + dynamic)
7.652 * fperiph + 84.73
consumption:
8.0743 * fperiph + 26.757
• FlexCAN in loop-back
mode
• XTAL@8MHz used as
CAN engine clock
source
• Message sending period
is 580 µs
Static consumption:
• eMIOS channel OFF
• Global prescaler enabled
28.7 * fperiph
Dynamic consumption:
• It does not change varying the
frequency (0.003 mA)
IDD_BV(SCI)
CC T SCI (LINFlex) supply
current on VDD_BV
Total (static + dynamic) consumption:
• LIN mode
• Baudrate: 20 Kbps
IDD_BV(SPI)
CC T SPI (DSPI) supply
current on VDD_BV
Ballast static consumption (only
clocked)
µA
3
4.7804 * fperiph + 30.946
Ballast dynamic consumption
(continuus communication):
• Baudrate: 2 Mbit
• Trasmission every 8 µs
• Frame: 16 bits
1
16.3 * fperiph
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
42
Freescale Semiconductor
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from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
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from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
Table 38. On-chip peripherals current consumption1 (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Min
IDD_BV(ADC)
CC T ADC supply current on VDD = 5.5 V Ballast static consumption
VDD_BV
(no conversion)
VDD = 5.5 V
Ballast dynamic
consumption (continuus
conversion)
IDD_HV_ADC(ADC) CC T ADC supply current on VDD = 5.5 V Analog static consumption
VDD_HV_ADC
(no conversion)
IDD_HV(FLASH)
IDD_HV(PLL)
1
Typ
Max
0.0409 * fperiph
0.0049 * fperiph
0.0017 * fperiph
VDD = 5.5 V
Analog dynamic
consumption (continuus
conversion)
0.075 * fperiph + 0.032
VDD = 5.5 V
-
8.21 (4.14 + 4.07)
CC T PLL supply current on VDD = 5.5 V
VDD_HV
-
0.0031 * fperiph
CC T CFlash + DFlash
supply current on
VDD_HV_ADC
mA
Operating conditions: TA = 25 °C, fperiph = 8 MHz to 64 MHz
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
43
4.18.2
DSPI characteristics
Table 39. DSPI characteristics
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tSCK
SR D SCK cycle time
64
—
—
ns
—
fDSPI
SR D DSPI digital controller frequency
—
—
fCPU
MHz
—
ΔtCSC CC D Internal delay between pad associated to SCK and
pad associated to CSn in master mode
—
—
1201
ns
2
tCSCext2 CC D CS to SCK delay
SR D
3
4
3
tASCext CC D After SCK delay
tSDC
Master mode
tCSCext = tCSC + ΔtCSC
Slave mode
32
Master mode
tASCext = tASC + ΔtCSC
SR D
Slave mode
CC D SCK duty cycle
Master mode
SR D
Slave mode
—
ns
—
ns
1/fDSPI + 5 ns
—
—
ns
—
tSCK/2
—
ns
tSCK/2
—
—
5
tA
SR D Slave access time
—
27
—
—
ns
6
tDI
SR D Slave SOUT disable time
—
0
—
—
ns
7
tSUI
SR D Data setup time for inputs
Master (MTFE = 0)
35
—
—
ns
Slave
5
—
—
Master (MTFE = 1)
35
—
—
Master (MTFE = 0)
0
—
—
Slave
24
—
—
Master (MTFE = 1)
0
—
—
Master (MTFE = 0)
—
—
32
Slave
—
—
34
Master (MTFE = 1)
—
—
32
Master (MTFE = 0)
2
—
—
5.5
—
—
2
—
—
8
9
10
tHI
tSUO5
tHO
(5)
SR D Data hold time for inputs
CC D Data valid after SCK edge
CC D Data hold time for outputs
Slave
Master (MTFE = 1)
ns
ns
ns
1
Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad.
The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields
in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than ΔtCSC to ensure
positive tCSCext.
3 The t
ASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in
DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than ΔtASC to ensure positive
tASCext.
4 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.
5 SCK and SOUT configured as MEDIUM pad
2
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
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from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
Figure 15. DSPI classic SPI timing – master, CPHA = 0
2
3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
SIN
10
First Data
Last Data
Data
12
SOUT
First Data
11
Data
Last Data
Note: Numbers shown reference Table 39.
Figure 16. DSPI classic SPI timing – master, CPHA = 1
PCSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
SIN
Data
First Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Note: Numbers shown reference Table 39.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
45
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from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
Figure 17. DSPI classic SPI timing – slave, CPHA = 0
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
First Data
SOUT
9
6
Data
Last Data
Data
Last Data
10
First Data
SIN
11
12
Note: Numbers shown reference Table 39.
Figure 18. DSPI classic SPI timing – slave, CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 39.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
Figure 19. DSPI modified transfer format timing – master, CPHA = 0
3
PCSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
SIN
10
First Data
Last Data
Data
12
SOUT
11
First Data
Last Data
Data
Note: Numbers shown reference Table 39.
Figure 20. DSPI modified transfer format timing – master, CPHA = 1
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
First Data
Data
12
SOUT
First Data
Data
Last Data
11
Last Data
Note: Numbers shown reference Table 39.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
47
Figure 21. DSPI modified transfer format timing – slave, CPHA = 0
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
First Data
SOUT
Data
6
Last Data
10
9
Data
First Data
SIN
12
11
5
Last Data
Note: Numbers shown reference Table 39.
Figure 22. DSPI modified transfer format timing – slave, CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
12
First Data
SOUT
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 39.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
Figure 23. DSPI PCS strobe (PCSS) timing
7
Freescale Semiconductor
8
PCSS
PCSx
Note: Numbers shown reference Table 39.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
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Electrical characteristics
49
4.18.3
Nexus characteristics
Table 40. Nexus characteristics
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tTCYC
CC D TCK cycle time
64
—
—
ns
2
tMCYC
CC D MCKO cycle time
32
—
—
ns
3
tMDOV
CC D MCKO low to MDO data valid
—
—
8
ns
4
tMSEOV
CC D MCKO low to MSEO_b data valid
—
—
8
ns
5
tEVTOV
CC D MCKO low to EVTO data valid
—
—
8
ns
10
tNTDIS
CC D TDI data setup time
15
—
—
ns
tNTMSS
CC D TMS data setup time
15
—
—
ns
tNTDIH
CC D TDI data hold time
5
—
—
ns
tNTMSH
CC D TMS data hold time
5
—
—
ns
11
12
tTDOV
CC D TCK low to TDO data valid
35
—
—
ns
13
tTDOI
CC D TCK low to TDO data invalid
6
—
—
ns
Figure 24. Nexus TDI, TMS, TDO timing
TCK
10
11
TMS, TDI
12
TDO
Note: Numbers shown reference Table 40.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
4.18.4
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Electrical characteristics
JTAG characteristics
Table 41. JTAG characteristics
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tJCYC
CC
D TCK cycle time
64
—
—
ns
2
tTDIS
CC
D TDI setup time
15
—
—
ns
3
tTDIH
CC
D TDI hold time
5
—
—
ns
4
tTMSS
CC
D TMS setup time
15
—
—
ns
5
tTMSH
CC
D TMS hold time
5
—
—
ns
6
tTDOV
CC
D TCK low to TDO valid
—
33
ns
7
tTDOI
CC
D TCK low to TDO invalid
—
—
ns
6
Figure 25. Timing diagram – JTAG boundary scan
TCK
2/4
DATA INPUTS
3/5
INPUT DATA VALID
6
DATA OUTPUTS
OUTPUT DATA VALID
7
DATA OUTPUTS
Note: Numbers shown reference Table 41.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
51
4.18.5
4.18.5.1
ADC electrical characteristics
Introduction
The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital converter.
Figure 26. ADC characteristic and error definitions
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
5
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
4
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error OSE
4.18.5.2
Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources
charge during the sampling phase, when the analog signal source is a high-impedance source.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 kΩ is obtained (REQ
= 1 / (fc*CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage
partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit
must be designed to respect the Equation 4:
Eqn. 4
R S + R F + R L + R SW + R AD
1
V A • --------------------------------------------------------------------------- < --- LSB
R EQ
2
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
53
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Electrical characteristics
Equation 4 generates a constraint for external network design, in particular on a resistive path. Internal switch resistances (RSW
and RAD) can be neglected with respect to external resistances.
Figure 27. Input equivalent circuit (precise channels)
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
Filter
RS
Current Limiter
RF
VA
Channel
Selection
Sampling
RSW1
RAD
RL
CF
CP1
CP2
CS
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL
Current Limiter Resistance
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
Figure 28. Input equivalent circuit (extended channels)
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
VA
Filter
RF
RL
CF
RS
RF
CF
RL
RSW
RAD
CP
CS
Current Limiter
CP1
Channel
Selection
Extended
Switch
Sampling
RSW1
RSW2
RAD
CP3
CP2
CS
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance (two contributions RSW1 and RSW2)
Sampling Switch Impedance
Pin Capacitance (three contributions, CP1, CP2 and CP3)
Sampling Capacitance
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are
initially charged at the source voltage VA (refer to the equivalent circuit in Figure 27): A charge sharing phenomenon is installed
when the sampling phase is started (A/D switch close).
Figure 29. Transient behavior during sampling phase
Voltage transient on CS
VCS
VA
VA2
ΔV < 0.5 LSB
1
2
τ1 < (RSW + RAD) CS << TS
τ2 = RL (CS + CP1 + CP2)
VA1
TS
t
In particular two different transient periods can be distinguished:
1.
A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series,
and the time constant is
CP • CS
τ 1 = ( R SW + R AD ) • --------------------CP + CS
Eqn. 5
Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS
is always much longer than the internal time constant:
Eqn. 6
τ 1 < ( R SW + R AD ) • C S « T S
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance
according to Equation 7:
Eqn. 7
V A1 • ( C S + C P1 + C P2 ) = V A • ( C P1 + C P2 )
2.
A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance
RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality
would be faster), the time constant is:
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
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Electrical characteristics
Eqn. 8
τ 2 < R L • ( C S + C P1 + C P2 )
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time TS, a constraints on RL sizing is obtained:
Eqn. 9
10 • τ 2 = 10 • R L • ( C S + C P1 + C P2 ) < TS
Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source
impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2
(at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge
balance assuming now CS already charged at VA1):
Eqn. 10
VA2 • ( C S + C P1 + C P2 + C F ) = V A • C F + V A1 • ( C P1 + C P2 + C S )
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to
provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of
the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
Figure 30. Spectral representation of input signal
Analog source bandwidth (VA)
Noise
TC < 2 RFCF (conversion rate vs. filter pole)
fF = f0 (anti-aliasing filtering condition)
2 f0 < fC (Nyquist)
f0
f
Anti-aliasing filter (fF = RC filter pole)
fF
f
Sampled signal spectrum (fC = conversion rate)
f0
fC
f
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF),
according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater
than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS,
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the
sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
voltage on CS:
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
Eqn. 11
VA
C P1 + C P2 + C F
------------ = -------------------------------------------------------V A2
C P1 + C P2 + C F + C S
From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of
half a count, a constraint is evident on CF value:
Eqn. 12
C F > 2048 • C S
4.18.5.3
ADC electrical characteristics
Table 42. ADC input leakage current
Value
Symbol C
Parameter
Conditions
Unit
Min
Typ
Max
ILKG CC C Input leakage current TA = −40 °C No current injection on adjacent pin
—
1
—
C
TA = 25 °C
—
1
—
C
TA = 105 °C
—
8
200
P
TA = 125 °C
—
45
400
nA
Table 43. ADC conversion characteristics
Symbol
C
Parameter
Value
Conditions1
Min
Typ
Max
Uni
t
VSS_ADC S
R
— Voltage on
VSS_HV_ADC (ADC
reference) pin with
respect to ground
(VSS)2
—
−0.1
—
0.1
V
VDD_ADC S
R
— Voltage on
VDD_HV_ADC pin
(ADC reference) with
respect to ground
(VSS)
—
VDD−0.1
—
VDD+0.1
V
VAINx
S
R
— Analog input voltage3
—
VSS_ADC−0.1
—
VDD_ADC+0.
1
V
fADC
S
R
— ADC analog
frequency
—
6
—
32 + 4%
MH
z
ΔADC_SY S
R
S
— ADC digital clock duty ADCLKSEL = 14
cycle (ipg_clk)
45
—
55
%
tADC_PU
— ADC power up delay
—
—
1.5
µs
S
R
—
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
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Electrical characteristics
Table 43. ADC conversion characteristics (continued)
Symbol
tADC_S
C
C
C
T
Parameter
Sample time5
Value
Conditions1
fADC = 32 MHz,
ADC_conf_sample_input = 17
Min
Typ
0.5
—
fADC = 6 MHz,
INPSAMP = 255
C
C
P
CS
C
C
D ADC input sampling
capacitance
CP1
C
C
CP2
fADC = 32 MHz,
ADC_conf_comp = 2
µs
42
0.625
—
—
—
—
3
pF
D ADC input pin
capacitance 1
—
—
—
3
pF
C
C
D ADC input pin
capacitance 2
—
—
—
1
pF
CP3
C
C
D ADC input pin
capacitance 3
—
—
—
1
pF
RSW1
C
C
D Internal resistance of
analog source
—
—
—
3
kΩ
RSW2
C
C
D Internal resistance of
analog source
—
—
—
2
kΩ
RAD
C
C
D Internal resistance of
analog source
—
—
—
0.1
kΩ
IINJ
S
R
— Input current Injection Current
injection on
one ADC input,
different from
the converted
one
VDD =
3.3 V ± 10%
−5
—
5
mA
VDD =
5.0 V ± 10%
−5
—
5
µs
| INL |
C
C
T
Absolute value for
integral non-linearity
No overload
—
0.5
1.5
LSB
| DNL |
C
C
T
Absolute differential
non-linearity
No overload
—
0.5
1.0
LSB
| OFS |
C
C
T
Absolute offset error
—
—
0.5
—
LSB
| GNE |
C
C
T
Absolute gain error
—
—
0.6
—
LSB
TUEp
C
C
P
Total unadjusted
error7 for precise
channels, input only
pins
Without current injection
−2
0.6
2
LSB
With current injection
−3
C
C
T
Total unadjusted
error(7) for extended
channel
Without current injection
−3
With current injection
−4
TUEx
1
Conversion time6
tADC_C
—
Max
Uni
t
T
T
3
1
3
LSB
4
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Electrical characteristics
2
3
4
5
6
7
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Electrical characteristics
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured
by internal divider by 2.
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the
end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC_S depend on programming.
This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
59
5
Package characteristics
5.1
Package mechanical data
Figure 31. 144 LQFP package mechanical drawing
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
60
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Package characteristics
Freescale Semiconductor
MPC5604B/C Microcontroller Data Sheet, Rev. 4
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Package characteristics
61
Figure 32. 100 LQFP package mechanical drawing
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Package characteristics
Freescale Semiconductor
MPC5604B/C Microcontroller Data Sheet, Rev. 4
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Package characteristics
63
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
64
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from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Package characteristics
Freescale Semiconductor
Figure 33. 208 MAPBGA package mechanical drawing
MPC5604B/C Microcontroller Data Sheet, Rev. 4
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Package characteristics
65
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Package characteristics
Freescale Semiconductor
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Ordering information
Ordering information
Table 44. Orderable Part Number Summary
Orderable Part
Number
MPC5602BEMLL
CPU
Code Flash /
SRAM
(Kbytes)
e200z0h
256 / 24
Package
Operating
Speed
temp.
(MHz)
(°C)
100 LQFP −40 to 125
60
Data
Flash
Voltage
4 x 16 KB 3.3/5 V
MPC5602BEMLLR
MPC5602BEMLQ
e200z0h
256 / 24
144 LQFP −40 to 125
60
4 x 16 KB 3.3/5 V
e200z0h
256 / 32
100 LQFP −40 to 125
60
4 x 16 KB 3.3/5 V
e200z0h
384 / 28
100 LQFP −40 to 125
60
4 x 16 KB 3.3/5 V
e200z0h
384 / 28
144 LQFP −40 to 125
60
4 x 16 KB 3.3/5 V
e200z0h
384 / 40
100 LQFP −40 to 125
60
4 x 16 KB 3.3/5 V
e200z0h
256 / 24
100 LQFP −40 to 105
64
4 x 16 KB 3.3/5 V
e200z0h
256 / 24
144 LQFP −40 to 105
64
4 x 16 KB 3.3/5 V
e200z0h
256 / 32
100 LQFP −40 to 105
64
4 x 16 KB 3.3/5 V
e200z0h
384 / 28
100 LQFP −40 to 105
64
4 x 16 KB 3.3/5 V
e200z0h
384 / 28
144 LQFP −40 to 105
64
4 x 16 KB 3.3/5 V
e200z0h
384 / 40
100 LQFP −40 to 105
64
4 x 16 KB 3.3/5 V
e200z0h
512 / 32
100 LQFP −40 to 125
60
4 x 16 KB 3.3/5 V
Tray
Tape & Reel
e200z0h
512 / 32
144 LQFP −40 to 125
60
4 x 16 KB 3.3/5 V
MPC5604BEMLQR
MPC5604BEVLL
Tray
Tape & Reel
MPC5604BEMLLR
MPC5604BEMLQ
Tray
Tape & Reel
MPC5603CEVLLR
MPC5604BEMLL
Tray
Tape & Reel
MPC5603BEVLQR
MPC5603CEVLL
Tray
Tape & Reel
MPC5603BEVLLR
MPC5603BEVLQ
Tray
Tape & Reel
MPC5602CEVLLR
MPC5603BEVLL
Tray
Tape & Reel
MPC5602BEVLQR
MPC5602CEVLL
Tray
Tape & Reel
MPC5602BEVLLR
MPC5602BEVLQ
Tray
Tape & Reel
MPC5603CEMLLR
MPC5602BEVLL
Tray
Tape & Reel
MPC5603BEMLQR
MPC5603CEMLL
Tray
Tape & Reel
MPC5603BEMLLR
MPC5603BEMLQ
Tray
Tape & Reel
MPC5602CEMLLR
MPC5603BEMLL
Tray
Tape & Reel
MPC5602BEMLQR
MPC5602CEMLL
Packing
Tray
Tape & Reel
e200z0h
512 / 32
100 LQFP −40 to 105
64
4 x 16 KB 3.3/5 V
MPC5604BEVLLR
Tray
Tape & Reel
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
67
Table 44. Orderable Part Number Summary (continued)
CPU
Code Flash /
SRAM
(Kbytes)
e200z0h
512 / 32
Orderable Part
Number
MPC5604BEVLQ
Package
Operating
Speed
temp.
(MHz)
(°C)
144 LQFP −40 to 105
64
Data
Flash
Voltage
Packing
4 x 16 KB 3.3/5 V
Tray
MPC5604BEVLQR
MPC5604CEMLL
Tape & Reel
e200z0h
512 / 48
100 LQFP −40 to 125
60
4 x 16 KB 3.3/5 V
Tray
MPC5604CEMLLR
MPC5604BEMMG
1
Tape & Reel
e200z0h
512 / 48
208 MAP −40 to 125
BGA1
64
4 x 16 KB 3.3/5 V
Tray
208 MAPBGA available only as development package for Nexus2+
Figure 34. Commercial product code structure
Example code:
M
PC
56
0
4
B
E
M
LL
R
Qualification Status
PowerPC Core
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Optional fields
Temperature spec.
Package Code
R = Tape & Reel (blank if Tray)
1
Qualification Status
Flash Size (z0 core)
Temperature spec.
M = MC status
S = Auto qualified
P = PC status
2 = 256 KB
3 = 384 KB
4 = 512 KB
C = -40 to 85 °C
V = -40 to 105 °C
M = -40 to 125 °C
Automotive Platform
Product
Package Code
56 = PPC in 90nm
57 = PPC in 65nm
B = Body
C = Gateway
LL = 100 LQFP
LQ = 144 LQFP
MG = 208 MAPBGA1
208 MAPBGA available only as development package for Nexus2+
7
Document revision history
Table 45 summarizes revisions to this document.
Table 45. Revision history
Revision
1
Date
Description of Changes
04-Apr-2008 Initial release.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
68
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from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Document revision history
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Document revision history
Table 45. Revision history (continued)
Revision
2
Date
Description of Changes
06-Mar-2009 Made minor editing and formatting changes to improve readability
Harmonized oscillator naming throughout document
Features:
—Replaced 32 KB with 48 KB as max SRAM size
—Updated descripiton of INTC
—Changed max number of GPIO pins from 121 to 123
Updated Section 1.1, “Introduction
Updated Table 2
Added Section 2, “Device blocks
Section 3, “Package pinouts: Removed signal descriptions (these are found in the device
reference manual)
Updated Figure 2:
—Replaced VPP with VSS_HV on pin 18
—Added MA[1] as AF3 for PC[10] (pin 28)
—Added MA[0] as AF2 for PC[3] (pin 116)
—Changed description for pin 120 to PH[10] / GPIO[122] / TMS
—Changed description for pin 127 to PH[9] / GPIO[121] / TCK
—Replaced NMI[0] with NMI on pin 11
Updated Figure 3:
—Replaced VPP with VSS_HV on pin 14
—Added MA[1] as AF3 for PC[10] (pin 22)
—Added MA[0] as AF2 for PC[3] (pin 77)
—Changed description for pin 81 to PH[10] / GPIO[122] / TMS
—Changed description for pin 88 to PH[9] / GPIO[121] / TCK
—Removed E1UC[19] from pin 76
—Replaced [11] with WKUP[11] for PB[3] (pin 1)
—Replaced NMI[0] with NMI on pin 7
Updated Figure 4:
—Changed description for ball B8 from TCK to PH[9]
—Changed description for ball B9 from TMS to PH[10]
—Updated descriptions for balls R9 and T9
Added Section 3.2, “Parameter classification and tagged parameters in tables where
appropriate
Added Section 3.3, “NVUSRO register
Updated Table 7
Section 3.5, “Recommended operating conditions: Added note on RAM data retention to
end of section
Updated Table 8 and Table 9
Added Section 3.6.1, “Package thermal characteristics
Updated Section 3.6.2, “Power considerations
Updated Figure 6
Updated Table 12, Table 13, Table 14, Table 15 and Table 16
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
69
Table 45. Revision history (continued)
Revision
Date
Description of Changes
2
06-Mar-2009 Added Section 3.7.4, “Output pin transition times
Updated Table 19
Updated Figure 7
Updated Table 20
Section 3.9.1, “Voltage regulator electrical characteristics: Amended description of
LV_PLL
Figure 9: Exchanged position of symbols CDEC1 and CDEC2
Updated Table 21
Added Figure 10
Updated Table 22 and Table 23
Updated Section 3.11, “Flash memory electrical characteristics
Added Section 3.12, “Electromagnetic compatibility (EMC) characteristics
Updated Section 3.13, “Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
Updated Section 3.14, “Slow external crystal oscillator (32 kHz) electrical characteristics
Updated Table 37, Table 38 and Table 39
Added Section 3.18, “On-chip peripherals
Added Table 44
Updated Table 45
Updated Table 49
Added Section Appendix A, “Abbreviations
4
06-Aug-2009 Updated Figure 4
Table 7
• VDD_ADC: changed min value for “relative to VDD“ condition
• VIN: changed min value for “relative to VDD“ condition
• ICORELV: added new row
Table 9
• TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part, TJ M-Grade Part:
added new rows
• Changed capacitance value in footnote
Table 17
• MEDIUM configuration: added condition for PAD3V5V = 0
Updated Figure 9
Table 21
• CDEC1: changed min value
• IMREG: changed max value
• IDD_BV: added max value footnote
Table 22
• VLVDHV3H: changed max value
• VLVDHV3L: added max value
• VLVDHV5H: changed max value
• VLVDHV5L: added max value
Updated Table 23
Table 26
• Retention: deleted min value footnote for “Blocks with 100,000 P/E cycles“
Table 34
• IFXOSC: added typ value
Table 36
• VSXOSC: changed typ value
• TSXOSCSU: added max value footnote
Table 37
• ΔtLTJIT: added max value
Updated Figure 33
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
70
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Document revision history
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
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Abbreviations
Appendix A
Abbreviations
Table 46 lists abbreviations used but not defined elsewhere in this document.
Table 46. Abbreviations
Abbreviation
Meaning
CMOS
Complementary metal–oxide–semiconductor
CPHA
Clock phase
CPOL
Clock polarity
CS
EVTO
Peripheral chip select
Event out
LED
Light emitting diode
MCKO
Message clock out
MDO
Message data out
MSEO
Message start/end out
MTFE
Modified timing format enable
SCK
Serial communications clock
SOUT
Serial data out
TBD
To be defined
TCK
Test clock input
TDI
Test data input
TDO
Test data output
TMS
Test mode select
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
71
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MPC5604BC
Rev. 4
08/2009
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
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