Mitel MT9041AP Multiple output trunk pll Datasheet

MT9041

Multiple Output Trunk PLL
Advance Information
Features
ISSUE 1
May 1995
Ordering Information
•
Provides T1 and E1 clocks, and ST-BUS/GCI
framing signals locked to an input reference of
either 8 kHz (frame pulse), 1.544 MHz (T1), or
2.048 MHz (E1)
•
Meets AT & T TR62411 and ETSI ETS 300 011
specifications for a 1.544 MHz (T1), or
2.048 MHz (E1) input reference
•
Typical unfiltered intrinsic output jitter is
0.013 UI peak-to-peak
•
Jitter attenuation of 15 dB @ 10 Hz,
34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz
•
Low power CMOS technology
Applications
•
Synchronization and timing control for T1 and
E1 digital transmission links
•
ST-BUS clock and frame pulse sources
•
Primary Trunk Rate Converters
VDD
MT9041AP
28 Pin PLCC
-40 °C to +85 °C
Description
The MT9041 is a digital phase-locked loop (PLL)
designed to provide timing and synchronization
signals for T1 and E1 primary rate transmission links
that are compatible with ST-BUS/GCI frame
alignment timing requirements. The PLL outputs can
be synchronized to either a 2.048 MHz, 1.544 MHz,
or 8 kHz reference. The T1 and E1 outputs are fully
compliant with AT & T TR62411 (ACCUNET® T1.5)
and ETSI ETS 300 011 intrinsic jitter and jitter
transfer
specifications,
respectively,
when
synchronized to primary reference input clock rates
of either 1.544 MHz or 2.048 MHz.
The PLL also provides additional high speed output
clocks at rates of 3.088 MHz, 4.096 MHz, 8.192
MHz, and 16.384 MHz for backplane synchronization.
VSS
MCLKo
MCLKi
C3
PRI
Phase
Detector
Loop
Filter
C1.5
DCO
C16
Interface
Circuit
C8
C4
C2
IC0
F0o
FP8-STB
IC1
FP8-GCI
Mode
Select
MS
Divider
FSEL1
FSEL2
Figure 1 - Functional Block Diagram
3-83
MT9041
4 3 2 1 28 27 26
5
25
24
6
7
23
22
8
21
9
10
20
19
11
12 13 14 15 16 17 18
IC0
IC0
MS
IC0
IC0
IC1
IC0
C3
C2
C4
VSS
C8
C16
VDD
VDD
MCLKo
MCLKi
FP8-GCI
F0o
FP8-STB
C1.5
IC0
VSS
RST
FSEL1
FSEL2
PRI
IC0
Advance Information
Figure 2 - Pin Connections
Pin Description
Pin #
Name
1
VSS
Negative Power Supply Voltage. Nominally 0 Volts.
2,3
IC0
Internal Connection 0. Connect to VSS.
4
PRI
Primary Reference Input (TTL compatible). This input (either 8 kHz, 1.544 MHz, or 2.048
MHz as controlled by the input frequency selection pins) is used as the primary reference
source for PLL synchronization.
5
VDD
Positive Supply Voltage. Nominally +5 volts.
6
MCLKo
Master Clock Oscillator Output. This is a CMOS buffered output used for driving a 20 MHz
crystal.
7
MCLKi
Master Clock Oscillator Input. This is a CMOS input for a 20 MHz crystal or crystal
oscillator. Signals should be DC coupled to this pin.
8
9
10
Description
FP8-GCI Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that
indicates the start of the active GCI-BUS frame. The pulse width is based upon the period of
the 8.192 MHz synchronization clock.
F0o
Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that
indicates the start of the active ST-BUS frame. The pulse width is based upon the period of
the 4.096 MHz synchronization clock. This is an active low signal.
FP8-STB Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that
indicates the start of the active ST-BUS frame. The pulse width is based upon the period of
the 8.192 MHz synchronization clock.
11
C1.5
Clock 1.544 MHz (CMOS compatible). This ouput is a 1.544 MHz (T1) output clock locked
to the reference input signal.
12
C3
Clock 3.088 MHz (CMOS compatible). This output is a 3.088 MHz output clock locked to
the reference input signal.
13
C2
Clock 2.048 MHz (CMOS compatible). This output is a 2.048 MHz (E1) output clock
locked to the reference input signal.
14
C4
Clock 4.096 MHz (CMOS compatible). This output is a 4.096 MHz output clock locked to
the reference input signal.
15
VSS
Negative Power Supply Voltage. Nominally 0 Volts.
16
C8
Clock 8.192 MHz (CMOS compatible). This output is an 8.192 MHz output clock locked to
the reference input signal.
3-84
MT9041
Advance Information
Pin Description (continued)
Pin #
Name
Description
17
C16
Clock 16.384 MHz (CMOS compatible). This output is a 16.384 MHz output clock locked
to the reference input signal.
18
VDD
Positive Supply Voltage. Nominally +5 volts.
19
IC0
Internal Connection 0. Connect to VSS.
20
IC1
Internal Connection 1. Leave open circuit.
21, 22
IC0
Internal Connection 0. Connect to VSS.
23
MS
Mode Select Input (TTL compatible). This input selects the PLL mode of operation (i.e. ,
NORMAL or FREERUN, see Table 1).
24, 25
IC0
Internal Connection 0. Connect to VSS.
26
FSEL2
Frequency Select - 2 Input (TTL compatible). This input, in conjunction with FSEL1,
selects the frequency of the input reference source (i.e., 8 kHz, 1.544 MHz, or 2.048 MHz;
see Table 3).
27
FSEL1
Frequency Select - 1 Input (TTL compatible). This input, in conjunction with FSEL2,
selects the frequency of the input reference source (i.e., 8 kHz, 1.544 MHz, or 2.048 MHz;
see Table 3).
28
RST
Reset (TTL compatible). This input (active LOW) puts the MT9041 in its reset state. To
guarantee proper operation, the device must be reset after power-up. The time constant for
a power-up reset circuit must be a minimum of five times the rise time of the power supply. In
normal operation, the RST pin must be held low for a minimum of 60 nsec to reset the
device.
3-85
MT9041
Advance Information
Functional Description
The MT9041 is a fully digital, phase-locked loop
designed to provide timing references to interface
circuits for T1 and E1 Primary Rate Digital
Transmission links. As shown in Figure 1, the PLL
employs a high resolution Digitally Controlled
Oscillator (DCO) to generate the T1 and E1 outputs.
The interface circuit on the output of the DCO
generates 1.544 MHz (C1.5), 3.088 MHz (C3), 2.048
MHz (C2), 4.096 MHz (C4), 8.192 MHz (C8), 16.384
MHz (C16), and three 8 kHz frame pulses F0o, FP8STB, and FP8-GCI.
fref
Phase
Detector
Loop
Filter
is controlled by the logic levels of FSEL1 and FSEL2,
as shown in Table 2. This variety of input frequencies
was chosen to allow the generation of all the
necessary T1 and E1 clocks from either a T1, E1 or
frame pulse reference source.
FSEL
2
FSEL
1
Input Reference
Frequency
0
0
Reserved
0
1
8 kHz
1
0
1.544 MHz
1
1
2.048 MHz
Table 2 - Input Frequency Selection of the MT9041
PLL Measures of Performance
DCO
fsync
To meet the requirements of AT & T TR62411 and
ETSI 300 011, the following PLL performance
parameters were measured:
Divider
Figure 3 - PLL Block Diagram
As shown in Figure 3, the PLL of the MT9041
consists of a phase detector (PD), a loop filter, a high
resolution DCO, and a digital frequency divider. The
digitally controlled oscillator (DCO) is locked in
frequency (n x fref) to one of three possible reference
frequencies, configured using pins FSEL1 and
FSEL2. The PLL is capable of providing a full range
of E1/T1 clock signals synchronized to the primary
PRI input. The loop filter is a first order lowpass
structure that provides approximately a 2 Hz
bandwidth.
Modes of Operation
The MT9041 can operate in one of two modes,
NORMAL or FREERUN, as controlled by mode
select pin MS (see Table 1).
MS
Description of Operation
0
NORMAL
1
FREERUN
Table 1- Operating Modes of the MT9041
Normal Mode
.
There are three possible input frequencies for
selection as the primary reference clock. These are 8
kHz, 1.544 MHz or 2.048 MHz. Frequency selection
3-86
•
locking range and lock time
•
free-run accuracy
•
intrinsic jitter
•
jitter transfer function
•
output jitter spectrum
•
wander
Locking Range and Lock Time
The locking range of the PLL is the range that the
input reference frequency can be deviated from its
nominal frequency while the output signals maintain
synchronization. The relevant value is usually
specified in parts-per-million (ppm). For both the T1
and E1 outputs, lock was maintained while an 8 kHz
input was varied between 7900 Hz to 8100 Hz
(corresponding to ±12500 ppm). This is well beyond
the required ±100 ppm. The lock range of 12500
ppm also applies to 1.544 MHz and 2.048 MHz
reference inputs.
The lock time is a measure of how long it takes the
PLL to reach steady state frequency after a
frequency step on the reference input signal. The
locking time is measured by applying an 8000 Hz
signal to the primary reference and an 8000.8 Hz
(+100 ppm) to the secondary reference. The output
is monitored with a time interval analyzer during slow
periodic rearrangements on the reference inputs.
The lock time for both the T1 and E1 outputs is
approximately 311 ms, which is well below the
required lock time of 1.0 seconds.
MT9041
Advance Information
Freerun Accuracy
Jitter Transfer Function
The Freerun accuracy of the PLL is a measure of
how accurately the PLL can reproduce the desired
output frequency. The freerun accuracy is a function
of master clock frequency which must be 20 MHz
±32 ppm in order to meet AT & T TR62411 and ETSI
specifications.
The jitter transfer function is a measure of the
transfer characteristics of the PLL to frequency
specific jitter on the referenced input of the PLL. It is
directly linked to the loop bandwidth and the
magnitude of the phase error suppression
characteristics of the PLL. It is measured by applying
jitter of specific magnitude and frequencies to the
input of the PLL, then measuring the magnitude of
the output jitter (both filtered and unfiltered) on the
T1 or E1 output.
Jitter Performance
The output jitter of a digital trunk PLL is composed of
intrinsic jitter, measured using a jitter free reference
clock, and frequency dependent jitter, measured by
applying known levels of jitter on the references
clock. The jitter spectrum indicates the frequency
content of the output jitter.
Care must be taken when measuring the transfer
characteristics to ensure that critical jitter alias
frequencies are included in the measurement (i.e.,
for digital phase locked loops using an 8 kHz input).
Tables 5 and 6 provide measured results for the jitter
transfer characteristics of the PLL for both a 1.544
MHz and 2.048 MHz reference input clock. The
transfer characteristics for an 8 kHz reference input
will be the same.
Intrinsic Jitter
Intrinsic jitter is the jitter added to an output signal by
the processing device, in this case the enhanced
PLL. Tables 3 and 4 show the average measured
intrinsic jitter of the T1 and E1 outputs. Each
measurement is an average based upon a ±100 ppm
deviation (in steps of 20 ppm) on the input reference
clock. Jitter on the master clock will increase intrinsic
jitter of the device, hence attention to minimization of
master clock jitter is required.
Figures 4 and 5 show the jitter attenuation
performance of the T1 and E1 outputs plotted
against AT & T TR62411 and ETSI requirements,
respectively.
Output Jitter in UIp-p
Reference Input
FLT0 Unfiltered
FLT1
10Hz - 8kHz
FLT2
10Hz - 40kHz
FLT3
8kHz - 40kHz
8 kHz
.011
.004
.006
.002
1.544 MHz
.011
.001
.002
.001
2.048 MHz
.011
.001
.002
.001
Table 3 -Typical Intrinsic Jitter for the T1 Output
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing .
Output Jitter in UIp-p
Reference Input
FLT0 Unfiltered
FLT1
20Hz - 100kHz
FLT2
700Hz - 100kHz
8 kHz
.011
.002
.002
1.544 MHz
.011
.002
.002
2.048 MHz
.011
.002
.002
Table 4 - Typical Intrinsic Jitter for the E1 Output
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing .
3-87
MT9041
Advance Information
Measured Jitter Output (UIp-p)
Input Jitter
Modulation
Frequency
(Hz)
Input Jitter
Magnitude
(UIp-p)
10
T1 Reference Input
E1 Reference Input
Output Jitter
Magnitude
(UIp-p)
Jitter
Attenuation
(dB)
Output Jitter
Magnitude
(UIp-p)
Jitter
Attenuation
(dB)
20
2.42
18.34
2.41
18.38
20
20
1.62
21.83
1.618
21.84
40
20
.900
26.94
.908
26.86
100
20
.375
34.54
.376
34.52
330
10
.060
44.44
.060
44.44
500
8
.032
47.96
.032
47.96
1000
7
.015
53.38
.015
53.38
5000
0.8
.003
48.52
.003
48.52
7900
1.044
.003
50.83
.003
50.83
7950
1.044
.003
50.83
.003
50.83
7980
1.044
.003
50.83
.003
50.83
7999
1.044
.003
50.83
.003
50.83
8001
1.044
.003
50.83
.003
50.83
8020
1.044
.003
50.83
.003
50.83
8050
1.044
.003
50.83
.003
50.83
8100
1.044
.003
50.83
.003
50.83
10000
0.4
.003
42.50
.003
42.50
Table 5 - Typical Jitter Transfer Function for the T1 Output
Notes
1) For input jitter from 10 kHz to 100 kHz, the jitter attenuation is of such magnitude that intrinsic jitter dominates the output
signal, rendering the jitter transfer function unmeasurable.
2) Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-88
MT9041
Advance Information
Measured Jitter Output (UIp-p)
Input Jitter
Modulation
Frequency
(Hz)
Input Jitter
Magnitude
(UIp-p)
10
T1 Reference Input
E1 Reference Input
Output Jitter
Magnitude
(UIp-p)
Jitter
Attenuation
(dB)
Output Jitter
Magnitude
(UIp-p)
Jitter
Attenuation
(dB)
1.5
.355
12.52
.351
12.62
20
1.5
.186
18.13
.185
18.18
40
1.5
.095
23.97
.096
23.88
100
1.5
.039
31.70
.039
31.70
200
1.5
.021
37.08
.020
37.50
400
1.5
.012
41.94
.012
41.94
1000
1.5
.006
47.96
.007
46.62
7900*
1.044
.002
54.35
.002
54.35
7950*
1.044
.002
54.35
.002
54.35
7980*
1.044
.002
54.35
.002
54.35
7999*
1.044
.002
54.35
.002
54.35
8001*
1.044
.002
54.35
.002
54.35
8020*
1.044
.002
54.35
.002
54.35
8050*
1.044
.002
54.35
.002
54.35
8100*
1.044
.002
54.35
.002
54.35
10000
0.35
.004
38.84
.003
41.34
100000
0.20
.004
33.98
.003
36.48
Table 6 - Typical Jitter Transfer Function for the E1 Output
Notes
1) For input jitter from 10 kHz to 100 kHz, the jitter attenuation is of such magnitude that intrinsic jitter dominates the output
signal, rendering the jitter transfer function unmeasurable.
2) Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Output jitter dominated by intrinsic jitter.
3-89
MT9041
Advance Information
0
b)
a)
10
JITTER ATTENUATION (dB)
SLOPE -20 dB PER DECADE
20
30
SLOPE -40 dB
PER DECADE
40
50
60
1
10
20
100
300
1K
10K
Frequency (Hz)
Figure 4 - Typical Jitter Attenuation for T1 Output
JITTER ATTENUATION (dB)
dB
-0.5
0
19.5
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
-20
dB/decade
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
10
40
Frequency (Hz)
400
Figure 5 - Typical Jitter Attenuation for E1 Output
3-90
10K
MT9041
Advance Information
Absolute Maximum Ratings*- Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter
Symbol
Min
Max
Units
VDD
-0.3
7.0
V
VI
VSS-0.3
VDD+0.3
V
IIK/OK
±150
mA
1
Supply Voltage
2
Voltage on any pin
3
Input/Output Diode Current
4
Output Source or Sink Current
IO
±150
mA
5
DC Supply or Ground Current
IDD/ISS
±300
mA
6
Storage Temperature
125
°C
7
Package Power Dissipation
900
mW
TST
PLCC
-55
PD
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
5.0
5.5
V
1
Supply Voltage
VDD
4.5
2
Input HIGH Voltage
VIH
2.0
VDD
V
3
Input LOW Voltage
VIL
VSS
0.8
V
4
Operating Temperature
TA
-40
85
°C
25
Test Conditions
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics -
Voltages are with respect to ground (VSS) unless otherwise stated.
VDD =5.0 V±10%; VSS =0V; TA =-40 to 85°C.
Characteristics
1
2
3
4
5
6
S
U
P
I
N
O
U
T
Supply Current
Sym
Min
Typ‡
Max
55
IDD
2.0
Units
Test Conditions
mA
Under operating condition
Input HIGH voltage
VIH
V
Input LOW voltage
VIL
Output current HIGH
IOH
-4
mA
VOH=2.4 V
Output current LOW
IOL
4
mA
VOL=0.4 V
Leakage current on all inputs
IIL
µA
VIN=VSS
0.8
10
V
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-91
MT9041
Advance Information
AC Electrical Characteristics (see Fig. 6)†-Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1
8 kHz reference clock period
tP8R
125
µs
2
1.544 MHz reference clock period
tP15R
648
ns
3
2.048 MHz reference clock period
tP20R
488
ns
Input to output propagation delay
with an 8 kHz reference clock
tPD8
183
ns
MCLKi =
20.000 000MHz
Input to output propagation delay
with a 1.544 MHz reference clock
tPD15
243
ns
MCLKi =
20.000 000MHz
Input to output propagation delay
with a 2.048 MHz reference clock
tPD20
183
ns
MCLKi =
20.000 000MHz
4
5
6
I
N
P
U
T
S
7
Input rise time (except MCLKi)
8
ns
8
Input fall time (except MCLKi)
8
ns
9
Delay between C1.5 and C2
tD-20-15
18
ns
10
Frame pulse F0o output pulse
width
tW-F0o
244
ns
11
Frame pulse F0o output rise time
tR-F0o
5
9
ns
Load = 85pF
12
Frame pulse F0o output fall time
tF-F0o
5
9
ns
Load = 85pF
13
Frame pulse FP8-STB output
pulse width
tW-FP8STB
122
14
Frame pulse FP8-STB output rise
time
tR-FP8STB
5
9
ns
15
Frame pulse FP8-STB output fall
time
tF-FP8STB
5
9
ns
Frame pulse FP8-GCI output
pulse width
tW-FP8GCI
122
Frame pulse FP8-GCI output rise
time
tR-FP8GCI
5
9
ns
Frame pulse FP8-GCI output fall
time
tF-FP8GCI
5
9
ns
16
17
18
O
U
T
P
U
T
S
ns
Load = 85pF
Load = 85pF
ns
Load = 85pF
Load = 85pF
19
C1.5 clock period
tP-C1.5
648
20
C1.5 clock output rise time
tRC1.5
5
9
ns
Load = 85pF
21
C1.5 clock output fall time
tFC1.5
5
9
ns
Load = 85pF
22
C1.5 clock output duty cycle
23
C3 clock period
24
ns
50
%
tP-C3
324
ns
C3 clock output rise time
tRC3
5
9
ns
Load = 85pF
25
C3 clock output fall time
tFC3
5
9
ns
Load = 85pF
26
C3 clock output duty cycle
27
C2 clock period
28
50
%
tP-C2
488
ns
C2 clock output rise time
tRC2
5
9
ns
Load = 85pF
29
C2 clock output fall time
tFC2
5
9
ns
Load = 85pF
30
C2 clock output duty cycle
3-92
50
%
MT9041
Advance Information
AC Electrical Characteristics (see Fig. 6)†-Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Min
Typ‡
Max
Units
Test Conditions
31
C4 clock period
tP-C4
244
32
C4 clock output rise time
tRC4
5
9
ns
Load = 85pF
33
C4 clock output fall time
tFC4
5
9
ns
Load = 85pF
34
35
36
37
38
†
Sym
O
U
T
P
U
T
S
C4 clock output duty cycle
ns
50
%
ns
C8 clock period
tP-C8
122
C8 clock output rise time
tRC8
5
9
ns
Load = 85pF
C8 clock output fall time
tFC8
5
9
ns
Load = 85pF
C8 clock output duty cycle
50
%
ns
39
C16 clock period
tP-C16
61
40
C16 clock output rise time
tRC16
5
9
ns
Load = 85pF
41
C16 clock output fall time
tFC16
5
9
ns
Load = 85pF
42
C16 clock output duty cycle
50
55
%
Duty cycle on
MCLKi =50%
43
-Timing is over recommended temperature & power supply voltages.
figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
‡ -Typical
3-93
MT9041
Advance Information
tPD-8
PRI- 8 kHz
tPD-20
PRI-2.048 MHz
tW-F0o
F0o
tW-FP8STB
FP8-STB
tW-FP8GCI
FP8-GCI
tP-C16
C16
tP-C8
C8
tP-C4
C4
tP-C2
C2
tP-C3
tD-20-15
C3
C1.5
tPD-15
PRI-1.544 MHz
tP-C1.5
Figure 6 - Timing Information for MT9041
3-94
MT9041
Advance Information
AC Electrical Characteristics (see Fig. 7)† - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
1 C
L
2
O
3 C
K
4
Sym
Min
Typ‡
Max
Units
Master clock input rise time
trMCLKi
4
ns
Master clock input fall time
tfMCLKi
4
ns
Master clock frequency
tpMCLKi
Duty Cycle of the master clock
19.99936
20
20.000640
MHz
40
50
60
%
Test Conditions
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing
tfMCLK
trMCLK
MCLKi
2.4V
1.5V
0.4V
Figure 7 - Master Clock Input
3-95
MT9041
Notes:
3-96
Advance Information
Similar pages