AD ADUM1311ARWZ1 Triple-channel digital isolator Datasheet

Triple-Channel Digital Isolators
ADuM1310/ADuM1311
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
VDD1
1
16
VDD2
GND1
2
15
GND2
VIA
3
ENCODE
DECODE
14
VOA
VIB
4
ENCODE
DECODE
13
VOB
VIC
5
ENCODE
DECODE
12
VOC
NC
6
11
NC
DISABLE
7
10
CTRL2
GND1
8
9
GND2
04904-001
Low power operation
5 V operation
1.7 mA per channel max @ 0 Mbps to 2 Mbps
4.0 mA per channel max @ 2 Mbps to 10 Mbps
3 V operation
1.0 mA per channel max @ 0 Mbps to 2 Mbps
2.1 mA per channel max @ 2 Mbps to 10 Mbps
Bidirectional communication
3 V/5 V level translation
Schmitt trigger inputs
High temperature operation: 105°C
Up to 10 Mbps data rate (NRZ)
Programmable default output state
High common-mode transient immunity: >25 kV/μs
16-lead Pb-free SOIC wide body package
8.1 mm external creepage
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE certificate of conformity
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000
VIORM = 560 V peak working voltage
Figure 1. ADuM1310
VDD1
1
16
VDD2
GND1
2
15
GND2
VIA
3
ENCODE
DECODE
14
VOA
VIB
4
ENCODE
DECODE
13
VOB
VOC
5
DECODE
ENCODE
12
VIC
NC
6
11
NC
CTRL1
7
10
CTRL2
GND1
8
9
GND2
General-purpose multichannel isolation
SPI® interface/data converter isolation
RS-232/RS-422/RS-485 transceiver
Industrial field bus isolation
04904-002
APPLICATIONS
Figure 2. ADuM1311
GENERAL DESCRIPTION
The ADuM131x1 are 3-channel digital isolators based on
Analog Devices, Inc. iCoupler® technology. Combining high
speed CMOS and monolithic air core transformer technology,
these isolation components provide outstanding performance
characteristics superior to alternatives such as optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain
current transfer ratios, maximum operating temperature, and
lifetime effects are eliminated with the simple iCoupler digital
interfaces and stable performance characteristics. The need for
external drivers and other discrete components is eliminated
with these iCoupler products. Furthermore, iCoupler devices
consume one-tenth to one-sixth the power of optocouplers at
comparable signal data rates. The iCoupler also offers higher
channel densities and more options for channel directionality.
The ADuM131x isolators provide three independent isolation
channels in a variety of channel configurations and data rates
up to 10 Mbps (see the Ordering Guide). All models operate
with the supply voltage on either side ranging from 2.7 V to
5.5 V, providing compatibility with lower voltage systems as well
as enabling voltage translation functionality across the isolation
barrier. All products allow the user to predetermine the default
output state in the absence of input VDD1 power with a simple
control pin. Unlike other optocoupler alternatives, the ADuM131x
isolators have a patented refresh feature that ensures dc correctness
in the absence of input logic transitions and during power-up/
power-down conditions.
1
Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075 329. Other patents
pending.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved.
ADuM1310/ADuM1311
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Operating Conditions .................................... 11
Applications....................................................................................... 1
Absolute Maximum Ratings ......................................................... 12
Functional Block Diagrams............................................................. 1
ESD Caution................................................................................ 12
General Description ......................................................................... 1
Pin Configurations and Function Descriptions ......................... 13
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 16
Specifications..................................................................................... 3
Application Information................................................................ 18
Electrical Characteristics—5 V Operation................................ 3
PC Board Layout ........................................................................ 18
Electrical Characteristics—3 V Operation................................ 5
Propagation Delay Related Parameters.................................... 18
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 7
DC Correctness and Magnetic Field Immunity..................... 18
Package Characteristics ............................................................. 10
Outline Dimensions ....................................................................... 20
Regulatory Information............................................................. 10
Ordering Guide .......................................................................... 20
Power Consumption .................................................................. 19
Insulation and Safety-Related Specifications.......................... 10
DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation
Characteristics ............................................................................ 11
REVISION HISTORY
1/07—Rev. E to Rev. F
Added ADuM1311 .............................................................Universal
Changes to Typical Performance Characteristics....................... 16
Changes to Ordering Guide .......................................................... 20
3/06—Rev. C to Rev. D
Added Note 1 and Changes to Figure 2..........................................1
Changes to Absolute Maximum Ratings..................................... 11
10/06—Rev. D to Rev. E
Removed ADuM1410 ........................................................Universal
Updated Format..................................................................Universal
Change to Figure 3 ......................................................................... 10
Changes to Table 10........................................................................ 10
Changes to Application Information ........................................... 12
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
5/05—Rev. SpA to Rev. SpB
Changes to Table 6.............................................................................9
11/05—Rev. SpB to Rev. C
10/04—Data Sheet Changed from Rev. Sp0 to Rev. SpA
Changes to Table 5.............................................................................9
6/04—Revision Sp0: Initial Version
Rev. F | Page 2 of 20
ADuM1310/ADuM1311
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION 1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless
otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter
DC SPECIFICATIONS
ADuM1310, Total Supply Current,
Three Channels 2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1311, Total Supply Current,
Three Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
For All Models
Input Currents
Symbol
Min
Typ
Max
Unit
Test Conditions
IDD1 (Q)
IDD2 (Q)
2.4
1.2
3.2
1.6
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
IDD1 (10)
IDD2 (10)
6.6
2.1
9.0
3.0
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
IDD1 (Q)
IDD2 (Q)
2.2
1.8
2.8
2.4
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
IDD1 (10)
IDD2 (10)
4.5
3.5
5.7
4.3
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
+0.01
+10
μA
0 ≤ VIA, VIB, VIC ≤ VDD1 or VDD2,
0 ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2,
0 ≤ VDISABLE ≤ VDD1
IIA, IIB, IIC, ICTRL1,
ICTRL2, IDISABLE
−10
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
VIH
VIL
VOAH, VOBH,
VOCH
2.0
Logic Low Output Voltages
VOAL, VOBL, VOCL
SWITCHING SPECIFICATIONS
ADuM131xARW
Minimum Pulse Width 3
Maximum Data Rate 4
Propagation Delay 5
Pulse Width Distortion, |tPLH − tPHL|5
Propagation Delay Skew 6
Channel-to-Channel Matching 7
ADuM131xBRW
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
Channel-to-Channel Matching,
Opposing-Directional Channels
0.8
VDD1, VDD2 − 0.1
VDD1, VDD2 − 0.4
5.0
4.8
0.0
0.2
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/OD
0.1
0.4
1000
1
20
100
40
50
50
PW
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
ns
Mbps
ns
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
30
5
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
6
ns
tPHL, tPLH
PWD
100
V
V
V
V
V
V
10
20
30
50
5
5
Rev. F | Page 3 of 20
ADuM1310/ADuM1311
Parameter
For All Models
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient
Immunity at Logic High
Output 8
Common-Mode Transient
Immunity at Logic Low Output
Refresh Rate
Input Enable Time 9
Input Disable Time9
Input Supply Current per Channel,
Quiescent 10
Output Supply Current per
Channel, Quiescent10
Input Dynamic Supply Current
per Channel 11
Output Dynamic Supply Current
per Channel11
Symbol
Min
Typ
tR/tF
|CMH|
25
|CML|
25
Unit
Test Conditions
2.5
35
ns
kV/μs
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
35
kV/μs
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
fr
tENABLE
tDISABLE
IDDI (Q)
1.2
Max
0.50
2.0
5.0
0.73
Mbps
μs
μs
mA
IDDO (Q)
0.38
0.53
mA
IDDI (D)
0.12
IDDO (D)
0.04
1
VIA, VIB, VIC = 0 V or VDD1
VIA, VIB, VIC = 0 V or VDD1
mA/
Mbps
mA/
Mbps
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 12).
10
IDDx (Q) is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in
the same orientation as Channel A must be included to account for the total current consumed.
11
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
2
Rev. F | Page 4 of 20
ADuM1310/ADuM1311
ELECTRICAL CHARACTERISTICS—3 V OPERATION 1
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless
otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.
Table 2.
Parameter
DC SPECIFICATIONS
ADuM1310, Total Supply Current,
Three Channels 2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1311, Total Supply Current,
Three Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM131xARW
Minimum Pulse Width 3
Maximum Data Rate 4
Propagation Delay 5
Pulse Width Distortion, |tPLH − tPHL|5
Propagation Delay Skew 6
Channel-to-Channel Matching 7
ADuM131xBRW
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
Channel-to-Channel Matching,
Opposing-Directional Channels7
Symbol
Typ
Max
Unit
Test Conditions
IDD1 (Q)
IDD2 (Q)
1.2
0.8
1.6
1.0
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
IDD1 (10)
IDD2 (10)
3.4
1.1
4.9
1.3
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
IDD1 (Q)
IDD2 (Q)
1.0
0.9
1.6
1.4
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
IDD1 (10)
IDD2 (10)
2.5
1.9
3.5
2.6
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
+0.01
+10
μA
0 ≤ VIA, VIB, VIC ≤ VDD1 or VDD2,
0 ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2,
0 ≤ VDISABLE ≤ VDD1
IIA, IIB, IIC, ICTRL1,
ICTRL2, IDISABLE
Min
−10
VIH
1.6
VIL
VOAH, VOBH, VOCH VDD1, VDD2 − 0.1 3.0
VDD1, VDD2 − 0.4 2.8
VOAL, VOBL, VOCL
0.0
0.2
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/OD
0.4
0.1
0.4
1000
1
20
100
40
50
50
PW
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
ns
Mbps
ns
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
30
5
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
6
ns
tPHL, tPLH
PWD
100
V
V
V
V
V
V
10
20
30
50
5
5
Rev. F | Page 5 of 20
ADuM1310/ADuM1311
Parameter
For All Models
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output 8
Common-Mode Transient Immunity
at Logic Low Output8
Refresh Rate
Input Enable Time 9
Input Disable Time9
Input Supply Current per Channel,
Quiescent 10
Output Supply Current per Channel,
Quiescent10
Input Dynamic Supply Current
per Channel 11
Output Dynamic Supply Current
per Channel11
Symbol
Min
Typ
tR/tF
|CMH|
25
|CML|
25
Unit
Test Conditions
2.5
35
ns
kV/μs
35
kV/μs
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
fr
tENABLE
tDISABLE
IDDI (Q)
1.1
2.0
5.0
0.25
0.38
Mbps
μs
μs
mA
IDDO (Q)
0.19
0.33
mA
IDDI (D)
0.07
IDDO (D)
0.02
1
Max
VIA, VIB, VIC = 0 V or VDD1
VIA, VIB, VIC = 0 V or VDD1
mA/
Mbps
mA/
Mbps
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (See Table 12).
10
IDDx (Q) is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in
the same orientation as Channel A must be included to account for the total current consumed.
11
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
2
Rev. F | Page 6 of 20
ADuM1310/ADuM1311
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION 1
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all min/max
specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C;
VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.0 V.
Table 3.
Parameter
DC SPECIFICATIONS
ADuM1310, Total Supply Current,
Three Channels 2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps (BRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
ADuM1311, Total Supply Current,
Three Channels2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps (BRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
For All Models
Input Currents
Logic High Input Threshold
VDDx = 5 V Operation
VDDx = 3 V Operation
Logic Low Input Threshold
VDDx = 5 V Operation
VDDx = 3 V Operation
Logic High Output Voltages
Logic Low Output Voltages
Symbol
Min
Typ
Max
Unit
Test Conditions
2.4
1.2
3.2
1.6
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
0.8
1.2
1.0
1.6
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
6.5
3.4
8.2
4.9
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
1.1
1.9
1.3
2.2
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
2.2
1.0
2.8
1.6
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
0.9
1.8
1.4
2.4
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
4.5
2.5
5.7
3.5
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
1.9
3.5
2.6
4.3
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
+0.01
+10
μA
0 ≤ VIA, VIB, VIC ≤ VDD1 or VDD2,
0 ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2,
0 ≤ VDISABLE ≤ VDD1
IDD1 (Q)
IDD2 (Q)
IDD1 (10)
IDD2 (10)
IDD1 (Q)
IDD2 (Q)
IDD1 (10)
IDD2 (10)
IIA, IIB, IIC, ICTRL1, −10
ICTRL2, IDISABLE
VIH
2.0
1.6
V
V
VIL
0.8
0.4
VOAH, VOBH, VOCH VDD1, VDD2 − 0.1 VDD1, VDD2
VDD1, VDD2 − 0.4 VDD1, VDD2 − 0.2
VOAL, VOBL, VOCL
0.0
0.1
0.2
0.4
Rev. F | Page 7 of 20
V
V
V
V
V
V
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
ADuM1310/ADuM1311
Parameter
SWITCHING SPECIFICATIONS
ADuM131xARW
Minimum Pulse Width 3
Maximum Data Rate 4
Propagation Delay 5
Pulse Width Distortion, |tPLH − tPHL|5
Propagation Delay Skew 6
Channel-to-Channel Matching 7
ADuM131xBRW
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
Channel-to-Channel Matching,
Opposing-Directional Channels7
For All Models
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
Common-Mode Transient Immunity
at Logic High Output 8
Common-Mode Transient Immunity
at Logic Low Output8
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
Input Enable Time 9
Input Disable Time9
Input Supply Current per Channel,
Quiescent 10
VDDx = 5 V Operation
VDDx = 3 V Operation
Output Supply Current per Channel,
Quiescent10
VDDx = 5 V Operation
VDDx = 3 V Operation
Input Dynamic Supply Current
per Channel 11
VDDx = 5 V Operation
VDDx = 3 V Operation
Symbol
Min
Typ
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/OD
1
25
Max
Unit
Test Conditions
1000
ns
Mbps
ns
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
100
40
50
50
PW
tPSK
tPSKCD
30
5
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
6
ns
tPHL, tPLH
PWD
100
10
20
60
5
5
tR/tF
CL = 15 pF, CMOS signal levels
|CMH|
25
2.5
2.5
35
ns
ns
kV/μs
|CML|
25
35
kV/μs
1.2
1.1
2.0
5.0
Mbps
Mbps
μs
μs
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
fr
tENABLE
tDISABLE
IDDI (Q)
IDDI (Q)
0.50
0.25
0.73
0.38
mA
mA
IDDO (Q)
IDDO (Q)
IDDI (D)
0.38
0.19
0.53
0.33
mA
mA
0.12
0.07
Rev. F | Page 8 of 20
mA/
Mbps
mA/
Mbps
VIA, VIB, VIC, VID = 0 V or VDD1
VIA, VIB, VIC, VID = 0 V or VDD1
ADuM1310/ADuM1311
Parameter
Output Dynamic Supply Current
per Channel
VDDx = 5 V Operation
VDDx = 3 V Operation
Symbol
IDDI (D)
Min
Typ
0.04
0.02
1
Max
Unit
Test Conditions
mA/
Mbps
mA/
Mbps
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (See Table 12).
10
IDDx (Q) is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in
the same orientation as Channel A must be included to account for the total current consumed.
11
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
2
Rev. F | Page 9 of 20
ADuM1310/ADuM1311
PACKAGE CHARACTERISTICS
Table 4.
Parameter
Resistance (Input-to-Output) 1
Capacitance (Input-to-Output)1
Input Capacitance 2
IC Junction-to-Case Thermal Resistance
Side 1
Side 2
Symbol
RI-O
CI-O
CI
Min
Typ
1012
2.2
4.0
Max
Unit
Ω
pF
pF
Test Conditions
f = 1 MHz
Thermocouple located at center of
package underside
θJCI
θJCO
33
28
°C/W
°C/W
1
Device considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and
Pin 16 shorted together.
2
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM131x have been approved by the organizations listed in Table 5.
Table 5.
UL 1
Recognized under 1577 component
recognition program
Single/basic insulation,
2500 V rms isolation voltage
File E214100
1
2
CSA
Approved under CSA Component
Acceptance Notice #5A
Reinforced insulation per CSA 60950-103 and IEC 60950-1,
400 V rms maximum working voltage
VDE 2
Certified according to DIN EN 60747-5-2
(VDE 0884 Part 2): 2003-01
Basic insulation, 560 V peak
Complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01,
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000
Reinforced insulation, 560 V peak
File 2471900-4880-0001
File 205078
In accordance with UL 1577, each ADuM131x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).
In accordance with DIN EN 60747-5-2, each ADuM131x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection
limit = 5 pC). The * marking branded on the component designates DIN EN 60747-5-2 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol Value
2500
L(I01)
7.7 min
Unit Conditions
V rms 1 minute duration
mm
Measured from input terminals to output terminals,
shortest distance through air
8.1 min
mm
Measured from input terminals to output terminals,
shortest distance path along body
0.017 min mm
Insulation distance through insulation
>175
V
DIN IEC 112/VDE 0303 Part 1
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Minimum External Tracking (Creepage)
L(I02)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
Rev. F | Page 10 of 20
ADuM1310/ADuM1311
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
The ADuM131x isolators are suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is
ensured by protective circuits. The * marking on packages denotes DIN EN 60747-5-2 approval.
Table 7.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110, Table 1)
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety-Limiting Values
Case Temperature
Side 1 Current
Side 2 Current
Insulation Resistance at TS
Conditions
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
Symbol
Characteristic
Unit
VIORM
VPR
I to IV
I to III
I to II
40/105/21
2
560
1050
V peak
V peak
896
672
V peak
V peak
VTR
4000
V peak
TS
IS1
IS2
RS
150
265
335
>109
°C
mA
mA
Ω
VPR
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Transient overvoltage, tTR = 10 sec
Maximum value allowed in the event of a failure;
see Figure 5
VIO = 500 V
RECOMMENDED OPERATING CONDITIONS
Table 8.
Parameter
Operating Temperature
Supply Voltages 1
Input Signal Rise and Fall Times
1
Symbol
TA
VDD1, VDD 2
Min
−40
2.7
Max
+105
5.5
1.0
Unit
°C
V
ms
All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields.
Rev. F | Page 11 of 20
ADuM1310/ADuM1311
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 9.
Parameter
Storage Temperature (TST)
Ambient Operating Temperature
(TA)
Supply Voltages (VDD1, VDD2)1
Input Voltage
(VIA, VIB, VIC, VDISABLE, VCTRL1, VCTRL2)1, 2
Output Voltage (VOA, VOB, VOC)1, 2
Average Output Current per Pin3
Side 1 (IO1)
Side 2 (IO2)
Common-Mode Transients 4
Rating
−65°C to +150°C
−40°C to +105°C
−0.5 V to +7.0 V
−0.5 V to VDDI + 0.5 V
ESD CAUTION
−0.5 V to VDDO + 0.5 V
−18 mA to +18 mA
−22 mA to +22 mA
−100 kV/μs to +100
kV/μs
1
All voltages are relative to their respective ground.
VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PC Board Layout section.
3
See Figure 5 for maximum rated current values for various temperatures.
4
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Ratings may cause latchup or permanent damage.
2
Rev. F | Page 12 of 20
ADuM1310/ADuM1311
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
16 VDD2
*GND1 2
15 GND2*
VIA 3
14 VOA
ADuM1310
13 VOB
TOP VIEW
VIC 5 (Not to Scale) 12 VOC
NC 6
DISABLE 7
*GND1 8
11 NC
10 CTRL2
9
NC = NO CONNECT
GND2*
04904-003
VIB 4
*Pin 2 and Pin 8 are internally connected, and connecting both to GND 1 is recommended.
Pin 9 and Pin 15 are internally connected, and connecting both to GND 2 is recommended.
Figure 3. ADuM1310 Pin Configuration
Table 10. ADuM1310 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
Mnemonic
VDD1
GND1
VIA
VIB
VIC
NC
DISABLE
8
9
10
GND1
GND2
CTRL2
11
12
13
14
15
16
NC
VOC
VOB
VOA
GND2
VDD2
Description
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
No Connection.
Input Disable. Disables the isolator inputs and halts the dc refresh circuits. Outputs take on the logic state
determined
by CTRL2.
Ground 1. Ground reference for isolator Side 1.
Ground 2. Ground reference for isolator Side 2.
Default Output Control. Controls the logic state the outputs take on when the input power is off. VOA, VOB, and VOC
outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA, VOB, and VOC outputs are low when CTRL2 is
low and VDD1 is off. When VDD1 power is on, this pin has no effect.
No Connection.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for isolator Side 2.
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. F | Page 13 of 20
ADuM1310/ADuM1311
VDD1 1
16 VDD2
*GND1 2
15 GND2*
VIA 3
14 VOA
ADuM1311
13 VOB
TOP VIEW
VOC 5 (Not to Scale) 12 VIC
NC 6
11 NC
CTRL1 7
10 CTRL2
*GND1 8
9
GND2*
NC = NO CONNECT
04904-004
VIB 4
*Pin 2 and Pin 8 are internally connected, and connecting both to GND 1 is recommended.
Pin 9 and Pin 15 are internally connected, and connecting both to GND 2 is recommended.
Figure 4. ADuM1311 Pin Configuration
Table 11. ADuM1311 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
Mnemonic
VDD1
GND1
VIA
VIB
VOC
NC
CTRL1
8
9
10
GND1
GND2
CTRL2
11
12
13
14
15
16
NC
VIC
VOB
VOA
GND2
VDD2
Description
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for isolator Side 1.
Logic Input A.
Logic Input B.
Logic Output C.
No Connection.
Default Output Control. Controls the logic state the outputs take on when the input power is off. VOC output is high
when CTRL1 is high or disconnected and VDD2 is off. VOC output is low when CTRL1 is low and VDD2 is off. When VDD2
power is on, this pin has no effect.
Ground 1. Ground reference for isolator Side 1.
Ground 2. Ground reference for isolator Side 2.
Default Output Control. Controls the logic state the outputs take on when the input power is off. VOA and VOB outputs
are high when CTRL2 is high or disconnected and VDD1 is off. VOA and VOB outputs are low when CTRL2 is low and VDD1 is
off. When VDD1 power is on, this pin has no effect.
No Connection.
Logic Input C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for isolator Side 2.
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. F | Page 14 of 20
ADuM1310/ADuM1311
Table 12. Truth Table (Positive Logic)
VIx
Input 1
H
L
X
X
X
CTRLx
Input 2
X
X
H or NC
L
H or NC
VDISABLE
State 3
L or NC
L or NC
H
H
X
VDDI
State 4
Powered
Powered
X
X
Unpowered
VDDO
State 5
Powered
Powered
Powered
Powered
Powered
X
L
X
Unpowered Powered
X
X
X
Powered
VOx
Output
H
L
H
L
H
L
Unpowered Z
Notes
Normal operation, data is high.
Normal operation, data is low.
Inputs disabled. Outputs are in the default state as determined by CTRLx.
Inputs disabled. Outputs are in the default state as determined by CTRLx.
Input unpowered. Outputs are in the default state as determined by CTRLx.
Outputs return to input state within 1 μs of VDDI power restoration. See the
pin function tables (Table 10 and Table 11) for more details.
Input unpowered. Outputs are in the default state as determined by CTRLx.
Outputs return to input state within 1 μs of VDDI power restoration. See the
pin function tables (Table 10 and Table 11) for more details.
Output unpowered. Output pins are in high impedance state.
Outputs return to input state within 1 μs of VDDO power restoration.
See the pin function tables (Table 10 and Table 11) for more details.
1
VIx and VOx refer to the input and output signals of a given channel (A, B, or C).
CTRLx refers to the default output control signal on the input side of a given channel (A, B, or C).
3
Available only on the ADuM1310.
4
VDDI refers to the power supply on the input side of a given channel (A, B, or C).
5
VDDO refers to the power supply on the output side of a given channel (A, B, or C).
2
Rev. F | Page 15 of 20
ADuM1310/ADuM1311
1.4
300
1.2
CURRENT/CHANNE L (mA)
350
250
SIDE 2
200
150
SIDE 1
100
0
0
50
100
150
CASE TEMPERATURE (°C)
1.0
5V
0.8
0.6
3V
0.4
0.2
04904-008
50
04904-005
SAFETY-LIMITING CURRENT (mA)
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
200
Figure 5. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN EN 60747-5-2
2
4
6
DATA RATE (Mbps)
8
10
Figure 8. Typical Supply Current per Output Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
2.0
6
5V
CURRENT (mA)
4
1.0
3V
3V
2
0
0
2
4
6
DATA RATE (Mbps)
8
04904-009
0.5
04904-006
CURRENT/CHANNE L (mA)
5V
1.5
0
10
0
Figure 6. Typical Supply Current per Input Channel vs. Data Rate
for 5 V and 3 V Operation
2
4
6
DATA RATE (Mbps)
8
10
Figure 9. Typical ADuM1310 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
1.0
6
0.9
5V
0.7
4
CURRENT (mA)
CURRENT/CHANNE L (mA)
0.8
0.6
0.5
0.4
3V
0.3
5V
2
3V
0.1
0
0
2
4
6
DATA RATE (Mbps)
8
04904-010
04904-007
0.2
0
10
0
Figure 7. Typical Supply Current per Output Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
2
4
6
DATA RATE (Mbps)
8
10
Figure 10. Typical ADuM1310 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
Rev. F | Page 16 of 20
ADuM1310/ADuM1311
6
6
5V
3V
2
0
0
2
4
6
DATA RATE (Mbps)
8
5v
2
3v
04904-012
CURRENT (mA)
4
04904-011
CURRENT (mA)
4
0
0
10
Figure 11. Typical ADuM1311 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
2
4
6
DATA RATE (Mbps)
8
10
Figure 12. Typical ADuM1311 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
Rev. F | Page 17 of 20
ADuM1310/ADuM1311
APPLICATION INFORMATION
PC BOARD LAYOUT
The ADuM131x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 13). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16
for VDD2. The capacitor value should be between 0.01 μF and
0.1 μF. The total lead length between both ends of the capacitor
and the input power supply pin should not exceed 20 mm.
Bypassing between Pin 1 and Pin 8 and between Pin 9 and
Pin 16 should be considered, unless both of the ground pins on
each package are connected together close to the package.
VDD1
VDD2
GND1
GND2
VIA
VOA
VIB
VOB
VIC/VOC
VOC/VIC
NC
CTRL2
GND1
GND2
04904-013
NC
CTRL1
Figure 13. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isolation
barrier is minimized. Furthermore, the board layout should be
designed such that any coupling that does occur equally affects
all pins on a given component side. Failure to ensure this can
cause voltage differentials between pins exceeding the device’s
absolute maximum ratings, thereby leading to latch-up or
permanent damage.
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-tooutput propagation delay time for a high-to-low transition may
differ from the propagation delay time of a low-to-high transition.
INPUT (VIx)
50%
OUTPUT (VOx)
tPHL
50%
04904-014
tPLH
Figure 14. Propagation Delay Parameters
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM131x component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM131x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is therefore either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than 2 μs, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than about 5 μs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 12)
by the watchdog timer circuit.
The magnetic field immunity of the ADuM131x is determined
by the changing magnetic field, which induces a voltage in the
transformer’s receiving coil large enough to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this can occur. The 3 V operating condition of the
ADuM131x is examined because it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt)∑πrn2; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM131x and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field at a given frequency can be calculated. The result
is shown in Figure 15.
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Rev. F | Page 18 of 20
ADuM1310/ADuM1311
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kguass)
100
for Various Current-to-ADuM131x Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces can
induce error voltages sufficient to trigger succeeding circuitry.
Care should be taken in the layout of such traces to avoid this
possibility.
10
1
POWER CONSUMPTION
0.1
The supply current at a given channel of the ADuM131x
isolator is a function of the supply voltage, the channel’s data
rate, and the channel’s output load.
0.001
1k
04904-015
0.01
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
For each input channel, the supply current is given by
100M
Figure 15. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V—still well above the 0.5 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM131x transformers. Figure 16 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown, the ADuM131x is extremely immune and
can be affected only by extremely large currents operated at
high frequency very close to the component. For the 1 MHz
example noted, one would have to place a 0.5 kA current 5 mm
away from the ADuM131x to affect the component’s operation.
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
04904-016
MAXIMUM ALLOWABLE CURRENT (kA)
1000
0.01
1k
10k
100k
1M
10M
IDDI = IDDI (Q)
f ≤ 0.5 fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q)
f > 0.5 fr
For each output channel, the supply current is given by
IDDO = IDDO (Q)
f ≤ 0.5 fr
−3
IDDO = (IDDO (D) + (0.5 × 10 ) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half of the input
data rate expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. The ADuM131x
contains an internal data channel that is not available to the
user. This channel is in the same orientation as Channel A and
consumes quiescent current. The contribution of this channel
must be included in the total quiescent current calculation for
each supply. Figure 6 and Figure 7 provide per-channel supply
currents as a function of data rate for an unloaded output
condition. Figure 8 provides per-channel supply current as a
function of data rate for a 15 pF output condition. Figure 9
through Figure 12 provide total VDD1 and VDD2 supply current as
a function of data rate for ADuM1310/ADuM1311 channel
configurations.
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 16. Maximum Allowable Current
Rev. F | Page 19 of 20
ADuM1310/ADuM1311
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
8
1
1.27 (0.0500)
BSC
0.75 (0.0295)
× 45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0.33 (0.0130) 0°
0.20 (0.0079)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 17. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimension shown in millimeters and (inches)
ORDERING GUIDE
Model
Number Number Maximum Maximum
Maximum
of Inputs, of Inputs, Data Rate Propagation Pulse Width Temperature
VDD1 Side VDD2 Side (Mbps)
Delay, 5 V (ns) Distortion (ns) Range
Package Description
Package
Option
ADuM1310ARWZ 1
ADuM1310ARWZ-RL1
ADuM1310BRWZ1
ADuM1310BRWZ-RL1
ADuM1311ARWZ1
ADuM1311ARWZ-RL1
ADuM1311BRWZ1
ADuM1311BRWZ-RL1
3
3
3
3
2
2
2
2
16-Lead SOIC_W
16-Lead SOIC_W, 13” Reel
16-Lead SOIC_W
16-Lead SOIC_W, 13” Reel
16-Lead SOIC_W
16-Lead SOIC_W, 13” Reel
16-Lead SOIC_W
16-Lead SOIC_W, 13” Reel
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
1
0
0
0
0
1
1
1
1
1
1
10
10
1
1
10
10
100
100
50
50
100
100
50
50
40
40
5
5
40
40
5
5
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Z = Pb-free part.
©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04904-0-1/07(F)
T
T
Rev. F | Page 20 of 20