LX1675 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET KEY FEATURES DESCRIPTION High current MOSFETs can be directly driven to provide an LDO output of 5A and 15A for each PWM controller. This is useful for I/O, memory, termination, and other supplies surrounding today’s micro-processor based designs. The LX1675 accepts a wide range of supply voltage ranging from 4.5V to 24V. Each PWM regulator output voltage is programmed via a simple voltage-divider network. The LX1675 design gives engineers maximum flexibility with respect to the MOSFET supply. Each phase can utilize different supply voltages for efficient use of available supply rails. Additionally, when two phases are configured in Bi-Phase output, the LoadSHARE™ topology can be programmed via inductor ESR selection. The split phase operation reduces power loss, noise due to the ESR of the input capacitors and allows for reduction in capacitance values while maximizing regulator response time. The internal reference voltage is buffered and brought out on a separate pin to be used as an external reference voltage. IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com LoadSHARE is a Trademark of Microsemi Corporation Protected by U.S. Patents 6,285,571 and 6,292,378 Four Independently Regulated Outputs Single Input Supply with Wide Voltage Range: 4.5-24V Outputs As Low As 0.8V Generated From a Precision Internal Reference Selectable PWM Frequency of 300KHz or 600KHz Buffered Reference Voltage Output Multiphase Output Reduces Need for Large Input Capacitance at High Currents Integrated High Current MOSFET Drivers Independent Soft-Start and Power Sequencing Adjustable Linear Regulator Driver Output No Current-Sense Resistors DDR Termination Compliant RoHS Compliant for Pb Free WWW . Microsemi .C OM The LX1675 is a highly integrated power supply controller IC featuring three voltage mode PWM switching regulator stages with an additional onboard linear regulator driver. Two of the constant frequency PWM phases can be easily configured for a single Bi-Phase high current output or operated as two independently regulated outputs. All outputs (PWM phases and LDO) have separate, programmable softstart sequencing. This versatility yields either three or four independently regulated outputs with full power sequencing capability giving system designers the ultimate flexibility in power supply design. Current limit for each PWM regulator is provided by monitoring the voltage drop across the lower MOSFET power stage during conduction, utilizing the Rds(on) impedance. This eliminates the need for expensive current sense resistors. Once current limit has been reached and persist for 4 clock cycles, the output is shut off and Soft Start is initialized to force a hiccup mode for protection. APPLICATIONS Multi-Output Power Supplies Video Card Power Supplies PC Peripherals Portable PC Processor and I/O Supply PACKAGE ORDER INFO PRODUCT HIGHLIGHT VIN 4.5V to 24V TA (°C) LQ Plastic MLPQ 38-Pin RoHS Compliant / Pb-free VIN VCCL 0 to 85 -40 to 85 HOX VSLR VCX LDGD HRX 5µh VOUT4 LDFB LX1675 VOUT1, 2, 3 CSX LOX AGND PGX EOX FBX Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1675CLQ-TR) LX1675 SSX LX1675CLQ LX1675ILQ ONE OF 3 PWM SECTIONS Copyright © 2004 Rev. 1.2a, 2006-02-16 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 1 LX1675 TM ® Multiple Output LoadSHARE™ PWM P RODUCTION D ATA S HEET PACKAGE PIN OUT Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of specified terminal. Limitations affecting transient pulse duration is thermally related to the clamping zener diodes connected to the supply pins, application of maximum voltage will increase current into that pin and increase power dissipation. x denotes respective pin designator 1, 2, or 3. 1 38 37 36 35 33 34 32 31 2 30 3 29 4 28 5 27 Connect Bottom to Power GND 6 7 26 25 8 24 9 23 10 22 21 11 12 13 14 15 16 17 18 19 20 HR3 LO3 PG3 VCCL VIN CS1 DGND CS3 FS EO3 FB3 SS3 LDGD VSLR SSL LDFB SS1 AGND VREF LO2 HR2 HO2 VC2 CS2 SF EO2 FB2 SS2 RF2 EO1 FB1 WWW . Microsemi .C OM Supply Voltage (VIN, VSLR, HRX) ............................................................... -0.3V to 24V Supply Voltage (VCCL) ................................................................................ -0.3V to 6.0V Driver Supply Voltage (VCX) ........................................................................ -0.3V to 30V Current Sense Inputs (CSX)............................................................................ -0.3V to 30V Error Amplifier Inputs (FBX, RF2, LDFB) .................................................... -0.3V to 5.5V Internal regulator Current (IVCCL)............................................................................... 50mA Output Drive Peak Current Source (HOX, LOX) ................................................ 1A (200ns) Output Drive Peak Current Sink (HOX, LOX) ................................................. 1.5A (200ns) Differential Voltage: VHOX – VHRX (High Side Return) .................................... -0.3V to 6V Soft Start Input (SSX, SSL) ............................................................................-0.3V to VREF Logic Inputs (SF, FS)..........................................................................-0.3V to VCCL + 0.5V LDO Gate Drive (LDGD) Output Drive can source .................................................. 10mA LDO Feedback (LDFB) Input.......................................................................................6.0V Operating Junction Temperature................................................................................ 150°C Operating Temperature Range .......................................................................-40°C to 85°C Storage Temperature Range.........................................................................-65°C to 150°C Peak Package Solder Reflow Temp. (40 seconds maximum exposure) ......... 260°C (+0 -5) PG1 LO1 HR1 HO1 VC1 VC3 HO3 ABSOLUTE MAXIMUM RATINGS LQ PACKAGE (Top View) RoHS / Pb-free 100% Matte Tin Lead Finish THERMAL DATA LQ Plastic MLPQ 38-Pin THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA 30 to 55°C/W Junction Temperature Calculation: TJ = TA + (PD x θJA). The θJA numbers are dependent on heat spreading and layout considerations for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. PACKAGE DATA Copyright © 2004 Rev. 1.2a, 2006-02-16 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 2 LX1675 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET FUNCTIONAL PIN DESCRIPTION Description FB1 Bi-Phase Operation: Phase 1 and 2 Voltage Feedback Single Phase Operation: Phase 1 Voltage Feedback, connect to the output through a resistor network to set desired output voltage of Phase 1. FB2 Bi-Phase Operation: Load Sharing Voltage Sense Feedback – Connect filtered phase 2 switching output (pre-inductor) to FB2 to ensure proper current sharing between phase 1 and phase 2. Single Phase Operation: Phase 2 Voltage Feedback, connect to the output through a resistor network to set desired output voltage of Phase 2. FB3 Phase 3 Voltage Feedback , connect to the output through a resistor network to set desired output voltage of Phase 3. RF2 Bi-Phase Operation: Load Sharing Voltage Sense Feedback Reference – Sets reference for current sharing control loop. Connecting filtered phase 1 switching output (pre-inductor) to RF2 forces the average current in phase 2 to be equal to phase 1. Single Phase Operation: Phase 2 Voltage Reference – connected to SS2 pin as the reference. EOX Error Amplifier Output – Sets external compensation for the corresponding phase denoted by “X”. VIN Controller supply voltage. WWW . Microsemi .C OM Name VCCL For 4.5V < VIN < 6V, this pin becomes the input voltage supply for the controller’s internal logic and gate drivers. For VIN > 6V this pin is an output of the internal 5V regulator that supplies internal logic, Low Side Gate drivers and High Side charge pump capacitor charging, if used. User must provide low ESR decoupling capacitor for pulse load currents AGND Analog ground reference. DGND Digital/Switching ground reference for current paths of the PWM driver circuits. VSLR Supply pin for LDO regulator section. LDFB Low Dropout Regulator Voltage Feedback – Sets the output voltage of external MOSFET via resistor network. LDGD Low Dropout Regulator Gate Drive – Connects to gate of external N-MOSFET for linear regulator supply. SSL LDO Enable and Soft-start/Hiccup Capacitor Pin - During start-up, the voltage on this pin ramps from 0V to VREF controlling the output voltage of the regulator. An internal 20kΩ resistor connected to VREF and the external capacitor set the time constant for soft-start function. The Soft-start function does not initialize until the supply voltage exceeds the UVLO threshold. SF Shared Fault - If SF input = Logic 1(VCCL) and current limit threshold is reached during 4 clock cycles all outputs are shutdown by discharging SS caps to zero and the start-up sequence begins again, this becomes hiccup mode protection with the duty cycle set by the size of the SS capacitor. When operated in Bi-phase mode, SF must be set High. If SF = logic 0, the other outputs continue to function normally and the faulted output enters the hiccup mode for current limit. FS Frequency Select Logic Input - Connect to ground for 300KHz and VCCL for 600KHz operation. Input has 100KΩ Pull down resistor. VREF Buffered version of the internal 0.8 voltage reference. Over-Current Limit Set – Connecting a resistor between CSX pin and the drain of the low-side MOSFET sets the currentlimit threshold for the corresponding phase denoted by “X”. A minimum of 500Ω must be in series with this input. Whenever the current limit threshold is reached for 4 consecutive clock cycles the soft start capacitor is discharged through an internal resistor initiating Soft Start and Hiccup mode. SSX Enable & Soft-start/Hiccup Capacitor Pin – During start-up, the voltage on this pin controls the output voltage of its respective regulator. An internal 20kΩ resistor and the external capacitor set the time constant for soft-start function. The Soft-start function does not initialize until the supply voltage exceeds the UVLO threshold. When an over-current condition occurs, this capacitor is used for the timing of hiccup mode protection. Pulling the SS pin below 0.1V disables the corresponding phase denoted by “X”. VCX PWM High-Side MOSFET Gate Driver Supply – Connect to separate supply or to boot strap supply to ensure proper high-side gate driver supply voltage. “X” denotes corresponding phase. If the phase is not used connect to VCC. HOX High Side MOSFET Gate Driver – “X” denotes corresponding phase. LOX Low Side MOSFET Gate Driver – “X” denotes corresponding phase. PGX Low-side Driver Power Ground. Connects to the source of the bottom N-channel MOSFETS of each phase, where X denotes corresponding phase. PG1 is the shared ground of PWM 1 and PWM 2 Low-side drivers. HRX High Side driver return, connect this pin to High Side MOSFET source. “X” denotes corresponding phase. Copyright © 2004 Rev. 1.2a, 2006-02-16 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 3 PACKAGE DATA CSX LX1675 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET For the LX1675ILQ the following specifications apply over the ambient temperature -40°C < TA < 85°C and for the LX1675CLQ 0°C ≤ TA ≤ 85°C except where otherwise noted and the following test conditions: VIN & VSLR = 12V, VCX = 17V, HOX and LOX =3000pF Load, FS = 0 (f = 300KHz). Parameter ` Operation Current Feedback Voltage Internal Reference Line Regulation Load Regulation High Side Minimum Pulse Width Maximum Duty Cycle ` Lox Minimum On Time Buffered Reference Voltage ERROR AMPLIFIER Input Offset Voltage DC Open Loop Gain Unity gain bandwidth High Output Voltage Low Output Voltage Input Common Mode Range Input Bias Current CURRENT SENSE CS Bias Current (Source) CS Trip Threshold CS Delay (Blanking) VIN VCX VCCL IVIN VFB PWMDC VLOx VREF VOS AVUGBW VOH VOL IIN ISET VTRIP TCSD VIH Shared Fault Mode VIL ` Min LX1675 Typ Max Units Maximum Load OSCILLATOR Copyright © 2004 Rev. 1.2a, 2006-02-16 4.5 Static 4.5V < VIN < 12V System Level measurement, Closed Loop Load = 3000pF 600kHz @ 25°C from 3V going high to 1V going low Max Load Current 0.5mA Common Mode Input Voltage = 1V I Source = 2mA I Sink = 100µA Input Offset Voltage < 20mV 0V and 3.5V Common Mode Voltage VCSX = -0.2V, VPGX = 0V @ 25°C Referenced to VCSX, VPGX = 0V Any PWM Output Activating Current Limit for More than 4 Clock Cycles, Soft Starts all PWM Outputs Current Limit Event of One PWM Does Not Effect the Continued Function of the Two Other PWM Regulators FSW 24 30 6 6 V mA 0.784 0.816 V -1 -1 1 1 % % nS % % nS V 50 74 85 180 0.778 225 -7.0 3.75 320 0.822 7.0 70 10 5.0 100 3.5 0.1 100 48 55 ±3 150 62 mV dB MHz V mV V nA µA mV nS 2 V 0.8 Static Static CL = 3000pF 2.5 3 50 mA mA nS Drive Load = 3000pF, VDRIVE < 1V 50 nS IHOx = 20mA, VCx – HRx = 5.0V IHOx = -20mA, VCx – HRx = 5.0V 4.8 ILOx = 20mA, VCCL – PGx = 5.0V ILOx = -20mA, VCCL – PGx = 5.0V VCx – HRx = 5.0V, Capacitive Load, PW < 200ns VCCL – PGx = 5.0V, Capacitive Load, PW < 200ns 4.8 QgMAX PWM Switching Frequency Ramp Amplitude ILOx Regulator Functional VFS <0.8V @ 25°C VFS >2V @ 25°C 255 510 VRAMP Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 4.9 0.1 4.9 0.1 ±1 V 0.2 V 0.2 APEAK ±1.5 APEAK 50 nC 300 600 1.6 345 690 KHz KHz VPP Page 4 ELECTRICALS OUTPUT DRIVERS – N Channel MOSFETS Low Side Driver Operating Current IVCCL High Side Driver Operating Current IVCX Drive Rise and Fall Time TR/F Dead Time – High Side to Low Side TDEAD or Low Side to High Side High Side Driver Voltage VHOx Drive High Drive Low Low Side Driver Voltage VLOx Drive High Drive Low High Side Driver Current IHOx Low Side Driver Current ` Test Conditions SWITCHING REGULATORS Input Voltage ` Symbol WWW . Microsemi .C OM ELECTRICAL CHARACTERISTICS LX1675 ® TM Multiple Output LoadSHARE™ PWM P RODUCTION D ATA S HEET ` ` ` INTERNAL 5V REGULATOR Regulated Output VCCL UVLO AND SOFT-START (SS) Start-Up Threshold (VCX, VCCL, VIN) Hysteresis SS Input Resistance RSS SS Shutdown Threshold VSHDN Hiccup Mode Duty Cycle LINEAR REGULATOR CONTROLLER Voltage Reference Tolerance LDO Supply IVSLR LDO Gate Drive Source Current Sink Current LDO Output Voltage Range Regulator Disable Threshold ILDGD ILDGD VOUT4 VSSL Load Regulation LOGIC INPUTS FS,SF ` 4.5 5.5 V Rising 3.75 4.38 V CSS = 0.1µF VLDFB = 0.8V, COUT = 330µF VSLR = 12V VOH, Output Source Current = 0.5mA VOH, Output Source Current = 10mA VLDGD = 7.5V VLDGD = 0.4V THERMAL SHUTDOWN Die Temperature TSD 0.30 20 100 6 V KΩ mV % 3 4 % mA 9.0 7.35 10 0.25 0.8 5.25 100 Note 2, 1V < VLDO – VOUT4 < 10V, IVOUT4 = 50mA Note 2 Line Regulation ` Internal + External Load: 0mA < IVCCL < 50mA Threshold Logic High Threshold Logic Low Pulldown Resistance Hiccup Mode Operation at Limit V mA mA V mV -1 1 % -1 1 % 2 V V KΩ °C 0.8 100 160 WWW . Microsemi .C OM ELECTRICAL CHARACTERISTICS (CONTINUED) For the LX1675ILQ the following specifications apply over the ambient temperature -40°C < TA < 85°C and for the LX1675CLQ 0°C < TA < 85°C except where otherwise noted and the following test conditions: VIN & VSLR = 12V, VCX = 17V, HOX and LOX =3000pF Load, FS = 0 (f = 300KHz). LX1675 Parameter Symbol Test Conditions Units Min Typ Max Note 1: X = Phase 1, 2, 3 Note 2: System Level Measurement; Closed Loop ELECTRICALS Copyright © 2004 Rev. 1.2a, 2006-02-16 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 5 LX1675 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET SIMPLIFIED BLOCK DIAGRAM WWW . Microsemi .C OM RSET +5V CSx VIN R1 VCx ISET CIN 50uA CS Comp R2 - PWM R + HOx Q LX HRx S CLK EOx ESR LOx 4 CYCLE COUNTER Error Comp COUT PGx VIN + + Hiccup - +5V + Amplifier/ Compensation SSx VIN Vref FBx OUT X SS COMP BG - 100mv +5V Regulator + VCCL + 20K VREF CSS RAMP CLK F 500k FAULT S Ramp Oscillator FS UVLO R SSMSK TSD AGND SF Figure 1 – Typical Block Diagram for Phases 1, and 3 VIN VSLR 9.6V Regualtor SSL + - LDOEA LDGD VOUT4 20K VREF BLOCK DIAGRAM CSS CIN + LDFB 500k F LDOFLT SF Figure 2 – LDO Controller Block Diagram Copyright © 2004 Rev. 1.2a, 2006-02-16 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 6 LX1675 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET SIMPLIFIED BLOCK DIAGRAM WWW . Microsemi .C OM RSET +5V CS2 VIN LPF2 VC2 ISET CIN 50uA CS Comp - PWM R + HO2 Q L2 HR2 S CLK EO2 ESR LO2 Error Comp 4 CYCLE COUNTER COUT PGx VIN + + Hiccup - +5V + Amplifier/ Compensation LPF1 VIN Vref FB2 OUT 2 RF2 BG SS COMP 100mv - +5V Regulator + VCCL + 20K VREF RAMP SS2 CLK Phase 1 500k F FAULT S Ramp Oscillator FS UVLO CSS R SSMSK TSD AGND Figure 3 – Block Diagram of Phase 2 Connected in LoadSHARE Mode BLOCK DIAGRAM Copyright © 2004 Rev. 1.2a, 2006-02-16 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 7 LX1675 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET APPLICATION CIRUIT CR1 +VIN +VIN TP37 TP2 MBR0530 CR3 C7 + 16V L2 6.8uh TP3 + MBR0530 TP4 C6 C1 TP5 470uF TP35 16V 10 C14 0.22uF 12 Q2 33 TP34 HO3 VC3 VC1 FS RF2 EO3 EO1 FB3 FB1 SS3 TP29 TP33 31 +VIN 30 29 C9 28 + 4.7uF 16V 27 C10 R14 26 4.7uF 25V R4 24 23 2.00K 22pF C16 +2.5V R5 1.2nF TP27 TP30 R9 R7 21.0K TP31 R22 45.3K VREF +2.5V OUT TP23 Q4B FDS6898A 100K 20 TP22 C21 470uF 16V 22 21 L3 6.8uh + C15 TP26 FS TP32 Q4A FDS6898A 2.00K 25 C18 0.33uF 0.0 C11 470uF C20 1.5nF 20 R10 24.3K IRF7822 TP12 TP15 C23 0.1uF R1 C8 470uF 16V HO1 HR1 LO1 SS2 R20 + PG1 CS3 13 +2.5V C5 470uF 16V 11 FB2 VREF 14.3K DGND 19 9 R13 CS1 U2 LX1675CLQ EO2 AGND 45.3K SF 18 8 VIN SS1 22pF CS2 LDFB 7 C19 R11 SF 100K 1.2nF 24.3K 1.5nF 6 VCCL 17 TP11 PG3 VC2 16 5 R6 R12 HO2 SSL TP10 4 15 C17 +1.2V OUT TP9 32 34 35 37 36 38 3 2.00K HR3 LO3 VSLR R8 R19 20 HR2 LDGD 2 LO2 14 1 + C28 0.33uF 2.10K R2 C29 TP24 VIA 470pF 1.69K TP17 C26 TP13 TP25 0.1uF +VIN TP7 TP16 TP6 C4 470uF Q1B FDS6898A C13 C22 L1 6.8uh + 0.1uF Q3B FDS6898A +1.8V OUT TP38 0.1uF 16V TP8 C2 470uF 16V TP36 Q1A FDS6898A + C12 TP21 4.7uF Q3A FDS6898A TP20 +3.3V OUT C32 470uF WWW . Microsemi .C OM CR2 MBR0530 TP1 22pF +VIN TP18 TP19 R16 R21 45.3K 20 R17 88.7K +VIN TP28 RTN + C27 100uF 25V C24 1.2nF R15 100K C25 1.5nF R18 24.3K Figure 4 – Four Separate Voltage Outputs with Sequential Power Up Sequence. All High-side MOSFET Drivers Bootstrapped to VIN. APPLICATIONS Copyright © 2004 Rev. 1.2a, 2006-02-16 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 8 LX1675 TM Multiple Output LoadSHARE™ PWM ® P RODUCTION D ATA S HEET THEORY OF OPERATION CONFIGURATION The basic principle used in LoadSHARE, in a multiple phase buck converter topology, is that if multiple, identical, inductors have the same identical voltage impressed across their leads, they must then have the same identical current passing through them. The current that we would like to balance between inductors is mainly the DC component along with as much as possible the transient current. All inductors in a multiphase buck converter topology have their output side tied together at the output filter capacitors. Therefore this side of all the inductors have the same identical voltage. If the input side of the inductors can be forced to have the same equivalent DC potential on this lead, then they will have the same DC current flowing. To achieve this requirement, phase 1 will be the control phase that sets the output operating voltage, under normal PWM operation. To force the current of phase 2 to be equal to the current of phase 1, a second feedback loop is used. Phase 2 has a low pass filter connected from the input side of each inductor. This side of the inductors has a square wave signal that is proportional to its duty cycle. The output of each LPF is a DC (+ some AC) signal that is proportional to the magnitude and duty cycle of its respective inductor signal. The second feedback loop will use the output of the phase 1 LPF as a reference signal for an error amplifier that will compare this reference to the output of the phase 2 LPF. This error signal will be amplified and used to control the PWM circuit of phase 2. Therefore, the duty cycle of phase 2 will be set so that the equivalent voltage potential will be forced across the phase 2 inductor as compared to the phase 1 inductor. This will force the current in the phase 2 inductor to follow and be equal to the current in the phase 1 inductor. There are four methods that can be used to implement the LoadSHARE feature of the LX1675 in the Bi-Phase mode of operation. Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 9 APPLICATIONS Copyright © 2004 Rev. 1.2a, 2006-02-16 Hiccup is disabled during the soft-start interval, allowing start up with maximum current. If the rate of rise of the output voltage is too fast, the required charging current to the output capacitor may be higher than the current limit setting. In this case, the peak MOSFET current is regulated to the limit-current by the current-sense comparator. If the MOSFET current still reaches its limit after the soft-start finishes, the hiccup is triggered again. When the output has a short circuit the hiccup circuit ensures that the average heat generation in both MOSFETs and the average current is much less than in normal operation. Over-current protection can also be implemented using a sense resistor, instead of using the RDS(ON) of the lower MOSFET, for greater set-point accuracy. OSCILLATOR FREQUENCY An internal oscillator has a selectable switching frequency of 300kHz or 600kHz set by the FS logic input pin. Connect FS to ground for 300kHz and to VCCL for 600kHz operation. THEORY OF OPERATION FOR A BI-PHASE, LOADSHARE WWW . Microsemi .C OM GENERAL DESCRIPTION The LX1675 is a voltage-mode pulse-width modulation controller integrated circuit. The internal ramp generator frequency is set to 300kHz or 600kHz by the FS logic input. The device has external compensation, for more flexibility of output current magnitude. UNDER VOLTAGE LOCKOUT (UVLO) At power up, the LX1675 monitors the supply voltage at the VCCL pin. The VIN supply voltage has to be sufficient to produce a voltage greater that 4.4 volts at the VCCL pin before the controller will come out of the under-voltage lock-out state. The soft-start (SS) pin is held low to prevent soft-start from beginning and the oscillator is disabled and all MOSFETs are held off. SOFT-START Once the VCCL output is above the UVLO threshold, the softstart capacitor begins to be charged by the reference through a 20kΩ internal resistor. The capacitor voltage at the SS pin rises as a simple RC circuit. The SS pin is connected to the error amplifier’s non-inverting input that controls the output voltage. The output voltage will follow the SS pin voltage if sufficient charging current is provided to the output capacitor. The simple RC soft-start allows the output to rise faster at the beginning and slower at the end of the soft-start interval. Thus, the required charging current into the output capacitor is less at the end of the soft-start interval. A comparator monitors the SS pin voltage and indicates the end of soft-start when SS pin voltage reaches 95% of VREF. OVER-CURRENT PROTECTION (OCP) AND HICCUP The LX1675 uses the RDS(ON) of the lower MOSFET, together with a resistor (RSET) to set the actual current limit point. The current sense comparator senses the MOSFET current 50nS after the lower MOSFET is switched on in order to reduce inaccuracies due to ringing. A current source supplies a current (ISET), whose magnitude is 50µA. The set resistor RSET is selected to set the current limit for the application. RSET should be connected directly at the lower MOSFET drain and the source needs a low impedance return to get an accurate measurement across the low resistance RDS(ON). When the sensed voltage across RDS(ON) plus the set resistor voltage drop exceeds the 0.0Volt, VTRIP threshold, the OCP comparator outputs a signal to reset the PWM latch on a cycle by cycle basis until the current limit counter has reached a count of 4. After a count of 4 the hiccup mode is started. The soft-start capacitor (CSS) is discharged slowly (14 times slower than when being charged up by RSS). When the voltage on the SS pin reaches a 0.1V threshold, hiccup finishes and the circuit soft-starts again. During hiccup both MOSFETs for that phase are held off. The Shared Fault, SF logic input, allows all phases to be totally independent if the SF pin is grounded. If the SF pin is tied to VCCL then when one phase has a fault and goes into the hiccup mode, all phases, including the LDO output will go into the hiccup mode together. LX1675 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET THEORY OF OPERATION (CONTINUED) BI-PHASE, LOADSHARE (FEEDBACK DIVIDER METHOD) The first method is to change the ratio of the inductors equivalent series resistance, (ESR). As can be seen in the previous example, if the offset error is zero and the ESR of the two inductors are identical, then the two inductor currents will be identical. To change the ratio of current between the two inductors, the value of the inductor’s ESR can be changed to allow more current to flow through one inductor than the other. The inductor with the lower ESR value will have the larger current. The inductor currents are directly proportional to the ratio of the inductor’s ESR value. Sometimes it is desirable to use the same inductor in both phases while having a much larger current in one phase versus the other. A simple resistor divider can be used on the input side of the Low Pass Filter that is taken off of the switching side of the inductors. If the Phase 2 current is to be larger than the current in Phase 1; the resistor divider is placed in the feedback path before the Low Pass Filter that is connected to the Phase 2 inductor. If the Phase 2 current needs to be less than the current in Phase 1; the resistor divider is then placed in the feedback path before the Low Pass Filter that is connected to the Phase 1 inductor. The following circuit description shows how to select the inductor ESR for each phase where a different amount of power is taken from two different input power supplies. A typical setup will have a +5V power supply connected to the phase 1 half bridge driver and a +3.3V power supply connected to the phase 2 half bridge driver. The combined power output for this core voltage is 18W (+1.5V @ 12A). For this example the +5V power supply will supply 7W and the +3.3V power supply will supply the other 11W. 7W @ 1.5V is a 4.67A current through the phase 1 inductor. 11W @ 1.5V is a 7.33A current through the phase 2 inductor. The ratio of inductor ESR is inversely proportional to the power level split. As in Figure 7, the millivolts of DC offset created by the resistor divider network in the feedback path, appears as a voltage generator between the ESR of the two inductors. ESR1 I2 = ESR 2 I1 The higher current inductor will have the lower ESR value. If the ESR of the phase 1 inductor is selected as 10mΩ, then the ESR value of the phase 2 inductor is calculated as: ⎛ 4.67 A ⎞ ⎜ ⎟ × 10 mΩ = 6.4 mΩ ⎝ 7.33A ⎠ Depending on the required accuracy of this power sharing; inductors can be chosen from standard vendor tables with an ESR ratio close to the required values. Inductors can also be designed for a given application so that there is the least amount of compromise in the inductor’s performance. +5V @ 7W 4.67A L1 A divider in the feedback path from Phase 2 will cause the voltage generator to be positive at Phase 2. With a divider in the feedback path of Phase 1 the voltage generator becomes positive at Phase 1. The Phase with the positive side of the voltage generator will have the larger current. Systems that operate continuously above a 30% power level can use this method. A down side is that the current difference between the two inductors still flows during a no load condition. This produces a low efficiency condition during a no load or light load state, this method should not be used if a wide range of output power is required. The following description and Figure 8 show how to determine the value of the resistor divider network required to generate the offset voltage necessary to produce the different current ratio in the two output inductors. The power sharing ratio is the same as that of Figure 7. The Offset Voltage Generator is symbolic for the DC voltage offset between Phase 1 & 2. This voltage is generated by small changes in the duty cycle of Phase 2. The output of the LPF is a DC voltage proportional to the duty cycle on its input. A small amount of attenuation by a resistor divider before the LPF of Phase 2 will cause the duty cycle of Phase 2 to increase to produce the added offset at V2. The high DC gain of the error amplifier will force LPF2 to always be equal to LPF1. The following calculations determine the value of the resistor divider necessary to satisfy this example. 10mΩ 6.4mΩ +3.3V @ 11W L2 APPLICATIONS 1.5V + 46.7mV 1.5V @ 12A 18W 7.33A Figure 7 –LoadSHARE Using Inductor ESR Copyright © 2004 Rev. 1.2a, 2006-02-16 WWW . Microsemi .C OM BI-PHASE, LOADSHARE (ESR METHOD) Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 10 LX1675 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET THEORY OF OPERATION (CONTINUED) L1, Switch Side 100 62k Not Used RF2 1.5V +46.7mV Resistor Divider 4700pF - 62k LPF2 - Offset Voltage Generator Vou 1.5V @ 12A 18W + 62k ESR L2 10mΩ V2 100 TBD 4.67A PWM Input FB2 L2, Switch Side ESR L1 10mΩ V1 Phase 1 + Resistor Divider LPF1 Phase 2 Error Amp WWW . Microsemi .C OM +5V @ 7W 1.5V +73.3mV 4700pF Phase 2 7.33A +3.3V @ 11W Figure 8 – LoadSHARE Using Feedback Divider Offset Where V1 = 1.5467 ; V2 = 1.5733 and K = V1 then TBD = V2 K × 100 1− K = 5.814 K APPLICATIONS Copyright © 2004 Rev. 1.2a, 2006-02-16 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 11 LX1675 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET THEORY OF OPERATION (CONTINUED) The best topology for generating a current ratio at full load and proportional between full load and no load is shown in figure 9. The DC voltage difference between LPF1 and VOUT is a voltage that is proportional to the current flowing in the Phase 1 inductor. This voltage can be amplified and used to offset the voltage at LPF2 through a large impedance that will not significantly alter the characteristics of the low pass filter. At no load there will be no offset voltage and no offset current between the two phases. This will give the highest efficiency at no load. The use of a MOSFET input amplifier is required for the buffer to prevent loading the low pass filter. The gain of the offset amplifier, and the value of Ra and Rb, will determine the ratio of currents between the phases at full load. Two external amplifiers are required or this method. WWW . Microsemi .C OM Also a speed up capacitor can be used between the offset amplifier output and the negative input of the Phase 2 error amplifier. This will improve the transient response of the Phase 2 output current, so that it will share more equally with phase 1 current during a transient condition. BI-PHASE, LOADSHARE (PROPORTIONAL METHOD) L1, Switch Side Offset Amp LPF1 + 62k + Rin - - Vos Rf 4700pF Phase 2 Error Amp 1.5V +46.7mV ESR L1 10mΩ V1 4.67A Phase 1 + PWM Input RF2 Offset Voltage Generator L2, Switch Side +5V @ 7W Vou 1.5V @ 12A 18W + FB2 62k LPF2 62k Ra 1.5V +73.3mV 4700pF 1M Rb ESR L2 10mΩ V2 Phase 2 7.33A +3.3V @ 11W Figure 9 – LoadSHARE Using Proportional Control APPLICATIONS Copyright © 2004 Rev. 1.2a, 2006-02-16 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 12 LX1675 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET THEORY OF OPERATION (CONTINUED) The first decision to be made is the current sharing ratio. Follow the previous examples to understand the basics of LoadSHARE. The most common reason to imbalance the currents in the two phases is because of limitations on the available power from the input rails for each phase. Use the available input power and total required output power to determine the inductor currents for each phase. All references are to Figure 9 1) Calculate the voltages V1 and V2. V 1 = L 1 Current × L 1 ESR + Vout V 2 = L 2 Current × L 2 ESR + Vout BI-PHASE, LOADSHARE (SERIES RESISTOR METHOD) A fourth but less desirable way to produce the ratio current between the two phases is to add a resistor in series with one of the inductors. This will reduce the current in the inductor that has the resistor and increase the current in the inductor of the opposite phase. The example of Figure 7 can be used to determine the current ratio by adding the value of the series resistor to the ESR value of the inductor. The added resistance will lower the overall efficiency LoadSHARE ERROR SOURCES With the high DC feedback gain of this second loop, all phase timing errors, RDS(On) mismatch, and voltage differences across the half bridge drivers are removed from the current sharing accuracy. The errors in the current sharing accuracy are derived from the tolerance on the inductor’s ESR and the input offset voltage specification of the error amplifier. The equivalent circuit is shown next for an absolute worst case difference of phase currents between the two inductors. 2) Select values for Ra and Rb (Ra is typically 62KΩ ; Rb is typically 1MΩ) 3) Calculate the offset voltage Vos at the output of the offset amplifier ⎛ V 2 − V1⎞ Vos = V 2 − ⎜ ⎟ × (Ra + Rb ) ⎝ Ra ⎠ ESR L1 V1 Offset Error 5mV + VOUT Phase 1 ESR L2 V2 Phase 2 Figure 10 – Error Amplitude 4) Calculate the value for Rf Nominal ESR of 6mΩ. ESR ±5% (select a value for Rin typically 5KΩ) Max offset Error = 6mV ⎛ Vos − Vout ⎞ ⎟ ⎝ Vout − V 1 ⎠ +5% ESR L1 = 6.3 mΩ Rf = Rin ⎜ -5% ESR L2 = 5.7 mΩ Due to the high impedances in this circuit layout can affect the actual current ratio by allowing some of the switching waveforms to couple into the current summing path. It may be necessary to make some adjustment in Rf after the final layout is evaluated. Also the equation for Rf requires very accurate numbers for the voltages to insure an accurate result. If phase 1 current = 12 A = V 1 - VOUT ESRL 1 V 1 − VOUT = 12 × 6.3 × 10 −3 = 75.6 mV V 2 = V1 + 6 mV = 81.6 mV V 2 - VOUT 81.6 x 10−3 = = 14.32 A ESR L 2 5.7 x 10−3 APPLICATIONS Phase 2 current = Phase 2 current is 2.32A greater than Phase 1. Input bias current also contributes to imbalance. Copyright © 2004 Rev. 1.2a, 2006-02-16 WWW . Microsemi .C OM The circuit in Figure 9 sums a current through a 1MΩ resistor (Rb) offsetting the phase 2 error amplifier to create an imbalance in the L1 and L2 currents. Although there are many ways to calculate component values the approach taken here is to pick Ra, Rb, Rin, Vout, and inductor ESR. A value for the remaining resistor Rf can then be calculated. Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 13 LX1675 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET APPLICATION NOTE OUTPUT CAPACITOR The output inductor should be selected to meet the requirements of the output voltage ripple in steady-state operation and the inductor current slew-rate during transient. The peak-topeak output voltage ripple is: D The output capacitor is sized to meet ripple and transient performance specifications. Effective Series Resistance (ESR) is a critical parameter. When a step load current occurs, the output voltage will have a step that equals the product of the ESR and the current step, ΔI. In an advanced microprocessor power supply, the output capacitor is usually selected for ESR instead of capacitance or RMS current capability. A capacitor that satisfies the ESR requirements usually has a larger capacitance and current capability than strictly needed. The allowed ESR can be found by: fs ESR × I RIPPLE + ΔI < VEX VRIPPLE = ESR × I RIPPLE where ΔI = VIN − VOUT × L ( ) ΔI is the inductor ripple current, L is the output inductor value and ESR is the Effective Series Resistance of the output capacitor. Where IRIPPLE is the inductor ripple current, ΔI is the maximum load current step change, and VEX is the allowed output voltage excursion in the transient. ΔI should typically be in the range of 20% to 40% of the maximum output current. Higher inductance results in lower output voltage ripple, allowing slightly higher ESR to satisfy the transient specification. Higher inductance also slows the inductor current slew rate in response to the load-current step change, ΔI, resulting in more output-capacitor voltage droop. When using electrolytic capacitors, the capacitor voltage droop is usually negligible, due to the large capacitance Electrolytic capacitors can be used for the output capacitor, but are less stable with age than tantalum capacitors. As they age, their ESR degrades, reducing the system performance and increasing the risk of failure. It is recommended that multiple parallel capacitors be used, so that, as ESR increase with age, overall performance will still meet the processor’s requirements. The inductor-current rise and fall times are: TRISE = L× (V ΔI IN − VOUT ) and TFALL = L× ΔI VOUT .The inductance value can be calculated by L= VIN − VOUT ΔI × WWW . Microsemi .C OM OUTPUT INDUCTOR There is frequently strong pressure to use the least expensive components possible; however, this could lead to degraded longterm reliability, especially in the case of filter capacitors. Microsemi’s demonstration boards use the CDE Polymer AL-EL (ESRE) filter capacitors, which are aluminum electrolytic, and have demonstrated reliability. The OS-CON series from Sanyo generally provides the very best performance in terms of long term ESR stability and general reliability, but at a substantial cost penalty. The CDE Polymer AL-EL (ESRE) filter series provides excellent ESR performance at a reasonable cost. Beware of offbrand, very low-cost filter capacitors, which have been shown to degrade in both ESR and general electrolytic characteristics over time. D fs APPLICATIONS Copyright © 2004 Rev. 1.2a, 2006-02-16 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 14 LX1675 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET APPLICATION NOTE (CONTINUED) The input capacitor and the input inductor, if used, are to filter the pulsating current generated by the buck converter to reduce interference to other circuits connected to the same 5V rail. In addition, the input capacitor provides local de-coupling for the buck converter. The capacitor should be rated to handle the RMS current requirements. The RMS current is: I RMS = I L Values of CSS equal to 0.1µF or greater are unlikely to result in saturation of the output inductor unless very large output capacitors are used. OVER-CURRENT PROTECTION Current limiting occurs at current level ICL when the voltage detected by the current sense comparator is greater than the current sense comparator threshold, VTRIP (0.0 Volts). d(1 − d) ISET •R SET -I CL •R DS(ON) =VTRIP Where IL is the inductor current and d is the duty cycle. The maximum value occurs when d = 50% then IRMS =0.5IL. For 5V input and output in the range of 2 to 3V, the required RMS current is very close to 0.5IL. So, R SET = SOFT-START CAPACITOR The value of the soft-start capacitor determines how fast the output voltage rises and how large the inductor current is required to charge the output capacitor. The output voltage will follow the voltage at the SS pin if the required inductor current does not exceed the maximum allowable current for the inductor. The SS pin voltage can be expressed as: ( VSS = V ref 1 − e − t/R SSCSS The current required to charge the output capacitor during the soft start interval is. Iout = Cout dVss dt VrefCout − t/R SS C SS e RssCss and at t = 0 Im ax = ISET I CL × R DS(ON) 50 µA R SET = 10 × 0.010 50 × 10 −6 = 2.00KΩ 1% Note: If RSET is 0.0Ω or the CSx pin has become shorted to ground the device will be continuously in the current limit mode. If the CSx pin is left open then the current limit will never be enabled. A resistor should be selected for the maximum desired current limit and this should also provide enough current to charge up the output filter capacitance during the soft-start time. The current limit comparator is followed by a counter that does not allow the hiccup mode until the current limit condition has existed for 4 PWM cycles. If the current limit condition goes away after a count of 2 the counter will be reset. This mode will prevent a single cycle current or noise glitch from starting the hiccup mode current limit. Taking the derivative with respect to time results in Iout = = Example: For 10A current limit, using FDS6670A MOSFET (10mΩ RDS(ON)): ) Where RSS and CSS are the soft-start resistor and capacitor. I CL × R DS(ON) VrefCout RssCss Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 APPLICATIONS The required inductor current for the output capacitor to follow the soft start voltage equals the required capacitor current plus the load current. The soft-start capacitor should be selected to provide the desired power on sequencing and insure that the overall inductor current does not exceed its maximum allowable rating. Copyright © 2004 Rev. 1.2a, 2006-02-16 WWW . Microsemi .C OM INPUT CAPACITOR Page 15 LX1675 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET APPLICATION NOTE (CONTINUED) The LX1675 MOSFET driver outputs are shut off by pulling the soft-start pin below 0.1V. The LDO voltage regulator has its own soft-start pin: SSL, that is the same as any of the other switching phases for control of its output voltage shut down. PROGRAMMING THE OUTPUT VOLTAGE The output voltage is sensed by the feedback pin (FBX) which is compared to a 0.8V reference. The output voltage can be set to any voltage above 0.8V (and lower than the input voltage) by means of a resistor divider R1-R2 (see Figure 1). VOUT = VREF (1 + R 1 /R 2 ) Note: This equation is simplified and does not account for error amplifier input current. Keep R1 and R2 close to 1kΩ (order of magnitude). AN 18 For more information see Microsemi Application Note 1307: LX1671 Product design Guide. The LX1675 and LX1671 have the same functionality and this information will be applicable. DDR VTT TERMINATION VOLTAGE Double Data Rate (DDR) SDRAM requires a termination voltage (VTT) in addition to the line driver supply voltage (VDDQ) and receiver supply voltage (VDD). Although it is not a requirement VDD is generally equal to VDDQ so that only VTT and VDDQ are required. The LX1675 can supply both voltages by using two of the three PWM phases. Since the currents for VTT and (VDD plus VDDQ) are quite often several amps, (2A to 6A is common) a switching regulator is a logical choice VTT for DDR memory can be generated with the LX1675 by using the positive input of the phase 2 error amplifier RF2 as a reference input from an external reference voltage VREF which is defined as one half of VDDQ. Using VREF as the reference input will insure that all voltages are correct and track each other as specified in the JEDEC (EIA/JESD8-9A) specification. The phase 2 output will then be equal to VREF and track the VDDQ supply as required. When an external reference is used the Soft Start will not be functional for that phase WWW . Microsemi .C OM OUTPUT ENABLE See Microsemi Application Note 1306: DDR SDRAM Memory Termination for more details. APPLICATIONS Copyright © 2004 Rev. 1.2a, 2006-02-16 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 16 LX1675 TM Multiple Output LoadSHARE™ PWM ® P RODUCTION D ATA S HEET APPLICATION NOTE CONSIDERATIONS 4. When phases 1 and 2 are used in the Bi-phase mode to current share into the same output load, the phase 2 current is forced to follow the phase 1 current. It is important to use a larger softstart capacitor on phase 2 than phase 1 so that the phase 1 current becomes active before phase 2 becomes active. This will minimize any start up transient. It is also important to disable phase 1 and 2 at the same time. Disabling phase 1 without disabling phase 2, in the Bi-phase mode, allows phase 2 turn on and off randomly because it has lost its reference. 5. The maximum output voltage when using LoadSHARE is limited by the input common mode voltage of the error amplifier and cannot exceed the input common mode voltage. WWW . Microsemi .C OM 1. The power N-MOSFET transistor’s total gate charge spec, (Qg) should not exceed 50nC. This condition will guarantee operation over the specified ambient temperature range with 600kHz operating frequency. The Qg value of the NMOSFET is directly related to the amount of power dissipation inside the IC package, from the three sets of MOSFET drivers. The equation relating Qg to the power dissipation of a MOSFET driver is: Pd = f * Qg * Vd . f = 300KHs and Vd is the supply voltage for the MOSFET driver. The three bottom MOSFET drivers are powered by the VCCL pin that is connected to +5V. The upper MOSFET drivers are connected to a bootstrap supply generated by its output bridge. The bootstrap supply will ride on top of the VIN rail. Depending on the thermal environment of the application circuit, the Qg value of the N-MOSFETs will have to be less than the 50nC value. A typical configuration of the input voltage rails to generate the output voltages required by having the VIN supply on all phases. At the max Qg value, the three bottom MOSFET drivers will dissipate 75mw each. The upper MOSFET drivers for all three phases will also operate off of +5volts. Their dissipation is 75mw each. The total power dissipation for all gate drives is 450mw. Icc x Vcc =15ma x 5 V= 75mW. Total package power dissipation = 525mW. Using the thermal equation of: Tj = Ta + Pd * Oja, the Junction temperature for this IC package is = 23 + .525 * 85 which = 68°C. This means that the ambient temperature rise has to be less than 82°C. At 600kHz the switching losses double so the ambient temperature rise has to be less than 44°C. 6. A resistor has been put in series with the gate of the LDO pass transistor to reduce the output noise level. The resistor value can be changed to optimize the output transient response versus output noise. 7. The LDO controller inside the IC uses the voltage at VSLR pin as the drive voltage. This pin should be connected to the VIN voltage to insure reliable operation of the LDO controller. An additional decoupling capacitor can be connected to this pin to eliminate any high frequency noise. 8. The LDO controller has its own soft-start pin so that its turn on delay can be set so that the voltage rail connected to its pass transistor has had time to come up first. This will allow a smooth ramp up of the LDO voltage rail. The voltage rail for the LDO pass transistor can come from any of the other PWM phases if desirable. 2. The Soft-Start reference input has a 100mv threshold, above which the PWM starts to operate. The internal operating reference level is set at 800mv. This means that the output voltage is 12.5% low when the PWM becomes active. This starts each phase up in the current limit mode without Hiccup operation. If more than one phase is using the 5V rail for conversion, then their soft-start capacitor values should be changed so that the two phases do not start up together. This will help reduce the amount of 5V input capacitance required. Also the VCCL pin should have sufficient decoupling capacitance to keep from drooping back below the UVLO set point during start up. Copyright © 2004 Rev. 1.2a, 2006-02-16 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 APPLICATIONS 3. It should be noted here that if the VIN power supply voltage falls between 4.5V to 6.0V the VIN pin and the VCCL pin should be connected together. If the VIN power supply voltage is greater than 6V then the two pins are kept separate and VCCL becomes a 5V output supply for the bootstrap capacitors. The UVLO is looking for the voltage at the VCCL pin to be above 4.4V to start up. Page 17 LX1675 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET PACKAGE DIMENSIONS WWW . Microsemi .C OM LQ 38-Pin Plastic MLPQ (5x7mm EP) D L Dim A A1 A3 b D D2 E E2 e L D2 E E2 3 2 1 e MILLIMETERS MIN MAX 0.80 1.00 0 0.05 0.20 REF 0.18 0.30 5.00 BSC 3.00 3.25 7.00 BSC 5.00 5.25 0.50 BSC 0.30 0.50 INCHES MIN MAX 0.031 0.039 0 0.002 0.008 REF 0.007 0.011 0.196 BSC 0.118 0.127 0.275 BSC 0.196 0.206 0.019 BSC 0.012 0.020 A b A1 Note: A3 Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(0.006”) on any side. Lead dimension shall not include solder coverage. Recommended Solder Pad Layout 7.50mm 6.10mm 5.20mm 0.25mm 0.50mm 5.50mm MECHANICALS 4.10mm 3.15mm Copyright © 2004 Rev. 1.2a, 2006-02-16 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 18 LX1675 TM Multiple Output LoadSHARE™ PWM ® P RODUCTION D ATA S HEET NOTES WWW . Microsemi .C OM NOTES PRODUCTION DATA – Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. Copyright © 2004 Rev. 1.2a, 2006-02-16 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 19