IDT IDT72291L20PFI Cmos supersync fifo Datasheet

CMOS SuperSync FIFO™
65,536 x 9
131,072 x 9
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FEATURES:
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Choose among the following memory organizations:
IDT72281
65,536 x 9
IDT72291
131,072 x 9
Pin-compatible with the IDT72261LA/72271LA SuperSync FIFOs
10ns read/write cycle time (6.5ns access time)
Fixed, low first word data latency time
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable
settings
Retransmit operation with fixed, low first word data
latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and writing
simultaneously)
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IDT72281
IDT72291
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64pin Slim Thin Quad Flat Pack (STQFP)
High-performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
DESCRIPTION:
The IDT72281/72291 are exceptionally deep, high speed, CMOS First-InFirst-Out (FIFO) memories with clocked read and write controls. These FIFOs
offer numerous improvements over previous SuperSync FIFOs, including the
following:
• The limitation of the frequency of one clock input with respect to the other has
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync family.)
SuperSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer
large amounts of data.
FUNCTIONAL BLOCK DIAGRAM
WEN
D0 -D8
WCLK
LD SEN
INPUT REGISTER
OFFSET REGISTER
FLAG
LOGIC
WRITE CONTROL
LOGIC
RAM ARRAY
65,536 x 9
131,072 x 9
WRITE POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
READ POINTER
READ
CONTROL
LOGIC
RT
OUTPUT REGISTER
MRS
PRS
RESET
LOGIC
RCLK
REN
OE
Q0 -Q8
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SEPTEMBER 2002
1
 2002
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4675/2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly to
the data output lines after three transitions of the RCLK signal. A REN does not
have to be asserted for accessing the first word. However, subsequent words
written to the FIFO do require a LOW on REN for access. The state of the FWFT/
SI input during Master Reset determines the timing mode in use.
For applications requiring more data storage capacity than a single FIFO can
provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/
IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable AlmostEmpty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions
are selected in IDT Standard mode. The IR and OR functions are selected in
DESCRIPTION (CONTINUED)
The input port is controlled by a Write Clock (WCLK) input and a Write Enable
(WEN) input. Data is written into the FIFO on every rising edge of WCLK when
WEN is asserted. The output port is controlled by a Read Clock (RCLK) input
and Read Enable (REN) input. Data is read from the FIFO on every rising edge
of RCLK when REN is asserted. An Output Enable (OE) input is provided for
three-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to fMAX with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
EF/OR
RCLK
REN
RT
OE
VCC
PAE
FF/IR
PAF
HF
MRS
LD
FWFT/SI
GND
WCLK
PRS
PIN CONFIGURATIONS
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
WEN
SEN
DC(1)
VCC
VCC
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
D8
D7
48
47
46
45
44
43
42
41
40
39
38
1
2
3
4
5
6
7
8
9
10
11
12
13
37
36
35
34
33
14
15
16
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
VCC
DNC(3)
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
Q8
Q7
Q6
GND
TQFP (PN64-1, ORDER CODE: PF)
STQFP (PP64-1, ORDER CODE: TF)
TOP VIEW
NOTES:
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.
2. This pin may either be tied to GND or left open.
3. DNC = Do Not Connect.
2
Q4
Q5
Q3
VCC
GND
Q0
Q1
GND
Q2
D1
D0
D5
D4
D3
D2
D6
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
Standard mode or FWFT mode. The LD pin selects either a partial flag default
setting of 127 with parallel programming or a partial flag default setting of 1,023
with serial programming. The flags are updated according to the timing mode
and default offsets selected.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag programming
method, and default or programmed offset settings existing before Partial Reset
remain unchanged. The flags are updated according to the timing mode and
offsets in effect. PRS is useful for resetting a device in mid-operation, when
reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO more than
once. A LOW on the RT input during a rising RCLK edge initiates a retransmit
operation by setting the read pointer to the first location of the memory array.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT72281/72291 are fabricated using IDT’s high speed submicron
CMOS technology.
DESCRIPTION (CONTINUED)
FWFT mode. HF, PAE and PAF are always available for use, irrespective of
timing mode.
PAE and PAF can be programmed independently to switch at any point in
memory. (See Table I and Table II.) Programmable offsets determine the flag
switching threshold and can be loaded by two methods: parallel or serial. Two
default offset settings are also provided, so that PAE can be set to switch at 127
or 1,023 locations from the empty boundary and the PAF threshold can be set
at 127 or 1,023 locations from the full boundary. These choices are made with
the LD pin during Master Reset.
For serial programming, SEN together with LD on each rising edge of WCLK,
are used to load the offset registers via the Serial Input (SI). For parallel
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via Dn. REN together with LD on each rising edge
of RCLK can be used to read the offsets in parallel from Qn regardless of whether
serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: The read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
PARTIAL RESET (PRS)
MASTER RESET (MRS)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
WRITE ENABLE (WEN)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
LOAD (LD)
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
IDT
72281
72291
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
FULL FLAG/INPUT READY (FF/IR)
HALF-FULL FLAG (HF)
PROGRAMMABLE ALMOST-FULL (PAF)
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Figure 1. Block Diagram of Single 65,536 x 9 and 131,072 x 9 Synchronous FIFO
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
PIN DESCRIPTION
Symbol
D0–D8
Name
Data Inputs
I/O
I
Description
MRS
Master Reset
I
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of two programmable flag default settings, and serial or parallel programming of the offset settings.
PRS
Partial Reset
I
RT
Retransmit
I
FWFT/SI
I
WCLK
First Word Fall
Through/Serial In
Write Clock
I
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and
programmable flag settings are all retained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to
LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, program
ming method, existing timing mode or programmable flag settings. RT is useful to reread data from
the first physical location of the FIFO.
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset,
this pin functions as a serial input for loading offset registers
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the
programmable registers for parallel programming, and when enabled by SEN, the rising edge of
WCLK writes one bit of data into the programmable register for serial programming.
WEN enables WCLK for writing data into the FIFO memory and offset registers.
Data inputs for a 9-bit bus.
WEN
Write Enable
I
RCLK
Read Clock
I
REN
Read Enable
I
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from
the programmable registers.
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE
SEN
Output Enable
Serial Enable
I
I
OE controls the output impedance of Qn.
SEN enables serial loading of programmable flag offsets.
LD
Load
I
During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023 and determines
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to
and reading from the offset registers.
DC
FF/IR
Don't Care
Full Flag/
Input Ready
I
O
This pin must be tied to either VCC or GND and must not toggle after Master Reset.
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO
memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is
space available for writing to the FIFO memory.
EF/OR
Empty Flag/
Output Ready
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO
memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there
is valid data available at the outputs.
PAF
Programmable
Almost-Full Flag
O
PAF goes LOW if the number of words in the FIFO memory is more than total word capacity of the
FIFO minus the full offset value m, which is stored in the Full Offset register. There are two possible
default values for m: 127 or 1,023.
PAE
Programmable
Almost-Empty Flag
O
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in
the Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values
for n can be programmed into the device.
HF indicates whether the FIFO memory is more or less than half-full.
HF
Half-Full Flag
O
Q0–Q8
V CC
Data Outputs
Power
O
GND
Ground
Data outputs for a 9-bus
+5 Volt power supply pins.
Ground pins.
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM
Rating
Terminal Voltage
with respect to GND
Commercial
–0.5 to +7
Unit
V
TSTG
Storage
Temperature
–55 to +125
°C
IOUT
DC Output Current
–50 to +50
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Supply Voltage(Com’l & Ind’l)
VCC
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Min.
4.5
Typ.
5.0
Max.
5.5
GND
Supply Voltage(Com’l & Ind’l)
0
0
0
V
VIH
Input High Voltage
(Com’l & Ind’l)
2.0
—
—
V
Input Low Voltage
(Com’’ & Ind’l)
—
—
0.8
V
VIL(1)
TA
Operating Temperature
Commercial
0
—
70
°C
TA
Operating Temperature
Industrial
-40

85
°C
NOTE
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = -40° to +85°C)
IDT72281
IDT72291
Commercial & Industrial(1)
tCLK = 10, 15, 20 ns
Symbol
Parameter
Min.
Max.
Unit
ILI(2)
ILO(3)
Input Leakage Current
Output Leakage Current
–1
–10
1
10
µA
µA
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
2.4
—
—
0.4
V
V
ICC1(4,5,6)
Active Power Supply Current
—
80
mA
Standby Current
—
20
mA
(4,7)
ICC2
NOTES:
1. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 20 + 1.8*fS + 0.02*CL*fS (in mA) with VCC = 5V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching
at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC – 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
Capacitance
VIN = 0V
10
pF
COUT(1,2)
Output
Capacitance
VOUT = 0V
10
pF
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
5
Unit
V
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)
Commercial & Industrial(2)
Commercial
IDT72281L10
IDT72291L10
Min.
Max.
—
100
IDT72281L15
IDT72291L15
Min.
Max.
—
66.7
IDT72281L20
IDT72291L20
Min.
Max.
—
50
Symbol
fS
Parameter
Clock Cycle Frequency
tA
Data Access Time
2
6.5
2
10
2
12
ns
tCLK
Clock Cycle Time
10
—
15
—
20
—
ns
tCLKH
Clock High Time
4.5
—
6
—
8
—
ns
tCLKL
Clock Low Time
4.5
—
6
—
8
—
ns
tDS
Data Setup Time
3
—
4
—
5
—
ns
tDH
Data Hold Time
0
—
1
—
1
—
ns
tENS
Enable Setup Time
3
—
4
—
5
—
ns
tENH
Enable Hold Time
0
—
1
—
1
—
ns
tLDS
Load Setup Time
3
—
4
—
5
—
ns
tLDH
Load Hold Time
0
—
1
—
1
—
ns
10
—
15
—
20
—
ns
(3)
Unit
MHz
tRS
Reset Pulse Width
tRSS
Reset Setup Time
10
—
15
—
20
—
ns
tRSR
Reset Recovery Time
10
—
15
—
20
—
ns
tRSF
Reset to Flag and Output Time
—
10
—
15
—
20
ns
tFWFT
Mode Select Time
0
—
0
—
0
—
ns
tRTS
Retransmit Setup Time
3
—
4
—
5
—
ns
(4)
tOLZ
Output Enable to Output in Low Z
0
—
0
—
0
—
ns
tOE
Output Enable to Output Valid
2
6
3
8
3
10
ns
tOHZ
Output Enable to Output in High Z(4)
2
6
3
8
3
10
ns
tWFF
Write Clock to FF or IR
—
6.5
—
10
—
12
ns
tREF
Read Clock to EF or OR
—
6.5
—
10
—
12
ns
tPAF
Write Clock to PAF
—
6.5
—
10
—
12
ns
tPAE
Read Clock to PAE
—
6.5
—
10
—
12
ns
tHF
Clock to HF
—
16
—
20
—
22
ns
tSKEW1
Skew time between RCLK and WCLK for FF/IR
5
—
6
—
10
—
ns
tSKEW2
Skew time between RCLK and WCLK for PAE and PAF
12
—
15
—
20
—
ns
tSKEW3
Skew time between RCLK and WCLK for EF/OR
60
—
60
—
60
—
ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5V
1.1K
D.U.T.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
680Ω
GND to 3.0V
3ns
1.5V
1.5V
See Figure 2
30pF*
4675 drw 04
* Includes jig and scope capacitances.
Figure 2. Output Load
6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
When configured in IDT Standard mode, the EF and FF outputs are
double register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
7, 8 and 11.
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD VS FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72281/72291 support two different timing modes of operation:
IDT Standard mode or First Word Fall Through (FWFT) mode. The selection of which mode will operate is determined during Master Reset, by the
state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag
function (FF) to indicate whether or not the FIFO has any free space for
writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to
indicate whether or not the FIFO has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes directly to Qn
after three RCLK rising edges, REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently depending on which timing mode is in effect.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 2. To write data into to the FIFO, WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of WCLK. After the first write is performed, the Output
Ready (OR) flag will go LOW. Subsequent writes will continue to fill up the
FIFO. PAE will go HIGH after n + 2 words have been loaded into the FIFO,
where n is the empty offset value. The default setting for this value is stated
in the footnote of Table 2. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the 32,770th
word for the IDT72281 and 65,538th word for the IDT72291, respectively
was written into the FIFO. Continuing to write data into the FIFO will cause
the PAF to go LOW. Again, if no reads are performed, the PAF will go LOW
after (65,537-m) writes for the IDT72281 and (131,073-m) writes for the
IDT72291, where m is the full offset value. The default setting for this value
is stated in the footnote of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
further write operations. If no reads are performed after a reset, IR will go
HIGH after D writes to the FIFO. D = 65,537 writes for the IDT72281 and
131,073 writes for the IDT72291, respectively. Note that the additional word
in FWFT mode is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO, where n is the empty offset value. Continuing read operations will
cause the FIFO to become empty. When the last word has been read from
the FIFO, OR will go HIGH inhibiting further read operations. REN is ignored when the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple registerbuffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10
and 12.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 1. To write data into to the FIFO, Write Enable
(WEN) must be LOW. Data presented to the DATA IN lines will be clocked
into the FIFO on subsequent transitions of the Write Clock (WCLK). After the
first write is performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable Almost-Empty flag
(PAE) will go HIGH after n + 1 words have been loaded into the FIFO,
where n is the empty offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW
once the 32,769th word for IDT72281 and 65,537th word for IDT72291
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW.
Again, if no reads are performed, the PAF will go LOW after (65,536-m)
writes for the IDT72281 and (131,072-m) writes for the IDT72291. The
offset “m” is the full offset value. The default setting for this value is stated in
the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D
writes to the FIFO. D = 65,536 writes for the IDT72281 and 131,072 for the
IDT72291, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the
conditions described in Table 1. If further read operations occur, without
write operations, PAE will go LOW when there are n words in the FIFO,
where n is the empty offset value. Continuing read operations will cause the
FIFO to become empty. When the last word has been read from the FIFO,
the EF will go LOW inhibiting further read operations. REN is ignored when
the FIFO is empty.
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT72281/
72291 has internal registers for these offsets. Default settings are stated in
the footnotes of Table 1 and Table 2. Offset values can be programmed into
the FIFO in one of two ways; serial or parallel loading method. The selection of the loading method is done using the LD (Load) pin. During Master
Reset, the state of the LD input determines whether serial or parallel flag
offset programming is enabled. A HIGH on LD during Master Reset selects
serial loading of offset values and in addition, sets a default PAE offset value
of 3FFH (a threshold 1,023 words from the empty boundary), and a default
PAF offset value of 3FFH (a threshold 1,023 words from the full boundary).
A LOW on LD during Master Reset selects parallel loading of offset values,
and in addition, sets a default PAE offset value of 07FH (a threshold 127
words from the empty boundary), and a default PAF offset value of 07FH (a
threshold 127 words from the full boundary). See Figure 3, Offset Register
Location and Default Values.
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
Number of
Words in
FIFO
IDT72281
IDT72291
FF
PAF
HF
PAE
EF
0
0
H
H
H
L
L
1 to n(1)
1 to n(1)
H
H
H
L
H
(n + 1) to 32,768
(n + 1) to 65,536
H
H
H
H
H
32,769 to (65,536–(m+1))
65,537 to (131,072–(m+1))
H
H
L
H
H
(2)
(2)
(65,536–m) to 65,535
(131,072–m) to 131,071
H
L
L
H
H
65,536
131,072
L
L
L
H
H
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE 2 — STATUS FLAGS FOR FWFT MODE
Number of
Words in
FIFO
IDT72281
IDT72291
FF
PAF
HF
PAE
EF
0
0
L
H
H
L
H
L
H
H
L
L
1 to n+ 1
(1)
1 to n+ 1
(1)
(n + 2) to 32,769
(n + 2) to 65,537
L
H
H
H
L
32,770 to (65,537–(m+1))(2)
65,538 to (131,073–(m+1))(2)
L
H
L
H
L
(65,537–m)(2) to 65,536
(131,073–m)(2) to 6131,072
L
L
L
H
L
65,537
131,073
H
L
L
H
L
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
IDT72281 (65,536 x 9  BIT)
8
7
IDT72291 (131,072 x 9  BIT)
0
8
7
0
EMPTY OFFSET (LSB) REGISTER
EMPTY OFFSET (LSB) REGISTER
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
8
7
0
8
7
0
EMPTY OFFSET (MID-BYTE) REGISTER
EMPTY OFFSET (MSB) REGISTER
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
8
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
0
7
8
1
0
EMPTY OFFSET
(MSB) REGISTER
FULL OFFSET (LSB) REGISTER
DEFAULT
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
0H
8
8
7
7
0
FULL OFFSET (LSB) REGISTER
0
FULL OFFSET (MSB) REGISTER
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
8
7
0
FULL OFFSET (MID-BYTE) REGISTER
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
8
1
0
FULL OFFSET
(MSB) REGISTER
DEFAULT
0H
4675 drw06
Figure 3. Offset Register Location and Default Values
LD
WEN REN SEN
WCLK
RCLK
X
0
0
1
1
0
1
0
1
0
1
1
0
X
1
1
1
1
0
X
X
1
X
0
X
X
1
1
1
X
X
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
X
X
IDT72281
IDT72291
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
X
Serial shift into registers:
32 bits for the IDT72281
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial shift into registers:
34 bits for the IDT72291
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
No Operation
No Operation
X
Write Memory
Write Memory
Read Memory
Read Memory
No Operation
No Operation
X
4675 drw07
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 4. Programmable Flag Offset Programming Sequence
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
ter. See Figure 15, Parallel Loading of Programmable Flag Registers for
the IDT72291, for the timing diagram for this mode.
The act of writing offsets in parallel employs a dedicated write offset
register pointer. The act of reading offsets employs a dedicated read offset
register pointer. The two pointers operate independently; however, a read
and a write should not be performed simultaneously to the offset registers. A
Master Reset initializes both pointers to the Empty Offset (LSB) register. A
Partial Reset has no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers
does not have to occur at one time. One, two or more offset registers can be
written and then by bringing LD HIGH, write operations can be redirected
to the FIFO memory. When LD is set LOW again, and WEN is LOW, the
next offset register in sequence is written to. As an alternative to holding
WEN LOW and toggling LD, parallel programming can also be interrupted
by setting LD LOW and toggling WEN.
Note that the status of a partial flag (PAE or PAF) output is invalid during
the programming process. From the time parallel programming has begun,
a partial flag output will not be valid until the appropriate offset word has
been written to the register(s) pertaining to that flag. Measuring from the
rising WCLK edge that achieves the above criteria; PAF will be valid after
two more rising WCLK edges plus tPAF, PAE will be valid after the next two
rising RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0Qn pins when LD is set LOW and REN is set LOW. For the IDT72281, data
are read via Qn from the Empty Offset LSB Register on the first LOW-toHIGH transition of RCLK. Upon the second LOW-to-HIGH transition of RCLK,
data are read from the Empty Offset MSB Register. Upon the third LOW-toHIGH transition of RCLK, data are read from the Full Offset LSB Register.
Upon the fourth LOW-to-HIGH transition of RCLK, data are read from the
Full Offset MSB Register. The fifth transition of RCLK reads, once again,
from the Empty Offset LSB Register. See Figure 16, Parallel Read of Programmable Flag Registers for the IDT72281, for the timing diagram for this
mode.
For the IDT72291, data is read via Qn from the Empty Offset LSB Register on the first LOW-to-HIGH transition of RCLK. Upon the second LOW-toHIGH transition of RCLK, data are read from the Empty Offset Mid-Byte
Register. Upon the third LOW-to-HIGH transition of RCLK, data are read
from the Empty Offset MSB Register. Upon the fourth LOW-to-HIGH transition of RCLK, data are read from the Full Offset LSB Register. Upon the fifth
LOW-to-HIGH transition of RCLK, data are read from the Full Offset MidByte Register. Upon the sixth LOW-to-HIGH transition of RCLK, data are
read from the Full Offset MSB Register. The seventh transition of RCLK
reads, once again, from the Empty Offset LSB Register. See Figure 17,
Parallel Read of Programmable Flag Registers for the IDT72291, for the
timing diagram for this mode.
It is permissible to interrupt the offset register read sequence with reads
or writes to the FIFO. The interruption is accomplished by deasserting
REN, LD, or both together. When REN and LD are restored to a LOW
level, reading of the offset registers continues where it left off. It should be
noted, and care should be taken from the fact that when a parallel read of
the flag offsets is performed, the data word that was present on the output
lines Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above,
then programming of PAE and PAF values can be achieved by using a
combination of the LD, SEN, WCLK and SI input pins. Programming PAE
and PAF proceeds as follows: when LD and SEN are set LOW, data on the
SI input are written, one bit for each WCLK rising edge, starting with the
Empty Offset LSB and ending with the Full Offset MSB. A total of 32 bits for
the IDT72281 and 34 bits for the IDT72291. See Figure 13, Serial Loading
of Programmable Flag Registers, for the timing diagram for this mode.
Using the serial method, individual registers cannot be programmed selectively. PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered.
When LD is LOW and SEN is HIGH, no serial write to the registers can
occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits does
not have to occur at once. A select number of bits can be written to the SI
input and then, by bringing LD and SEN HIGH, data can be written to FIFO
memory via Dn by toggling WEN. When WEN is brought HIGH with LD and
SEN restored to a LOW, the next offset bit in sequence is written to the
registers via SI. If an interruption of serial programming is desired, it is
sufficient either to set LD LOW and deactivate SEN or to set SEN LOW and
deactivate LD. Once LD and SEN are both restored to a LOW level, serial
offset programming continues.
From the time serial programming has begun, neither partial flag will be
valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above
criteria; PAF will be valid after two more rising WCLK edges plus tPAF, PAE
will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2.
It is not possible to read the flag offset values in a serial mode.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above,
then programming of PAE and PAF values can be achieved by using a
combination of the LD, WCLK , WEN and Dn input pins. For the IDT72281,
programming PAE and PAF proceeds as follows: when LD and WEN are
set LOW, data on the inputs Dn are written into the Empty Offset LSB
Register on the first LOW-to-HIGH transition of WCLK. Upon the second
LOW-to-HIGH transition of WCLK, data are written into the Empty Offset
MSB Register. Upon the third LOW-to-HIGH transition of WCLK, data are
written into the Full Offset LSB Register. Upon the fourth LOW-to-HIGH
transition of WCLK, data are written into the Full Offset MSB Register. The
fifth transition of WCLK writes, once again, to the Empty Offset LSB Register.
See Figure 14, Parallel Loading of Programmable Flag Registers for the
IDT72281, for the timing diagram for this mode.
For the IDT72291, programming PAE and PAF proceeds as follows:
when LD and WEN are set LOW, data on the inputs Dn are written into the
Empty Offset LSB Register on the first LOW-to-HIGH transition of WCLK.
Upon the second LOW-to-HIGH transition of WCLK, data are written into the
Empty Offset Mid-Byte Register. Upon the third LOW-to-HIGH transition of
WCLK, data are written into the Empty Offset MSB Register. Upon the fourth
LOW-to-HIGH transition of WCLK, data are written into the Full Offset LSB
Register. Upon the fifth LOW-to-HIGH transition of WCLK, data are written
into the Full Offset Mid-Byte Register. Upon the sixth LOW-to-HIGH transition of WCLK, data are written into the Full Offset MSB Register. The seventh transition of WCLK writes, once again, into the Empty Offset LSB Regis10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
Retransmit setup requires a LOW on REN to enable the rising edge of
RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for the
relevant timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time,
the contents of the first location appear on the outputs. Since FWFT mode
is selected, the first word appears on the outputs, no LOW on REN is
necessary. Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
For either IDT Standard mode or FWFT mode, updating of the PAE,
HF and PAF flags begin with the rising edge of RCLK that RT is setup.
PAE is synchronized to RCLK, thus on the second rising edge of RCLK
after RT is setup, the PAE flag will be updated. HF is asynchronous, thus
the rising edge of RCLK that RT is setup will update HF. PAF is synchronized to WCLK, thus the second rising edge of WCLK that occurs tSKEW
after the rising edge of RCLK that RT is setup will update PAF. RT is
synchronized to RCLK.
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets
the read pointer to the first location of memory, then the actual retransmit,
which consists of reading out the memory contents, starting at the beginning of memory.
Retransmit setup is initiated by holding RT LOW during a rising RCLK
edge. REN and WEN must be HIGH before bringing RT LOW. At least
one word, but no more than D– 2 words should have been written into
the FIFO between Reset (Master or Partial) and the time of Retransmit
setup. D = 65,536 for the IDT72281 and D = 131,072 for the IDT72291
in IDT Standard mode. In FWFT mode, D = 65,537 for the IDT72281
and D = 131,073 for the IDT72291.
If IDT Standard mode is selected, the FIFO will mark the beginning of
the Retransmit setup by setting EF LOW. The change in level will only be
noticeable if EF was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read operations may begin starting with the first location in memory. Since IDT Standard mode is selected, every word read including the first word following
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
the read pointer to the first location of memory, then the actual retransmit,
which consists of reading out the memory contents, starting at the beginning
of the memory.
Retransmit setup is initiated by holding RT LOW during a rising RCLK
edge. REN and WEN must be HIGH before bringing RT LOW.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting EF LOW. The change in level will only be
noticeable if EF was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard
mode is selected, every word read including the first word following Retransmit setup requires a LOW on REN to enable the rising edge of RCLK.
See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant
timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time, the
contents of the first location appear on the outputs. Since FWFT mode is
selected, the first word appears on the outputs, no LOW on REN is necessary. Reading all subsequent words requires a LOW on REN to enable the
rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for
the relevant timing diagram.
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D0 - D8)
Data inputs for 9-bit wide data.
CONTROLS:
MASTER RESET (MRS)
A Master Reset is accomplished whenever the MRS input is taken to a
LOW state. This operation sets the internal read and write pointers to the first
location of the RAM array. PAE will go LOW, PAF will go HIGH, and HF
will go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
If LD is LOW during Master Reset, then PAE is assigned a threshold 127
words from the empty boundary and PAF is assigned a threshold 127
words from the full boundary; 127 words corresponds to an offset value of
07FH. Following Master Reset, parallel loading of the offsets is permitted,
but not serial loading.
If LD is HIGH during Master Reset, then PAE is assigned a threshold
1,023 words from the empty boundary and PAF is assigned a threshold
1,023 words from the full boundary; 1,023 words corresponds to an offset
value of 3FFH. Following Master Reset, serial loading of the offsets is
permitted, but not parallel loading.
Parallel reading of the registers is always permitted. (See section describing the LD pin for further details.)
During a Master Reset, the output register is initialized to all zeroes. A
Master Reset is required after power up, before a write operation can take
place. MRS is asynchronous.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/
SI input determines whether the device will operate in IDT Standard mode
or First Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether
or not there are any words present in the FIFO memory. It also uses the
Full Flag function (FF) to indicate whether or not the FIFO memory has any
free space for writing. In IDT Standard mode, every word read from the
FIFO, including the first, must be requested using the Read Enable (REN)
and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to
indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to Qn
after three RCLK rising edges, REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading PAE and
PAF offsets into the programmable registers. The serial input function can
only be used when the serial loading method has been selected during
Master Reset. Serial programming using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.
PARTIAL RESET (PRS)
A Partial Reset is accomplished whenever the PRS input is taken to a
LOW state. As in the case of the Master Reset, the internal read and write
pointers are set to the first location of the RAM array, PAE goes LOW, PAF
goes HIGH, and HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
or First Word Fall Through, that mode will remain selected. If the IDT
Standard mode is active, then FF will go HIGH and EF will go LOW. If the
First Word Fall Through mode is active, then OR will go HIGH, and IR will
go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active
at the time of Partial Reset is also retained. The output register is initialized
to all zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming partial flag offset settings may not be convenient.
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the
FF/IR, PAF and HF flags will not be updated. (Note that WCLK is only
capable of updating HF flag to LOW.) The Write and Read Clocks can
either be independent or coincident.
RETRANSMIT (RT)
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
OUTPUT ENABLE (OE)
When Output Enable is enabled (LOW), the parallel output buffers receive data from the output register. When OE is HIGH, the output data bus
(Qn) goes into a high impedance state.
WRITE ENABLE (WEN)
When the WEN input is LOW, data may be loaded into the FIFO RAM
array on the rising edge of every WCLK cycle if the device is not full. Data
is stored in the RAM array sequentially and independently of any ongoing
read operation.
When WEN is HIGH, no new data is written in the RAM array on each
WCLK cycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read
cycle, FF will go HIGH allowing a write to occur. The FF is updated by two
WCLK cycles + tSKEW after the RCLK cycle.
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle, IR will
go LOW allowing a write to occur. The IR flag is updated by two WCLK
cycles + tSKEW after the valid RCLK cycle.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard
mode.
LOAD (LD)
This is a dual purpose pin. During Master Reset, the state of the LD
input determines one of two default offset values (127 or 1,023) for the PAE
and PAF flags, along with the method by which these offset registers can be
programmed, parallel or serial. After Master Reset, LD enables write operations to and read operations from the offset registers. Only the offset
loading method currently selected can be used to write to the registers.
Offset registers can be read only in parallel. A LOW on LD during Master
Reset selects a default PAE offset value of 07FH (a threshold 127 words
from the empty boundary), a default PAF offset value of 07FH (a threshold
127 words from the full boundary), and parallel loading of other offset
values. A HIGH on LD during Master Reset selects a default PAE offset
value of 3FFH (a threshold 1,023 words from the empty boundary), a
default PAF offset value of 3FFH (a threshold 1,023 words from the full
boundary), and serial loading of other offset values.
After Master Reset, the LD pin is used to activate the programming
process of the flag offset values PAE and PAF. Pulling LD LOW will begin a
serial loading or parallel load or read of these offset values. See Figure 4,
Programmable Flag Offset Programming Sequence.
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can
be read on the outputs, on the rising edge of the RCLK input. It is permissible to stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE and
HF flags will not be updated. (Note that RCLK is only capable of updating the
HF flag to HIGH.) The Write and Read Clocks can be independent or
coincident.
OUTPUTS:
READ ENABLE (REN)
When Read Enable is LOW, data is loaded from the RAM array into the
output register on the rising edge of every RCLK cycle if the device is not
empty.
When the REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using REN. When the last
word has been read from the FIFO, the Empty Flag (EF) will go LOW,
inhibiting further read operations. REN is ignored when the FIFO is empty.
Once a write is performed, EF will go HIGH allowing a read to occur. The EF
flag is updated by two RCLK cycles + tSKEW after the valid WCLK cycle.
In the FWFT mode, the first word written to an empty FIFO automatically
goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK +
tSKEW after the first write. REN does not need to be asserted LOW. In
order to access all other words, a read must be executed using REN. The
RCLK LOW to HIGH transition after the last word has been read from the
FIFO, Output Ready (OR) will go HIGH with a true read (RCLK with REN
= LOW), inhibiting further read operations. REN is ignored when the FIFO
is empty.
FULL FLAG (FF/IR)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF)
function is selected. When the FIFO is full, FF will go LOW, inhibiting further
write operations. When FF is HIGH, the FIFO is not full. If no reads are
performed after a reset (either MRS or PRS), FF will go LOW after D writes
to the FIFO (D = 65,536 for the IDT72281 and 131,072 for the IDT72291).
See Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for
the relevant timing information.
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
when memory space is available for writing in data. When there is no
longer any free space left, IR goes HIGH, inhibiting further write operations.
If no reads are performed after a reset (either MRS or PRS), IR will go
HIGH after D writes to the FIFO (D = 65,537 for the IDT72281 and 131,073
for the IDT72291) See Figure 9, Write Timing (FWFT Mode), for the
relevant timing information.
The IR status not only measures the contents of the FIFO memory, but
also counts the presence of a word in the output register. Thus, in FWFT
mode, the total number of writes necessary to deassert IR is one greater
than needed to assert FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR
are double register-buffered outputs.
SERIAL ENABLE (SEN)
The SEN input is an enable used only for serial programming of the
offset registers. The serial programming method must be selected during
Master Reset. SEN is always used in conjunction with LD. When these
lines are both LOW, data at the SI input can be loaded into the program
register one bit for each LOW-to-HIGH transition of WCLK. (See Figure 4.)
When SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded. SEN functions the same way in both IDT
Standard and FWFT modes.
EMPTY FLAG (EF/OR)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
(EF) function is selected. When the FIFO is empty, EF will go LOW,
inhibiting further read operations. When EF is HIGH, the FIFO is not empty.
See Figure 8, Read Cycle, Empty Flag and First Word Latency Timing
(IDT Standard Mode), for the relevant timing information.
In FWFT mode, the Output Ready (OR) function is selected. OR goes
LOW at the same time that the first word written to an empty FIFO appears
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition
that shifts the last word from the FIFO memory to the outputs. OR goes
HIGH only with a true read (RCLK with REN = LOW). The previous data
stays at the outputs, indicating the last word was read. Further data reads
are inhibited until OR goes LOW again. See Figure 10, Read Timing
(FWFT Mode), for the relevant timing information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode, EF is a double register-buffered output. In FWFT
mode, OR is a triple register-buffered output.
LOW when there are n words or less in the FIFO. The offset “n” is the
empty offset value. The default setting for this value is stated in the footnote
of Table 1.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in the footnote of
Table 2.
See Figure 19, Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Mode), for the relevant timing information.
PAE is synchronous and updated on the rising edge of RCLK.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D – m) words are
written to the FIFO. The PAF will go LOW after (65,536–m) writes for the
IDT72281 and (131,072–m) writes for the IDT72291. The offset “m” is the
full offset value. The default setting for this value is stated in the footnote of
Table 1.
In FWFT mode, the PAF will go LOW after (65,53–m) writes for the
IDT72281 and (131,073–m) writes for the IDT72291, where m is the full
offset value. The default setting for this value is stated in the footnote of
Table 2.
See Figure 18, Programmable Almost-Full Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
PAF is synchronous and updated on the rising edge of WCLK.
HALF-FULL FLAG (HF)
This output indicates a half-full FIFO. The rising WCLK edge that fills the
FIFO beyond half-full sets HF LOW. The flag remains LOW until the difference between the write and read pointers becomes less than or equal to
half of the total depth of the device; the rising RCLK edge that accomplishes
this condition sets HF HIGH.
In IDT Standard mode, if no reads are performed after reset (MRS or
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 65,536
for the IDT72281 and 131,072 for the IDT72291.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 65,537 for the
IDT72281 and 131,073 for the IDT72291.
See Figure 20, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because HF is updated by both RCLK
and WCLK, it is considered asynchronous.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode, PAE will go
DATA OUTPUTS (Q0-Q8)
(Q0 - Q8) are data outputs for 9-bit wide data.
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
tRS
MRS
tRSR
tRSS
REN
tRSS
tRSR
WEN
tRSR
tFWFT
FWFT/SI
tRSS
tRSR
LD
tRSS
RT
tRSS
SEN
If FWFT = HIGH, OR = HIGH
tRSF
EF/OR
If FWFT = LOW, EF = LOW
tRSF
If FWFT = LOW, FF = HIGH
FF/IR
If FWFT = HIGH, IR = LOW
tRSF
PAE
tRSF
PAF, HF
tRSF
OE = HIGH
Q0 - Qn
OE = LOW
Figure 5. Master Reset Timing
15
4675 drw 08
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
PRS
tRS
tRSS
tRSR
tRSS
tRSR
REN
WEN
tRSS
RT
tRSS
SEN
If FWFT = HIGH, OR = HIGH
tRSF
EF/OR
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
tRSF
FF/IR
If FWFT = HIGH, IR = LOW
tRSF
PAE
tRSF
PAF, HF
tRSF
OE = HIGH
Q0 - Qn
OE = LOW
Figure 6. Partial Reset Timing
16
4675 drw 09
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
t CLK
t CLKH
NO WRITE
WCLK
t SKEW1
tCLKL
NO WRITE
2
1
1
(1)
(1)
t DS
D0 - Dn
2
t SKEW1
t DH
t DS
t DH
DX
t WFF
DX+1
t WFF
t WFF
t WFF
WEN
RCLK
t ENS
t ENS
t ENH
t ENH
REN
tA
tA
Q0 - Qn
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
4675 drw 10
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH.
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLKH
RCLK
1
tENS
tCLK
tCLKL
2
tENH
tENS
REN
NO OPERATION
tENH
tENH
tENS
NO OPERATION
tREF
tREF
tREF
EF
tA
tA
Q0 - Qn
LAST WORD
tOLZ
OE
LAST WORD
tA
D0
D1
t OLZ
tOHZ
tOE
(1)
tSKEW3
WCLK
tENS
tENH
tENS
tDHS
tDS
tENH
WEN
tDS
D0 - Dn
D0
tDH
D1
4675 drw 11
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW3, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
17
18
tDS
W1
W2
2
DATA IN OUTPUT REGISTER
1
tSKEW3(1)
tDH
W3
3
tREF
tA
W4
tDS
W1
W[n +2]
W[n+3]
1
tPAE
tSKEW2 (2)
2
W[n+4]
W[ D-1
]
tDS
W[ D-1
]
tHF
W[ D-1
]
W[D-m-2]
tDS
W[D-m-1]
W[D-m]
1
tPAF
W[D-m+1]
W[D-m+2]
W[D-1]
WD
4675 drw 12
tWFF
tENH
Figure 9. Write Timing (First Word Fall Through Mode)
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of
RCLK is less than tSKEW3, then OR assertion may be delayed one extra RCLK cycle.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAE. If the time between the rising edge of WCLK and the rising edge of
RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE = LOW.
4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.
5. D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
IR
PAF
HF
PAE
OR
Q0 - Q8
REN
RCLK
D0 - D8
WEN
WCLK
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
19
tDS
tENS
W1
tOHZ
WD
tENS
tWFF
tDH
tENH
W1
tOE
tA
W2
1
(1)
tSKEW1
tA
2
tWFF
W3
(2)
Wm+2
tSKEW2
W[m+3]
tA
tPAF
W[m+4]
W[ D-1 ]
tHF
W[ D-1 ]
tA
W[D-n-1]
tA
W[D-n]
tPAE
W[D-n+1]
W[D-n+2]
W[D-1]
tA
tENS
WD
4675 drw 13
tREF
Figure 10. Read Timing (First Word Fall Through Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of
WCLK is less than tSKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAF. If the time between the rising edge of RCLK and the rising edge of
WCLK is less than tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH.
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
IR
PAF
HF
PAE
OR
Q0 - Q8
OE
REN
RCLK
D0 - D8
WEN
WCLK
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
1
RCLK
tENS
tENH
2
tENS
tRTS
tENH
REN
tA
Q0 - Qn
tA
Wx
tA
Wx+1
W1
(3)
W2
(3)
tSKEW2
1
WCLK
2
tRTS
WEN
tENS
tENH
RT
tREF
tREF
(5)
EF
tPAE
PAE
tHF
HF
tPAF
PAF
4675 drw 14
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D – 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup
procedure. D = 65,536 for the IDT72281 and 131,072 for the IDT72291.
5. EF goes HIGH at 60 ns + 1 RCLK cycle + tREF.
Figure 11. Retransmit Timing (IDT Standard Mode)
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
tENH
tENS
3
2
1
RCLK
4
tENH
tENH
tRTS
REN
tA
Q0 - Qn
Wx
Wx+1
tA
W1
(4)
W2
W3
tSKEW2
1
WCLK
2
tRTS
WEN
tENS
tENH
RT
tREF (5)
tREF
OR
tPAE
PAE
tHF
HF
tPAF
PAF
4675 drw 15
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D – 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
procedure. D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. OR goes LOW at 60 ns + 2 RCLK cycles + tREF.
Figure 12. Retransmit Timing (FWFT Mode)
WCLK
tENS
tENH
tENH
SEN
tLDS
tLDH
tLDH
LD
tDH
tDS
SI
BIT 0
BIT X
(1)
BIT 0
BIT X
FULL OFFSET
EMPTY OFFSET
NOTE:
1. X = 15 for the IDT72281 and X = 16 for the IDT72291.
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
21
(1)
4675 drw16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
tCLK
tCLKH
tCLKL
WCLK
tLDS
tLDH
tLDH
LD
tENS
tENH
tENH
WEN
tDS
tDH
tDH
D0 - D7
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
4675 drw 17
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72281
tCLK
tCLKH
tCLKL
WCLK
tLDS
tLDH
tLDH
LD
tENS
tENH
tENH
WEN
tDS
tDH
tDH
D0 - D7
PAE OFFSET
(LSB)
PAE OFFSET
(MID-BYTE)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MID-BYTE)
PAF OFFSET
(MSB)
4675 drw 18
Figure 15. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72291
t CLK
t CLKH
t CLKL
RCLK
t LDS
t LDH
t LDH
LD
t ENS
t ENH
t ENH
REN
tA
tA
PAE OFFSET
(LSB)
DATA IN OUTPUT
REGISTER
Q0 - Q7
PAF OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(MSB)
4675 drw 19
NOTE:
1. OE = LOW.
Figure 16. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72281
t CLK
t CLKH
t CLKL
RCLK
t LDS
t LDH
t LDH
t ENS
t ENH
t ENH
LD
REN
tA
Q0 - Q7
DATA IN OUTPUT REGISTER
PAE OFFSET
(LSB)
PAE OFFSET
(MID-BYTE)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
tA
PAF OFFSET
(MID-BYTE)
PAF OFFSET
(MSB)
4675 drw 20
NOTE:
1. OE = LOW.
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72291
22
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
t CLKH
t CLKL
WCLK
1
2
1
t ENS
2
t ENH
WEN
t PAF
PAF
t PAF
D-(m+1) words
in FIFO(2)
D - m words in FIFO(2)
D - (m+1) words in FIFO(2)
t SKEW2
(3)
RCLK
t ENH
t ENS
REN
4675 drw 21
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 65,536 for the IDT72281 and 131,072 for the IDT72291.
In FWFT mode: D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAF). If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 18. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t CLKH
t CLKL
WCLK
t ENS
t ENH
WEN
n words in FIFO (2),
n+1 words in FIFO (3)
PAE
t SKEW2 (4)
RCLK
n+1 words in FIFO
n+2 words in FIFO
t PAE
1
n words in FIFO (2),
n+1 words in FIFO (3)
(2)
,
(3)
t PAE
2
1
t ENS
2
t ENH
REN
4675 drw 22
NOTES:
1. n = PAE offset.
2. For IDT Standard mode.
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
Figure 19. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
tHF
HF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1),
D-1
2 +1
[
[D-1
2
] words in FIFO
(2)
]
+ 2 words in FIFO(2)
D/2 words in FIFO(1),
[D-1
2
]
+ 1 words in FIFO(2)
tHF
RCLK
tENS
REN
4675 drw 23
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72281 and 131,072 for the IDT72291.
2. For FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
Figure 20. Half-Full Flag Timing (IDT Standard and FWFT Modes)
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can be
created by ORing OR of every FIFO, and separately ORing IR of every FIFO.
Figure 23 demonstrates a width expansion using two IDT72281/72291
devices. D0 - D8 from each device form a 18-bit wide input bus and Q0-Q8 from
each device form a 18-bit wide output bus. Any word width can be attained by
adding additional IDT72281/72291 devices.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the IR
and OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m+n
DATA IN
D0 - Dm
m
n
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
OUTPUT ENABLE (OE)
LOAD (LD)
FULL FLAG/INPUT READY (FF/IR) #1
IDT
72281
72291
IDT
72281
72291
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
(1)
FULL FLAG/INPUT READY (FF/IR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
PROGRAMMABLE (PAE)
FIFO
#1
FIFO
#2
m
n
Qm+1 - Qn
m+n
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 21. Block Diagram of 65,536 x 18 and 131,072 x 18 Width Expansion
24
GATE
DATA OUT
4675 drw 24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
•
FWFT/SI
TRANSFER CLOCK
FWFT/SI
WRITE CLOCK
WCLK
WRITE ENABLE
WEN
INPUT READY
IR
RCLK
OR
IDT
72281
72291
REN
OE
DATA IN
FWFT/SI
•
Dn
RCLK
WEN
REN
READ ENABLE
OR
OUTPUT READY
OE
OUTPUT ENABLE
IR
IDT
72281
72291
GND
n
Qn
n
READ CLOCK
WCLK
n
DATA OUT
Qn
Dn
4675 drw 25
Figure 22. Block Diagram of 131,072 x 9 and 262,144 x 9 Depth Expansion
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72281 can easily be adapted to applications requiring depths greater
than 65,536 and 131,072 for the IDT72291 with a 9-bit bus width. In FWFT
mode, the FIFOs can be connected in series (the data outputs of one FIFO
connected to the data inputs of the next) with no external logic necessary. The
resulting configuration provides a total depth equivalent to the sum of the depths
associated with each single FIFO. Figure 24 shows a depth expansion using
two IDT72281/72291 devices.
Care should be taken to select FWFT mode during Master Reset for all FIFOs
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain–no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the data
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for OR of
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
The "ripple down" delay is only noticeable for the first word written to an empty
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will "bubble up" from the last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding FIFO
to write a word to fill it.
For a full expansion configuration, the amount of time it takes for IR of the first
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the tSKEW1
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK period.
Note that extra cycles should be added for the possibility that the tSKEW3
25
ORDERING INFORMATION
IDT
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process /
Temperature
Range
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
TF
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack (STQFP, PP64-1)
10
15
20
Commercial Only
Com'l & Ind'l
Com'l & Ind'l
L
Low Power
72281
72291
65,536 x 9 SuperSyncFIFO
131,072 x 9 SuperSyncFIFO
Clock Cycle Time (tCLK)
Speed in Nanoseconds
4675 drw26
NOTE:
1. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device.
DATASHEET DOCUMENT HISTORY
04/24/2001
pgs. 1, 5, 6 and 26.
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26
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