RDIMM DDR2 SDRAM DDR2 Registered SDRAM MODULE 240pin Registered Module based on 1Gb C-die 72-bit ECC 60FBGA & 63FBGA with Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM Table of Contents 1.0 DDR2 Registered DIMM Ordering Information ..........................................................................4 2.0 Features ........................................................................................................................................4 3.0 Address Configuration ................................................................................................................4 4.0 Pin Configurations (Front side/Back side) ................................................................................5 5.0Pin Description .............................................................................................................................5 6.0 Input/Output Function Description ............................................................................................6 7.0 Functional Block Diagram ...........................................................................................................7 7.1 2GB, 256Mx72 Module - M393T5663CZ3/M393T5663CZA ...................................................................7 7.2 2GB, 256Mx72 Module - M393T5660CZ3/M393T5660CZA ...................................................................8 7.3 4GB, 512MBx72 Module - M393T5160CZ3/M393T5160CZA .................................................................9 7.4 4GB, 512MBx72 Module - M392T5160CJ ........................................................................................10 7.5 8GB, 1GBx72 Module - M393T1G60CJA ........................................................................................ 11 8.0 Absolute Maximum DC Ratings ................................................................................................12 9.0 AC & DC Operating Conditions ................................................................................................12 9.1 Recommended DC Operating Conditions (SSTL - 1.8) .....................................................................12 9.2 Operating Temperature Condition ................................................................................................13 9.3 Input DC Logic Level ..................................................................................................................13 9.4 Input AC Logic Level ..................................................................................................................13 9.5 AC Input Test Conditions ............................................................................................................13 10.0 IDD Specification Parameters Definition ............................................................................... 14 11.0 Operating Current Table ..........................................................................................................15 11.1 M393T5663CZ3 / M393T5663CZA : 2GB(128Mx8 *18) Module .........................................................15 11.2 M393T5663CZ3 / M393T5663CZA : 2GB(128Mx8 *18) Module .........................................................15 11.3 M393T5660CZ3 / M393T5660CZA : 2GB(256Mx4 *18) Module .........................................................16 11.4 M393T5660CZ3 / M393T5660CZA : 2GB(256Mx4 *18) Module .........................................................16 11.5 M393T5160CZ3 / M393T5160CZA / M392T5160CJA : 4GB(256Mx4 *36 / 512Mx4 *18) Module ..............17 11.6 M393T5160CZ3 / M393T5160CZA / M392T5160CJA : 4GB(256Mx4 *36 / 512Mx4 *18) Module ..............17 11.7 M393T1G60CJA : 8GB(512Mx4 *36) Module ................................................................................18 11.8 M393T1G60CJA : 8GB(512Mx4 *36) Module .................................................................................18 12.0 Input/Output Capacitance .......................................................................................................19 13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 .....................................19 13.1 Refresh Parameters by Device Density ......................................................................................19 13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ...........................................19 13.3 Timing Parameters by Speed Grade ..........................................................................................20 14.0 Physical Dimensions : .............................................................................................................22 14.1 128Mbx8/256Mbx4 based 256Mx72 Module (2/1 Ranks) ................................................................22 14.2 256Mbx4 based 512Mx72 Module (2 Ranks) ................................................................................23 14.3 DDP 512Mbx4 based 512Mx72 Module (2 Ranks) ........................................................................24 14.4 DDP 512Mbx4 based 1Gx72 Module (4 Ranks) ............................................................................25 15.0 240 Pin DDR2 Registered DIMM Clock Topology .................................................................26 2 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM Revision History Revision Month Year History 1.0 March 2007 - Initial Release 1.1 April 2007 - Add the 2GB Registered DIMM Product 1.2 June 2007 1.3 July 2007 - Corrected Typo 1.4 November 2007 - Changed ordering information - Added IDD values for DDR2-800 - Corrected Typo 3 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 1.0 DDR2 Registered DIMM Ordering Information Density Organization Component Composition Number of Rank Parity Register Height M393T5663CZ3-CD5/CC Part Number 2GB 256Mx72 128Mx8(K4T1G084QC)*18EA 2 X 30.00mm M393T5663CZA-CF7/E6 2GB 256Mx72 128Mx8(K4T1G084QC)*18EA 2 O 30.00mm M393T5660CZ3-CD5/CC 2GB 256Mx72 256Mx4(K4T1G044QC)*18EA 1 X 30.00mm M393T5660CZA-CF7/E6 2GB 256Mx72 256Mx4(K4T1G044QC)*18EA 1 O 30.00mm M393T5160CZ3-CD5/CC 4GB 512Mx72 256Mx4(K4T1G044QC)*36EA 2 X 30.00mm M393T5160CZA-CF7/E6 4GB 512Mx72 256Mx4(K4T1G044QC)*36EA 2 O 30.00mm M392T5160CJA-CF7/E6 4GB 512Mx72 DDP512Mx4(K4T2G044QC)*18EA 2 O 18.30mm M393T1G60CJA-CE6/D5 8GB 1Gx72 DDP512Mx4(K4T1G044QC)*36EA 4 O 30.00mm Note : 1. “Z” of Part number(11th digit) stand for Lead-free products. and "J" of Part number(11th digit) stand for dual-die package products. 2. “3” of Part number(12th digit) stand for Non-parity Register products. and "A" of Part number(12th digit) stand for Parity Register products. 3. "92" of Part number(3~4th digit) stand for VLP(Very Low Profile) Register products. 2.0 Features • Performance range F7(DDR2-800) E6(DDR2-667) D5(DDR2-533) CC(DDR2-400) Unit Speed@CL3 - 400 400 400 Mbps Speed@CL4 533 533 533 400 Mbps Speed@CL5 667 667 - - Mbps Speed@CL6 800 - - - Mbps CL-tRCD-tRP 6-6-6 5-5-5 4-4-4 3-3-3 CK • JEDEC standard 1.8V ± 0.1V Power Supply • VDDQ = 1.8V ± 0.1V • 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin • 8 Banks • Posted CAS • Programmable CAS Latency: 3, 4, 5, 6 • Programmable Additive Latency: 0, 1 , 2 , 3, 4 and 5 • Write Latency(WL) = Read Latency(RL) -1 • Burst Length: 4 , 8(Interleave/nibble sequential) • Programmable Sequential / Interleave Burst Mode • Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) • Off-Chip Driver(OCD) Impedance Adjustment • On Die Termination with selectable values(50/75/150 ohms or disable) • PASR(Partial Array Self Refresh) • Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C - support High Temperature Self-Refresh rate enable feature • Serial presence detect with EEPROM • DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8 • All of Lead-free products are compliant for RoHS Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram. 3.0 Address Configuration Organization Row Address Column Address Bank Address Auto Precharge 256Mx4(1Gb) based Module A0-A13 A0-A9, A11 BA0-BA2 A10 128Mx8(1Gb) based Module A0-A13 A0-A9 BA0-BA2 A10 4 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 4.0 Pin Configurations (Front side/Back side) Pin 1 Front VREF Pin 121 Back VSS Pin 31 Front DQ19 Pin 151 Back VSS Pin 61 Front A4 Pin 181 Back VDDQ Pin 91 Front VSS Pin 211 Back DM5/DQS14 NC/DQS14 2 VSS 122 DQ4 32 VSS 152 DQ28 62 VDDQ 182 A3 92 DQS5 212 3 DQ0 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 VSS 4 DQ1 124 VSS 34 DQ25 154 VSS 64 VDD 184 VDD 94 VSS 214 DQ46 DQ47 5 VSS 125 DM0/DQS9 35 VSS 155 DM3/DQS12 95 DQ42 215 6 DQS0 126 NC/DQS9 36 DQS3 156 NC/DQS12 65 VSS KEY 185 CK0 96 DQ43 216 VSS 7 DQS0 127 VSS 37 DQS3 157 VSS 66 VSS 186 CK0 97 VSS 217 DQ52 8 VSS 128 DQ6 38 VSS 158 DQ30 67 VDD 187 VDD 98 DQ48 218 DQ53 9 DQ2 129 DQ7 39 DQ26 159 DQ31 68 NC/Par_In 188 A0 99 DQ49 219 VSS 10 DQ3 130 VSS 40 DQ27 160 VSS 69 VDD 189 VDD 100 VSS 220 S2 11 VSS 131 DQ12 41 VSS 161 CB4 70 A10/AP 190 BA1 101 SA2 221 S3 12 DQ8 132 DQ13 42 CB0 162 CB5 71 BA0 191 VDDQ 102 NC(TEST) 222 VSS 13 DQ9 133 VSS 43 CB1 163 VSS 72 VDDQ 192 RAS 103 VSS 223 DM6/DQS15 NC/DQS15 14 VSS 134 DM1/DQS10 44 VSS 164 DM8/DQS17 73 WE 193 S0 104 DQS6 224 15 DQS1 135 NC/DQS10 45 DQS8 165 NC/DQS17 74 CAS 194 VDDQ 105 DQS6 225 VSS 16 DQS1 136 VSS 46 DQS8 166 VSS 75 VDDQ 195 ODT0 106 VSS 226 DQ54 17 VSS 137 RFU 47 VSS 167 CB6 76 S1 196 A13 107 DQ50 227 DQ55 18 RESET 138 RFU 48 CB2 168 CB7 77 ODT1 197 VDD 108 DQ51 228 VSS 19 NC 139 VSS 49 CB3 169 VSS 78 VDDQ 198 VSS 109 VSS 229 DQ60 20 VSS 140 DQ14 50 VSS 170 VDDQ 79 VSS 199 DQ36 110 DQ56 230 DQ61 21 DQ10 141 DQ15 51 VDDQ 171 CKE1 80 DQ32 200 DQ37 111 DQ57 231 VSS 22 DQ11 142 VSS 52 CKE0 172 VDD 81 DQ33 201 VSS 112 VSS 232 DM7/DQS16 23 VSS 143 DQ20 53 VDD 173 NC 82 VSS 202 DM4/DQS13 113 DQS7 233 NC/DQS16 24 DQ16 144 DQ21 54 BA2 174 NC 83 DQS4 203 NC/DQS13 114 DQS7 234 VSS 25 DQ17 145 VSS 55 NC/Err_Out 175 VDDQ 84 DQS4 204 VSS 115 VSS 235 DQ62 DQ63 26 VSS 146 DM2/DQS11 56 VDDQ 176 A12 85 VSS 205 DQ38 116 DQ58 236 27 DQS2 147 NC/DQS11 57 A11 177 A9 86 DQ34 206 DQ39 117 DQ59 237 VSS 28 DQS2 148 VSS 58 A7 178 VDD 87 DQ35 207 VSS 118 VSS 238 VDDSPD 29 VSS 149 DQ22 59 VDD 179 A8 88 VSS 208 DQ44 119 SDA 239 SA0 30 DQ18 150 DQ23 60 A5 180 A6 89 90 DQ40 DQ41 209 210 DQ45 VSS 120 SCL 240 SA1 NC = No Connect, RFU = Reserved for Future Use 1. RESET (Pin 18) is connected to both OE of PLL and Reset of register. 2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs) 3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity. 5.0Pin Description Pin Name Description Pin Name Description CK0 CK0 Clock Inputs, positive line ODT0~ODT1 On die termination Clock inputs, negative line DQ0~DQ63 Data Input/Output CKE0, CKE1 Clock Enables CB0~CB7 Data check bits Input/Output RAS Row Address Strobe DQS0~DQS8 Data strobes CAS Column Address Strobe DQS0~DQS8 Data strobes, negative line WE Write Enable DM(0~8), DQS(9~17) Data Masks / Data strobes (Read) S0~ S3 Chip Selects DQS9~DQS17 Data strobes (Read), negative line A0~A9, A11~A13 Address Inputs RFU Reserved for Future Use A10/AP Address Input/Autoprecharge NC No Connect BA0~BA2 DDR2 SDRAM Bank Address TEST Memory bus test tool (Not Connect and Not Useable on DIMMs) SCL Serial Presence Detect (SPD) Clock Input VDD Core Power SDA SPD Data Input/Output VDDQ I/O Power SA0~SA2 SPD address VSS Ground Par_In Parity bit for the Address and Control bus VREF Input/Output Reference Err_Out Parity error found in the Address and Control bus VDDSPD SPD Power RESET Register and PLL control pin * The VDD and VDDQ pins are tied to the single power-plane on PCB. 5 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 6.0 Input/Output Function Description Symbol Type Description CK0 Input Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. CK0 Input Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL. CKE0~CKE1 Input Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. S0~S3 Input Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored but previous operations continue. These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. ODT0~ODT1 Input I/O bus impedance control signals. RAS, CAS, WE Input When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. VREF Supply Reference voltage for SSTL_18 inputs VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity BA0~BA2 Input Selects which SDRAM bank of eight is activated. A0~A9,A10/AP A11~A13 Input During a Bank Activate command cycle, Address defines the row address. During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are used to define which bank to precharge. DQ0~63, CB0~CB7 In/Out Data and Check Bit Input/Output pins DM0~DM8 Input Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once the write command is registered into the SDRAM. VDD, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic DQS0~DQS17 In/Out Positive line of the differential data strobe for input and output data. DQS0~DQS17 In/Out Negative line of the differential data strobe for input and output data. SA0~SA2 Input These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. SDA In/Out This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD to act as a pullup. SCL Input This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD to act as a pullup. VDDSPD Supply Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6 Volt operation). RESET Input The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchronized with the input clock ) Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even) Par_In Input Err_Out Output Parity error found in the Address and Control bus TEST In/Out Used by memory bus analysis tools (unused on memory DIMMs) 6 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 7.0 Functional Block Diagram 7.1 2GB, 256Mx72 Module - M393T5663CZ3/M393T5663CZA(populated as 2 rank of x8 DDR2 SDRAMs) RS1 RS0 DQS0 DQS0 DM0/DQS9 NC/DQS9 DQS4 DQS4 DM4/DQS13 NC/DQS13 DM/ NU/ CS RDQS RDQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM/ NU/ CS RDQS RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 DQS DQS DM/ NU/ CS RDQS RDQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D9 DQS1 DQS1 DM1/DQS10 NC/DQS10 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM/ NU/ CS RDQS RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D4 DQS DQS D13 DQS5 DQS5 DM5/DQS14 NC/DQS14 DM/ NU/ CS RDQS RDQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM/ NU/ CS RDQS RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 DQS DQS D10 DQS2 DQS2 DM2/DQS11 NC/DQS11 DM/ NU/ CS RDQS RDQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM/ NU/ CS RDQS RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 DQS DQS D14 DQS6 DQS6 DM6/DQS15 NC/DQS15 DM/ NU/ CS RDQS RDQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM/ NU/ CS RDQS RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 DQS DQS D11 DQS3 DQS3 DM3/DQS12 NC/DQS12 DM/ NU/ CS RDQS RDQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM/ NU/ CS RDQS RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 DQS DQS D15 DQS7 DQS7 DM7/DQS16 NC/DQS16 DM/ NU/ CS RDQS RDQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM/ NU/ CS RDQS RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 DQS DQS D12 DQS8 DQS8 DM8/DQS17 NC/DQS17 DM/ NU/ CS RDQS RDQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS SCL CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 S0* S1* BA0-BA2 A0-A13 RAS CAS WE CKE0 CKE1 ODT0 ODT1 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1:2 R E G I S T E R RESET** D8 DQS DQS DM/ NU/ CS RDQS RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SDA WP A0 DQS DQS A1 A2 SA0 SA1 SA2 D17 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D7 Serial PD DM/ NU/ CS RDQS RDQS DM/ NU/ CS RDQS RDQS DQS DQS D16 VDDSPD Serial PD VDD/VDDQ D0 - D17 VREF D0 - D17 VSS D0 - D17 Note : 1. DQ-to-I/O wiring may be changed per nibble. 2. Unless otherwise noted, resister values are 22 Ohms 3. RS0 and RS1 alternate between the back and front sides of the DIMM RSO-> CS : DDR2 SDRAMs D0-D8 RS1-> CS : DDR2 SDRAMs D9-D17 RBA0-RBA2 -> BA0-BA2: DDR2 SDRAMs D0-D17 RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17 RRAS -> RAS : DDR2 SDRAMs D0-D17 RCAS -> CAS : DDR2 SDRAMs D0-D17 RWE -> WE : DDR2 SDRAMs D0-D17 RCKE0 -> CKE : DDR2 SDRAMs D0-D8 RCKE1 -> CKE : DDR2 SDRAMs D9-D17 RODT0 -> ODT0 : DDR2 SDRAMs D0-D8 RODT1 -> ODT1 : DDR2 SDRAMs D9-D17 Signals for Address and Command Parity Function (M393T5663CZA) VSS VDD C0 C1 Register A PAR_IN PAR_IN 100K ohms PPO VDD VDD C0 C1 Register B PAR_IN PPO QERR QERR Err_Out The resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register Options for Unused Address inputs" RST PCK7** PCK7** * S0 connects to DCS and S1 connects to CSR on a Register, S1 connects to DCS and S0 connects to CSR on another Register. ** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers. CK0 CK0 RESET 7 of 26 P L L OE PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17 PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17 PCK7 -> CK : Register PCK7 -> CK : Register Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 7.2 2GB, 256Mx72 Module - M393T5660CZ3/M393T5660CZA (populated as 1 rank of x4 DDR2 SDRAMs) VSS RS0 DQS0 DQS0 DM0/DQS9 NC/DQS9 DM DQ0 DQ1 DQ2 DQ3 DQS1 DQS1 I/O 0 I/O 1 I/O 2 I/O 3 DM DQ8 DQ9 DQ10 DQ11 I/O 0 I/O 1 I/O 2 I/O 3 CS DQS DQS D0 CS DQS DQS D1 I/O 0 I/O 1 I/O 2 I/O 3 CS DQS DQS D2 I/O 0 I/O 1 I/O 2 I/O 3 CS DQS DQS D3 I/O 0 I/O 1 I/O 2 I/O 3 CS DQS DQS DQS DQS D11 CS I/O 0 I/O 1 I/O 2 I/O 3 DQS DQS D12 DM DQ36 DQ37 DQ38 DQ39 D4 DQS5 DQS5 CS I/O 0 I/O 1 I/O 2 I/O 3 DQS DQS D13 DM5/DQS14 NC/DQS14 DM I/O 0 I/O 1 I/O 2 I/O 3 CS DQS DQS DM DQ44 DQ45 DQ46 DQ47 D5 DQS6 DQS6 CS I/O 0 I/O 1 I/O 2 I/O 3 DQS DQS D14 Serial PD SCL DM6/DQS15 NC/DQS15 DM I/O 0 I/O 1 I/O 2 I/O 3 CS DQS DQS CS I/O 0 I/O 1 I/O 2 I/O 3 DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DQS DQS DM DQ60 DQ61 DQ62 DQ63 D7 DQS8 DQS8 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 CS D8 DQS DQS DM CB4 CB5 CB6 CB7 DQS DQS D16 CS I/O 0 I/O 1 I/O 2 I/O 3 A2 SA0 SA1 SA2 DM8/DQS17 NC/DQS17 DM A1 D15 DM7DQS16 NC/DQS16 DM SDA WP A0 DM DQ52 DQ53 DQ54 DQ55 D6 DQS7 DQS7 CB0 CB1 CB2 CB3 CS DM4/DQS13 NC/DQS13 DM DQ56 DQ57 DQ58 DQ59 DQS DQS D10 I/O 0 I/O 1 I/O 2 I/O 3 DM DQ28 DQ29 DQ30 DQ31 DQS4 DQS4 DQ48 DQ49 DQ50 DQ51 CS DM3/DQS12 NC/DQS12 DM DQ40 DQ41 DQ42 DQ43 D9 I/O 0 I/O 1 I/O 2 I/O 3 DM DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DQ32 DQ33 DQ34 DQ35 DQS DQS DM2/DQS11 NC/DQS11 DM DQ24 DQ25 DQ26 DQ27 CS I/O 0 I/O 1 I/O 2 I/O 3 DM DQ12 DQ13 DQ14 DQ15 DQS2 DQS2 DQ16 DQ17 DQ18 DQ19 DM DQ4 DQ5 DQ6 DQ7 DM1/DQS10 NC/DQS10 DQS DQS VDDSPD Serial PD VDD/VDDQ D0 - D17 VREF D0 - D17 VSS D0 - D17 D17 Signals for Address and Command Parity Function (M393T5660CZA) 1:2 R E G I S T E R S0* BA0-BA2 A0-A13 RAS CAS WE CKE0 ODT0 RESET** VSS VDD RSO-> CS : DDR2 SDRAMs D0-D17 RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D17 RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17 RRAS -> RAS : DDR2 SDRAMs D0-D17 RCAS -> CAS : DDR2 SDRAMs D0-D17 RWE -> WE : DDR2 SDRAMs D0-D17 RCKE0 -> CKE : DDR2 SDRAMs D0-D17 RODT0 -> ODT0 : DDR2 SDRAMs D0-D17 C0 C1 Register A PAR_IN PAR_IN PPO VDD VDD C0 C1 PAR_IN PPO QERR QERR 100K ohms Register B Err_Out The resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register Options for Unused Address inputs" RST PCK7** CK0 PCK7** CK0 * S0 connects to DCS of Register1 and CSR of Register2. CSR of register 1 and DCS of register 2 connects to VDD. RESET P L L OE PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8 PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8 PCK7 -> CK : Register PCK7 -> CK : Register Note : 1. DQ-to-I/O wiring may be changed per nibble. 2. Unless otherwise noted, resister values are 22 Ohms ** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers. S1, CKE1 and ODT1 are NC. 8 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 7.3 4GB, 512MBx72 Module - M393T5160CZ3/M393T5160CZA (populated as 2 rank of x4 DDR2 SDRAMs) VSS RS1 RS0 DM0/DQS9 NC/DQS9 DQS0 DQS0 DM DQ0 DQ1 DQ2 DQ3 DQS1 DQS1 DM DQ8 DQ9 DQ10 DQ11 CS DQS DQS I/O 0 I/O 1 D0 I/O 2 I/O 3 CS DM/ CS DQS DQS I/O 0 I/O 1 D18 I/O 2 I/O 3 DQS DQS I/O 0 I/O 1 D1 I/O 2 I/O 3 DM/ CS DQS DQS CS DQS DQS I/O 0 I/O 1 D2 I/O 2 I/O 3 DM/ CS DQS DQS CS DQS DQS I/O 0 I/O 1 D3 I/O 2 I/O 3 DM CS DM DQS DQS CS DQS DQS CS DQS DQS I/O 0 I/O 1 D28 I/O 2 I/O 3 CS DM DQS DQS I/O 0 I/O 1 D11 I/O 2 I/O 3 DM DQ28 DQ29 DQ30 DQ31 DM CS DQS DQS CS DQS DQS I/O 0 I/O 1 D29 I/O 2 I/O 3 CS DM DQS DQS I/O 0 I/O 1 D12 I/O 2 I/O 3 DM DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 D22 I/O 2 I/O 3 I/O 0 I/O 1 D4 I/O 2 I/O 3 DQS5 DQS5 CS DQS DQS I/O 0 I/O 1 D30 I/O 2 I/O 3 CS DM DQS DQS CS DQS DQS I/O 0 I/O 1 D31 I/O 2 I/O 3 I/O 0 I/O 1 D13 I/O 2 I/O 3 DM5/DQS14 NC/DQS14 DM CS DQS DQS I/O 0 I/O 1 D5 I/O 2 I/O 3 DM CS DQS DQS DM DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 D23 I/O 2 I/O 3 DQS6 DQS6 CS DM DQS DQS I/O 0 I/O 1 D14 I/O 2 I/O 3 CS DQS DQS I/O 0 I/O 1 D32 I/O 2 I/O 3 DM6/DQS15 NC/DQS15 DM CS DQS DQS I/O 0 I/O 1 D6 I/O 2 I/O 3 DM CS DQS DQS DM DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 D24 I/O 2 I/O 3 DQS7 DQS7 CS DM DQS DQS I/O 0 I/O 1 D15 I/O 2 I/O 3 CS DQS DQS I/O 0 I/O 1 D33 I/O 2 I/O 3 Serial PD DM7DQS16 NC/DQS16 DM CS DQS DQS I/O 0 I/O 1 D7 I/O 2 I/O 3 DM CS DQS DQS SCL DM DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 D25 I/O 2 I/O 3 DQS8 DQS8 CS DM DQS DQS I/O 0 I/O 1 D16 I/O 2 I/O 3 CS DQS DQS I/O 0 I/O 1 D34 I/O 2 I/O 3 CS I/O 0 I/O 1 D8 I/O 2 I/O 3 S0* DQS DQS DM CS DQS DQS I/O 0 I/O 1 D26 I/O 2 I/O 3 DM CB4 CB5 CB6 CB7 CS DM DQS DQS CS DQS DQS I/O 0 I/O 1 D35 I/O 2 I/O 3 I/O 0 I/O 1 D17 I/O 2 I/O 3 SDA WP A0 A1 A2 SA0 SA1 SA2 DM8/DQS17 NC/DQS17 DM CB0 CB1 CB2 CB3 DQS DQS DM4/DQS13 NC/DQS13 DM DQ56 DQ57 DQ58 DQ59 DM DQS DQS I/O 0 I/O 1 D10 I/O 2 I/O 3 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 D21 I/O 2 I/O 3 DQS4 DQS4 DQ48 DQ49 DQ50 DQ51 CS CS I/O 0 I/O 1 D27 I/O 2 I/O 3 DM3/DQS12 NC/DQS12 DM DQ40 DQ41 DQ42 DQ43 DM I/O 0 I/O 1 D20 I/O 2 I/O 3 DQS3 DQS3 DQ32 DQ33 DQ34 DQ35 DM DQS DQS DM2/DQS11 NC/DQS11 DM DQ24 DQ25 DQ26 DQ27 CS I/O 0 I/O 1 D9 I/O 2 I/O 3 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 D19 I/O 2 I/O 3 DQS2 DQS2 DQ16 DQ17 DQ18 DQ19 DM DQ4 DQ5 DQ6 DQ7 DM1/DQS10 NC/DQS10 VDDSPD Serial PD VDD/VDDQ D0 - D35 VREF D0 - D35 VSS D0 - D35 RSO-> CS : DDR2 SDRAMs D0-D17 S1* BA0-BA1 A0-A13 RAS CAS WE CKE0 CKE1 ODT0 ODT1 RESET** 1:2 R E G I S T E R RS1-> CS : DDR2 SDRAMs D18-D35 RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35 RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35 RRAS -> RAS : DDR2 SDRAMs D0-D35 RCAS -> CAS : DDR2 SDRAMs D0-D35 RWE -> WE : DDR2 SDRAMs D0-D35 RCKE0 -> CKE : DDR2 SDRAMs D0-D17 RCKE1 -> CKE : DDR2 SDRAMs D18-D35 RODT0 -> ODT0 : DDR2 SDRAMs D0-D17 RODT1 -> ODT1 : DDR2 SDRAMs D18-D35 Signals for Address and Command Parity Function (M393T5160CZA) VSS VDD C0 C1 Register A PAR_IN PAR_IN 100K ohms PPO VDD VDD C0 C1 Register B PAR_IN QERR PPO QERR Err_Out The resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register RST Options for Unused Address inputs" PCK7** PCK7** * S0 connects to DCS and S1 connects to CSR on a pair of Registers, S1 connects to DCS and S0 connects to CSR on another pair of Registers. ** RESET, PCK7 and PCK7 connects to all Registers. Other signals connect to one pair of four Registers. CK0 CK0 RESET 9 of 26 P L L OE PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35 PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35 PCK7 -> CK : Register PCK7 -> CK : Register Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 7.4 4GB, 512MBx72 Module - M392T5160CJ (populated as 2 rank of x4 DDR2 SDRAMs) VSS RS1 RS0 DM0/DQS9 NC/DQS9 DQS0 DQS0 DM DQ0 DQ1 DQ2 DQ3 DQS1 DQS1 DM DQ8 DQ9 DQ10 DQ11 CS DQS DQS I/O 0 I/O 1 D0 I/O 2 I/O 3 CS DM/ CS DQS DQS I/O 0 I/O 1 D18 I/O 2 I/O 3 DQS DQS I/O 0 I/O 1 D1 I/O 2 I/O 3 DM/ CS DQS DQS CS DQS DQS I/O 0 I/O 1 D2 I/O 2 I/O 3 DM/ CS DQS DQS CS DQS DQS I/O 0 I/O 1 D3 I/O 2 I/O 3 DM CS DM DQS DQS CS DQS DQS CS DQS DQS I/O 0 I/O 1 D28 I/O 2 I/O 3 CS DM DQS DQS I/O 0 I/O 1 D11 I/O 2 I/O 3 DM DQ28 DQ29 DQ30 DQ31 DM CS DQS DQS CS DQS DQS I/O 0 I/O 1 D29 I/O 2 I/O 3 CS DM DQS DQS I/O 0 I/O 1 D12 I/O 2 I/O 3 DM DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 D22 I/O 2 I/O 3 I/O 0 I/O 1 D4 I/O 2 I/O 3 DQS5 DQS5 CS DQS DQS I/O 0 I/O 1 D30 I/O 2 I/O 3 CS DM DQS DQS CS DQS DQS I/O 0 I/O 1 D31 I/O 2 I/O 3 I/O 0 I/O 1 D13 I/O 2 I/O 3 DM5/DQS14 NC/DQS14 DM CS DQS DQS I/O 0 I/O 1 D5 I/O 2 I/O 3 DM CS DQS DQS DM DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 D23 I/O 2 I/O 3 DQS6 DQS6 CS DM DQS DQS I/O 0 I/O 1 D14 I/O 2 I/O 3 CS DQS DQS I/O 0 I/O 1 D32 I/O 2 I/O 3 DM6/DQS15 NC/DQS15 DM CS DQS DQS I/O 0 I/O 1 D6 I/O 2 I/O 3 DM CS DQS DQS DM DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 D24 I/O 2 I/O 3 DQS7 DQS7 CS DM DQS DQS I/O 0 I/O 1 D15 I/O 2 I/O 3 CS DQS DQS I/O 0 I/O 1 D33 I/O 2 I/O 3 Serial PD DM7DQS16 NC/DQS16 DM CS DQS DQS I/O 0 I/O 1 D7 I/O 2 I/O 3 DM CS DQS DQS SCL DM DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 D25 I/O 2 I/O 3 DQS8 DQS8 CS DM DQS DQS I/O 0 I/O 1 D16 I/O 2 I/O 3 CS CS I/O 0 I/O 1 D8 I/O 2 I/O 3 S0* DQS DQS DM CS DQS DQS I/O 0 I/O 1 D26 I/O 2 I/O 3 DM CB4 CB5 CB6 CB7 CS I/O 0 I/O 1 D34 I/O 2 I/O 3 DM DQS DQS CS WP A0 A1 A2 SA0 SA1 SA2 DQS DQS I/O 0 I/O 1 D35 I/O 2 I/O 3 I/O 0 I/O 1 D17 I/O 2 I/O 3 SDA DQS DQS DM8/DQS17 NC/DQS17 DM CB0 CB1 CB2 CB3 DQS DQS DM4/DQS13 NC/DQS13 DM DQ56 DQ57 DQ58 DQ59 DM DQS DQS I/O 0 I/O 1 D10 I/O 2 I/O 3 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 D21 I/O 2 I/O 3 DQS4 DQS4 DQ48 DQ49 DQ50 DQ51 CS CS I/O 0 I/O 1 D27 I/O 2 I/O 3 DM3/DQS12 NC/DQS12 DM DQ40 DQ41 DQ42 DQ43 DM I/O 0 I/O 1 D20 I/O 2 I/O 3 DQS3 DQS3 DQ32 DQ33 DQ34 DQ35 DM DQS DQS DM2/DQS11 NC/DQS11 DM DQ24 DQ25 DQ26 DQ27 CS I/O 0 I/O 1 D9 I/O 2 I/O 3 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 D19 I/O 2 I/O 3 DQS2 DQS2 DQ16 DQ17 DQ18 DQ19 DM DQ4 DQ5 DQ6 DQ7 DM1/DQS10 NC/DQS10 VDDSPD Serial PD VDD/VDDQ D0 - D35 VREF D0 - D35 VSS D0 - D35 RSO-> CS : DDR2 SDRAMs D0-D17 S1* BA0-BA1 A0-A13 RAS CAS WE CKE0 CKE1 ODT0 ODT1 RESET** 1:2 R E G I S T E R RS1-> CS : DDR2 SDRAMs D18-D35 RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35 RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35 RRAS -> RAS : DDR2 SDRAMs D0-D35 RCAS -> CAS : DDR2 SDRAMs D0-D35 RWE -> WE : DDR2 SDRAMs D0-D35 RCKE0 -> CKE : DDR2 SDRAMs D0-D17 RCKE1 -> CKE : DDR2 SDRAMs D18-D35 RODT0 -> ODT0 : DDR2 SDRAMs D0-D17 RODT1 -> ODT1 : DDR2 SDRAMs D18-D35 Signals for Address and Command Parity Function VSS VSS 100K ohms PPO1 PPO2 VDD VDD C1 C2 Register B PAR_IN1 PAR_IN2 PPO1 PPO2 Err_Out QERR QERR The resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register PCK7** Options for Unused Address inputs" PCK7** ** RESET, PCK7 and PCK7 connects to all Registers. Other signals connect to one pair of four Registers. Register A PAR_IN1 PAR_IN2 PAR_IN RST * S0 connects to DCS and S1 connects to CSR on a pair of Registers, S1 connects to DCS and S0 connects to CSR on another pair of Registers. C1 C2 CK0 CK0 RESET 10 of 26 P L L OE PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35 PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35 PCK7 -> CK : Register PCK7 -> CK : Register Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 7.5 8GB, 1GBx72 Module - M393T1G60CJA (populated as 4 rank of x4 DDR2 SDRAMs) DQS DQS DQ3~0 DM CS0 CS1 CKE0 CKE1 ODT0 ODT0 CS0 CS1 CKE0 CKE1 ODT0 ODT0 D7 DQS DQS DQ3~0 DM D23 DQS DQS DQ3~0 DM D24 DQS DQS DQ3~0 DM D25 CS0 CS1 CKE0 CKE1 ODT0 ODT0 CS0 CS1 CKE0 CKE1 ODT0 ODT0 CS0 CS1 CKE0 CKE1 ODT0 ODT0 D29 CS0 CS1 CKE0 CKE1 ODT0 ODT0 CS0 CS1 CKE0 CKE1 ODT0 ODT0 D17 DQS DQS DQ3~0 DM DQS DQS DQ3~0 DM D30 CS0 CS1 CKE0 CKE1 ODT0 ODT0 CS0 CS1 CKE0 CKE1 ODT0 ODT0 CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS DQS DQ3~0 DM D28 DQS DQS DQ3~0 DM D35 RODT1 RCKE1 RS3 RS2 DQS13 DQS13 DQ39~36 DQS DQS DQ3~0 DM DQS14 DQS14 DQ47~44 DQS DQS DQ3~0 DM DQS15 DQS15 DQ55~52 DQS DQS DQ3~0 DM DQS16 DQS16 DQ63~60 DQS DQS DQ3~0 DM D13 D14 D15 D16 CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS7 DQS7 DQ59~56 D6 DQS17 DQS17 CB7~4 D12 DQS DQS DQ3~0 DM DQS DQS DQ3~0 DM D31 CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS DQS DQ3~0 DM CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS6 DQS6 DQ51~48 D5 D22 CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS DQS DQ3~0 DM DQS DQS DQ3~0 DM CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS5 DQS5 DQ43~40 D4 DQS DQS DQ3~0 DM RODT0 RCKE0 RS1 RS0 CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS DQS DQ3~0 DM CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS4 DQS4 DQ35~32 DQS12 DQS12 DQ31~28 D11 D27 DQS DQS DQ3~0 DM D32 CS0 CS1 CKE0 CKE1 ODT0 ODT0 D26 DQS DQS DQ3~0 DM DQS DQS DQ3~0 DM DQS DQS DQ3~0 DM D33 CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS DQS DQ3~0 DM RODT1 RCKE1 RS3 RS2 CS0 CS1 CKE0 CKE1 ODT0 ODT0 RODT0 RCKE0 RS1 RS0 D21 DQS11 DQS11 DQ23~20 D10 CS0 CS1 CKE0 CKE1 ODT0 ODT0 CS0 CS1 CKE0 CKE1 ODT0 ODT0 CS0 CS1 CKE0 CKE1 ODT0 ODT0 CS0 CS1 CKE0 CKE1 ODT0 ODT0 D8 DQS DQS DQ3~0 DM DQS DQS DQ3~0 DM CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS DQS DQ3~0 DM D20 DQS10 DQS10 DQ15~12 D9 CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS8 DQS8 CB3~0 D3 DQS DQS DQ3~0 DM DQS DQS DQ3~0 DM CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS DQS DQ3~0 DM D19 DQS9 DQS9 DQ7~4 CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS3 DQS3 DQ27~24 D2 DQS DQS DQ3~0 DM RODT1 RCKE1 RS3 RS2 CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS DQS DQ3~0 DM CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS2 DQS2 DQ19~16 D1 D18 CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS DQS DQ3~0 DM DQS DQS DQ3~0 DM CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS1 DQS1 DQ11~8 D0 CS0 CS1 CKE0 CKE1 ODT0 ODT0 DQS DQS DQ3~0 DM CS0 CS1 CKE0 CKE1 ODT0 ODT0 22 Ω DQS0 DQS0 DQ3~0 RODT0 RCKE0 RS1 RS0 CS0 CS1 CKE0 CKE1 ODT0 ODT0 RODT1 RCKE1 RS3 RS2 CS0 CS1 CKE0 CKE1 ODT0 ODT0 RODT0 RCKE0 RS1 RS0 DQS DQS DQ3~0 DM D34 Register PARIN 0Ω PAR_IN RS0-> CS0 : DDR2 SDRAMs D0-D17, RS2-> CS0 : DDR2 SDRAMs D18-D35 10 KΩ S0,2* S1,3** BA0-BA2 A0-A15 RAS CAS WE CKE0 CKE1 ODT0 ODT1 RESET** 1:2 R E G I S T E R RST PCK7** PCK7** PTYERR Register PARIN 0Ω ERR_OUT PTYERR RS1-> CS1 : DDR2 SDRAMs D0-D17, RS3-> CS1 : DDR2 SDRAMs D18-D35 RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35 Serial PD RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35 RRAS -> RAS : DDR2 SDRAMs D0-D35 SCL SDA RCAS -> CAS : DDR2 SDRAMs D0-D35 WP A0 A1 A2 RWE -> WE : DDR2 SDRAMs D0-D35 RCKE0 -> CKE : DDR2 SDRAMs D0-D17 SA0 SA1 SA2 RCKE1 -> CKE : DDR2 SDRAMs D18-D35 RODT0 -> ODT0 : DDR2 SDRAMs D0-D17 P CK0 PCK7-> CK : Register RODT1 -> ODT1 : DDR2 SDRAMs D18-D35 L CK0 PCK7-> CK : Register L PCK0-PCK6, PCK8, PCK9-> CK : DDR2 SDRAMs D0-D35 OE RESET PCK0-PCK6, PCK8, PCK9-> CK : DDR2 SDRAMs D0-D35 * S0 connects to DCS0, S1 to DCS1 on the first register, S2 connects DCS0, S3 connects DCS1, on the secon register S2 and S3 have required pull up resistors (100K ohms), not indicated here. **A13-15, BA2 have optional pull down resistors (100K ohms), not indicated here. 11 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 8.0 Absolute Maximum DC Ratings Symbol Rating Units Notes Voltage on VDD pin relative to VSS - 1.0 V ~ 2.3 V V 1 VDDQ Voltage on VDDQ pin relative to VSS - 0.5 V ~ 2.3 V V 1 VDDL Voltage on VDDL pin relative to VSS - 0.5 V ~ 2.3 V V 1 Voltage on any pin relative to VSS - 0.5 V ~ 2.3 V V 1 -55 to +100 °C 1, 2 VDD VIN, VOUT TSTG Parameter Storage Temperature Note : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 9.0 AC & DC Operating Conditions 9.1 Recommended DC Operating Conditions (SSTL - 1.8) Symbol Parameter Rating Min. Typ. Max. Units Notes VDD Supply Voltage 1.7 1.8 1.9 V VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 4 VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 4 VREF Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 1,2 Termination Voltage VREF-0.04 VREF VREF+0.04 V 3 VTT Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDL tied together. 12 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 9.2 Operating Temperature Condition Symbol Parameter Rating Units Notes TOPER Operating Temperature 0 to 95 °C 1, 2, 3 Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard. 2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate. 9.3 Input DC Logic Level Symbol Parameter Min. Max. Units VIH(DC) DC input logic high VREF + 0.125 VDDQ + 0.3 V VIL(DC) DC input logic low - 0.3 VREF - 0.125 V Notes 9.4 Input AC Logic Level Symbol Parameter VIH (AC) VIL (AC) DDR2-400, DDR2-533 DDR2-667, DDR2-800 Units Min. Max. Min. Max. AC input logic high VREF + 0.250 - VREF + 0.200 - V AC input logic low - VREF - 0.250 - VREF - 0.200 V 9.5 AC Input Test Conditions Symbol VREF VSWING(MAX) SLEW Condition Value Units Notes 0.5 * VDDQ V 1 Input signal maximum peak to peak swing 1.0 V 1 Input signal minimum slew rate 1.0 V/ns 2, 3 Input reference voltage Note: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions. VDDQ VIH(AC) min VIH(DC) min VSWING(MAX) VREF VIL(DC) max VIL(AC) max delta TF Falling Slew = delta TR VREF - VIL(AC) max delta TF Rising Slew = VSS VIH(AC) min - VREF delta TR < AC Input Test Signal Waveform > 13 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 10.0 IDD Specification Parameters Definition (IDD values are for full operating range of Voltage and Temperature) Symbol Proposed Conditions Units IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD1 Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA IDD2P Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2Q Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA IDD5B Burst auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA Fast PDN Exit MRS(12) = 0mA mA Slow PDN Exit MRS(12) = 1mA mA Normal mA Low Power mA IDD6 Self refresh current; CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for detailed timing conditions 14 of 26 Note mA Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 11.0 Operating Current Table 11.1 M393T5663CZ3 / M393T5663CZA : 2GB(128Mx8 *18) Module Symbol F7(800@CL=6) E6(667@CL=5) IDD0 1260 IDD1 1350 IDD2P 270 270 (TA=0oC, VDD= 1.9V) D5(533@CL=4) CC(400@CL=3) Unit 1170 1125 1080 mA 1260 1215 1170 mA 270 270 mA IDD2Q 810 810 810 720 mA IDD2N 900 810 810 720 mA mA IDD3P-F 810 720 630 630 IDD3P-S 324 324 324 324 mA IDD3N 1035 945 945 855 mA IDD4W 2025 1800 1665 1440 mA IDD4R 2115 1800 1575 1395 mA IDD5B 2115 2025 1980 1890 mA IDD6* 270 270 270 270 mA IDD7 3150 2925 2745 2520 mA Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 11.2 M393T5663CZ3 / M393T5663CZA : 2GB(128Mx8 *18) Module - considering Register and PLL current value (TA=0oC, VDD= 1.9V) Symbol F7(800@CL=6) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Unit IDD0 1950 1760 1615 1470 mA mA IDD1 2120 1920 1765 1610 IDD2P 910 850 790 730 mA IDD2Q 1520 1430 1340 1160 mA IDD2N 1470 1310 1240 1080 mA IDD3P-F 1540 1350 1160 1060 mA IDD3P-S 1054 954 854 754 mA IDD3N 1595 1435 1365 1205 mA IDD4W 2675 2360 2135 1820 mA IDD4R 2905 2480 2145 1855 mA IDD5B 2945 2705 2510 2270 mA IDD6* 270 270 270 270 mA IDD7 4180 3795 3455 3070 mA Notes * IDD6 = DRAM current + standby current of PLL and Register ** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 15 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 11.3 M393T5660CZ3 / M393T5660CZA : 2GB(256Mx4 *18) Module (TA=0oC, VDD= 1.9V) Symbol F7(800@CL=6) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Unit IDD0 1620 1530 1440 1440 mA IDD1 1800 1710 1620 1620 mA IDD2P 270 270 270 270 mA IDD2Q 810 810 810 720 mA IDD2N 900 810 810 720 mA IDD3P-F 810 720 630 630 mA IDD3P-S 324 324 324 324 mA IDD3N 1170 1080 1080 990 mA IDD4W 2880 2430 2160 2070 mA IDD4R 2880 2430 2160 1890 mA IDD5B 3330 3240 3150 3060 mA IDD6* 270 270 270 270 mA IDD7 5400 5040 4680 4320 mA Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 11.4 M393T5660CZ3 / M393T5660CZA : 2GB(256Mx4 *18) Module - considering Register and PLL current value (TA=0oC, VDD= 1.9V) Symbol F7(800@CL=6) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Unit IDD0 2310 2120 1930 1830 mA IDD1 2570 2370 2170 2060 mA mA IDD2P 910 850 790 730 IDD2Q 1520 1430 1340 1160 mA IDD2N 1470 1310 1240 1080 mA IDD3P-F 1540 1350 1160 1060 mA IDD3P-S 1054 954 854 754 mA mA IDD3N 1730 1570 1500 1340 IDD4W 3530 2990 2630 2450 mA IDD4R 3670 3110 2730 2350 mA IDD5B 4160 3920 3680 3440 mA IDD6* 270 270 270 270 mA IDD7 6430 5910 5390 4870 mA Notes * IDD6 = DRAM current + standby current of PLL and Register ** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 16 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 11.5 M393T5160CZ3 / M393T5160CZA / M392T5160CJA : 4GB(256Mx4 *36 / 512Mx4 *18) Module(TA=0oC, VDD= 1.9V) Symbol F7(800@CL=6) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Unit IDD0 2520 2340 2250 2160 mA IDD1 2700 2520 2430 2340 mA IDD2P 540 540 540 540 mA IDD2Q 1620 1620 1620 1440 mA mA IDD2N 1800 1620 1620 1440 IDD3P-F 1620 1440 1260 1260 mA IDD3P-S 648 648 648 648 mA mA IDD3N 2070 1890 1890 1710 IDD4W 3780 3240 2970 2790 mA IDD4R 3780 3240 2970 2610 mA IDD5B 4230 4050 3960 3780 mA IDD6* 540 540 540 540 mA IDD7 6300 5850 5490 5040 mA Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 11.6 M393T5160CZ3 / M393T5160CZA / M392T5160CJA : 4GB(256Mx4 *36 / 512Mx4 *18) Module (TA=0oC, VDD= 1.9V) - considering Register and PLL current value Symbol F7(800@CL=6) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Unit IDD0 3540 3210 2970 2730 mA IDD1 3860 3520 3270 3020 mA IDD2P 1490 1400 1310 1220 mA IDD2Q 2680 2540 2400 2080 mA IDD2N 2600 2320 2220 1940 mA IDD3P-F 2710 2380 2050 1900 mA IDD3P-S 1738 1588 1438 1288 mA IDD3N 2860 2580 2480 2200 mA IDD4W 4770 4090 3680 3360 mA IDD4R 4870 4180 3760 3250 mA IDD5B 5450 5050 4740 4340 mA IDD6* 540 540 540 540 mA IDD7 8010 7300 6680 5970 mA Notes * IDD6 = DRAM current + standby current of PLL and Register ** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 17 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 11.7 M393T1G60CJA : 8GB(512Mx4 *36) Module (TA=0oC, VDD= 1.9V) Symbol E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Unit IDD0 3960 3870 3600 mA IDD1 4140 4050 3780 mA IDD2P 1080 1080 1080 mA IDD2Q 3240 3240 2880 mA IDD2N 3240 3240 2880 mA IDD3P-F 2880 2520 2520 mA IDD3P-S 1296 1296 1296 mA mA IDD3N 3510 3510 3150 IDD4W 4860 4590 4230 mA IDD4R 4860 4590 4050 mA IDD5B 5670 5580 5220 mA IDD6* 1080 1080 1080 mA IDD7 7470 7110 6480 mA Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 11.8 M393T1G60CJA : 8GB(512Mx4 *36) Module - considering Register and PLL current value (TA=0oC, VDD= 1.9V) Symbol E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Unit IDD0 4830 4590 4170 mA mA IDD1 5140 4890 4460 IDD2P 1940 1850 1760 mA IDD2Q 4160 4020 3520 mA mA IDD2N 3940 3840 3380 IDD3P-F 3820 3310 3160 mA IDD3P-S 2236 2086 1936 mA IDD3N 4200 4100 3640 mA IDD4W 5710 5300 4800 mA IDD4R 5800 5380 4690 mA IDD5B 6670 6360 5780 mA IDD6* 1080 1080 1080 mA IDD7 8920 8300 7410 mA Notes * IDD6 = DRAM current + standby current of PLL and Register ** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 18 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 12.0 Input/Output Capacitance (VDD=1.8V, VDDQ=1.8V, TA=25oC) Parameter Min Sym. Part-Number Max Min M393T5663CZ3 M393T5663CZA Max Min Max Min M393T5160CZ3 M393T5160CZA M392T5160CJA M393T5660CZ3 M393T5660CZA Max M393T1G60CJA Input capacitance, CK and CK CCK - 11 - 11 - 11 - 11 Input capacitance, CKE and CS CI1 - 12 - 12 - 12 - 12 Input capacitance, Addr,RAS,CAS,WE CI2 - 12 - 12 - 12 - 12 Input/output capacitance, DQ, DM, DQS, DQS CIO - 10 - 10 - 10 - 10 Units pF * DM is internally loaded to match DQ and DQS identically. 13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 (0 °C < TOPER < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V) 13.1 Refresh Parameters by Device Density Parameter Symbol 256Mb 512Mb 1Gb 2Gb 4Gb Units tRFC 75 105 127.5 195 327.5 ns 0 °C ≤ TCASE ≤ 85°C 7.8 7.8 7.8 7.8 7.8 µs 85 °C < TCASE ≤ 95°C 3.9 3.9 3.9 3.9 3.9 µs Refresh to active/Refresh command time Average periodic refresh interval tREFI 13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin Speed DDR2-800(F7) Bin(CL - tRCD - tRP) Parameter DDR2-667(E6) 6-6-6 min DDR2-533(D5) 5-5-5 max DDR2-400(CC) 4-4-4 min max 3-3-3 Units min max min max tCK, CL=3 - - 5 8 5 8 5 8 ns tCK, CL=4 3.75 8 3.75 8 3.75 8 5 8 ns tCK, CL=5 3 8 3 8 3.75 8 - - ns tCK, CL=6 2.5 8 - - - - - - ns tRCD 15 - 15 - 15 - 15 - ns tRP 15 - 15 - 15 - 15 - ns tRC 60 - 60 - 60 - 55 - ns tRAS 45 70000 45 70000 45 70000 40 70000 ns 19 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 13.3 Timing Parameters by Speed Grade Parameter Symbol DDR2-800 min max DDR2-667 min max DDR2-533 min DDR2-400 max min max Units DQ output access time from CK/CK tAC - 400 400 -450 +450 -500 +500 -600 +600 ps DQS output access time from CK/CK tDQSCK - 350 350 -400 +400 -450 +450 -500 +500 ps CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK half period tHP min(tCL,t CH) x min(tCL, tCH) x min(tCL, tCH) x min(tCL, tCH) x ps Clock cycle time, CL=x tCK 2500 8000 3000 8000 3750 8000 5000 8000 ps DQ and DM input hold time tDH(base) 125 x 175 x 225 x 275 x ps DQ and DM input setup time tDS(base) 50 x 100 x 100 x 150 x ps Control & Address input pulse width for each input tIPW 0.6 x 0.6 x 0.6 x 0.6 x tCK 0.35 x 0.35 x 0.35 x 0.35 x tCK DQ and DM input pulse width for each input tDIPW Data-out high-impedance time from CK/CK tHZ x tAC max x tAC max x tAC max x tAC max ps DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max tAC min tAC max tAC min tAC max ps DQ low-impedance time from CK/CK tLZ(DQ) 2* tAC min tAC max 2*tAC min tAC max 2* tACmin tAC max 2* tACmin tAC max ps DQS-DQ skew for DQS and associated DQ tDQSQ signals x 200 x 240 x 300 x 350 ps DQ hold skew factor tQHS x 300 x 340 x 400 x 450 ps DQ/DQS output hold time from DQS tQH tHP tQHS x tHP tQHS x tHP tQHS x tHP tQHS x ps First DQS latching transition to associated clock edge tDQSS - 0.25 0.25 -0.25 0.25 -0.25 0.25 -0.25 0.25 tCK DQS input high pulse width tDQSH 0.35 x 0.35 x 0.35 x 0.35 x tCK DQS input low pulse width tDQSL 0.35 x 0.35 x 0.35 x 0.35 x tCK DQS falling edge to CK setup time tDSS 0.2 x 0.2 x 0.2 x 0.2 x tCK DQS falling edge hold time from CK tDSH 0.2 x 0.2 x 0.2 x 0.2 x tCK Mode register set command cycle time tMRD Write postamble tWPST Write preamble Address and control input hold time 2 x 2 x 2 x 2 x tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK tWPRE 0.35 x 0.35 x 0.35 x 0.35 x tCK tIH(base) 250 x 275 x 375 x 475 x ps Address and control input setup time tIS(base) 175 x 200 x 250 x 350 x ps Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK Active to active command period for 1KB page size products tRRD 7.5 x 7.5 x 7.5 x 7.5 x ns Active to active command period for 2KB page size products tRRD 10 x 10 x 10 x 10 x ns Four Activate Window for 1KB page size products tFAW 35 37.5 37.5 37.5 ns Four Activate Window for 2KB page size products tFAW 45 50 50 50 ns CAS to CAS command delay tCCD 2 x 2 2 2 tCK Write recovery time tWR 15 x 15 x 15 x 15 x ns WR+tRP x WR+tRP x WR+tRP x WR+tRP x tCK x 7.5 x 10 x ns Auto precharge write recovery + precharge tDAL time Internal write to read command delay tWTR 7.5 7.5 Internal read to precharge command delay tRTP 7.5 7.5 7.5 7.5 ns Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 tRFC + 10 tRFC + 10 ns Exit self refresh to a read command tXSRD 200 x 200 200 200 tCK Exit precharge power down to any nonread command tXP 2 x 2 20 of 26 x 2 x 2 Notes x tCK Rev. 1.4 November 2007 RDIMM Parameter DDR2 SDRAM Symbol Exit active power down to read command tXARD Exit active power down to read command (slow exit, lower power) tXARDS CKE minimum pulse width (high and low pulse width) ODT turn-on delay DDR2-800 DDR2-667 DDR2-533 DDR2-400 min max min max min max min max 2 x 2 x 2 x 2 x 8 - AL 7 - AL 6 - AL 6 - AL tCKE 3 3 3 3 tAOND 2 2 tAC(max) + 0.7 2 2 tAC(min) tAC(max) +0.7 2 2 tAC(min) tAC(max) +1 2 2 tCK tAC(min) tAC(max) +1 ns ns tAC(min) ODT turn-on(Power-Down mode) tAONPD 2tCK + tAC(min)+ tAC(min)+ 2tCK+tAC tAC(min)+ 2tCK+tAC tAC(min)+ 2tCK+tAC tAC(max) 2 2 (max)+1 2 (max)+1 2 (max)+1 +1 ODT turn-off delay tAOFD 2.5 2.5 2.5 tAC(min) tAC(max) + 0.6 2.5 2.5 tAC(min) tAC(max)+ 0.6 2.5 2.5 tCK tAC(min) tAC(max)+ 0.6 ns ns ODT turn-off tAOF tAC(min) ODT turn-off (Power-Down mode) tAOFPD 2.5tCK + 2.5tCK+ 2.5tCK+ tAC(min)+ tAC(min)+ 2.5tCK+tA tAC(min)+ tAC(min)+ tAC(max) tAC(max) tAC(max) 2 2 C(max)+1 2 2 +1 +1 +1 ODT to power down entry latency tANPD 3 3 3 3 ODT power down exit latency tAXPD 8 8 8 8 OCD drive mode output delay tOIT 0 Minimum time clocks remains ON after CKE asynchronously drops LOW tDelay tIS+tCK +tIH 12 0 tIS+tCK +tIH 21 of 26 12 0 tIS+tCK +tIH 12 tCK tCK tAON tAC(max) + 0.6 0 tIS+tCK +tIH Notes tCK ODT turn-on 2.5 Units tCK tCK 12 ns ns Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 14.0 Physical Dimensions : 14.1 128Mbx8/256Mbx4 based 256Mx72 Module (2/1 Ranks) Units : Millimeters - M393T5663CZ3/M393T5663CZA/M393T5660CZ3/M393T5660CZA 133.35 Register 4.00 30.00 PLL 1.0 max 1.27 ± 0.10 A B 63.00 Register 55.00 4.00 4.00 3.00 2.50±0.20 5.00 0.80±0.05 3.80 2.50 1.50±0.10 Detail A 0.20 1.00 4.00 Detail B The used device is 128M x8 / 256M x4 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T1G084QC / K4T1G044QC 22 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 14.2 256Mbx4 based 512Mx72 Module (2 Ranks) Units : Millimeters - M393T5160CZ3 / M393T5160CZA 133.35 4.00 Register PLL 30.00 1.0 max 1.27 ± 0.10 A B 63.00 Register 55.00 4.00 4.00 3.00 2.50±0.20 5.00 0.80±0.05 3.80 2.50 1.50±0.10 Detail A 0.20 1.00 4.00 Detail B The used device is 256M x4 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T1G044QC 23 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 14.3 DDP 512Mbx4 based 512Mx72 Module (2 Ranks) Units : Millimeters - M392T5160CJA 133.35 2x 3.00 MIN 2.20 128.95 PLL Register 2.30 5.175 10.00 17.80 18.30 ± 0.15 4.17 63 55 123 A 1.4 max B 1.27 ± 0.10 Register 18.30 ± 0.15 5.00 4.00 4.00 2.50±0.20 133.35 0.80±0.05 3.80 2.50 0.20 1.00 1.50±0.10 Detail A Detail B The used device is DDP 512M x4 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T2G044QC 24 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 14.4 DDP 512Mbx4 based 1Gx72 Module (4 Ranks) Units : Millimeters - M393T1G60CJA 133.35 4.17 PLL Register 30.00 1.0 max 1.27 ± 0.10 A B 63.00 55.00 Register 4.00 4.00 3.00 2.50±0.20 5.00 0.80±0.05 3.80 2.50 1.50±0.10 Detail A 0.20 1.00 4.00 Detail B The used device is 256M x4 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T1G044QC 25 of 26 Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 15.0 240 Pin DDR2 Registered DIMM Clock Topology 0ns (nominal) PLL DDR2 SDRAM 120 ohms OUT1 CK0 120 ohms IN DDR2 SDRAM CK0 Reg.A 120 ohms C OUTN C Feedback In Feedback Out 120 ohms Reg.B Note: 1. 2. 3. 4. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal). Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible. 26 of 26 Rev. 1.4 November 2007