Cypress CY14B101Q1-LHXI 1 mbit (128k x 8) serial spi nvsram Datasheet

CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
1 Mbit (128K x 8) Serial SPI nvSRAM
Features
■
■
1 Mbit Nonvolatile SRAM
❐ Internally organized as 128K x 8
❐ STORE to QuantumTrap nonvolatile elements initiated automatically on power down (AutoStore) or by user using HSB
pin (Hardware Store) or SPI instruction (Software Store)
❐ RECALL to SRAM initiated on power up (Power Up Recall)
or by SPI Instruction (Software RECALL)
❐ Automatic STORE on power down with a small capacitor
High Reliability
❐ Infinite Read, Write, and RECALLl cycles
❐ 200,000 STORE cycles to QuantumTrap
❐ Data Retention: 20 Years
■
Low Power Consumption
❐ Single 3V +20%, –10% operation
❐ Average VCC current of 10 mA at 40 MHz operation
■
Industry Standard Configurations
❐ Commercial and industrial temperatures
❐ CY14B101Q1 has identical pin configuration to industry standard 8-pin NV Memory
❐ 8-pin DFN and 16-pin SOIC Packages
❐ RoHS compliant
Functional Overview
■
High Speed Serial Peripheral Interface (SPI)
❐ 40 MHz Clock rate
❐ Supports SPI Modes 0 (0,0) and 3 (1,1)
■
Write Protection
❐ Hardware Protection using Write Protect (WP) Pin
❐ Software Protection using Write Disable Instruction
❐ Software Block Protection for 1/4,1/2, or entire Array
The
Cypress
CY14B101Q1/CY14B101Q2/CY14B101Q3
combines a 1 Mbit nonvolatile static RAM with a nonvolatile
element in each memory cell. The memory is organized as 128K
words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most
reliable nonvolatile memory. The SRAM provides infinite read
and write cycles, while the QuantumTrap cell provides highly
reliable nonvolatile storage of data. Data transfers from SRAM to
the nonvolatile elements (STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
Both STORE and RECALL operations can also be triggered by
the user.
Logic Block Diagram
CS
WP
SCK
VCC
Quantum Trap
128K X 8
Instruction decode
Write protect
Control logic
STORE
SRAM ARRAY
HOLD
RECALL
128K X 8
Instruction
register
Address
Decoder
VCAP
Power Control
STORE/RECALL
Control
HSB
D0-D7
A0-A16
SI
Data I/O register
SO
Status register
Cypress Semiconductor Corporation
Document #: 001-50091 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 02, 2009
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CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
Pinouts
Figure 1. Pin Diagram - 8-Pin DFN[1, 3, 2]
CS
SO
WP
GND
1 CY14B101Q1
2
Top View
3
not to scale
4
8
VCC
CS
7
HOLD
SO
6
SCK
5
SI
VCAP
GND
1 CY14B101Q2
2
Top View
3
not to scale
4
8
VCC
7
HOLD
6
SCK
5
SI
Figure 2. Pin Diagram - 16-Pin SOIC
NC
1
16
VCC
NC
2
15
NC
NC
3
14
VCAP
13
SO
12
SI
SCK
CY14B101Q3
NC
4
WP
5
HOLD
6
11
7
10
8
9
NC
GND
Top View
not to scale
CS
HSB
Table 1. Pin Definitions
Pin Name
I/O Type
Description
CS
Input
Chip Select. Activates the device when pulled LOW. Driving this pin high puts the device in low
power standby mode.
SCK
Input
Serial Clock. Runs at speeds up to max 40 MHz. All inputs are latched at the rising edge of this
clock. Outputs are driven at the falling edge of the clock.
SI
Input
Serial Input. Pin for input of all SPI instructions and data.
SO
Output
WP
Input
Serial Output. Pin for output of data through SPI.
Write Protect. Implements hardware write protection in SPI.
HOLD
Input
HOLD Pin. Suspends Serial Operation.
HSB
Input/Output
Hardware STORE Busy: A weak internal pull up keeps this pin pulled high. If not used, this pin is
left as No Connect.
Output: Indicates busy status of nvSRAM when LOW.
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
Power Supply
AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It
must never be connected to GND.
NC
No Connect
No Connect: This pin is not connected to the die.
GND
Power Supply
Ground
VCC
Power Supply
Power Supply (2.7 to 3.6V)
Notes
1. HSB pin is not available in 8 DFN packages.
2. CY14B101Q1 part does not have VCAP pin and does not support AutoStore.
3. CY14B101Q2 part does not have WP pin
Document #: 001-50091 Rev. *B
Page 2 of 22
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PRELIMINARY
CY14B101Q1
CY14B101Q2
CY14B101Q3
Device Operation
SRAM Write
CY14B101Q1/CY14B101Q2/CY14B101Q3 is 1 Mbit nvSRAM
memory with a nonvolatile element in each memory cell. All the
reads and writes to nvSRAM happen to the SRAM which gives
nvSRAM the unique capability to handle infinite writes to the
memory. The data in SRAM is secured by a STORE sequence
which transfers the data in parallel to the nonvolatile Quantum
Trap cells. A small capacitor (VCAP) is used to AutoStore the
SRAM data in nonvolatile cells when power goes down providing
power down data security. The Quantum Trap nonvolatile
elements built in the reliable SONOS technology make nvSRAM
the ideal choice for secure data storage.
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
enables user to perform infinite write operations. A Write cycle is
performed through the SPI WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, three bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
The 1 Mbit memory array is organized as 128K words x 8 bits.
The memory can be accessed through a standard SPI interface
that enables very high clock speeds upto 40 MHz with zero cycle
delay read and write cycles. This device supports SPI modes 0
and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as SPI slave.
The device is enabled using the Chip Select pin (CS) and
accessed through Serial Input (SI), Serial Output (SO), and
Serial Clock (SCK) pins.
This device provides the feature for hardware and software write
protection through WP pin and WRDI instruction respectively
along with mechanisms for block write protection (1/4, 1/2, or full
array) using BP0 and BP1 pins in the status register. Further, the
HOLD pin can be used to suspend any serial communication
without resetting the serial sequence.
CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard
SPI opcodes for memory access. In addition to the general SPI
instructions for read and write, it provides four special
instructions which enable access to four nvSRAM specific
functions: STORE, RECALL, AutoStore Disable (ASDISB), and
AutoStore Enable (ASENB).
The major benefit of nvSRAM SPI over serial EEPROMs is that
all reads and writes to nvSRAM are performed at the speed of
SPI bus with zero delay. Therefore, no wait time is required after
any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware STORE Busy (HSB) pin and also reflected on
the RDY bit of the Status Register.
The Device is available in three different pin configurations that
enable the user to choose a part which fits in best in their application. The feature summary is given in Table 2.
Table 2. Feature Summary
Feature
CY14B101Q1
CY14B101Q2
CY14B101Q3
WP
Yes
No
Yes
VCAP
No
Yes
Yes
HSB
No
No
Yes
AutoStore
No
Yes
Yes
Power Up
RECALL
Yes
Yes
Yes
Hardware
STORE
No
No
Yes
Software
STORE
Yes
Yes
Yes
Document #: 001-50091 Rev. *B
The device allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached, the address rolls over to 0x0000 and the
device continues to write.
The SPI write cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.
SRAM Read
A read cycle is performed at the SPI bus speed and the data is
read out with zero cycle delay after the READ instruction is
performed. The READ instruction is issued through the SI pin of
the nvSRAM and consists of the READ opcode and 3 bytes of
address. The data is read out on the SO pin.
This device allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x0000 and the device continues to read.
The SPI read cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.
STORE Operation
STORE operation transfers the data from the SRAM to the
nonvolatile Quantum Trap cells. The device stores data to the
nonvolatile cells using one of three STORE operations:
AutoStore, activated on device power down; Software STORE,
activated by a STORE instruction in the SPI; Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated, further input and output are disabled until the cycle is
completed.
The HSB signal or the RDY bit in the Status register can be
monitored by the system to detect if a STORE cycle is in
progress. The busy status of nvSRAM is indicated by HSB being
pulled LOW or RDY bit being set to ‘1’. To avoid unnecessary
nonvolatile STOREs, AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken
place since the most recent STORE or RECALL cycle. Software
initiated STORE cycles are performed regardless of whether a
write operation has taken place.
Page 3 of 22
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CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap during
power down. This Store mechanism is implemented using a
capacitor (VCAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from VCC to
charge the capacitor connected to the VCAP pin. When the
voltage on the VCC pin drops below VSWITCH during power down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the VCAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since last RECALL.
Note If a capacitor is not connected to VCAP pin, Autostore must
be disabled by issuing the AutoStore Disable instruction
specified in AutoStore Disable (ASDISB) on page 12. If
AutoStore is enabled without a capacitor on VCAP pin, the device
will attempt an AutoStore operation without sufficient charge to
complete the Store. This may corrupt the data stored in nvSRAM
and Status register. In such case, WRSR instruction needs to be
issued to update the non-volatile bits BP0, BP1, WPEN to
resume normal functionality.
The HSB pin also acts as an open drain driver that is internally
driven LOW to indicate a busy condition, when a STORE cycle
(initiated by any means) or Power up RECALL is in progress.
Upon completion of the STORE operation, the nvSRAM remains
disabled until the HSB pin returns HIGH. Leave the HSB pin
unconnected if not used.
Note CY14B101Q1/CY14B101Q2 do not have HSB pin. RDY bit
of the SPI status register may be probed to determine the Ready
or Busy status of nvSRAM
Figure 3. AutoStore Mode
Vcc
0.1uF
10kOhm
AutoStore Operation
Vcc
CS
VSS
During power down, the memory accesses are inhibited after the
voltage on VCC pin drops below VSWITCH. To avoid inadvertent
writes, it must be ensured that CS is not left floating prior to this
event. Therefore, during power down the device must be
deselected and CS must be allowed to follow VCC.
Figure 3 shows the proper connection of the storage capacitor
(VCAP) for AutoStore operation. Refer to DC Electrical Characteristics on page 13 for the size of the VCAP.
Note CY14B101Q1 does not support AutoStore operation. The
user must perform Software STORE operation by using the SPI
STORE instruction to secure the data.
Software Store Operation
Software STORE enables the user to trigger a STORE operation
through a special SPI instruction. This operation is initiated
irrespective of whether a write has been performed since last nv
operation.
A STORE cycle takes tSTORE to complete, during which all the
memory accesses to nvSRAM are inhibited. The RDY bit of the
Status register or the HSB pin may be polled to find the Ready
or Busy status of the nvSRAM. After the tSTORE cycle time is
completed, the SRAM is activated again for read and write
operations.
Hardware STORE and HSB pin Operation
The HSB pin in CY14B101Q3 is used to control and
acknowledge STORE operations. If no STORE or RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, nvSRAM conditionally
initiates a STORE operation after tDELAY duration. An actual
STORE cycle starts only if a write to the SRAM has been
performed since the last STORE or RECALL cycle. Reads and
Writes to the memory are inhibited for tSTORE duration or as long
as HSB pin is LOW.
Document #: 001-50091 Rev. *B
VCAP
VCAP
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
Quantum Trap elements to the SRAM. A RECALL may be
initiated in two ways: Hardware RECALL, initiated on power up;
and Software RECALL, initiated by a SPI RECALL instruction.
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared. Next, the nonvolatile information is transferred
into the SRAM cells. All memory accesses are inhibited while a
RECALL cycle is in progress. The RECALL operation does not
alter the data in the nonvolatile elements.
Hardware Recall (Power Up)
During power up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power Up Recall cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin can be
used to detect the Ready status of the device. user
Software RECALL
Software RECALL enables the user to initiate a RECALL
operation to restore the content of nonvolatile memory on to the
SRAM. A Software RECALL is issued by using the SPI
instruction for RECALL.
A Software RECALL takes tRECALL to complete during which all
memory accesses to nvSRAM are inhibited. The controller must
provide sufficient delay for the RECALL operation to complete
before issuing any memory access instructions.
Page 4 of 22
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PRELIMINARY
CY14B101Q1
CY14B101Q2
CY14B101Q3
Disabling and Enabling AutoStore
Chip Select (CS)
If the application does not require the AutoStore feature, it can
be disabled by using the ASDISB instruction. If this is done, the
nvSRAM does not perform a STORE operation at power down.
For selecting any slave device, the master needs to pull down
the corresponding CS pin. Any instruction can be issued to a
slave device only while the CS pin is LOW. When the device is
not selected, data through the SI pin is ignored and the serial
output pin (SO) remains in a high impedance state.
AutoStore can be re-enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if the user
needs this setting to survive power cycle, a STORE operation
must be performed following Autostore Disable or Enable
operation.
Note A new instruction must begin with the falling edge of Chip
Select (CS). Therefore, only one opcode can be issued for each
active Chip Select cycle.
Note CY14B101Q2/CY14B101Q3 has AutoStore Enabled from
the factory. In CY14B101Q1, VCAP pin is not present and
AutoStore option is not available. The Autostore Enable and
Disable instructions to CY14B101Q1 are ignored.
Serial Clock (SCK)
Note If AutoStore is disabled and VCAP is not required, leave it
open. VCAP pin must never be connected to GND. Power Up
Recall operation cannot be disabled in any case.
CY14B101Q1/CY14B101Q2/CY14B101Q3 enables SPI modes
0 and 3 for data communication. In both these modes, the inputs
are latched by the slave device on the rising edge of SCK and
outputs are issued on the falling edge. Therefore, the first rising
edge of SCK signifies the arrival of first bit (MSB) of SPI
instruction on the SI pin. Further, all data inputs and outputs are
synchronized with SCK.
Serial Peripheral Interface
SPI Overview
The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO) and Serial Clock (SCK) pins.
CY14B101Q1/CY14B101Q2/CY14B101Q3 provides serial
access to nvSRAM through SPI interface. The SPI bus on this
device can run at speeds up to 40 MHz
The SPI is a synchronous serial interface which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on SPI bus is activated using a chip select
pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both these modes, data is clocked into nvSRAM on rising edge
of SCK starting from the first rising edge after CS goes active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms used in SPI protocol are given below:
SPI Master
The SPI Master device controls the operations on a SPI bus. An
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and master
may select any of the slave devices using the Chip Select pin.
All the operations must be initiated by the master activating a
slave device by pulling the CS pin of the slave LOW. The master
also generates the Serial Clock (SCK) and all the data transmission on SI and SO lines are synchronized with this clock.
SPI Slave
SPI slave device is activated by the master through the Chip
Select line. A slave device gets the Serial Clock (SCK) as an
input from the SPI master and all the communication is synchronized with this clock. SPI slave never initiates a communication
on the SPI bus and acts on the instruction from the master.
CY14B101Q1/CY14B101Q2/CY14B101Q3 operates as a SPI
slave and may share the SPI bus with other SPI slave devices.
Document #: 001-50091 Rev. *B
Serial clock is generated by the SPI master and the communication is synchronized with this clock after CS goes LOW.
Data Transmission - SI and SO
SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as MOSI (Master Out
Slave In) and SO is referred to as MISO (Master In Slave Out).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
The 1 Mbit serial nvSRAM requires a 3-byte address for any read
or write operation. However, since the actual address is only 17
bits, it implies that the first seven bits which are fed in are ignored
by the device. Although these seven bits are ‘don’t care’,
Cypress recommends that these bits are treated as 0s to enable
seamless transition to higher memory densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard
opcodes for memory accesses. In addition to the memory
accesses, it provides additional opcodes for the nvSRAM
specific functions: STORE, RECALL, AutoStore Enable, and
AutoStore Disable. Refer to Table 3 on page 7 for details.
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin till the next
falling edge of CS and the SO pin remains tristated.
Status Register
CY14B101Q1/CY14B101Q2/CY14B101Q3 has an 8-bit status
register. The bits in the status register are used to configure the
SPI bus. These bits are described in Table 5 on page 8.
Page 5 of 22
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CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
Figure 4. System Configuration Using SPI nvSRAM
SCK
M OSI
M IS O
SCK
SI
SO
SCK
SI
SO
u C o n tro lle r
C Y14B 101Q x
CS
C Y14B 101Q x
HO LD
CS
HO LD
CS1
HO LD 1
CS2
HO LD 2
SPI Modes
CY14B101Q1/CY14B101Q2/CY14B101Q3 may be driven by a
microcontroller with its SPI peripheral running in either of the
following two modes:
The two SPI modes are shown in Figure 5 and Figure 6. The
status of clock when the bus master is in Standby mode and not
transferring data is:
■
SCK remains at 0 for Mode 0
SCK remains at 1 for Mode 3
■
SPI Mode 0 (CPOL=0, CPHA=0)
■
■
SPI Mode 3 (CPOL=1, CPHA=1)
CPOL and CPHA bits must be set in the SPI controller for either
Mode 0 or Mode 3. The device detects the SPI mode from the
status of SCK pin when the device is selected by bringing the CS
pin LOW. If SCK pin is LOW when device is selected, SPI Mode
0 is assumed and if SCK pin is HIGH, it works in SPI Mode 3.
For both these modes, input data is latched-in on the rising edge
of Serial Clock (SCK) starting from the first rising edge after CS
goes active. If the clock starts from a HIGH state (in mode 3), the
first rising edge, after the clock toggles, is considered. The output
data is available on the falling edge of Serial Clock (SCK).
Figure 6. SPI Mode 3
Figure 5. SPI Mode 0
CS
CS
0
1
2
3
4
5
6
1
2
3
4
5
6
7
SCK
SCK
SI
0
7
7
6
5
4
MSB
Document #: 001-50091 Rev. *B
3
2
1
0
LSB
SI
7
MSB
6
5
4
3
2
1
0
LSB
Page 6 of 22
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CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
SPI Operating Features
Active Power and Standby Power Modes
Power Up
When Chip Select (CS) is LOW, the device is selected, and is in
the Active Power mode. The device consumes ICC current, as
specified in DC Electrical Characteristics on page 13. When Chip
Select (CS) is HIGH, the device is deselected and the device
goes into the Standby Power mode if a STORE or RECALL cycle
is not in progress. If a STORE or RECALL cycle is in progress,
device goes into the Standby Power Mode after the STORE or
RECALL cycle is completed. In the Standby Power mode, the
current drawn by the device drops to ISB.
Power up is defined as the condition when the power supply is
turned on and VCC crosses Vswitch voltage. During this time, the
Chip Select (CS) must be allowed to follow the VCC voltage.
Therefore, CS must be connected to VCC through a suitable pull
up resistor. As a built-in safety feature, Chip Select (CS) is both
edge sensitive and level sensitive. After power up, the device is
not selected until a falling edge is detected on Chip Select (CS).
This ensures that Chip Select (CS) must have been HIGH,
before going Low to start the first operation.
As described earlier, nvSRAM performs a Power Up Recall
operation after power up and therefore, all memory accesses are
disabled for tRECALL duration after power up. The HSB pin can
be probed to check the ready or busy status of nvSRAM after
power up.
Power On Reset
A Power On Reset (POR) circuit is included to prevent
inadvertent writes. At power up, the device does not respond to
any instruction until the VCC reaches the Power On Reset
threshold voltage (VSWITCH). After VCC transitions the POR
threshold, the device is internally reset and performs an Power
Up Recall operation. The device is in the following state after
POR:
■
Deselected (after Power up, a falling edge is required on Chip
Select (CS) before any instructions are started).
■
Standby Power mode
■
Not in the Hold Condition
Status register state:
❐ Write Enable (WEN) bit is reset to 0.
❐ WPEN, BP1, BP0 unchanged from previous power down
The WPEN, BP1, and BP0 bits of the Status Register are nonvolatile bits and remain unchanged from the previous power down.
SPI Functional Description
The CY14B101Q1/CY14B101Q2/CY14B101Q3 uses an 8-bit
instruction register. Instructions and their opcodes are listed in
Table 3. All instructions, addresses, and data are transferred with
the MSB first and start with a HIGH to LOW CS transition. There
are, in all, 12 SPI instructions which provide access to most of
the functions in nvSRAM. Further, the WP and HOLD pins
provide additional functionality driven through hardware.
Table 3. Instruction Set
Instruction
Category
Status Register
Control Instructions
Instruction
Name
Opcode
Operation
WREN
0000 0110
Set Write Enable
Latch
WRDI
0000 0100
Reset Write
Enable Latch
RDSR
0000 0101
Read Status
Register
WRSR
0000 0001
Write Status
Register
READ
0000 0011
Read Data From
Memory Array
WRITE
0000 0010
Write Data To
Memory Array
STORE
0011 1100 Software STORE
RECALL
0110 0000
■
Before selecting and issuing instructions to the memory, a valid
and stable VCC voltage must be applied. This voltage must
remain valid until the end of the transmission of the instruction.
Power Down
At power down (continuous decay of VCC), when VCC drops from
the normal operating voltage and below the VSWITCH threshold
voltage, the device stops responding to any instruction sent to it.
If a write cycle is in progress during power down, it is allowed
tDELAY time to complete after Vcc transitions below VSWITCH,
after which all memory accesses are inhibited and a conditional
AutoStore operation is performed (AutoStore is not performed if
no writes have happened since last RECALL cycle). This feature
prevents inadvertent writes to nvSRAM from happening during
power down.
However, to completely avoid the possibility of inadvertent writes
during power down, ensure that the device is deselected and is
in Standby Power Mode, and the Chip Select (CS) follows the
voltage applied on VCC.
Document #: 001-50091 Rev. *B
SRAM
Read/Write
Instructions
Special NV
Instructions
Reserved
Software
RECALL
ASENB
0101 1001 AutoStore Enable
ASDISB
0001 1001 AutoStore Disable
- Reserved - 0001 1110
Reserved for
Internal use
The SPI instructions are divided based on their functionality in
the following types:
❐ Status Register Access: WRSR and RDSR instructions
❐ Write Protection Functions: WREN and WRDI instructions
along with WP pin and WEN, BP0, and BP1 bits
❐ SRAM memory Access: READ and WRITE instructions
❐ nvSRAM special instructions: STORE, RECALL, ASENB,
and ASDISB
Page 7 of 22
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CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
Status Register
The status register bits are listed in Table 3. The status register consists of Ready bit (RDY) and data protection bits BP1, BP0, WEN,
and WPEN. The RDY bit can be polled to check the Ready or Busy status while a nvSRAM STORE cycle is in progress. The status
register can be modified by WRSR instruction and read by RDSR instruction. However, only WPEN, BP1, and BP0 bits of the Status
Register can be modified by using WRSR instruction. WRSR instruction has no effect on WEN and RDY bits. The default value shipped
from the factory for BP1, BP2 and WPEN bits is ‘0’.
Table 4. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN (0)
X
X
X
BP1 (0)
BP0 (0)
WEN
RDY
Table 5. Status Register Bit Definition
Bit
Definition
Description
Bit 0 (RDY)
Ready
Read Only bit indicates the ready status of device to perform a memory access. This bit is
set to “1” by the device while a STORE or Software RECALL cycle is in progress.
Bit 1 (WEN)
Write Enable
WEN indicates if the device is write-enabled. Setting WEN = '1' enables writes and setting
WEN = '0' disables all write operations
Bit 2 (BP0)
Block Protect bit ‘0’
Used for block protection. For details see Table 6 on page 9.
Bit 3 (BP1)
Block Protect bit ‘1’
Used for block protection. For details see Table 6 on page 9.
Bit 7 (WPEN) Write Protect Enable bit Used for enabling the function of Write Protect Pin (WP). For details see Table 7 on page 10.
Read Status Register (RDSR) Instruction
WRSR instruction is a write instruction and needs writes to be
enabled (WEN bit set to ‘1’) using the WREN instruction before
it is issued. The instruction is issued after the falling edge of CS
using the opcode for WRSR followed by 8 bits of data to be
stored in the Status Register. Since, only bits 2, 3, and 7 can be
modified by WRSR instruction, it is recommended to leave the
other bits as ‘0’ while writing to the Status Register
The Read Status Register instruction provides access to the
status register. This instruction is used to probe the Write Enable
Status of the device or the Ready status of the device. RDY bit
is set by the device to 1 whenever a STORE cycle is in progress.
The Block Protection and WPEN bits indicate the extent of
protection employed.
Note In CY14B101Q1/CY14B101Q2/CY14B101Q3, the values
written to Status Register are saved to nonvolatile memory only
after a STORE operation. If AutoStore is disabled (or while using
CY14B101Q1), any modifications to the Status Register must be
secured by using a Software STORE operation
This instruction is issued after the falling edge of CS using the
opcode for RDSR.
Write Status Register (WRSR) Instruction
The WRSR instruction enables the user to write to the Status
register. However, this instruction cannot be used to modify bit 0
and bit 1 (WEN and RDY). The BP0 and BP1 bits can be used
to select one of four levels of block protection. Further, WPEN bit
can be set to ‘1’ to enable the use of Write Protect (WP) pin.
Note CY14B101Q2 does not have WP pin. Any modification to
bit 7 of the Status register has no effect on the functionality of
CY14B101Q2.
Figure 7. Read Status Register (RDSR) Instruction Timing
CS
0
1
2
3
4
5
6
7
0
1
0
MSB
1
2
3
4
5
6
7
SCK
SI
SO
0
0
0
0
HI-Z
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Document #: 001-50091 Rev. *B
LSB
Data
LSB
Page 8 of 22
[+] Feedback
CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
Figure 8. Write Status Register (WRSR) Instruction Timing
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Data in
Opcode
SI
0
0
0
0
0
0
0
1 D7 0
0
0 D3 D2 0
MSB
0
LSB
HI-Z
SO
Write Protection and Block Protection
Write Disable (WRDI) Instruction
CY14B101Q1/CY14B101Q2/CY14B101Q3 provides features
for both software and hardware write protection using WRDI
instruction and WP. Additionally, this device also provides block
protection mechanism through BP0 and BP1 pins of the Status
Register.
Write Disable instruction disables the write by clearing the WEN
bit to ‘0’ in order to protect the device against inadvertent writes.
This instruction is issued following falling edge of CS followed by
opcode for WRDI instruction. The WEN bit is cleared on the
rising edge of CS following a WRDI instruction.
Figure 10. WRDI Instruction
The write enable and disable status of the device is indicated by
WEN bit of the status register. The write instructions (WRSR and
WRITE) and nvSRAM special instruction (STORE, RECALL,
ASENB, and ASDISB) need the write to be enabled (WEN bit =
1) before they can be issued.
Write Enable (WREN) Instruction
On power up, the device is always in the write disable state. The
following WRITE, WRSR, or nvSRAM special instruction must
therefore be preceded by a Write Enable instruction. If the device
is not write enabled (WEN = ‘0’), it ignores the write instructions
and returns to the standby state when CS is brought HIGH. A
new CS falling edge is required to re-initiate serial communication. The instruction is issued following the falling edge of CS.
When this instruction is used, the WEN bit of status register is
set to ‘1’. WEN bit defaults to ‘0’ on power up.
Note After completion of a write instruction (WRSR or WRITE)
or nvSRAM special instruction (STORE, RECALL, ASENB, and
ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to
provide protection from any inadvertent writes. Therefore,
WREN instruction needs to be used before a new write
instruction is issued.
Figure 9. WREN Instruction
CS
1
2
3
4
5
6
0
0
0
0
0
Hi-Z
Document #: 001-50091 Rev. *B
1
1
0
1
2
3
4
5
6
7
SCK
0
SI
0
0
0
0
1
0
0
Hi-Z
SO
Block Protection
Block protection is provided using the BP0 and BP1 pins of the
Status register. These bits can be set using WRSR instruction
and probed using the RDSR instruction. The nvSRAM is divided
into four array segments. One-quarter, one-half, or all of the
memory segments can be protected. Any data within the
protected segment is read only. Table 6 shows the function of
Block Protect bits.
Table 6. Block Write Protect Bits
7
SCK
SO
0
Level
0
SI
CS
Status Register
Bits
Array Addresses Protected
BP1
BP0
0
0
0
None
1 (1/4)
0
1
0x18000-0x1FFFF
2 (1/2)
1
0
0x10000-0x1FFFF
3 (All)
1
1
0x00000-0x1FFFF
Page 9 of 22
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CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
Write Protect (WP) Pin
followed for a read operation: After the CS line is pulled LOW to
select a device, the read opcode is transmitted through the SI
line followed by three bytes of address. The Most Significant
address byte contains A16 in bit 0 and other bits as ‘don’t cares’.
Address bits A15 to A0 are sent in the following two address
bytes. After the last address bit is transmitted on the SI pin, the
data (D7-D0) at the specific address is shifted out on the SO line
on the falling edge of SCK. Any other data on SI line after the last
address bit is ignored.
The write protect pin (WP) is used to provide hardware write
protection. WP pin enables all normal read and write operations
when held HIGH. When the WP pin is brought LOW and WPEN
bit is “1”, all write operations to the status register are inhibited.
The hardware write protection function is blocked when the
WPEN bit is “0”. This enables the user to install the device in a
system with the WP pin tied to ground, and still write to the status
register.
CY14B101Q1/CY14B101Q2/CY14B101Q3 allows reads to be
performed in bursts through SPI which can be used to read
consecutive addresses without issuing a new READ instruction.
If only one byte is to be read, the CS line must be driven HIGH
after one byte of data comes out. However, the read sequence
may be continued by holding the CS line LOW and the address
is automatically incremented and data continues to shift out on
SO pin. When the last data memory address (0x1FFFF) is
reached, the address rolls over to 0x0000 and the device
continues to read.
WP pin can be used along with WPEN and Block Protect bits
(BP1 and BP0) of the status register to inhibit writes to memory.
When WP pin is LOW and WPEN is set to “1”, any modifications
to status register are disabled. Therefore, the memory is
protected by setting the BP0 and BP1 bits and the WP pin inhibits
any modification of the status register bits, providing hardware
write protection.
Note WP going LOW when CS is still LOW has no effect on any
of the ongoing write operations to the status register.
Note CY14B101Q2 does not have WP pin and therefore does
not provide hardware write protection.
Write Sequence (WRITE)
The write operations on this device are performed through the
Serial Input (SI) pin. To perform a write operation, if the device is
write disabled, then the device must first be write enabled
through the WREN instruction. When the writes are enabled
(WEN = ‘1’), WRITE instruction is issued after the falling edge of
CS. A WRITE instruction constitutes transmitting the WRITE
opcode on SI line followed by 3 bytes address sequence and the
data (D7-D0) which is to be written. The Most Significant address
byte contains A16 in bit 0 with other bits being ‘don’t cares’.
Address bits A15 to A0 are sent in the following two address
bytes.
Table 7 summarizes all the protection features of this device
Table 7. Write Protection Operation
Unprotected
WEN Protected
Blocks
Blocks
Status
Register
WPEN
WP
X
X
0
Protected
Protected
0
X
1
Protected
Writable
Writable
1
LOW
1
Protected
Writable
Protected
1
HIGH
1
Protected
Writable
Writable
Protected
CY14B101Q1/CY14B101Q2/CY14B101Q3 enables writes to be
performed in bursts through SPI which can be used to write
consecutive addresses without issuing a new WRITE instruction.
If only one byte is to be written, the CS line must be driven HIGH
after the D0 (LSB of data) is transmitted. However, if more bytes
are to be written, CS line must be held LOW and address is
incremented automatically. The following bytes on the SI line are
treated as data bytes and written in the successive addresses.
When the last data memory address (0x1FFFF) is reached, the
address rolls over to 0x0000 and the device continues to write.
The WEN bit is reset to “0” on completion of a WRITE sequence.
Memory Access
All memory accesses are done using the READ and WRITE
instructions. These instructions cannot be used while a STORE
or RECALL cycle is in progress. A STORE cycle in progress is
indicated by the RDY bit of the status register and the HSB pin.
Read Sequence (READ)
The read operations on this device are performed by giving the
instruction on Serial Input pin (SI) and reading the output on
Serial Output (SO) pin. The following sequence needs to be
Figure 11. Read Instruction Timing
CS
1
2
3
4
5
6
7
0
1
2
3
4
5
SCK
Op-Code
SI
0
0
0
0
0
SO
Document #: 001-50091 Rev. *B
0
6
7
~
~ ~
~
0
20 21 22 23 0
1
2
3
4
5
6
7
17-bit Address
1
1
0 0
MSB
0
0
0
0
0 A16
A3 A2 A1 A0
LSB
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
Data
Page 10 of 22
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CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
Figure 12. Burst Mode Read Instruction Timing
CS
2
3
4
5
6
1
0
7
2
3
4
5
6
7
Op-Code
0
0
0
0
1
2
3
4
5
6
7
0
0
7
1
2
3
4
5
6
7
17-bit Address
0
1
0
1
0
0
0
0
0
0
~
~
SI
20 21 22 23 0
~
~
1
~
~
0
SCK
A16
0
MSB
A3 A2 A1 A0
LSB
Data Byte N
SO
~
~
Data Byte 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
MSB
LSB
Figure 13. Write Instruction Timing
CS
1
2
3
4
5
0
7
6
1
2
3
4
5
6
7
~
~ ~
~
0
SCK
Op-Code
SI
0
0
0
0
0
20 21
22 23
0
1
2
3
4
5
6
7
17-bit Address
0
1
0
0
0
0
0
0
0
A16
0
MSB
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
LSB MSB
LSB
Data
HI-Z
SO
Figure 14. Burst Mode Write Instruction Timing
CS
4
5
6
7
0
1
2
3
4
5
6
Op-Code
SI
0
0
0
0
0
7
20 21 22 23 0
1
2
3
4
5
1
0
0
0
MSB
0
0
0
0
0
A16
0
7
0
1
2
3
4
5
6
7
Data Byte N
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
SO
nvSRAM Special Instructions
CY14B101Q1/CY14B101Q2/CY14B101Q3
provides
four
special instructions which enables access to four nvSRAM
specific functions: STORE, RECALL, ASDISB, and ASENB.
Table 8 lists these instructions.
Software STORE
When a STORE instruction is executed, nvSRAM performs a
Software STORE operation. The STORE operation is issued
irrespective of whether a write has taken place since last STORE
or RECALL operation.
Document #: 001-50091 Rev. *B
7
Data Byte 1
17-bit Address
0
6
~
~
3
~
~
2
~
~
1
~
~
0
SCK
LSB MSB
LSB
HI-Z
Table 8. nvSRAM Special Instructions
Function Name
STORE
RECALL
ASENB
ASDISB
Opcode
0011 1100
0110 0000
0101 1001
0001 1001
Operation
Software STORE
Software RECALL
AutoStore Enable
AutoStore Disable
To issue this instruction, the device must be write enabled (WEN
bit = ‘1’). The instruction is performed by transmitting the STORE
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the STORE
instruction.
Page 11 of 22
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CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
AutoStore Enable (ASENB)
Figure 15. Software STORE Operation
The AutoStore Enable instruction enables the AutoStore on
CY14B101Q1. This setting is not nonvolatile and needs to be
followed by a STORE sequence to survive the power cycle.
CS
0
1
2
3
4
5
6
7
To issue this instruction, the device must be write enabled (WEN
= ‘1’). The instruction is performed by transmitting the ASENB
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the ASENB
instruction.
SCK
0
SI
0
1
1
1
1
0
0
Hi-Z
SO
Note If ASDISB and ASENB instructions are executed in
CY14B101Q1, the device is busy for the duration of software
sequence processing time (tSS). However, ASDISB and ASENB
instructions have no effect on CY14B101Q1 as AutoStore is
internally disabled.
Software RECALL
When a RECALL instruction is executed, nvSRAM performs a
Software RECALL operation. To issue this instruction, the device
must be write enabled (WEN = ‘1’).
The instruction is performed by transmitting the RECALL opcode
on the SI pin following the falling edge of CS. The WEN bit is
cleared on the positive edge of CS following the RECALL
instruction.
Figure 16. Software RECALL Operation
Figure 18. AutoStore Enable Operation
CS
0
1
SI
0
1
CS
0
1
2
3
4
5
6
3
4
5
6
7
0
1
1
0
0
1
Hi-Z
SO
7
2
SCK
SCK
1
1
0
0
0
0
HOLD Pin Operation
0
Hi-Z
SO
AutoStore Disable (ASDISB)
AutoStore is enabled by default in CY14B101Q2/CY14B101Q3.
The ASDISB instruction disables the AutoStore. This setting is
not nonvolatile and needs to be followed by a STORE sequence
to survive the power cycle.
To issue this instruction, the device must be write enabled (WEN
= ‘1’). The instruction is performed by transmitting the ASDISB
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the ASDISB
instruction.
Figure 17. AutoStore Disable Operation
The HOLD pin is used to pause the serial communication. When
the device is selected and a serial sequence is underway, HOLD
is used to pause the serial communication with the master device
without resetting the ongoing serial sequence. To pause, the
HOLD pin must be brought LOW when the SCK pin is LOW. To
resume serial communication, the HOLD pin must be brought
HIGH when the SCK pin is LOW (SCK may toggle during HOLD).
While the device serial communication is paused, inputs to the
SI pin are ignored and the SO pin is in the high impedance state.
This pin can be used by the master with the CS pin to pause the
serial communication by bringing the pin HOLD LOW and
deselecting an SPI slave to establish communication with
another slave device, without the serial communication being
reset. The communication may be resumed at a later point by
selecting the device and setting the HOLD pin HIGH.
Figure 19. HOLD Operation
CS
CS
0
1
2
3
4
5
6
7
SCK
~
~
~ ~
0
SI
SCK
SI
SO
0
0
0
1
1
0
0
1
HOLD
SO
Hi-Z
Document #: 001-50091 Rev. *B
Page 12 of 22
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CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Storage Temperature ................................. –65°C to +150°C
Surface Mount Lead Soldering
Temperature (3 Seconds) .......................................... +260°C
Maximum Accumulated Storage Time
At 150°C Ambient Temperature................... ..... 1000h
At 85°C Ambient Temperature..................... 20 Years
Ambient Temperature with
Power Applied ............................................ –55°C to +150°C
Supply Voltage on VCC Relative to GND ........–0.5V to +4.1V
DC Voltage Applied to Outputs
in High-Z State....................................... –0.5V to VCC + 0.5V
Input Voltage.......................................... –0.5V to VCC + 0.5V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V
DC Output Current (1 output at a time, 1s duration).....15 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch up Current.................................................... > 200 mA
Table 9. Operating Range
Range
Ambient Temperature
VCC
0°C to +70°C
2.7V to 3.6V
Commercial
Industrial
–40°C to +85°C
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V)
Parameter
Description
Test Conditions
Min
Typ[4]
Max
Unit
2.7
3.0
3.6
V
10
mA
VCC
Power Supply Voltage
ICC1
Average Vcc Current
ICC2
Average VCC Current All Inputs Don’t Care, VCC = Max.
during STORE
Average current for duration tSTORE
10
mA
ICC4
Average VCAP Current All Inputs Don’t Care, VCC = Max.
during AutoStore
Average current for duration tSTORE
Cycle
5
mA
ISB
VCC Standby Current CS > (VCC – 0.2V). VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
5
mA
IIX[5]
Input Leakage Current VCC = Max, VSS < VIN < VCC
(except HSB)
–1
+1
µA
Input Leakage Current VCC = Max, VSS < VIN < VCC
(for HSB)
–100
+1
µA
–1
+1
µA
At fSCK = 40 MHz.
Values obtained without output loads (IOUT = 0 mA)
IOZ
Off State Output
Leakage Current
VCC = Max, VSS < VOUT < VCC
VIH
Input HIGH Voltage
2.0
VCC + 0.5
V
VIL
Input LOW Voltage
VSS – 0.5
0.8
V
0.4
V
180
µF
VOH
Output HIGH Voltage IOUT = –2 mA
VOL
Output LOW Voltage
IOUT = 4 mA
VCAP
Storage Capacitor
Between VCAP pin and VSS, 5V Rated
2.4
61
V
68
Notes
4. Typical values are at 25°C, VCC= VCC (Typ) . Not 100% tested.
5. The HSB pin has IOUT = -2 uA for VOH of 2.4V when both active high and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
Document #: 001-50091 Rev. *B
Page 13 of 22
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CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
Data Retention and Endurance
Parameter
Description
Min
Unit
DATAR
Data Retention
20
Years
NVC
Nonvolatile STORE Operations
200
K
Max
Unit
6
pF
8
pF
Capacitance
Parameter[6]
Description
Test Conditions
CIN
Input Capacitance
COUT
Output Pin Capacitance
TA = 25°C, f = 1MHz,
VCC = VCC (Typ)
Thermal Resistance
Parameter [6]
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA / JESD51.
16-SOIC
8-DFN
Unit
TBD
TBD
°C/W
TBD
TBD
°C/W
Figure 20. AC Test Loads and Waveforms
577Ω
577Ω
3.0V
3.0V
R1
R1
OUTPUT
OUTPUT
30 pF
R2
789Ω
5 pF
R2
789Ω
AC Test Conditions
Input Pulse Levels.................................................... 0V to 3V
Input Rise and Fall Times (10% - 90%) ....................... <3 ns
Input and Output Timing Reference Levels.....................1.5V
Note
6. These parameters are guaranteed by design and are not tested.
Document #: 001-50091 Rev. *B
Page 14 of 22
[+] Feedback
CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
AC Switching Characteristics
Cypress
Parameter
Alt.
Parameter
fSCK
tCL
tCH
tCS
tCSS
tCSH
tSD
tHD
tHH
tSH
tCO
tHHZ
tHLZ
tOH
tHZCS
40MHz
Description
fSCK
tWL
tWH
tCE
tCES
tCEH
tSU
tH
tHD
tCD
Clock Frequency, SCK
Clock Pulse Width Low
Clock Pulse Width High
CS High Time
CS Setup Time
CS Hold Time
Data In Setup Time
Data In Hold Time
HOLD Hold Time
HOLD Setup Time
tV
tHZ
tLZ
tHO
tDIS
Output Valid
HOLD to Output High Z
HOLD to Output Low Z
Output Hold Time
Output Disable Time
Min
Unit
Max
40
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
11
20
10
10
5
5
5
5
9
15
15
ns
ns
ns
ns
ns
0
25
Figure 21. Synchronous Data Timing (Mode 0)
tCS
CS
tCSS
tCH
tCL
tCSH
SCK
tSD
tHD
VALID IN
SI
tCO
SO
tOH
tHZCS
HI-Z
HI-Z
~
~
~ ~
Figure 22. HOLD Timing
CS
SCK
tSH
tHH
tHH
tSH
HOLD
tHHZ
tHLZ
SO
Document #: 001-50091 Rev. *B
Page 15 of 22
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CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
AutoStore or Power Up RECALL
Parameters
Power Up RECALL Duration
tFA [7]
tSTORE
CY14B101Q1/CY14B101Q2/
CY14B101Q3
Min
Max
20
Description
Unit
ms
[8]
STORE Cycle Duration
8
ms
[9]
Time Allowed to Complete SRAM Cycle
25
ns
2.65
V
μs
tDELAY
VSWITCH
tVCCRISE
[6]
Low Voltage Trigger Level
VCC Rise Time
150
VHDIS[6]
HSB Output Disable Voltage
1.9
V
tLZHSB[6]
tHHHD[6]
HSB To Output Active Time
5
μs
500
ns
HSB High Active Time
Switching Waveforms
Figure 23. AutoStore or Power Up RECALL[10]
VCC
VSWITCH
VHDIS
8
VVCCRISE
Note
8
tSTORE
Note
tSTORE
11
tHHHD
Note
tHHHD
HSB OUT
tDELAY
tLZHSB
AutoStore
tLZHSB
tDELAY
POWERUP
RECALL
Read & Write
Inhibited
(RWI)
tFA
POWER-UP
RECALL
Read & Write
tFA
BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write
POWER
DOWN
AutoStore
Notes
7. tFA starts from the time VCC rises above VSWITCH.
8. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware Store is not initiated
9. On a Hardware STORE, Software Store / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY.
10. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
11. HSB pin is driven high to VCC only by internal 100kOhm resistor, HSB driver is disabled.
Document #: 001-50091 Rev. *B
Page 16 of 22
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CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
Software Controlled STORE and RECALL Cycles
Parameter
CY14B101Q1/CY14B101Q2/
CY14B101Q3
Description
Min
Unit
Max
tRECALL
RECALL Duration
200
μs
tSS [12, 13]
Soft Sequence Processing Time
100
μs
Switching Waveforms
Figure 24. Software STORE Cycle[12]
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
1
1
1
1
0
0
tSTORE
Hi-Z
RWI
RDY
Figure 25. Software RECALL Cycle[12]
CS
0
1
2
3
4
5
6
7
0
1
1
0
0
0
0
0
SCK
SI
tRECALL
RWI
Hi-Z
RDY
Notes
12. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
13. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: 001-50091 Rev. *B
Page 17 of 22
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CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
Hardware STORE Cycle
Parameter
CY14B101Q3
Description
Min
tDHSB
HSB To Output Active Time when write latch not set
tPHSB
Hardware STORE Pulse Width
Switching Waveforms
Write Latch set
Max
25
15
Unit
ns
ns
Figure 26. Hardware STORE Cycle[8]
~
~
tPHSB
HSB (IN)
tSTORE
tDELAY
~
~
~
~
HSB (OUT)
tHHHD
SO
tLZHSB
RWI
HSB (OUT)
tDELAY
RWI
Document #: 001-50091 Rev. *B
tDHSB
HSB pin is driven high to VCC only by Internal
100K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
tDHSB
~
~
tPHSB
HSB (IN)
~
~
Write Latch not set
Page 18 of 22
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CY14B101Q1
CY14B101Q2
CY14B101Q3
PRELIMINARY
Part Numbering Nomenclature
CY 14 B 101 Q 1-SF X C T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (-40 to 85°C)
Pb-Free
Package:
SF - 16 SOIC
LH - 8 DFN
1 - 8 DFN (with WP)
2 - 8 DFN (With VCAP)
3 - 16 SOIC
Q - Serial SPI nvSRAM
Density:
101 - 1 Mb
Voltage:
B - 3.0V
nvSRAM
14 - Auto Store + Software STORE + Hardware STORE
Cypress
Ordering Information
Ordering Code
Package
Diagram
Package Type
CY14B101Q1-LHXIT
001-50671
8 DFN (with WP)
CY14B101Q1-LHXI
001-50671
8 DFN (with WP)
CY14B101Q1-LHXCT
001-50671
8 DFN (with WP)
CY14B101Q1-LHXC
001-50671
8 DFN (with WP)
CY14B101Q2-LHXIT
001-50671
8 DFN (with VCAP)
CY14B101Q2-LHXI
001-50671
8 DFN (with VCAP)
CY14B101Q2-LHXCT
001-50671
8 DFN (with VCAP)
CY14B101Q2-LHXC
001-50671
8 DFN (with VCAP)
CY14B101Q3-SFXIT
51-85022
16 SOIC
CY14B101Q3-SFXI
51-85022
16 SOIC
CY14B101Q3-SFXCT
51-85022
16 SOIC
CY14B101Q3-SFXC
51-85022
16 SOIC
Operating
Range
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
All the above parts are Pb - free. The above table contains advance information. Contact your local Cypress sales representative for availability of these parts.
Document #: 001-50091 Rev. *B
Page 19 of 22
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PRELIMINARY
CY14B101Q1
CY14B101Q2
CY14B101Q3
Package Diagrams
Figure 27. 8-Pin (196 mil) DFN Package (001-50671)
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS
2. PACKAGE WEIGHT: TBD
3. BASED ON REF JEDEC # MO-240 EXCEPT DIMENSIONS (L) and (b)
Document #: 001-50091 Rev. *B
001-50671 *A
Page 20 of 22
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PRELIMINARY
CY14B101Q1
CY14B101Q2
CY14B101Q3
Package Diagrams (continued)
Figure 28. 16-Pin (300 mil) SOIC (51-85022)
51-85022 *B
Document #: 001-50091 Rev. *B
Page 21 of 22
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PRELIMINARY
CY14B101Q1
CY14B101Q2
CY14B101Q3
Document History Page
Document Title: CY14B101Q1/CY14B101Q2/CY14B101Q3 1 MBit (128K x 8) Serial SPI nvSRAM
Document Number: 001-50091
Orig. of
Submission
REV.
ECN NO.
Description of Change
Change
Date
**
2607408
GSIN/
12/19/08
New Datasheet
GVCH/AESA
*A
2654487 GVCH/PYRS 02/04/2009 Moved from Advance information to Preliminary
Changed part number from CY14B101QxA to CY14B101Qx
Updated pin description of VCAP pin
Updated Device operation and SPI peripheral interface description
Added Factory setting values for BP1, BP2 and WPEN bits
Updated Real Time Clock operation description
Changed ICC2 from 5mA to 10mA
*B
2733293 GVCH/AESA 07/08/2009 Corrected typo error in the Document History Page (Description of change)
Corrected Typo error of footnote 2 and 3
Updated AtoStore operation description
Updated test condition of ICC1 and ISB parameter
Updated VHDIS parameter description
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© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-50091 Rev. *B
Revised July 02, 2009
Page 22 of 22
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