Integrated Circuit Systems, Inc. ICS853111-01 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS853111-01 is a low skew, high performance 1-to-9 Differential-to-3.3V LVPECL/ECL HiPerClockS™ Fa n o u t B u f fe r a n d a m e m b e r o f t h e HiPerClock S ™ family of High Performance Clock Solutions from ICS. The PCLK, nPCLK pair can accept LVPECL, CML and SSTL differential input levels. The ICS853111-01 is characterized to operate from a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS853111-01 ideal for those clock distribution applications demanding well defined performance and repeatability. • 9 differential 3.3V LVPECL / ECL outputs ICS • 1 differential LVPECL input pair • PLCK, nPLCK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2GHz (typical) • Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input • Additive phase jitter, RMS: 0.03ps (typical) • Output skew: 35ps (maximum) • Part-to-part skew: 300ps (maximum) • Propagation delay: 675ps (maximum) • LVPECL mode operating voltage supply range: VCC = 3V to 3.8V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -3V to -3.8V • -40°C to 85°C ambient operating temperature • Lead-Free package RoHS compliant 23 22 21 20 19 18 Q3 nc 27 17 nQ3 PCLK 28 16 Q4 15 VCCO ICS853111-01 nQ4 VBB 3 13 Q5 nc 4 12 nQ5 5 6 7 8 9 10 11 Q6 14 nQ6 2 Q7 nPCLK VCCO 1 nQ7 VCC 28-Lead PLCC 11.6mm x 11.4mm x 4.1mm package body V Package Top View Q8 nQ8 853111AV-01 24 26 Q6 nQ6 Q7 nQ7 25 VEE Q8 Q5 nQ5 nQ2 V BB Q2 Q4 nQ4 nQ1 Q3 nQ3 VCCO Q2 nQ2 Q1 Q1 nQ1 nQ0 Q0 nQ0 Q0 PCLK nPCLK PIN ASSIGNMENT nQ8 BLOCK DIAGRAM www.icst.com/products/hiperclocks.html 1 REV. A APRIL 25, 2005 ICS853111-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type 1 VCC Power 2 nPCLK Input 3 VBB Output 4, 27 nc Unused Description Core supply pin. Pullup/ Inver ting differential LVPECL clock input. Bias to VCC/2 w/no input. Pulldown1 Bias voltage. No connect. 5, 6 nQ8, Q8 Output Differential output pair. LVPECL interface levels. 7, 9 nQ7, Q7 Output Differential output pair. LVPECL interface levels. 8, 15, 22 VCCO Power Output supply pins. 10, 11 nQ6, Q6 Output Differential output pair. LVPECL interface levels. 12, 13 nQ5, Q5 Output Differential output pair. LVPECL interface levels. 14, 16 nQ4, Q4 Output Differential output pair. LVPECL interface levels. 17, 18 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 19, 20 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 21, 23 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 24, 25 nQ0, Q0 Output Differential output pair. LVPECL interface levels. 26 VEE Power 28 PCLK Input Negative supply pin. Pulldown Non-inver ting differential LVPECL clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance RPULLUP Input Pullup Resistor 50 KΩ Input Pulldown Resistor 75 KΩ Input Pulldown Resistor 50 KΩ RPULLDOWN 1 RPULLDOWN 853111AV-01 Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units 1 pF REV. A APRIL 25, 2005 ICS853111-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Inputs, VI (LVPECL mode) 4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (LVECL mode, VCC = 0) to the device. These ratings are stress specifi-0.5V to V + 0.5 V Inputs, VI (LVECL mode) 0.5V to VEE - 0.5V Supply Voltage, VCC Negative Supply Voltage, VEE Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB CC cations only. Functional operation of product at these conditions or any conditions beyond those 50mA 100mA listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maxi- ± 0.5mA mum rating conditions for extended periods may affect product reliability. Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 37.8°C/W (0 lfpm) (Junction-to-Ambient) TABLE 3A. LVPECL POWER SUPPLY DC CHARACTERISTICS, VCC = 3V TO 3.8V; VEE = 0V Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.0 3.3 3.8 V VCCO Output Supply Voltage 3.0 3. 3 3.8 V IEE Power Supply Current 75 mA Table 3B. LVPECL DC Characteristics, VCC = 3.3V; VEE = 0V Symbol -40°C Parameter 25°C Min Typ Max Min Typ 85°C Max Min Typ Max Units VOH Output High Voltage; NOTE 1 2.175 2.275 2.38 2.225 2.295 2.37 2.295 2.33 2.365 V VOL Output Low Voltage; NOTE 1 1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63 V VIH Input High Voltage(Single-Ended) 2.075 2.36 2.075 2.36 2.075 2.36 V VIL Input Low Voltage(Single-Ended) 1.43 1.765 1.43 1.765 1.43 1.765 V VBB Output Voltage Reference; NOTE 2 1.86 1.98 1.86 1.98 1.86 1.98 V VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK, nPCLK High Current 150 1200 150 1200 150 1200 V 3.3 1.2 3.3 1.2 3. 3 V 150 µA VCMR IIH 800 1.2 800 150 15 0 Input -150 -150 -150 PCLK, nPCLK Low Current Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. IIL 853111AV-01 www.icst.com/products/hiperclocks.html 3 800 µA REV. A APRIL 25, 2005 ICS853111-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER TABLE 3C. ECL POWER SUPPLY DC CHARACTERISTICS, VCC = 0V; VEE = -3V TO -3.8V Symbol Parameter VEE Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum Units -3.0 -3.3 -3.8 V 55 mA Table 3D. ECL DC Characteristics, VCC = 0V; VEE = -3V to -3.8V Symbol Parameter VOH -40°C 25°C Min Typ Max Min Typ Output High Voltage; NOTE 1 -1.125 -1.025 -0.92 -1.075 VOL Output Low Voltage; NOTE 1 -1.895 -1.755 -1.62 -1.875 VIH Input High Voltage(Single-Ended) -1.225 -0.94 VIL Input Low Voltage(Single-Ended) -1.87 VBB Output Voltage Reference; NOTE 2 -1.44 VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK, nPCLK High Current 150 VCMR IIH 85°C Max Min -1.005 -0.93 -1.78 -1.685 -1.225 -0.94 -1.535 -1.87 -1.32 -1.44 1200 150 0 VEE+1.2V 800 VEE+1.2V Units Typ Max -1.005 -0.97 -0.935 V -1.86 -1.765 -1.67 V -1.225 -0.94 V -1.535 -1.87 -1.535 V -1.32 -1.44 -1.32 V 1200 150 1200 V 0 VEE+1.2V 0 V 150 µA 800 150 800 150 Input -150 -150 -150 PCLK, nPCLK Low Current Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. IIL µA TABLE 4. AC CHARACTERISTICS, VCC = 3V TO 3.8V; VEE = 0V OR VCC = 0V; VEE = -3V TO -3.8V -40°C Symbol Parameter fMAX Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Output Skew; NOTE 2, 4 tpLH tpHL tsk(o) tsk(pp) tjit tR/tF Min Max Min >2 20% to 80% Typ 85°C Max Min >2 Typ Max >2 Units GHz 350 500 650 385 525 675 410 350 700 ps 450 600 750 480 620 760 515 650 785 ps 20 35 20 35 20 35 ps 200 ps Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Typ 25°C 200 200 0.03 90 200 0.03 315 100 203 0.03 310 95 210 ps 300 ps All parameters measured at f ≤ 1GHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 853111AV-01 www.icst.com/products/hiperclocks.html 4 REV. A APRIL 25, 2005 ICS853111-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 -20 Input/Output Additive Phase Jitter at 155.52MHz -30 = 0.03ps (typical) -40 SSB PHASE NOISE dBc/HZ -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 853111AV-01 vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html 5 REV. A APRIL 25, 2005 ICS853111-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V VCC Qx V CC SCOPE nPCLK LVPECL V V Cross Points PP nQx CMR PCLK VEE -1.3V ± 0.3V V EE DIFFERENTIAL INPUT LEVEL OUTPUT LOAD AC TEST CIRCUIT nQx PART 1 Qx nQx Qx nQy PART 2 Qy nQy t sk(pp) Qy t sk(o) OUTPUT SKEW PART-TO-PART SKEW nPCLK 80% 80% VSW I N G PCLK Clock Outputs nQ0:nQ8 20% 20% tR tF Q0:Q8 tPD OUTPUT RISE/FALL TIME PROPAGATION DELAY 853111AV-01 www.icst.com/products/hiperclocks.html 6 REV. A APRIL 25, 2005 ICS853111-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS negative input. The C1 capacitor should be located as close as possible to the input pin. Figure 1 shows an example of the differential input that can be wired to accept single ended levels. The reference voltage level VBB generated from the device is connected to the VCC C1 0.1u CLK_IN PCLK VBB nPCLK FIGURE 1. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION 853111AV-01 FIN 50Ω 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 7 REV. A APRIL 25, 2005 ICS853111-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm R2 50 Zo = 50 Ohm PCLK R1 100 Zo = 50 Ohm nPCLK PCLK nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK HiPerClockS PCLK/nPCLK CML Built-In Pullup FIGURE 3A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 PCLK PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 VBB nPCLK HiPerClockS Input PC L K/n PC LK R5 100 - 200 R2 84 FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER R6 100 - 200 R1 50 R2 50 FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 2.5V 3.3V 3.3V 3.3V 2.5V R3 120 SSTL Zo = 50 Ohm R4 120 C1 LVDS Zo = 60 Ohm PCLK PCLK R5 100 Zo = 60 Ohm nPCLK R1 120 nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK PC L K /n PC L K R1 1K R2 120 FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER 853111AV-01 VBB C2 FIGURE 3F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER www.icst.com/products/hiperclocks.html 8 R2 1K REV. A APRIL 25, 2005 ICS853111-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER SCHEMATIC EXAMPLE example of the ICS853111-01 LVPECL clock buffer. In this example, the input is driven by an LVPECL driver. This application note provides general design guide using ICS853111-01 LVPECL buffer. Figure 4 shows a schematic Zo = 50 + Zo = 50 R2 50 VCC 32 31 30 29 28 27 26 25 C6 (Option) 0.1u Zo = 50 Ohm 1 2 3 4 5 6 7 8 Zo = 50 Ohm R4 1K R10 50 C8 (Option) 0.1u R11 50 9 10 11 12 13 14 15 16 R9 50 VCC CLK_SEL PCLK0 nPCLK0 VBB PCLK1 nPCLK1 VEE Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 VCCO nQ9 Q9 nQ8 Q8 nQ7 Q7 VCCO 3.3V LVPECL VCCO Q0 nQ0 Q1 nQ1 Q2 nQ2 VCCO VCC - R1 50 R3 50 24 23 22 21 20 19 18 17 U1 ICS853111 VCC Zo = 50 + VCC=3.3V Zo = 50 (U1-9) VCC (U1-16) (U1-25) (U1-32) - (U1-1) R8 50 C1 0.1uF C2 0.1uF C3 0.1uF C4 0.1uF R7 50 C5 0.1uF C7 (Option) 0.1u R13 50 FIGURE 4. EXAMPLE ICS853111-01 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC 853111AV-01 www.icst.com/products/hiperclocks.html 9 REV. A APRIL 25, 2005 ICS853111-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS853111-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853111-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 75mA = 285mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 30.94mW = 278.5mW Total Power_MAX (3.8V, with all outputs switching) = 285mW + 278.5mW = 563.5mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.564W * 31.1°C/W = 102°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5. THERMAL RESISTANCE θJA FOR 28-PIN PLCC, FORCED CONVECTION θ by Velocity (Linear Feet per Minute) JA 0 Multi-Layer PCB, JEDEC Standard Test Boards 37.8°C/W 200 500 31.1°C/W 28.3°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 853111AV-01 www.icst.com/products/hiperclocks.html 10 REV. A APRIL 25, 2005 ICS853111-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER 3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 5. VCCO Q1 VOUT RL 50 VCCO - 2V Figure 5. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX =V OL_MAX CCO_MAX -V OL_MAX CCO_MAX – 0.935V ) = 0.935V For logic low, VOUT = V (V =V CCO_MAX – 1.67V ) = 1.67V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V CCO_MAX L -V OH_MAX )= [(2V - 0.935V)/50Ω] * 0.935V = 19.92mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.67V)/50Ω] * 1.67V = 11.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW 853111AV-01 www.icst.com/products/hiperclocks.html 11 REV. A APRIL 25, 2005 ICS853111-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 28 LEAD PLCC θ by Velocity (Linear Feet per Minute) JA 0 Multi-Layer PCB, JEDEC Standard Test Boards 37.8°C/W 200 500 31.1°C/W 28.3°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS853111-01 is: 265 Pin compatible with MC100LVE111 853111AV-01 www.icst.com/products/hiperclocks.html 12 REV. A APRIL 25, 2005 ICS853111-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER PACKAGE OUTLINE - V SUFFIX FOR 28 LEAD PLCC TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM MAXIMUM 28 N A 4.19 4.57 A1 2.29 3.05 A2 1.57 2.11 b 0.33 0.53 c 0.19 0.32 D 12.32 12.57 D1 11.43 11.58 D2 4.85 5.56 E 12.32 12.57 E1 11.43 11.58 E2 4.85 5.56 Reference Document: JEDEC Publication 95, MS-018 853111AV-01 www.icst.com/products/hiperclocks.html 13 REV. A APRIL 25, 2005 ICS853111-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS853111AV-01 ICS853111AV-01 28 Lead PLCC Tube -40°C to 85°C ICS853111AV-01T ICS853111AV-01 28 Lead PLCC 500 Tape & Reel -40°C to 85°C ICS853111AV-01LF TBD 28 Lead "Lead-Free" PLCC Tube -40°C to 85°C ICS853111AV-01LFT TBD 28 Lead "Lead-Free" PLCC 500 Tape & Reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the pat number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark. HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853111AV-01 www.icst.com/products/hiperclocks.html 14 REV. A APRIL 25, 2005 Integrated Circuit Systems, Inc. ICS853111-01 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER REVISION HISTORY SHEET Rev 853111AV-01 Table Page 1 5 Description of Change Features Section - added Lead-Free bullet. Added Additive Phase jitter section. www.icst.com/products/hiperclocks.html 15 Date 4/25/05 REV. A APRIL 25, 2005