Intersil ISL84052IVZ Low voltage, single and dual supply, 8-to-1 multiplexer, dual 4-to-1 multiplexer and a triple spdt analog switch Datasheet

Low Voltage, Single and Dual Supply, 8-to-1
Multiplexer, Dual 4-to-1 Multiplexer and a Triple SPDT
Analog Switch
ISL84051, ISL84052, ISL84053
Features
The Intersil ISL84051, ISL84052, ISL84053 devices are
precision, bidirectional, analog switches configured as a
8-Channel multiplexer/demultiplexer (ISL84051), a dual
differential 4-Channel multiplexer/demultiplexer (ISL84052)
and a triple single pole/double throw (SPDT) switch (ISL84053)
designed to operate from a single +2V to +12V supply or from a
±2V to ±6V supply. All devices have an inhibit pin to
simultaneously open all signal paths.
• Drop-in Replacements for MAX4051/MAX4051A,
MAX4052/MAX4052A and MAX4053/MAX4053A
ON-resistance is 60Ω with a ±5V supply and 125Ω with a single
+5V supply. Each switch can handle rail to rail analog signals.
The off-leakage current is only 5nA at +85°C with a ±5V
supply.
All digital inputs have 0.8V to 2.4V logic thresholds, ensuring
TTL/CMOS logic compatibility when using a single +3.3V and
+5V supply or dual ±5V supplies.
The ISL84051 is a 8-to-1 multiplexer device. The ISL84052 is a
dual 4-to-1 multiplexer device. The ISL84053 is a committed
triple SPDT, which is perfect for use in 2-to-1 multiplexer
applications.
Table 1 summarizes the performance of this family.
±5V rON
±5V tON/tOFF
5V rON
5V tON/tOFF
3V rON
3V tON/tOFF
Packages
ISL84051
ISL84052
ISL84053
8:1 Mux
DUAL
4:1 Mux
TRIPLE SPDT
60Ω
60Ω
60Ω
50ns/40ns
50ns/40ns
50ns/40ns
125Ω
125Ω
125Ω
90ns/60ns
90ns/60ns
90ns/60ns
250Ω
250Ω
250Ω
180ns/100ns 180ns/100ns 180ns/100ns
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld QSOP
16 Ld QSOP
16 Ld QSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
• Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2pC
• Single Supply Operation. . . . . . . . . . . . . . . . . . . . . . . +2V to +12V
• Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . . . . . . ±2V to ±6
• Fast Switching Action (VS = +5V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ns
• Guaranteed Max Off-leakage @ VS = ±5V . . . . . . . . . . . . . . 5nA
• Break-Before-Make
• TTL, CMOS Compatible
Applications
• Portable Equipment
Related Literature
May 16, 2011
FN6047.10
• ON-Resistance (rON) Max, VS = ±5V . . . . . . . . . . . . . . . . . 100Ω
• ON-Resistance (rON) Max, VS = +5V . . . . . . . . . . . . . . . . . 225Ω
• rON Matching Between Channels . . . . . . . . . . . . . . . . . . . . . . <6Ω
• Pb-Free Available (RoHS Compliant)
TABLE 1. FEATURES AT A GLANCE
CONFIGURATION
• Pin Compatible with MAX4581, MAX4582, MAX4583 and
with Industry Standard 74HC4051, 74HC4052 and
74HC4053
• Communications Systems
- Radios
- Telecom Infrastructure
- ADSL, VDSL Modems
• Test Equipment
- Medical Ultrasound
- Magnetic Resonance Image
- CT and PET Scanners (MRI)
- ATE
- Electrocardiograph
• Audio and Video Signal Routing
• Various Circuits
- +3V/+5V DACs and ADCs
- Sample and Hold Circuits
- Operational Amplifier Gain Switching Networks
- High Frequency Analog Switching
- High Speed Multiplexing
- Integrator Reset Circuits
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2003, 2004, 2006, 2007, 2010, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL84051, ISL84052, ISL84053
Pin Configurations
ISL84052
(16 LD SOIC, QSOP, TSSOP)
TOP VIEW
ISL84051
(16 LD SOIC, QSOP, TSSOP)
TOP VIEW
NO1 1
16 V+
NO0B 1
16 V+
NO3 2
15 NO2
NO1B 2
15 NO1A
COM 3
14 NO4
COMB 3
14 NO2A
NO7 4
13 NO0
NO3B 4
13 COMA
NO5 5
12 NO6
NO2B 5
12 NO0A
INH 6
11 NO3A
INH 6
11 ADDC
LOGIC
V- 7
10 ADDB
V- 7
GND 8
9 ADDA
GND 8
LOGIC
10 ADDB
9 ADDA
ISL84053
(16 LD SOIC, QSOP, TSSOP)
TOP VIEW
NOB 1
16 V+
NCB 2
15 COMB
NOA 3
14 COMC
COMA 4
13 NOC
NCA 5
12 NCC
INH 6
11 ADDC
V- 7
10 ADDB
GND 8
9 ADDA
NOTE:
1. Switches Shown for Logic “0” Inputs.
Pin Description
PIN NUMBER
PIN NAME
ISL84051
ISL84052
ISL84053
V+
16
16
16
Positive Power Supply Input
V-
7
7
7
Negative Power Supply Input. Connect to GND for Single Supply Configurations.
GND
8
8
8
Ground Connection
INH
6
6
6
Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all
switches off.
COM
3
-
-
Analog Switch Common Pin
COMA
-
13
4
COMB
-
3
15
COMC
-
-
14
NO1, NO3,
NO7, NO5,
NO6, NO4, NO2
1, 2,
4, 5,
12, 14, 15
-
-
2
FUNCTION
Analog Switch Normally Open Pin
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Pin Description (Continued)
PIN NUMBER
PIN NAME
ISL84051
ISL84052
ISL84053
NO0B, NO1B,
NO3B, NO2B,
NO3A, NO0A,
NO2A, NO1A
-
1, 2,
4, 5,
11, 12,
14, 15
-
NOB, NOA, NOC
-
-
1, 3, 13
NCB, NCA, NCC
-
-
2, 5, 12
ADDA, ADDB,
ADDC
9, 10
11
9, 10
-
9, 10
11
FUNCTION
Analog Switch Normally Open Pin
Analog Switch Normally Closed Pin
Address Input Pin
Ordering Information
PART
NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL84051IAZ
84051 IAZ
-40 to +85
16 Ld QSOP
M16.15A
ISL84051IBZ
84051IBZ
-40 to +85
16 Ld SOIC
M16.15
ISL84051IVZ
84051 IVZ
-40 to +85
16 Ld TSSOP
M16.173
ISL84052IAZ
84052 IAZ
-40 to +85
16 Ld QSOP
M16.15A
ISL84052IBZ
84052IBZ
-40 to +85
16 Ld SOIC
M16.15
ISL84052IVZ
84052 IVZ
-40 to +85
16 Ld TSSOP
M16.173
ISL84053IAZ
84053 IAZ
-40 to +85
16 Ld QSOP
M16.15A
ISL84053IBZ
84053IBZ
-40 to +85
16 Ld SOIC
M16.15
ISL84053IVZ
84053 IVZ
-40 to +85
16 Ld TSSOP
M16.173
NOTES:
2. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL84051, ISL84052, ISL84053. For more information on MSL please
see techbrief TB363.
3
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Truth Tables
ISL84052
ISL84051
INH
ADDC
ADDB
ADDA
SWITCH
ON
1
X
X
X
None
0
0
0
0
NO0
0
0
0
1
NO1
0
0
1
0
NO2
0
0
1
1
NO3
0
1
0
0
NO4
0
1
0
1
NO5
0
1
1
0
NO6
0
1
1
1
NO7
INH
ADDB
ADDA
SWITCH ON
1
X
X
None
0
0
0
NO0
0
0
1
NO1
0
1
0
NO2
0
1
1
NO3
ISL84053
INH
ADDC
ADDB
ADDA
SWITCH ON
1
X
X
X
None
0
X
X
0
NCA
0
X
X
1
NOA
0
X
0
X
NCB
0
X
1
X
NOB
0
0
X
X
NCC
0
1
X
X
NOC
NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V, with V+ between 2.7V and
10V. X = Don’t Care.
4
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Absolute Maximum Ratings
Thermal Information
V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V
V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15V to 0.3V
Input Voltages
INH, NO, NC, ADD (Note 5). . . . . . . . . . . . . . . . ((V-) - 0.3) to ((V+) + 0.3V)
Output Voltages
COM (Note 5). . . . . . . . . . . . . . . . . . . . . . . . . . . ((V-) - 0.3) to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . ±30mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max). . . . . . . . . . . . . . . . . . . . . . . . ±100mA
ESD Rating
Human Body Model (Per MIL-STD-883, Method 3015.7) . . . . . . . . >2kV
Thermal Resistance (Typical, Notes 6, 7)
θJA (°C/W) θJC (°C/W)
16 Ld SOIC Package . . . . . . . . . . . . . . . . . .
75
39
16 Ld QSOP Package. . . . . . . . . . . . . . . . . .
95
56
16 Ld TSSOP Package . . . . . . . . . . . . . . . . .
110
33
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. Signals on NC, NO, COM, ADD, or INH exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings.
6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
7. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications 5V Supply
Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note
8), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
TEMP
(°C)
MIN
(Notes 9, 10)
TYP
MAX
(Notes 9, 10)
UNITS
Full
V-
-
V+
V
VS = ±5V, ICOM = 1mA, VNO or VNC = ±3V
(see Figure 5)
+25
-
60
100
Ω
Full
-
-
125
Ω
rON Matching Between Channels,
ΔrON
VS = ±5V, ICOM = 1mA, VNO or VNC = ±3V (Note 11)
+25
-
-
6
Ω
Full
-
-
12
Ω
rON Flatness, rFLAT(ON)
VS = ±5V, ICOM = 1mA, VNO or VNC = ±3V, 0V
(Note 12)
+25
-
-
10
Ω
Full
-
-
15
Ω
VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = ±4.5V
(Note 12)
+25
-
0.002
-
nA
Full
-5
-
5
nA
COM OFF Leakage Current, ICOM(OFF), VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = ±4.5V
(ISL84051)
(Note 12)
+25
-
0.002
-
nA
Full
-5
-
5
nA
COM OFF Leakage Current, ICOM(OFF), VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = ±4.5V
(ISL84052, ISL84053)
(Note 12)
+25
-
0.002
-
nA
Full
-2.5
-
2.5
nA
COM ON Leakage Current, ICOM(ON),
(ISL84051)
VS = ±5.5V, VCOM = VNO or VNC = ±4.5V
(Note 12)
+25
-
0.002
-
nA
Full
-5
-
5
nA
COM ON Leakage Current, ICOM(ON),
(ISL84052, ISL84053)
VS = ±5.5V, VCOM = VNO or VNC = ±4.5V (Note 12)
+25
-
0.002
-
nA
Full
-2.5
-
2.5
nA
Input Voltage High, VINH, VADDH
Full
2.4
-
-
V
Input Voltage Low, VINL, VADDL
Full
-
-
0.8
V
Full
-1
0.03
1
µA
PARAMETER
TEST CONDITIONS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL, IADDH, IADDL
5
VS = ±5.5V, VINH, VADD = 0V or V+
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Electrical Specifications 5V Supply
Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note
8), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
TEMP
(°C)
MIN
(Notes 9, 10)
TYP
MAX
(Notes 9, 10)
UNITS
VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
VIN = 0V to 3V (see Figure 1)
+25
-
50
-
ns
Full
-
60
-
ns
VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
VIN = 0V to 3V (see Figure 1)
+25
-
40
-
ns
Full
-
50
-
ns
Address Transition Time, tTRANS
VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,
VIN = 0V to 3V (see Figure 1)
+25
-
75
-
ns
Break-Before-Make Time, tBBM
VS = ±5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
VIN = 0V to 3V (see Figure 3)
+25
-
10
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2)
+25
-
2
-
pC
NO/NC OFF-Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7)
+25
-
3
-
pF
COM OFF-Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V (see
Figure 7)
ISL84051
+25
-
21
-
pF
ISL84052
+25
-
12
-
pF
ISL84053
+25
-
9
-
pF
ISL84051
+25
-
26
-
pF
ISL84052
+25
-
18
-
pF
ISL84053
+25
-
14
-
pF
+25
-
<90
-
dB
+25
-
< -90
-
dB
Full
±2
-
±6
V
+25
-1
0.1
1
µA
Full
-10
-
10
µA
25
-1
0.1
1
µA
Full
-10
-
10
µA
PARAMETER
TEST CONDITIONS
DYNAMIC CHARACTERISTICS
Inhibit Turn-ON Time, tON
Inhibit Turn-OFF Time, tOFF
COM ON-Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V (see
Figure 7)
OFF Isolation
RL = 50Ω, CL = 15pF, f = 100kHz
VNO or VNC = 1VRMS (see Figures 4 and 6)
Crosstalk, (Note 9) (ISL84052,
ISL84053 Only)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
VS = ±5.5V, VINH, VADD = 0V or V+, Switch On or Off
Negative Supply Current, I-
Electrical Specifications 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V
(Note 8), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
MAX
TEMP
(°C)
(Notes 9, 10)
TYP
(Notes 9, 10)
UNITS
Full
0
-
V+
V
V+ = 5V, ICOM = 1.0mA, VNO or VNC = 3.5V
(see Figure 5)
+25
-
125
225
Ω
Full
-
-
280
Ω
V+ = 5.5V, VCOM = 0V, 4.5V, VNO or VNC = 4.5V, 0V (Note
12)
+25
-
0.002
-
nA
Full
-10
-
10
nA
COM OFF Leakage Current, ICOM(OFF), V+ = 5.5V, VCOM = 0V, 4.5V, VNO or VNC = 4.5V, 0V (Note
(ISL84051)
12)
+25
-
0.002
-
nA
Full
-10
-
10
nA
COM OFF Leakage Current, ICOM(OFF), V+ = 5.5V, VCOM = 0V, 4.5V, VNO or VNC = 4.5V, 0V (Note
(ISL84052, ISL84053)
12)
+25
-
0.002
-
nA
Full
-5
-
5
nA
PARAMETER
TEST CONDITIONS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
6
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Electrical Specifications 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V
(Note 8), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
TEMP
(°C)
(Notes 9, 10)
TYP
(Notes 9, 10)
UNITS
+25
-
0.002
-
nA
Full
-10
-
10
nA
Input Voltage High, VINH, VADDH
Full
2.4
-
-
V
Input Voltage Low, VINL, VADDL
Full
-
-
0.8
V
Input Current, IINH, IINL, IADDH, IADDL V+ = 5.5V, VINH, VADD = 0V or V+
Full
-1
0.03
1
µA
V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN
= 0 to 3V (see Figure 1)
+25
-
90
-
ns
Full
-
100
-
ns
V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN
= 0V to 3V (see Figure 1)
+25
-
60
-
ns
Full
-
70
-
ns
Break-Before-Make Time, tBBM
V+ = 5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN
= 0V to 3V (see Figure 3)
+25
-
30
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2)
+25
-
2
-
pC
OFF Isolation
RL = 50Ω, CL = 15pF, f = 100kHz VNO or VNC = 1VRMS
(see Figures 4 and 6)
+25
-
<90
-
dB
+25
-
<-90
-
dB
Full
2
-
12
V
+25
-1
-
1
µA
Full
-10
-
10
µA
PARAMETER
TEST CONDITIONS
COM ON Leakage Current, ICOM(ON)
V+ = 5.5V, VCOM = VNO or VNC = 4.5V (Note 12)
DIGITAL INPUT CHARACTERISTICS
DYNAMIC CHARACTERISTICS
Inhibit Turn-ON Time, tON
Inhibit Turn-OFF Time, tOFF
Crosstalk, (Note 9) (ISL84052,
ISL840533 Only)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = 5.5V, V- = 0V, VINH, VADD = 0V or V+, Switch On
or Off
Electrical Specifications 3.3V Supply Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V
(Note 8), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
MAX
TEMP
(°C)
(Notes 9, 10)
TYP
(Notes 9, 10)
UNITS
Full
0
-
V+
V
+25
-
250
-
Ω
Full
-
270
-
Ω
V+ = 3.6V, VCOM = 0V, 3V, VNO or VNC = 3V, 0V
(Note 12)
+25
-
0.002
-
nA
Full
-10
-
10
nA
COM OFF Leakage Current, ICOM(OFF), V+ = 3.6V, VCOM = 0V, 3V, VNO or VNC = 3V, 0V
(ISL84051)
(Note 12)
+25
-
0.002
-
nA
Full
-10
-
10
nA
COM OFF Leakage Current, ICOM(OFF), V+ = 3.6V, VCOM = 0V, 3V, VNO or VNC = 3V, 0V
(ISL84052, ISL84053)
(Note 12)
+25
-
0.002
-
nA
Full
-5
-
5
nA
+25
-
0.002
-
nA
Full
-10
-
10
nA
Full
2.4
-
-
V
PARAMETER
TEST CONDITIONS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V
ON-Resistance, rON
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
COM ON Leakage Current, ICOM(ON)
V+ = 3.6V, VCOM = VNO or VNC = 3V (Note 12)
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, VINH, VADDH
7
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Electrical Specifications 3.3V Supply Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V
(Note 8), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
TEMP
(°C)
(Notes 9, 10)
TYP
(Notes 9, 10)
UNITS
Input Voltage Low, VINL, VADDL
Full
-
-
0.8
V
Input Current, IINH, IINL, IADDH, IADDL V+ = 3.6V, VINH, VADD = 0V or V+
Full
-1
0.03
1
µA
V+ = 3V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN
= 0V to 3V (see Figure 1)
+25
-
180
-
ns
Full
-
280
-
ns
V+ = 3V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN
= 0V to 3V (see Figure 1)
+25
-
100
-
ns
Full
-
200
-
ns
Break-Before-Make Time, tBBM
V+ = 3.6V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF,
VIN = 0V to 3V (see Figure 3)
+25
-
90
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2)
+25
-
1
-
pC
OFF Isolation
RL = 50Ω, CL = 15pF, f = 100kHz
VNO or VNC = 1VRMS, (see Figures 4 and 6)
+25
-
<90
-
dB
+25
-
<-90
-
dB
Full
2
-
12
V
+25
-1
-
1
µA
Full
-10
-
10
µA
PARAMETER
TEST CONDITIONS
DYNAMIC CHARACTERISTICS
Inhibit Turn-ON Time, tON
Inhibit Turn-OFF Time, tOFF
Crosstalk, (Note 9) (ISL84052,
ISL84053 Only)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
V+ = 3.6V, V- = 0V, VINH, VADD = 0V or V+
Switch On or Off
Positive Supply Current, I+
NOTES:
8. VIN = Input voltage to perform proper function.
9. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
11. ΔrON = rON (MAX) - rON (MIN).
12. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
13. Between any two switches.
8
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Test Circuits and Waveforms
C
V+
V+
V-
C
NO0
ISL84051
NO1-NO7
INH
3V
LOGIC
INPUT
V-
C
CL
35pF
RL
300Ω
C
tr < 20ns
tf < 20ns
50%
0V
V+
tON
90%
SWITCH
OUTPUT
V+
VOUT
COM
GND ADDA-C
LOGIC
INPUT
C
C
VOUT
NO0
ISL84052
NO1-NO3
INH
90%
VOUT
COM
GND ADDA-B
LOGIC
INPUT
CL
35pF
RL
300Ω
0V
tOFF
Logic input waveform is inverted for switches that have the opposite
logic sense.
C
V+
V+
NCX
NOX
INH
LOGIC
INPUT
C
V-
C
ISL84053
COMX
GND ADDX
VOUT
CL
35pF
RL
300Ω
Repeat test for other switches. CL includes fixture and stray
capacitance.
RL
--------------------V OUT = V
(NO or NC) R + r
L
ON
FIGURE 1A. INHIBIT tON / tOFF MEASUREMENT POINTS
FIGURE 1B. INHIBIT tON / tOFF TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
9
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Test Circuits and Waveforms
(Continued)
V+
C
V+
NO0
V-
V-
C
ISL84051
NO7
C
C
VOUT
COM
NO1-NO6
ADDA-C GND
INH
LOGIC
INPUT
V+
C
3V
LOGIC
INPUT
50%
V+
VOUT
NO0
V-
tTRANS
SWITCH
OUTPUT
C
tr < 20ns
tf < 20ns
0V
VNOX
V-
C
CL
35pF
RL
300Ω
ISL84052
NO3
C
ADDA-B GND
90%
VOUT
COM
NO1-NO2
INH
LOGIC
INPUT
0V
CL
35pF
RL
300Ω
10%
VNOX
V+
C
tTRANS
Logic input waveform is inverted for switches that have the opposite
logic sense.
V+
NCX
V-
V-
C
ISL84053
NOX
COMX
C
ADDX
LOGIC
INPUT
C
GND
INH
VOUT
CL
35pF
RL
300Ω
Repeat test for other switches. CL includes fixture and stray
capacitance.
RL
--------------------V OUT = V
(NO or NC) R + r
L
ON
FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS
FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1. SWITCHING TIMES (Continued)
10
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Test Circuits and Waveforms
(Continued)
V+
3V
ON
COM
NO or NC
0V
C
VOUT
RG
OFF
OFF
LOGIC
INPUT
V-
C
0Ω
ADDX
SWITCH
OUTPUT
VOUT
VG
DVOUT
GND
INH
CL
1nF
LOGIC
INPUT
Q = DVOUT x CL
Repeat test for other switches.
FIGURE 2B. Q TEST CIRCUIT
FIGURE 2A. Q MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
C
V-
C
NO0-NO7
V+
C
VOUT
COM
ISL84051
LOGIC
INPUT
GND
tr < 20ns
tf < 20ns
3V
V+
C
LOGIC
INPUT
INH
V-
C
C
0V
NO0-NO3
V+
0V
ISL84052
GND
V+
C
V+
CL
35pF
RL
300Ω
LOGIC
INPUT
tBBM
VOUT
COM
ADDA-B
80%
SWITCH
OUTPUT
VOUT
CL
35pF
RL
300Ω
ADDA-C
V-
C
NOX
NCX
INH
COMX
ISL84053
C
VOUT
CL
35pF
RL
300Ω
ADDX
LOGIC
INPUT
GND
INH
Repeat test for other switches. CL includes fixture and stray
capacitance.
FIGURE 3A. tBBM MEASUREMENT POINTS
FIGURE 3B. tBBM TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
11
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Test Circuits and Waveforms
V+
V-
C
(Continued)
V+
C
V-
C
C
rON = V1/1mA
SIGNAL
GENERATOR
NO or NC
NO or NC
VNX
1mA
0V OR V+
ADDX
ANALYZER
0V OR V+
COM
GND
0V OR V+
V1
ADDX
COM
INH
GND
INH
RL
FIGURE 5. rON TEST CIRCUIT
FIGURE 4. OFF ISOLATION TEST CIRCUIT
V+
SIGNAL
GENERATOR
V-
C
50Ω
NOA or NCA
0V OR V+
ADDX
COMB
GND
V-
C
C
NO OR NC
COMA
ISL84052
AND
ISL84053
NOB or NCB
ANALYZER
V+
C
0V OR V+
ADDX
IMPEDANCE
ANALYZER
NC
COM
GND
INH
INH
RL
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL84051, ISL84052, ISL84053 analog switches offer
precise switching capability from a bipolar ±2V to ±6V or a
single 2V to 12V supply with low on-resistance (60Ω) and high
speed operation (tON = 50ns, tOFF = 40ns). The devices are
especially well suited to portable battery powered equipment
thanks to the low operating supply voltage (2V), low power
consumption (3µW), low leakage currents (5nA max). High
frequency applications also benefit from the wide bandwidth,
and the very high off isolation and crosstalk rejection.
Supply Sequencing And Overvoltage
Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
12
FIGURE 7. CAPACITANCE TEST CIRCUIT
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to V- (see Figure
8). To prevent forward biasing these diodes, V+ and V- must be
applied before any input signals, and input signal voltages
must remain between V+ and V-. If these conditions cannot be
guaranteed, then one of the following two protection methods
should be employed.
Logic inputs can easily be protected by adding a 1kΩ resistor in
series with the input (see Figure 8). The resistor limits the input
current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
This method is not applicable for the signal path inputs.
Adding a series resistor to the switch input defeats the purpose
of using a low rON switch, so two small signal diodes can be
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
added in series with the supply pins to provide overvoltage
protection for all pins (see Figure 8). These additional diodes
limit the analog signal from 1V below V+ to 1V above V-. The
low leakage current performance is unaffected by this
approach, but the switch resistance may increase, especially
at low supply voltages.
OPTIONAL
PROTECTION
RESISTOR
FOR LOGIC
INPUTS
1kΩ
OPTIONAL PROTECTION
DIODE
V+
LOGIC
VNO OR NC
VCOM
VOPTIONAL PROTECTION
DIODE
FIGURE 8. INPUT OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL8405x construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and GND.
V+ and V- drive the internal CMOS switches and set their
analog voltage limits, so there are no connections between the
analog signal path and GND. Unlike switches with a 13V
maximum supply voltage, the ISL8405x 15V maximum supply
voltage provides plenty of room for the 10% tolerance of 12V
supplies (±6V or 12V single supply), as well as room for
overshoot and noise spikes.
This family of switches performs equally well when operated
with bipolar or single voltage supplies. The minimum
recommended supply voltage is 2V or ±2V. It is important to
note that the input signal range, switching times, and
ON-resistance degrade at lower supply voltages. Refer to the
“Electrical Specification” tables beginning on page 5 and
“Typical Performance Curves” beginning on page 14 for
details.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals.
13
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no affect
on logic thresholds. This switch family is TTL compatible (0.8V
and 2.4V) over a V+ supply range of 2.7V to 10V. At 12V the VIH
level is about 3.5V. This is still below the CMOS guaranteed
high output minimum level of 4V, but noise margin is reduced.
For best results with a 12V supply, use a logic family that
provides a VOH greater than 4V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving the
digital input signals from GND to V+ with a fast transition time
minimizes power dissipation.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
100MHz (see Figure 17). Figure 17 also illustrates that the
frequency response is very consistent over varying analog
signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off isolation is the
resistance to this feed through, while crosstalk indicates the
amount of feed through from one switch to another. Figure 18
details the high off isolation and crosstalk rejection provided
by this family. At 10MHz, off isolation is about 55dB in 50Ω
systems, decreasing approximately 20dB per decade as
frequency increases. Higher load impedances decrease off
isolation and crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One of
these diodes conducts if any analog signal exceeds V+ or V-.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given signal
pin are identical and therefore fairly well balanced, they are
reverse biased differently. Each is biased by either V+ or V- and
the analog signal. This means their leakages will vary as the
signal varies. The difference in the two diode leakages to the
V+ and V- pins constitutes the analog-signal-path leakage
current. All analog leakage current flows between each pin
and one of the supply terminals, not to the other switch
terminal. This is why both sides of a given switch can show
leakage currents of the same or opposite polarity. There is no
connection between the analog signal paths and GND.
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
225
200
70
VCOM = (V+) - 1V
ICOM = 1mA
V- = -5V
60
50
+85°C
40
+25°C
30
-40°C
rON (Ω)
rON (Ω)
V- = 0V
300
+85°C
+25°C
100
-40°C
0
3
2
4
5
6
7
V+ (V)
8
9
10
11
12
+85°C
V+ = 5V
+25°C
V+ = 3.3V
-40°C
V- = 0V
V- = 0V
-40°C
3
2
5
4
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
2
VS = ±2V
+85°C
V+ = 2.7V
V- = 0V
VCOM (V)
+25°C
1
-40°C
VS = ±3V
0
+85°C
Q (pC)
rON (Ω)
ICOM = 1mA
+25°C
-40°C
75
160
140
120
100
80
60
100
90
+85°C
80
70 +25°C
60
50
40
1
0
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE
120
110
100
90
80
70
60
50
90
80
70
60
50
40
30
60
+85°C
125
100
20
400
200
ICOM = 1mA
175
150
+25°C
-40°C
V+ = 5V
V- = 0V
-1
VS = ±5V
50
VS = ±5V
+85°C
+25°C
-2
40
30
20
-40°C
-5
-3
-3
-4
-2
-1
1
0
VCOM (V)
2
3
-5
5
4
400
+25°C
200
100
+25°C
50
+85°C
+85°C
tOFF (ns)
tON (ns)
+25°C
100
+25°C
-40°C
0
250
V- = 0V
200
+85°C
150
100
50
3
0
100
V- = 0V
80
+85°C
+25°C
40
20
-40°C
2
-40°C
60
+25°C
0
4
VCOM = (V+) - 1V
V- = -5V
-40°C
150
-40°C
300
0
200
VCOM = (V+) - 1V
V- = -5V
5
2.5
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
500
0
VCOM (V)
-2.5
5
6
7
8
9
10
11
V+ (V)
FIGURE 13. INHIBIT TURN-ON TIME vs SUPPLY VOLTAGE
14
12
-40°C
2
3
4
5
6
7
8
9
10
11
12
V+ (V)
FIGURE 14. INHIBIT TURN-OFF TIME vs SUPPLY VOLTAGE
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
300
250
VCOM = (V+) - 1V
250
200
tRANS (ns)
200
150
100
150
100
+25°C
+25°C
+85°C
50
+85°C
50
-40°C
-40°C
0
0
2
3
4
5
6
7
8
9
11
10
13
12
2
3
4
5
6
V± (V)
V+ (V)
FIGURE 15. ADDRESS TRANS TIME vs SINGLE SUPPLY VOLTAGE
FIGURE 16. ADDRESS TRANS TIME vs DUAL SUPPLY VOLTAGE
3
ISL84053
GAIN
0
ISL84052
ISL84053
PHASE
ISL84051
ISL84052
0
45
90
135
180
RL = 50Ω
1M
10M
100M
FREQUENCY (Hz)
FIGURE 17. FREQUENCY RESPONSE
600M
CROSSTALK (dB)
ISL84051
-3
10
V+ = 3V TO 12V or
-20 VS = ±2V TO ±5V
RL = 50Ω
-30
VIN = 0.2VP-P TO 5VP-P
PHASE (°)
NORMALIZED GAIN (dB)
-10
VS = ±5V
20
30
-40
40
-50
50
-60
60
ISOLATION
-70
70
-80
80
CROSSTALK
-90
90
-100
-110
1k
OFF ISOLATION (dB)
tRANS (ns)
VCOM = (V+) - 1V
V- = 0V
100
10k
100k
1M
10M
110
100M 500M
FREQUENCY (Hz)
FIGURE 18. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
V-
TRANSISTOR COUNT:
ISL84051: 193
ISL84052: 193
ISL84053: 193
PROCESS:
Si Gate CMOS
15
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
05/02/11
FN6047.10
CHANGE
-Converted to new datasheet template.
-Updated Intersil Trademark statement at bottom of page 1 per directive from Legal.
-Added TSSOP Package option to ISL84053 in Pin Configuration and ordering information.
-Updated ordering information by removing withdrawn and obsolete non pb-free parts: ISL84051IA,
ISL84051IA-T, ISL84051IB, ISL84051IB-T, ISL84052IA, ISL84051IB, ISL84053IA-T
Updated notes in ordering information
-Updated “Parameters...” note in Electrical Specifications tables to new “Compliance...” note according to
standards
-M16.173 - Converted to new POD format by moving dimensions from table onto drawing and adding land
pattern. No dimension changes.
-Added Revision History and Products Information.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL84051, ISL84052, ISL84053
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
16
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
N
INDEX
AREA
H
0.25(0.010) M
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
B M
INCHES
E
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3859
0.3937
9.80
10.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
-
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
α
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
H
N
NOTES:
MILLIMETERS
16
0°
16
8°
0°
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
17
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Package Outline Drawing
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
5.00 ±0.10
SEE DETAIL "X"
9
16
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
8
B
0.65
0.09-0.20
END VIEW
TOP VIEW
1.00 REF
- 0.05
H
C
1.20 MAX
SEATING
PLANE
0.90 +0.15/-0.10
GAUGE
PLANE
0.25 +0.05/-0.06 5
0.10 M C B A
0.10 C
0°-8°
0.05 MIN
0.15 MAX
SIDE VIEW
0.25
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
18
FN6047.10
May 16, 2011
ISL84051, ISL84052, ISL84053
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M16.15A
N
INDEX
AREA
H
0.25(0.010) M
E
2
INCHES
GAUGE
PLANE
-B1
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
B M
3
0.25
0.010
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
α
A2
A1
B
0.17(0.007) M
L
C
0.10(0.004)
C A M
B S
NOTES:
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.061
0.068
1.55
1.73
-
A1
0.004
0.0098
0.102
0.249
-
A2
0.055
0.061
1.40
1.55
-
B
0.008
0.012
0.20
0.31
9
C
0.0075
0.0098
0.191
0.249
-
D
0.189
0.196
4.80
4.98
3
E
0.150
0.157
3.81
3.99
4
e
0.025 BSC
0.635 BSC
-
H
0.230
0.244
5.84
6.20
-
h
0.010
0.016
0.25
0.41
5
L
0.016
0.035
0.41
0.89
6
8°
0°
N
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
MILLIMETERS
α
16
0°
16
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
7
8°
Rev. 2 6/04
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.10mm (0.004 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
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19
FN6047.10
May 16, 2011