CS4373A
Low-power, High-performance ∆Σ Test DAC
Features
Description
∆Σ Input from CS5376A Digital Filter
z Selectable Differential Analog Outputs
The CS4373A is a high-performance, differential output
digital-to-analog converter (DAC) with programmable attenuation and multiple operational modes. AC test
modes measure system dynamic performance through
THD and CMRR tests while DC test modes are for gain
calibration and pulse tests.
z Digital
• Precision output (OUT±) for electronics tests
• Buffered output (BUF±) for sensor tests
z Multiple
AC and DC Operational Modes
• Signal bandwidth: DC to 100 Hz
• Max AC amplitude: 5 VPP differential
• Max DC amplitude: + 2.5 Vdc differential
z Selectable
Attenuation for CS3301A / CS3302A
• 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64
z Outstanding
Performance
The CS4373A is driven by a ∆Σ digital bit stream from the
CS5376A digital filter test bit stream (TBS) generator. It
has two sets of differential analog outputs, OUT and
BUF, to simplify system design as dedicated outputs for
testing the electronics channel and for in-circuit sensor
tests. Analog output attenuation is selected by simple pin
settings
and
matches
the
gain
of
the
CS3301A / CS3302A differential amplifiers for full-scale
testing at all gain ranges.
• AC (OUT): -116 dB THD typical, -112 dB max
• AC (BUF): -108 dB THD typical, -90 dB max
• DC absolute accuracy: 0.4% typical, 1% max The CS4373A test DAC provides self-test and precision
z Low
Power Consumption
• AC modes / DC modes: 40 mW / 20 mW
• Sleep mode / Power Down: 1 mW / 10 µW
z Extremely
Small Footprint
calibration capability for high-resolution, low-frequency
multi-channel measurement systems designed from
CS3301A / CS3302A
differential
amplifiers,
CS5371A / CS5372A ∆Σ modulators and the CS5376A
digital filter.
• 28-pin SSOP package, 8 mm x 10 mm
z Bipolar
Power Supply Configuration
• VA+ = +2.5 V;VA- = -2.5 V; VD = +3.3 V
VA+
MODE(0, 1, 2)
ORDERING INFORMATION
See page 34.
ATT(0, 1, 2)
VD
TDATA
OUT+
Attenuator
OUTBUF+
24-Bit ∆Σ
DAC
BUF-
VREF+
VREF-
VA-
http://www.cirrus.com
MCLK
Clock
Generator
CAP+ CAP-
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
MSYNC
GND
DEC ‘06
DS699F2
CS4373A
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
2. GENERAL DESCRIPTION ..................................................................................................... 16
2.1 Digital Inputs .................................................................................................................... 16
2.2 Analog Outputs ................................................................................................................ 16
2.3 Multiple Operational Modes ............................................................................................. 16
2.4 Low Power ....................................................................................................................... 16
3. SYSTEM DIAGRAMS .......................................................................................................... 17
4. POWER MODES ..................................................................................................................... 18
4.1 Power Down ..................................................................................................................... 18
4.2 Sleep Modes .................................................................................................................... 18
4.3 AC Test Modes ................................................................................................................ 18
4.4 DC Test Modes ................................................................................................................ 18
5. OPERATIONAL MODES ........................................................................................................ 19
5.1 Sleep Modes .................................................................................................................... 19
5.2 AC Test Modes ................................................................................................................ 19
5.2.1 AC Differential ..................................................................................................... 19
5.2.2 AC Common Mode .............................................................................................. 20
5.2.3 AC Stability .......................................................................................................... 20
5.3 DC Test Modes ................................................................................................................ 20
5.3.1 DC Common Mode ............................................................................................. 20
5.3.2 DC Differential ..................................................................................................... 20
6. DIGITAL INPUTS .................................................................................................................... 22
6.1 TDATA Connection .......................................................................................................... 22
6.2 MCLK Connection ............................................................................................................ 22
6.3 MSYNC Connection ......................................................................................................... 22
6.4 GPIO Connections ........................................................................................................... 23
7. ANALOG OUTPUTS ............................................................................................................... 24
7.1 Differential Signals ........................................................................................................... 24
7.2 Analog Output Attenuation ............................................................................................... 24
7.3 OUT± Precision Output .................................................................................................... 25
7.4 BUF± Buffered Output ..................................................................................................... 25
7.5 CAP± Analog Output ........................................................................................................ 25
8. VOLTAGE REFERENCE ........................................................................................................ 26
8.1 VREF Power Supply ........................................................................................................ 26
8.2 VREF RC Filter ................................................................................................................ 26
8.3 VREF PCB Routing .......................................................................................................... 26
8.4 VREF Input Impedance .................................................................................................... 27
8.5 VREF Accuracy ................................................................................................................ 27
8.6 VREF Independence ....................................................................................................... 27
9. POWER SUPPLIES ................................................................................................................ 28
9.1 Power Supply Bypassing ................................................................................................. 28
9.2 PCB Layers and Routing ................................................................................................. 28
9.3 Power Supply Rejection ................................................................................................... 28
9.4 SCR Latch-up .................................................................................................................. 29
9.5 DC-DC Converters .......................................................................................................... 29
10. TERMINOLOGY .................................................................................................................... 30
11. PIN DESCRIPTION ............................................................................................................... 31
12. PACKAGE DIMENSIONS ..................................................................................................... 33
13. ORDERING INFORMATION ................................................................................................ 34
14. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .......................... 34
15. REVISION HISTORY ........................................................................................................... 34
2
DS699F2
CS4373A
LIST OF FIGURES
Figure 1. Digital Input Rise and Fall Times ................................................................................... 12
Figure 2. System Timing Diagram................................................................................................. 14
Figure 3. MCLK / MSYNC Timing Detail ....................................................................................... 14
Figure 4. CS4373A Block Diagram ............................................................................................... 16
Figure 6. Connection Diagram ...................................................................................................... 17
Figure 5. System Diagram ............................................................................................................ 17
Figure 7. Power Mode Diagram .................................................................................................... 18
Figure 8. AC Differential Modes .................................................................................................... 19
Figure 9. AC Common Mode ........................................................................................................ 20
Figure 10. DC Test Modes ............................................................................................................ 21
Figure 11. Digital Inputs ................................................................................................................ 22
Figure 12. Analog Outputs ............................................................................................................ 24
Figure 13. Voltage Reference Circuit ............................................................................................ 26
Figure 14. Power Supply Diagram ................................................................................................ 28
LIST OF TABLES
Table 1. Selections for Operational Mode and Attenuation............................................................. 4
Table 2. Operational Modes.......................................................................................................... 19
Table 3. Output Attenuation Settings ............................................................................................ 24
DS699F2
3
CS4373A
1.
CHARACTERISTICS AND SPECIFICATIONS
•
Min / Max characteristics and specifications are guaranteed over the Specified Operating Conditions.
•
Typical performance characteristics and specifications are measured at nominal supply voltages and TA = 25°C.
•
GND = 0 V. Single-ended voltages with respect to GND, differential voltages with respect to opposite half.
•
Device is connected as shown in Figure 6 on page 17, unless otherwise noted.
SPECIFIED OPERATING CONDITIONS
Parameter
Symbol
Min
Nom
Max
Unit
VA+
2.45
2.50
2.55
V
VA-
-2.45
-2.50
-2.55
V
VD
3.20
3.30
3.40
V
(Note 2, 3)
VREF
-
2.500
-
V
(Note 4)
VREF-
-
VA -
-
V
TA
-40
25
85
°C
Bipolar Power Supplies
± 2%
(Note 1) ± 2%
± 3%
Positive Analog
Negative Analog
Positive Digital
Voltage Reference Input
{VREF+} - {VREF-}
VREFThermal
Ambient Operating Temperature
Industrial (-IS, -ISZ)
Notes: 1. VA- must always be the most-negative input voltage to avoid potential SCR latch-up conditions.
2. By design, a 2.500 V voltage reference input results in the best signal-to-noise performance.
3. Full-scale accuracy is directly proportional to the voltage reference absolute accuracy.
4. VREF inputs must satisfy: VA- < VREF- < VREF+ < VA+.
Attenuation
Modes of Operation
Selection
ATT[2:0]
Attenuation
dB
Sleep mode.
0
000
1/1
0 dB
001
AC OUT and BUF outputs.
1
001
1/2
-6.02 dB
2
010
AC OUT only, BUF high-z.
2
010
1/4
-12.04 dB
3
0 11
AC BUF only, OUT high-z.
3
0 11
1/8
-18.06 dB
4
100
DC common mode output.
4
100
1/16
-24.08 dB
5
101
DC differential output.
5
101
1/32
-30.10 dB
6
11 0
AC common mode output.
6
11 0
1/64
-36.12 dB
7
111
Sleep mode.
7
111
reserved
reserved
Selection
MODE[2:0]
0
000
1
Mode Description
Table 1. Selections for Operational Mode and Attenuation
4
DS699F2
CS4373A
TEMPERATURE CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
TA
-40
-
+85
ºC
Storage Temperature Range
TSTG
-65
-
150
ºC
Allowable Junction Temperature
TJCT
-
-
125
ºC
Junction to Ambient Thermal Impedance (4-layer PCB)
ΘJA
-
65
-
ºC / W
Ambient Operating Temperature
ABSOLUTE MAXIMUM RATINGS
Parameter
DC Power Supplies
Positive Analog
Negative Analog
Digital
Symbol
Min
Max
Parameter
VA+
VAVD
-0.5
-6.8
-0.5
6.8
0.5
6.8
V
V
V
Analog Supply Differential
(VA+) - (VA-)
VADIFF
-
6.8
V
Digital Supply Differential
(VD) - (VA-)
VDDIFF
-
7.6
V
mA
IOUT
-
±50
±10
±25
Power Dissipation
PDN
-
500
mW
Analog Input Voltages
VINA
(VA-) - 0.5
(VA+) + 0.5
V
Digital Input Voltages
VIND
-0.5
(VD) + 0.5
V
Input Current, Power Supplies
(Note 5)
IIN
-
Input Current, Any Pin Except Supplies
(Note 5)
IIN
-
Output Current
(Note 5)
mA
mA
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Notes: 5. Transient currents up to ±100 mA will not cause SCR latch-up.
DS699F2
5
CS4373A
ANALOG CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
VREF
-
2.500
-
V
VREF Input
{VREF+} - {VREF-}
VREF-
(Note 2, 3)
VREF-
-
VA -
-
V
VREF Input Current, AC modes
(Note 4)
VREFIAC
-
80
-
µA
VREF Input Current, DC modes
VREFIDC
-
40
-
µA
VREFIN
-
-
1
µVrms
RLOUT
CLOUT
50
-
-
50
MΩ
pF
VREF Input Noise
(Note 6)
Analog OUT± Output
Analog External Load at OUT±
(Note 7, 8)
Load Resistance
Load Capacitance
Differential Output Impedance
1/1
1/2
1/4
1/8
1/16
1/32
1/64
ZDIFOUT
-
1.4
10.1
7.9
5.1
3.3
2.3
1.7
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
Single-ended Output Impedance
1/1
1/2
1/4
1/8
1/16
1/32
1/64
ZSEOUT
-
0.7
7.4
9.0
9.4
9.5
9.5
9.4
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
High-Z Impedance
(Note 8)
HZOUT
-
3
-
MΩ
Crosstalk to BUF± High-Z Output
(Note 8)
XTOUT
-
-120
-
dB
Load Resistance
Load Capacitance
RLBUF
CLBUF
1
-
-
2
kΩ
nF
1/1 - 1/64
ZDIFBUF
-
6
-
Ω
1/1 - 1/32
(Note 9) (BUF-) 1/64
(Note 9) (BUF+) 1/64
ZSEBUF
-
3
3
50
-
Ω
Analog BUF± Output
Analog External Load at BUF±
(Note 8)
Differential Output Impedance
Single-ended Output Impedance
High-Z Impedance
(Note 8)
HZBUF
-
4.5
-
MΩ
Crosstalk to OUT± High-Z Output
(Note 8)
XTBUF
-
-120
-
dB
Notes: 6. Maximum integrated noise over the measurement bandwidth for the voltage reference device attached
to the VREF± inputs.
7. Load on the precision OUT± outputs is normally from the CS3301A / CS3302A amplifiers, which have
1 GΩ/1 TΩ typical input impedance and 18 pF typical input capacitance.
8. Guaranteed by design and/or characterization.
9. Single-ended output impedance at 1/64 is different for BUF+ and BUF- due to the output attenuator
architecture.
6
DS699F2
CS4373A
AC DIFFERENTIAL MODES 1, 2, 3
Parameter
Symbol
Min
Typ
Max
Unit
1/1
1/2
1/4
1/8
1/16
1/32
1/64
VACFS
-
5
2.5
1.25
625
312.5
156.25
78.125
-
Vpp
Vpp
Vpp
mVpp
mVpp
mVpp
mVpp
(Note 8)
VACBW
-
-
100
Hz
(Note 8, 10)
VACIMP
-
-
-20
dBfs
Full-scale Accuracy
(Note 3, 11)
1/1
VACABS
- 0.5
- 0.2
0.2
%FS
Relative Accuracy
(Note 12)
1/2
1/4
1/8
1/16
1/32
1/64
VACREL
- 0.2
-
± 0.1
± 0.1
± 0.1
- 0.1 ± 0.2
- 0.2 ± 0.3
- 0.5 ± 0.5
0.2
-
%
%
%
%
%
%
(Note 14)
VACTC
-
25
-
µV/°C
(Note 13)
VACCM
-
(VA-)+2.35
-
V
-
300
-
µV/°C
AC Differential Characteristics
Full-scale Differential AC Output
Full-scale Bandwidth
Impulse Amplitude
AC Differential Accuracy
Full-scale Drift
DC Common Mode Characteristics
Common Mode
Common Mode Drift
(Note 13, 14) VACCMTC
Notes: 10. Maximum amplitude for operation above 100 Hz. A reduced amplitude for higher frequencies is required
to guarantee stability of the low-power delta-sigma architecture.
11. Full-scale accuracy compares the defined full-scale 1/1 amplitude to the measured 1/1 amplitude.
Specification is for unloaded outputs. Applying a differential load lowers the output amplitude ratiometric
to the differential output impedance.
12. Relative accuracy compares the measured 1/2,1/4,1/8,1/16,1/32,1/64 amplitude to the measured 1/1
amplitude.
13. Common mode voltage is defined as [(SIG+) + (SIG-)] / 2.
14. Specification is for the parameter over the specified temperature range and is for the device only. It does
not include the effects of external components.
DS699F2
7
CS4373A
AC DIFFERENTIAL MODES 1, 2, 3 (CONT.)
Parameter
Symbol
Min
Typ
Max
Unit
Signal to Noise
Signal to Noise
(OUT± Unloaded)
(Note 15)
1/1
1/2
1/4
1/8
1/16
1/32
1/64
-> 1x
-> 2x
-> 4x
-> 8x
-> 16x
-> 32x
-> 64x
SNROUT
-
114
114
114
113
111
108
103
-
dB
dB
dB
dB
dB
dB
dB
Signal to Noise
(BUF± Unloaded, 1 kΩ Load)
(Note 15, 16)
1/1
1/2
1/4
1/8
1/16
1/32
1/64
-> 1x
-> 2x
-> 4x
-> 8x
-> 16x
-> 32x
-> 64x
SNRBUF
-
110
106
101
95
89
83
77
-
dB
dB
dB
dB
dB
dB
dB
Total Harmonic Distortion
(OUT± Unloaded)
(Note 17, 18)
1/1
1/2
1/4
1/8
1/16
1/32
1/64
-> 1x
-> 2x
-> 4x
-> 8x
-> 16x
-> 32x
-> 64x
THDOUT
-
- 116
- 115
- 114
- 112
- 111
- 110
- 106
- 112
-
dB
dB
dB
dB
dB
dB
dB
Total Harmonic Distortion
(BUF± Unloaded)
(Note 16, 17, 18)
1/1
1/2
1/4
1/8
1/16
1/32
1/64
-> 1x
-> 2x
-> 4x
-> 8x
-> 16x
-> 32x
-> 64x
THDBUF
-
- 108
- 105
- 100
- 94
- 88
- 82
- 76
- 90
-
dB
dB
dB
dB
dB
dB
dB
Total Harmonic Distortion
(BUF± 1 kΩ Load)
(Note 16, 17, 18)
1/1
1/2
1/4
1/8
1/16
1/32
1/64
-> 1x
-> 2x
-> 4x
-> 8x
-> 16x
-> 32x
-> 64x
THDBUFL
-
- 102
- 101
- 97
- 92
- 87
- 82
- 76
- 80
-
dB
dB
dB
dB
dB
dB
dB
Total Harmonic Distortion
Notes: 15. Specification measured using CS3301A amplifier at corresponding gain with the CS5371A / CS5372A
modulator measuring a 430 Hz bandwidth. Amplified noise dominates for x16, x32, x64 amplifier gains.
16. Buffered outputs (BUF±) include 1/f noise not present on the precision outputs (OUT±).
17. Tested with a 31.25 Hz sine wave at -1 dB amplitude.
18. Specification measured using CS3301A amplifier at corresponding gain using the CS5371A / CS5372A
modulator measuring a 430 Hz bandwidth. Amplified noise in the harmonic bins dominates THD
measurements for x16, x32, x64 amplifier gains.
8
DS699F2
CS4373A
DC COMMON MODE 4
Parameter
Symbol
Min
Typ
Max
Unit
VDCCM
-
(VA-)+2.35
-
V
-
300
-
µV/°C
VDCCMM
-5
±1
5
mV
DC Common Mode Characteristics
Common Mode Output
Common Mode Drift
(Note 14) VDCCMTC
DC Common Mode Accuracy
Common Mode Match
1/1
Noise
Noise (OUT± Unloaded)
(Note 15)
1/1
1/2
1/4
1/8
1/16
1/32
1/64
-> 1x
-> 2x
-> 4x
-> 8x
-> 16x
-> 32x
-> 64x
NOUT
-
6
7
7
7
7
9
14
-
µVrms
µVrms
µVrms
µVrms
µVrms
µVrms
µVrms
Noise (BUF± Unloaded, 1 kΩ Load)
(Note 15, 16)
1/1
1/2
1/4
1/8
1/16
1/32
1/64
-> 1x
-> 2x
-> 4x
-> 8x
-> 16x
-> 32x
-> 64x
NBUF
-
7
10
17
33
64
130
257
-
µVrms
µVrms
µVrms
µVrms
µVrms
µVrms
µVrms
DS699F2
9
CS4373A
DC DIFFERENTIAL MODE 5
Parameter
Symbol
Min
Typ
Max
Unit
1/1
1/2
1/4
1/8
1/16
1/32
1/64
VDCFS
-
2.5
1.25
625
312.5
156.25
78.125
39.0625
-
V
V
mV
mV
mV
mV
mV
Full-scale Accuracy
(Note 3, 11)
1/1
VDCABS
- 1.0
- 0.4
0.2
%FS
Relative Accuracy
(Note 12)
1/2
1/4
1/8
1/16
1/32
1/64
VDCREL
- 0.2
-
± 0.1
± 0.1
-0.1 ± 0.4
-0.2 ± 0.9
-0.5 ± 1.7
-1.0 ± 3.6
0.2
-
%
%
%
%
%
%
(Note 14)
VDCTC
-
25
-
µV/°C
(Note 13)
VDCCM
-
(VA-)+2.35
-
V
-
300
-
µV/°C
DC Differential Mode Characteristics
Full-scale Differential DC Output
(Note 19)
DC Differential Accuracy
Full-scale Drift
DC Common Mode Characteristics
Common Mode
Common Mode Drift
(Note 13, 14) VDCCMTC
Noise
Noise (OUT± Unloaded)
(Note 15, 19)
1/1
1/2
1/4
1/8
1/16
1/32
1/64
-> 1x
-> 2x
-> 4x
-> 8x
-> 16x
-> 32x
-> 64x
NOUT
-
9
9
9
9
10
11
15
-
µVrms
µVrms
µVrms
µVrms
µVrms
µVrms
µVrms
Noise (BUF± Unloaded, 1 kΩ Load)
(Note 15, 16, 19)
1/1
1/2
1/4
1/8
1/16
1/32
1/64
-> 1x
-> 2x
-> 4x
-> 8x
-> 16x
-> 32x
-> 64x
NBUF
-
10
12
18
32
67
122
265
-
µVrms
µVrms
µVrms
µVrms
µVrms
µVrms
µVrms
Notes: 19. DC differential output is chopper stabilized and includes low-level 32 kHz out-of-band noise which is
rejected by the digital filter during acquisition.
10
DS699F2
CS4373A
AC COMMON MODE 6
Parameter
Symbol
Min
Typ
Max
Unit
VCMFS
-
2.5
1.25
625
312.5
156.25
78.125
-
Vpp
Vpp
mVpp
mVpp
mVpp
mVpp
(Note 8)
VCMBW
-
-
100
Hz
(Note 8, 10)
VCMIMP
-
-
-20
dBfs
Common Mode Match (OUT± Unloaded)
(Note 17, 20)
VCMCMM
-
-115
-105
dB
Common Mode Match (BUF± Unloaded, 1 kΩ Load)
(Note 16, 17, 20)
VCMCMM
-
-95
-85
dB
1/1
VACABS
-
- 0.3
-
%FS
1/2
1/4
1/8
1/16
1/32
VACREL
-
- 0.1
- 0.5
- 1.0
-2.0
-5.0
-
%
%
%
%
%
(Note 14)
VCMTC
-
25
-
µV/°C
(Note 21)
VCMCM
-
(VA-)+2.35
-
V
-
300
-
µV/°C
AC Common Mode Characteristics
Full-scale Common Mode AC Output
(Note 20)
Full-scale Bandwidth
Impulse Amplitude
1/1
1/2
1/4
1/8
1/16
1/32
AC Common Mode Accuracy
Full-scale Accuracy
(Note 3, 11)
Relative Accuracy
(Note 12, 20)
Full-scale Drift
DC Common Mode Characteristics
Common Mode Mean
Common Mode Mean Drift
(Note 14, 21) VCMCMTC
Notes: 20. No AC common mode signal is output at 1/64 attenuation due to the attenuator architecture.
21. Common mode mean is defined as [(SIGmax) + (SIGmin)] / 2.
DS699F2
11
CS4373A
DIGITAL CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
-
VD
V
Digital Inputs
High-level Input Drive Voltage
(Note 22)
VIH
0.6*VD
Low-level Input Drive Voltage
(Note 22)
VIL
0.0
-
0.8
V
IIN
-
+1
+10
µA
Input Leakage Current
Digital Input Capacitance
(Note 8)
CIN
-
9
-
pF
Rise Times Except MCLK
(Note 8)
tRISE
-
-
100
ns
Fall Times Except MCLK
(Note 8)
tFALL
-
-
100
ns
(Note 23)
ftdata
-
256
-
kbits/s
(Note 8)
INROD
25
-
75
%
TBSGAIN Full-scale Code
(Note 24)
TBSFS
-
0x04B8F2
-
TBSGAIN -20 dB Code
(Note 24)
TBS-20dB
-
0x0078E5
-
TDATA Input
TDATA Input Bit Rate
TDATA Input One’s Density Range
Notes: 22. Device is intended to be driven with CMOS logic levels.
23. TDATA is generated by the test bit stream generator in the CS5376A digital filter.
24. TBSGAIN register value in the CS5376A digital filter.
t rise
t fall
0.9 * VD
0.1 * VD
Figure 1. Digital Input Rise and Fall Times
12
DS699F2
CS4373A
DIGITAL CHARACTERISTICS (CONT.)
Parameter
Symbol
Min
Typ
Max
Unit
fCLK
-
2.048
-
MHz
Master Clock
MCLK Frequency
(Note 25)
MCLK Period
(Note 25)
tmclk
-
488
-
ns
MCLK Duty Cycle
(Note 8)
MCLKDC
40
-
60
%
MCLK Rise Time
(Note 8)
tRISE
-
-
50
ns
MCLK Fall Time
(Note 8)
tFALL
-
-
50
ns
MCLK Jitter (In-band or aliased in-band)
(Note 8)
MCLKIBJ
-
-
300
ps
MCLK Jitter (Out-of-band)
(Note 8) MCLKOBJ
-
-
1
ns
Master Sync
MSYNC Setup Time to MCLK rising
(Note 8, 26)
tmss
20
122
-
ns
MSYNC Period
(Note 8, 26)
tmsync
40
976
-
ns
MSYNC Hold Time after MCLK falling
(Note 8, 26)
tmsh
20
122
-
ns
MSYNC Instant to TDATA Start
(Note 8, 27)
ttdata
-
1220
-
ns
Notes: 25. MCLK is generated by the CS5376A digital filter. If MCLK is disabled, the device automatically enters
a power-down state.
26. MSYNC is generated by the CS5376A digital filter and is latched on MCLK rising edge, synchronization
instant (t0) on next MCLK rising edge.
27. TDATA can be delayed from 0 to 63 full bit periods by the CS5376A test bit stream generator. The timing
diagram shows no TBSDATA delay.
DS699F2
13
CS4373A
DIGITAL CHARACTERISTICS (CONT.)
SYNC
MCLK
(2.048 MHz)
MSYNC
t0
TDATA
(256 kHz)
Figure 2. System Timing Diagram
MCLK
(2.048 MHz)
MSYNC
tmss
tmsh
tmclk
t0
tmsync
TDATA
(256 kHz)
ttdata
Figure 3. MCLK / MSYNC Timing Detail
14
DS699F2
CS4373A
POWER SUPPLY CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
AC Mode Supply Current (MODE = 1, 2, 3, 6)
Analog Power Supply Current
(Note 28)
IA
-
8
10
mA
Digital Power Supply Current
(Note 28)
ID
-
20
-
µA
DC Mode Supply Current (MODE = 4)
Analog Power Supply Current
(Note 28)
IA
-
2.7
-
mA
Digital Power Supply Current
(Note 28)
ID
-
20
-
µA
Analog Power Supply Current
(Note 28)
IA
-
4.2
-
mA
Digital Power Supply Current
(Note 28)
ID
-
20
-
µA
Analog Power Supply Current
(Note 28)
IA
-
200
-
µA
Digital Power Supply Current
(Note 28)
ID
-
260
-
µA
Analog Power Supply Current
(Note 28)
IA
-
1
-
µA
Digital Power Supply Current
(Note 28)
ID
-
20
-
µA
(Note 8)
PDTC
-
40
-
µS
(Note 29)
PSRR
-
90
-
dB
DC Mode Supply Current (MODE = 5)
Sleep Mode Supply Current (MODE = 0, 7)
Power Down Supply Current (MCLK = 0)
Time to Enter Power Down (MCLK disabled)
Power Supply Rejection
Power Supply Rejection Ratio
Notes: 28. All outputs unloaded. Digital inputs forced to VD or DGND respectively.
29. Power supply rejection is characterized by applying a 100 mVp-p 50-Hz sine wave to each supply.
DS699F2
15
CS4373A
VA+
MODE(0, 1, 2)
ATT(0, 1, 2)
VD
TDATA
OUT+
Attenuator
OUTBUF+
24-Bit ∆Σ
DAC
BUF-
VREF+
VREF-
MCLK
Clock
Generator
VA-
CAP+ CAP-
MSYNC
GND
Figure 4. CS4373A Block Diagram
2. GENERAL DESCRIPTION
The CS4373A is a differential output digital-toanalog converter with multiple operational
modes and programmable output attenuation.
It provides self-test and precision calibration
capability for high-resolution, low-frequency
measurement systems designed from
CS3301A / CS3302A differential amplifiers,
CS5371A / CS5372A ∆Σ modulators, and the
CS5376A digital filter.
2.1 Digital Inputs
The CS4373A is driven by a ∆Σ digital bit
stream from the CS5376A digital filter test bit
stream (TBS) generator. The digital filter also
provides clock and sync signals as well as
GPIO control signals to set the operational
mode and attenuation.
2.2 Analog Outputs
Two sets of differential analog outputs, OUT
and BUF, simplify system design as dedicated
outputs for testing the electronics channel and
for in-circuit sensor tests. Output attenuator
settings are binary weighted (1, 1/2, 1/4, 1/8,
1/16,
1/32,
1/64)
and
match
the
CS3301A / CS3302A amplifier input levels for
full-scale testing at all gain ranges.
16
For maximum performance, the precision outputs (OUT±) must drive only high-impedance
loads such as the CS3301A / CS3302A amplifier inputs. The buffered outputs (BUF±) can
drive lower-impedance loads, down to 1 kΩ,
but with reduced performance compared to
the precision outputs.
2.3 Multiple Operational Modes
The CS4373A operates in either AC or DC test
modes. AC test modes (MODE 1, 2, 3, 6) are
used to measure system THD and CMRR performance. DC test modes (MODE 4, 5) are for
gain calibration and pulse tests.
2.4 Low Power
The CS4373A is optimized for low-power operation and has a restricted operational bandwidth in the AC modes. For stable operation,
full-scale AC test signals must not contain frequencies above 100 Hz. AC test signals above
100 Hz (TBS impulse mode, for example)
must have a -20 dB reduced amplitude to ensure stability of the CS4373A low-power ∆Σ architecture.
DS699F2
CS4373A
3. SYSTEM DIAGRAMS
Geophone
or
Hydrophone
Sensor
CS3301A
CS3302A
M
U
X
Geophone
or
Hydrophone
Sensor
CS5371A
CS5372A
AMP
System Telem etry
∆Σ
Modulator
CS3301A
CS3302A
M
U
X
AMP
µController
or
Configuration
EEPROM
CS5376A
Digital Filter
Geophone
or
Hydrophone
Sensor
CS3301A
CS3302A
M
U
X
Geophone
or
Hydrophone
Sensor
CS5371A
CS5372A
AMP
∆Σ
Modulator
CS3301A
CS3302A
M
U
X
Com m unication
Interface
AMP
CS4373A
Test
DAC
Switch
Switch
MUX
MUX
Figure 5. System Diagram
VA+
0.1µF
SWITCH
CONTROL
0.1µF
VA-
10nF
C0G
SENSOR
CAP-
CH1 BUF
CH2 BUF
Analog
Switches
CH3 BUF
CH4 BUF
Route BUF as diff pair
BUF+
TDATA
CS4373A
Route OUT as diff pair
OUT+
OUT-
VA+
10 Ω
2.5 V
VREF
MCLK
MSYNC
TBSDATA
BUF-
ELECTRONICS
CH1,2,3,4 OUT
Route VREF as diff pair
100µF
VREF+
VREF-
+
VA-
VA-
VD
MCLK
MSYNC
CAP+
VD
VA-
0.1µF
MODE0
MODE1
MODE2
GPIO
GPIO
ATT0
ATT1
ATT2
GPIO
GPIO
DGND
GPIO
GPIO
CS5376A
SIGNALS
Figure 6. Connection Diagram
DS699F2
17
CS4373A
POWER DOWN
MCLK = OFF
MODE = XXX
SLEEP MODES
MCLK = ON
MODE = 0, 7
AC TEST MODES
MCLK = ON
MODE = 1, 2, 3, 6
DC TEST MODES
MCLK = ON
MODE = 4, 5
Figure 7. Power Mode Diagram
4. POWER MODES
The CS4373A has four power modes. AC test
modes and DC test modes are operational
modes, while the power down and sleep
modes are non-operational, standby modes.
sleep mode for normal data acquisition. In
sleep mode the AC and DC test circuitry is inactive and the analog outputs are high impedance.
4.1 Power Down
If MCLK is stopped, an internal loss-of-clock
detection circuit automatically places the
CS4373A into power down. Power down is independent of the MODE and ATT pin settings,
and is automatically invoked after approximately 40 µs without an incoming MCLK edge.
4.3 AC Test Modes
With MCLK and TDATA active, selecting an
AC test mode (MODE 1, 2, 3, 6) causes the
CS4373A to output AC waveforms on the enabled analog outputs. AC test modes use the
low-power ∆Σ circuitry in the CS4373A to create precision differential or common mode analog AC output signals from the encoded
digital test bit stream (TBS) input.
In power down the AC and DC test circuitry is
inactive and the analog outputs are high impedance. When used with the CS5376A digital
filter, the CS4373A is powered down immediately after reset since MCLK is disabled by default.
4.2 Sleep Modes
With MCLK enabled, selecting either of the
sleep modes (MODE 0, 7) places the
CS4373A into a micropower sleep state. Following completion of the AC and DC system
self-tests, the CS4373A is typically set into
18
4.4 DC Test Modes
With MCLK active, selecting a DC test mode
(MODE 4, 5) causes the CS4373A to generate
precision DC voltages on the analog outputs.
DC test modes use switch-capacitor levelshifting buffer circuitry in the CS4373A to create differential or common mode DC analog
output voltages from the voltage reference input.
DS699F2
CS4373A
5. OPERATIONAL MODES
The CS4373A has six operational modes and
two sleep modes selected by the MODE2,
MODE1, and MODE0 pins.
only the BUF analog output is enabled, and
OUT is high impedance.
OUT+
Selection MODE[2:0]
Mode Description
OUT-
CS4373A
MODE 1
0
000
Sleep mode.
1
001
AC OUT and BUF outputs.
2
010
AC OUT only, BUF high-z.
3
0 11
AC BUF only, OUT high-z.
4
100
DC common mode output.
5
101
DC differential output.
6
11 0
AC common mode output.
OUT+
7
111
Sleep mode.
OUT-
Table 2. Operational Modes
BUF+
BUF-
5.2 AC Test Modes
AC test modes use the digital test bit stream
(TBS) input from the CS5376A digital filter to
construct analog AC waveforms. The digital bit
stream input to the TDATA pin encodes the
analog waveform as over-sampled one bit ∆Σ
data, which is then converted into precision
differential or common mode analog AC signals by the CS4373A.
5.2.1
AC Differential
The first three AC test modes (MODE 1, 2, 3)
create precision differential analog signals for
THD and impulse testing of the measurement
channel. In mode 1, both sets of differential analog outputs (OUT and BUF) are enabled. In
mode 2 only the OUT analog output is enabled, and BUF is high impedance. In mode 3
DS699F2
Maximum
5 Vpp
Differential
Maximum
5 Vpp
Differential
CS4373A
MODE 2
BUF+
5.1 Sleep Modes
Sleep modes (MODE 0, 7) save power during
normal acquisition by turning off the AC and
DC test circuitry after system self-tests are
complete. In sleep mode the OUT and BUF
analog outputs are high impedance.
Maximum
5 Vpp
Differential
BUF-
OUT+
OUT-
High
Impedance
High
Impedance
CS4373A
MODE 3
BUF+
BUF-
Maximum
5 Vpp
Differential
Figure 8. AC Differential Modes
Differential AC signals out of the CS4373A
consist of two halves with equal but opposite
magnitude, varying about a common mode
voltage. A full-scale 5 VPP differential AC signal centered on a -0.15 V common mode voltage will have:
SIG+ = -0.15 V + 1.25 V = +1.1 V
SIG- = -0.15 V - 1.25 V = -1.4 V
SIG+ is +2.5 V relative to SIG19
CS4373A
For the opposite case:
SIG+ = -0.15 V - 1.25 V = -1.4 V
SIG- = -0.15 V + 1.25 V = +1.1 V
SIG+ is -2.5 V relative to SIGSo the total swing for SIG+ relative to SIG- is
(+2.5 V) - (-2.5 V) = 5 Vpp differential. A similar
calculation can be done for SIG- relative to
SIG+. It’s important to note that a 5 Vpp differential signal centered on a -0.15 V common
mode voltage never exceeds +1.1 V with respect to ground and never drops below -1.4 V
with respect to ground on either half. By definition, differential voltages are measured with
respect to the opposite half, not relative to
ground. A voltmeter differentially measuring
between SIG+ and SIG- in the above example
would read 1.767 Vrms, or 5 Vpp.
5.2.2
AC Common Mode
The final AC test mode (MODE 6) creates a
matched AC common mode analog signal for
CMRR testing of the measurement channel. In
mode 6, both sets of analog outputs (OUT and
BUF) are enabled. There is no common mode
AC waveform output for an attenuator setting
of 1/64.
OUT+
OUT-
Maximum
2.5 Vpp
Common
Mode
CS4373A
MODE 6
BUF+
BUF-
Maximum
2.5 Vpp
Common
Mode
Figure 9. AC Common Mode
Gross leakage in the sensor channel can be
detected by applying a full-scale AC common
mode signal. If there is a significant differential
mismatch in the channel due to sensor leakage, the AC common mode signal will be con20
verted to a measurable differential signal at
the fundamental frequency.
5.2.3
AC Stability
For the CS4373A low-power ∆Σ architecture to
remain stable, the TDATA input bit stream
should only encode 100 Hz or lower bandwidth analog signals. For TDATA bit stream
frequencies above 100 Hz (for example, TBS
impulse mode), the encoded amplitude must
be reduced -20 dB below full scale to guarantee stability.
If the CS4373A low-power ∆Σ architecture becomes unstable, persistent elevated noise will
be present on the analog outputs and AC linearity will be poor. To recover stability, place
the CS4373A into power down or sleep mode
and restart the CS5376A test bit stream generator before placing the CS4373A back into an
AC test mode.
5.3 DC Test Modes
DC test modes create precision level-shifted
and buffered versions of the voltage reference
input as precision DC common mode and DC
differential analog outputs. The absolute accuracy of the DC test modes is highly dependent
on the absolute accuracy of the voltage reference input voltage.
5.3.1
DC Common Mode
The first DC test mode (MODE 4) creates a
matched DC common mode analog output
voltage as a baseline measurement for gain
calibration and differential pulse tests. In mode
4, both sets of analog outputs (OUT and BUF)
are enabled.
5.3.2
DC Differential
The second DC test mode (MODE 5) creates
a precision differential DC analog output voltage as the final measurement for gain calibration and as the step/pulse output for
differential pulse tests. In mode 5, both sets of
analog outputs (OUT and BUF) are enabled.
DS699F2
CS4373A
In DC differential output mode (MODE 5) the
level-shifting buffer circuitry adds low-level
32 kHz switched-capacitor noise to the DC
output. This noise is out of the measurement
bandwidth for systems designed with
CS3301A / CS3302A
amplifiers
and
CS5371A / CS5372A modulators, and is rejected by the CS5376A digital filter. This
32 kHz switch-capacitor noise does not affect
DC system tests, though it may be visible on
an oscilloscope at high gain levels.
OUT+
OUT-
Approx
-0.15 VDC
Common
Mode
CS4373A
MODE 4
BUF+
BUF-
OUT+
OUT-
Approx
-0.15 VDC
Common
Mode
Maximum
2.5 VDC
Differential
CS4373A
MODE 5
BUF+
BUF-
Maximum
2.5 VDC
Differential
Figure 10. DC Test Modes
By measuring both DC test modes
(MODE 4, 5), precision gain-calibration coefficients can be calculated for the measurement
DS699F2
channel. By first measuring the differential offset of the DC common mode output (MODE 4)
and then measuring the DC differential mode
amplitude (MODE 5), a precise offset corrected volts-to-codes conversion ratio can be calculated. This known ratio is then used to
normalize the full-scale amplitude using the
CS5376A digital filter GAIN registers to match
other channels in the measurement network.
By switching between DC common mode
(MODE 4) and DC differential mode
(MODE 5), pulse waveforms can be created to
characterize the step response of the measurement channel. If a pulse test requires precise timing control, an external controller
should directly toggle the MODE pins of the
CS4373A to avoid delays associated with writing to the CS5376A digital filter GPIO registers.
Sensor impedance can be measured using
DC differential mode (MODE 5), provided
matched series resistors are installed between
the BUF analog outputs and the sensor. Applying the known DC differential voltage to the
resistor-sensor-resistor string permits a ratiometric sensor impedance calculation from the
measured voltage drop across the sensor.
Switching between DC differential mode
(MODE 5) and sleep mode (MODE 0, 7) can,
in the case of a moving-coil geophone, test basic parameters of the electro-mechanical
transfer function. The voltage relaxation characteristic of the sensor when switching the analog outputs from a differential DC voltage to
high impedance depends primarily on the geophone resonant frequency and damping factor.
21
CS4373A
VA+
0.1µF
SWITCH
CONTROL
0.1µF
VA-
10nF
C0G
SENSOR
CAP+
Analog
Switches
CH2 BUF
CH3 BUF
Route BUF as diff pair
VD
MCLK
MSYNC
CAP-
CH1 BUF
BUF+
TDATA
CS4373A
ELECTRONICS
CH1,2,3,4 OUT
Route OUT as diff pair
OUT+
OUT-
10 Ω
2.5 V
VREF
Route VREF as diff pair
100µF
MCLK
MSYNC
TBSDATA
BUF-
CH4 BUF
VA+
VD
VREF+
VREF-
+
VA-
VA-
VA-
0.1µF
MODE0
MODE1
MODE2
GPIO
ATT0
ATT1
ATT2
GPIO
DGND
GPIO
GPIO
GPIO
GPIO
CS5376A
SIGNALS
Figure 11. Digital Inputs
6. DIGITAL INPUTS
The CS4373A is designed to operate with the
CS5376A digital filter. The digital filter generates one-bit ∆Σ test bit stream data (TDATA),
a master clock (MCLK) and a synchronization
signal (MSYNC). In addition, the digital filter
GPIO pins control the CS4373A operational
mode (MODE) and attenuator (ATT) settings.
6.1 TDATA Connection
The TDATA digital input expects encoded
one-bit ∆Σ data nominally at a 256 kHz rate.
The one’s density input range is approximately
25% minimum to 75% maximum, with differential mid-scale at 50% one’s density.
The CS5376A digital filter test bit stream
(TBS) generator can encode two types of AC
signals as over-sampled, one-bit ∆Σ data - a
pure sine wave for THD and CMRR testing or
a triggerable impulse waveform for synchronization testing and impulse response characterization. In the AC operational modes, the
CS4373A converts the over-sampled bit
stream digital data into precision differential or
common mode analog AC signals.
The CS5376A TBS sine mode encodes an approximately 5 Vpp full-scale sine wave signal
with a digital filter TBSGAIN register setting of
0x04B8F2. Because TBS impulse mode encodes frequencies above 100 Hz, a maximum
0x0078E5 TBSGAIN impulse mode register
setting is specified to guarantee stability of the
22
CS4373A low-power ∆Σ circuitry. Details on
the setup and operation of the digital filter TBS
generator can be found in the CS5376A data
sheet.
6.2 MCLK Connection
The CS5376A digital filter generates the master clock for CS4373A, typically 2.048 MHz,
from a synchronous CLK input from the external system. By default, MCLK is disabled at reset and is enabled by writing the digital filter
CONFIG register. If MCLK is disabled during
operation, the CS4373A will enter power down
after approximately 40 µS.
MCLK must have low in-band jitter to guarantee full analog performance, requiring a crystal- or VCXO-based system clock into the
digital filter. Clock jitter on the digital filter external CLK input directly translates to jitter on
MCLK.
6.3 MSYNC Connection
The CS5376A digital filter also provides a synchronization signal to the CS4373A. The
MSYNC signal is generated following a rising
edge received on the digital filter SYNC input.
By default MSYNC generation is disabled at
reset and is enabled by writing to the digital filter CONFIG register.
The input SYNC signal to the CS5376A digital
filter sets a common reference time t0 for meaDS699F2
CS4373A
surement events, thereby synchronizing analog sampling across a measurement network.
The timing accuracy of the input SYNC signal
from measurement node to measurement
node must be +/- 1 MCLK to maximize
MSYNC analog sample synchronization accuracy.
The CS4373A MSYNC input is rising-edge
triggered and resets the internal MCLK
counter/divider to guarantee synchronous operation with other system devices. While the
MSYNC signal synchronizes the internal operation of the CS4373A, by default, it does not
synchronize the phase of the encoded digital
test bit stream (TBS) sine wave unless enabled in the digital filter TBSCFG register.
6.4 GPIO Connections
The CS5376A controls 12 general-purpose in-
DS699F2
put output (GPIO) pins through the digital filter
GPCFG registers. These GPIO pins are typically assigned to operate the CS4373A mode
and attenuator pins, along with the
CS3301A / CS3302A amplifiers input mux and
gain pins. The gain and attenuation settings of
the CS3301A / CS3302A amplifiers and
CS4373A are identically decoded to allow fullscale performance testing at all system gain
ranges with shared GAIN and ATT control signals.
If precise timing control of operational modes
is required (for example, switching between
DC modes for pulse generation), an external
controller should directly toggle the MODE
pins of the CS4373A to avoid the delay associated with writing to the CS5376A digital filter
GPCFG registers.
23
CS4373A
VA+
0.1µF
SWITCH
CONTROL
VA10nF
C0G
SENSOR
Analog
Switches
CH3 BUF
CH4 BUF
Route BUF as diff pair
VD
MCLK
MSYNC
CAP+
CAP-
CH1 BUF
CH2 BUF
BUF+
TDATA
ELECTRONICS
CH1,2,3,4 OUT
Route OUT as diff pair
OUT+
OUT-
10 Ω
2.5 V
VREF
Route VREF as diff pair
100µF
MCLK
MSYNC
TBSDATA
BUF-
CS4373A
VA+
VD
0.1µF
MODE0
MODE1
MODE2
GPIO
GPIO
GPIO
ATT0
ATT1
ATT2
GPIO
VREF+
VREF-
+
VA-
VA-
VA-
DGND
GPIO
GPIO
CS5376A
SIGNALS
0.1µF
Figure 12. Analog Outputs
7. ANALOG OUTPUTS
The CS4373A has multiple differential analog
outputs. The best possible analog performance is achieved from the precision outputs
(OUT±), but with only minimal drive capability.
A buffered output (BUF±) can drive an external
load, but with reduced analog performance.
The internal anti-alias filter requires a dedicated capacitor connection (CAP±) to eliminate
undesired high-frequency signals.
7.1 Differential Signals
Differential AC signals out of the CS4373A
consist of two halves with equal but opposite
magnitude varying about a common mode
voltage. A full-scale 5 VPP differential AC signal centered on a -0.15 V common mode voltage will have:
SIG+ = -0.15 V + 1.25 V = +1.1 V
SIG- = -0.15 V - 1.25 V = -1.4 V
SIG+ is +2.5 V relative to SIGFor the opposite case:
SIG+ = -0.15 V - 1.25 V = -1.4 V
SIG- = -0.15 V + 1.25 V = +1.1 V
SIG+ is -2.5 V relative to SIGSo the total swing for SIG+ relative to SIG- is
(+2.5 V) - (-2.5 V) = 5 Vpp differential. A similar
calculation can be done for SIG- relative to
SIG+. It’s important to note that a 5 Vpp differential signal centered on a -0.15 V common
24
mode voltage never exceeds +1.1 V with respect to ground and never drops below -1.4 V
with respect to ground on either half. By definition, differential voltages are measured with
respect to the opposite half, not relative to
ground. A voltmeter differentially measuring
between SIG+ and SIG- in the above example
would read 1.767 Vrms, or 5 Vpp.
7.2 Analog Output Attenuation
The CS4373A has seven analog output attenuation settings from 1/1 to 1/64 selected with
the ATT2, ATT1, and ATT0 pins. At 1/64 attenuation in AC Common Mode (MODE 6) there
is no output signal amplitude due to the attenuator architecture.
Selection ATT[2:0]
Attenuation
dB
0
000
1/1
0 dB
1
001
1/2
-6.02 dB
2
010
1/4
-12.04 dB
3
0 11
1/8
-18.06 dB
4
100
1/16
-24.08 dB
5
101
1/32
-30.10 dB
6
11 0
1/64
-36.12 dB
7
111
reserved
reserved
Table 3. Output Attenuation Settings
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CS4373A
When enabled, attenuation is applied to both
the OUT and BUF differential analog outputs.
The OUT± pins connect directly into the internal attenuator resistors and so attenuation accuracy is highly sensitive to load impedance
on the OUT± pins. Loading on the BUF± pins
does not affect attenuator accuracy.
The attenuation settings of CS4373A match
the gain ranges of the CS3301A / CS3302A
differential amplifiers to enable full-scale testing
at
all
gain
ranges.
The
CS3301A / CS3302A amplifier gain settings
(GAIN) are decoded identical to the CS4373A
attenuator settings (ATT) and so can share
GPIO signals from the digital filter.
7.3 OUT± Precision Output
The OUT± pins are precision differential analog outputs for testing the high-performance
electronics measurement channel. These precision outputs have higher performance specifications than the BUF outputs, but with a
much higher sensitivity to external loading. Excessive resistive or capacitive loading on the
OUT± pins will degrade the analog performance characteristics of the CS4373A in all
operational modes.
The OUT± precision output is optimized for direct connection to the CS3301A / CS3302A
amplifier differential inputs, which have very
high input impedance. These amplifiers include a pin-controlled input multiplexer to
switch between an internal differential termination for noise tests and two external differential
inputs. One external amplifier input is typically
dedicated to sensor measurements and the
other to testing the electronics channel.
The OUT± outputs are enabled in all operational modes except “AC BUF Only” mode
(MODE 3) and sleep modes (MODE 0, 7). In
DS699F2
AC BUF Only and sleep modes the OUT± pins
are high impedance.
7.4 BUF± Buffered Output
The BUF± pins are buffered differential analog
outputs for testing external sensors such as
geophones or hydrophones. The buffered outputs have reduced performance specifications
compared with the OUT outputs, but are less
sensitive to external loading.
The BUF± outputs are enabled in all operational modes except “AC OUT Only” mode
(MODE 2) and sleep modes (MODE 0, 7). In
AC OUT Only and sleep modes the BUF± pins
are high impedance to ensure they do not interfere with sensor operation during normal
data acquisition.
For sensor impedance testing, it is required to
place matched series resistors in between the
BUF± outputs and the differential sensor. With
known series resistors and a known DC differential source voltage, sensor resistance can
be calculated ratiometrically from the measured voltage drop across the sensor.
7.5 CAP± Analog Output
The CS4373A requires a 10 nF C0G or NPOtype capacitor connected differentially across
the CAP± pins. This capacitor creates an internal anti-alias filter to eliminate high-frequency
signals from the OUT± and BUF± analog outputs and helps to maintain the stability of the
low-power ∆Σ circuitry.
A COG, NPO or similar high-quality capacitor
is required for CAP± since other capacitor
types, such as X7R, do not have the required
linearity. Using a poor-quality capacitor on
CAP± will significantly degrade THD performance in the AC operational modes.
25
CS4373A
To VA+
Regulator
100 µF
0.1 µF
10 Ω
2.500 V
VREF
To VARegulator
100 µF
0.1 µF
Route VREF± as a differential pair
from the 100uF RC filter capacitor
+ 100 µF
0.1 µF
0.1 µF
0.1 µF
To VREF+
To VREF-
Figure 13. Voltage Reference Circuit
8. VOLTAGE REFERENCE
The CS4373A requires a 2.500 V precision
voltage reference to be supplied to the VREF±
pins.
ogy LT1019AIS8-2.5 voltage reference yields
acceptable noise levels if the output is filtered
with a low-pass RC filter.
8.1 VREF Power Supply
To guarantee proper regulation headroom for
the voltage reference device, the voltage reference GND pin should be connected to VA- instead of system ground, as shown in
Figure 13. This connection results in VREFvoltage equal to VA- and VREF+ voltage very
near ground potential [(VA-) + 2.500 VREF].
A separate RC filter is required for each system device connected to a given voltage reference. By sharing a common RC filter, signaldependent sampling of the voltage reference
by one system device could cause unwanted
tones to appear in the measurement bandwidth of another system device via common
impedance coupling.
Power supply inputs to the voltage reference
device should be bypassed to system ground
with 0.1 µF capacitors placed as close as possible to the power and ground pins. In addition
to 0.1 µF local bypass capacitors, at least
100 µF of bulk capacitance to system ground
should be placed on each power supply near
the voltage regulator outputs. Bypass capacitors should be X7R, C0G, tantalum, or other
high-quality dielectric type.
8.3 VREF PCB Routing
To minimize the possibility of outside noise
coupling into the CS4373A voltage reference
input, the VREF± traces should be routed as a
differential pair from the large capacitor of the
voltage reference RC filter. Careful control of
the voltage reference source and return currents by routing VREF± as a differential pair
will improve immunity from external noise.
8.2 VREF RC Filter
A primary concern in selecting a precision voltage reference is noise performance in the
measurement bandwidth. The Linear Technol-
26
To further improve noise rejection of the
VREF± routing, include 0.1 µF bypass capacitors to system ground as close as possible
to the VREF+ and VREF- pins of the
CS4373A.
DS699F2
CS4373A
8.4 VREF Input Impedance
The switched-capacitor input architecture of
the VREF± inputs results in an input impedance that depends on the internal capacitor
size and the clock frequency. With a 15 pF internal capacitor and a 2.048 MHz MCLK the
VREF input impedance is approximately
[1 / [(2.048 MHz) * (15 pF)]] = 32 kΩ.
While
the size of the internal capacitor is fixed, the
voltage reference input impedance will vary
with MCLK.
The voltage reference external RC filter series
resistor creates a voltage divider with the
VREF input impedance to reduce the effective
applied input voltage. To minimize gain error
resulting from this voltage divider effect, the
RC filter series resistor should be the minimum
size recommended in the voltage reference
device data sheet.
8.5 VREF Accuracy
The nominal voltage reference input is specified as 2.500 V across the VREF± pins, and all
CS4373A gain accuracy specifications are
measured with a nominal voltage reference input. Any variation from a nominal VREF input
will proportionally vary the analog full-scale
gain accuracy.
DS699F2
Since temperature drift of the voltage reference results in gain drift of the analog full-scale
amplitude, care should be taken to minimize
temperature drift effects through careful selection of passive components and the voltage
reference device itself. Gain drift specifications
of the CS4373A do not include the temperature drift effects of external passive components or of the voltage reference device itself.
8.6 VREF Independence
If the test signal source is required to be fully
independent of the measurement channel, a
separate voltage reference device for the
CS4373A is required. Using a separate voltage reference minimizes the possibility of undetected ratiometric errors when the same
voltage reference is used by both the test signal source and the measurement channel.
Because modern precision voltage references
are highly reliable, requirements for separate
modulator and test DAC voltage references
should be considered carefully. In the unlikely
event of voltage reference failure independent
of other system components, the CS4373A
volts-to-codes ratio will be out of spec and performance will be poor during system self-tests.
27
CS4373A
To VA+
Regulator
To VD
Regulator
100 uF
0.1 uF
0.1 uF
VA+
100 uF
VD
CS4373A
VA-
GND
To VARegulator
100 uF
0.1 uF
Figure 14. Power Supply Diagram
9. POWER SUPPLIES
The CS4373A has a positive analog power
supply pin (VA+), a negative analog power
supply pin (VA-), a digital power supply pin
(VD), and a ground pin (GND).
For proper operation, power must be supplied
to all power supply pins, and the ground pin
must be connected to system ground. The
CS4373A digital power supply (VD) and the
CS5376A
digital
power
supplies
(VDD1 / VDD2) must share a common power
supply voltage.
9.1 Power Supply Bypassing
The VA+, VA-, and VD power supplies should
be bypassed to system ground with 0.1 µF capacitors placed as close as possible to the
power pins of the device. In addition to the
0.1 µF local bypass capacitors, at least 100 µF
bulk capacitance to system ground should be
placed on each power supply near the voltage
regulator output, with additional power supply
bulk capacitance placed among the analog
component route if space permits. Bypass capacitors should be X7R, C0G, tantalum, or
other high-quality dielectric type.
9.2 PCB Layers and Routing
The CS4373A is a high-performance device,
and special care must be taken to ensure power and ground routing is correct. Power can be
supplied either through dedicated power
28
planes or routed traces. When routing power
traces, it is recommended to use a “star” routing scheme with the star point either at the
voltage regulator output or at a local power
supply bulk capacitor.
It is also recommended to dedicate a full PCB
layer to a solid ground plane, without splits or
routing. All bypass capacitors should connect
between the power supply circuit and the solid
ground plane as near as possible to the device
power supply pins.
The CS4373A analog outputs are differentially
routed and do not normally require connection
to a separate analog ground. However, if a
separate analog ground is required, it should
be routed using a “star” routing scheme on a
separate layer from the solid ground plane and
connected to the ground plane only at the star
point. Be sure all active devices and passive
components connected to the analog ground
are included in the “star” route to ensure sensitive analog currents do not return through the
ground plane.
9.3 Power Supply Rejection
Power supply rejection of the CS4373A is frequency dependent. The CS5376A digital filter
rejects power supply noise for frequencies
above the selected digital filter corner frequency. Power supply noise frequencies between
DC and the digital filter corner frequency are
DS699F2
CS4373A
rejected
as
specified
in
Power Supply Characteristics table.
the
9.4 SCR Latch-up
The VA- pin is tied to the CS4373A CMOS
substrate and must always be the most-negative voltage applied to the device to ensure
SCR latch-up does not occur. In general,
latch-up may occur when any pin voltage exceeds
the
limits
of
the
Absolute Maximum Ratings table.
It is recommended to connect the VA- power
supply to system ground (GND) with a reverse-biased Schottky diode. At power up, if
the VA+ power supply ramps before the VAsupply is established, the VA- pin voltage
could be pulled above ground potential
through the CS4373A device. If the VA- supply
is pulled 0.7 V or more above GND, SCR
latch-up can occur. A reverse-biased Schottky
diode will clamp the VA- voltage a maximum of
0.3 V above ground to ensure SCR latch-up
does not occur at power up.
are battery powered and utilize DC-DC converters to efficiently generate power supply
voltages. To minimize interference effects, operate the DC-DC converter at a frequency
which is rejected by the digital filter, or operate
it synchronous to the MCLK rate.
A synchronous DC-DC converter whose operating frequency is derived from MCLK will theoretically minimize the potential for “beat
frequencies” to appear in the measurement
bandwidth. However this requires the source
clock to remain jitter-free within the DC-DC
converter circuitry. If clock jitter can occur within the DC-DC converter (as in a PLL-based architecture), it’s better to use a nonsynchronous DC-DC converter whose switching frequency is rejected by the digital filter.
During PCB layout, do not place high-current
DC-DC converters near sensitive analog components. Carefully routing a separate DC-DC
“star” ground will help isolate noisy switching
currents away from the sensitive analog components.
9.5 DC-DC Converters
Many low-frequency measurement systems
DS699F2
29
CS4373A
10. TERMINOLOGY
Signal-to-Noise Ratio (Dynamic Range) - Ratio of the rms magnitude of the full-scale signal to the integrated
rms noise from DC to 430 Hz. The following formula is used to calculate SNR:
SNR = 20log
Total Harmonic Distortion - Ratio of the power of the fundamental frequency to the sum of the powers of all
harmonic frequencies from DC to 430 Hz. The following formula is used to calculate THD:
THD = 10log
the powers of the harmonic frequencies
( sum ofpower
of the fundamental frequency
(
•
of full scale signal
( rmsrmsmagnitude
magnitude of noise floor
(
•
•
Full-scale Bandwidth - The bandwidth in which the converter can generate a full-scale signal while maintaining
performance specifications.
•
Impulse Amplitude - The maximum amplitude of the output signal beyond the full-scale bandwidth.
•
Differential Output Level - The voltage between the analog output pins of the device.
•
Full-scale Accuracy - Variation in the measured output voltage from the theoretical full-scale output voltage at
1x attenuation. The following formula is used to calculate full-scale accuracy:
|
•100%
Relative Accuracy - Variation in the measured output voltage from the theoretical attenuated output voltage at
each of the attenuation ranges. The following formula is used to calculate relative accuracy:
(
(
|
measured attenuated voltage - theoretical attenuated voltage
relative accuracy = theoretical attenuated voltage (relative to the measured full scale voltage) •100%
|
•
(
voltage - theoretical full scale voltage
( measured full scale
theoretical full scale voltage
|
full scale accuracy =
•
Full Scale Drift - The variation of the measured full-scale voltage across the specified temperature range.
•
Common Mode Drift - The variation in the measured common mode voltage across the specified temperature
range.
30
DS699F2
CS4373A
11. PIN DESCRIPTION
Positive Capacitor Output
CAP+
1
28
GND
System Ground
Negative Capacitor Output
CAP-
2
27
MODE0
Mode Select
Positive Buffered Output
BUF+
3
26
MODE1
Mode Select
Negative Buffered Output
BUF-
4
25
MODE2
Mode Select
Positive High Precision Output
OUT+
5
24
ATT0
Attenuation Range Select
Negative High Precision Output
OUT-
6
23
ATT1
Attenuation Range Select
Positive Analog Power Supply
VA+
7
22
ATT2
Attenuation Range Select
Negative Analog Power Supply
VA-
8
21
TDATA
Signal Bitstream Input
Negative Voltage Reference
VREF-
9
20
VD
Positive Digital Power Supply
Positive Voltage Reference
VREF+
10
19
GND
System Ground
No Connect
NC
11
18
MCLK
Master Clock Input
No Connect
NC
12
17
MSYNC
Master Sync Input
No Connect
NC
13
16
DNC
Do Not Connect
No Connect
NC
14
15
DNC
Do Not Connect
Pin Name
CAP+,
CAPBUF+,
BUFOUT+,
OUTVA+,
VAVREF-,
VREF+
MSYNC
MCLK
GND
VD
TDATA
DS699F2
Pin # I/O
Pin Description
1
2
O Capacitor connection for internal anti-alias filter.
3
4
O Buffered differential analog output.
5
6
O Precision differential analog output.
7
8
I
Analog power supply. Refer to the Specified Operating Conditions.
9
10
I
Voltage reference input. Refer to the Specified Operating Conditions.
17
I
Master Sync Input. Low to high transition resets the internal clock phasing.
18
I
Master Clock Input. CMOS compatible clock input.
19
System ground.
20
Digital power supply. Refer to the Specified Operating Conditions.
21
I
Test Bit Stream input from digital filter TBS generator.
31
CS4373A
Pin Name
ATT2,
ATT1,
ATT0
MODE2,
MODE1,
MODE0
GND
32
Pin # I/O
22,
23,
24
25,
26,
27
28
I
Pin Description
Attenuation Range. Selects the output attenuation range.
Attenuation
I
Selection
ATT[2:0]
Attenuation
dB
0
000
1/1
0 dB
1
001
1/2
-6.02 dB
2
010
1/4
-12.04 dB
3
0 11
1/8
-18.06 dB
4
100
1/16
-24.08 dB
5
101
1/32
-30.10 dB
6
11 0
1/64
-36.12 dB
7
111
reserved
reserved
Mode Selection. Determines the operational mode of the device.
Selection
MODE[2:0]
Mode Description
0
000
Sleep mode.
1
001
AC OUT and BUF outputs.
2
010
AC OUT only, BUF tri-state.
3
0 11
AC BUF only, OUT tri-state.
4
100
DC common mode output.
5
101
DC differential output.
6
11 0
AC common mode output.
7
111
Sleep mode.
System ground.
DS699F2
CS4373A
12. PACKAGE DIMENSIONS
28L SSOP PACKAGE DRAWING
N
D
E11
A2
E
e
b2
SIDE VIEW
A
∝
A1
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
DIM
A
A1
A2
b
D
E
E1
e
L
∝
MIN
-0.002
0.064
0.009
0.390
0.291
0.197
0.022
0.025
0°
INCHES
NOM
-0.006
0.069
-0.4015
0.307
0.209
0.026
0.0354
4°
MAX
0.084
0.010
0.074
0.015
0.413
0.323
0.220
0.030
0.041
8°
MIN
-0.05
1.62
0.22
9.90
7.40
5.00
0.55
0.63
0°
MILLIMETERS
NOM
-0.15
1.75
-10.20
7.80
5.30
0.65
0.90
4°
NOTE
MAX
2.13
0.25
1.88
0.38
10.50
8.20
5.60
0.75
1.03
8°
2,3
1
1
JEDEC #: MO-150
Controlling Dimension is Millimeters
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS699F2
33
CS4373A
13.ORDERING INFORMATION
Model
CS4373A-ISZ (lead free)
Temperature
Package
-40 to +85 °C
28-pin SSOP
14.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
260 °C
3
7 Days
CS4373A-ISZ (lead free)
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
15.REVISION HISTORY
Revision
Date
PP1
MAR 2003
Preliminary release for CS4373.
Changes
PP2
SEP 2005
Update for new CS4373A features and most-current characterization data.
PP3
NOV 2005
Remove references to CS5378. Update for most-current characterization data.
F1
DEC 2005
Updated with final characterization data.
F2
DEC 2006
Updated to final status with most-recent characterization data for Cirrus QPL process.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
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34
DS699F2