July 2000
PRELIMINARY
ML4833*
Electronic Dimming Ballast Controller
GENERAL DESCRIPTION
FEATURES
The ML4833 is a complete solution for a dimmable or a
non-dimmable, high power factor, high efficiency
electronic ballast. The BiCMOS ML4833 contains
controllers for “boost” type power factor correction as
well as for a dimming ballast. The ML4833 was designed
to minimize the number of external components required
to build an electronic ballast.
■
The PFC circuit uses a new, simple PFC topology which
requires only one loop for compensation. This system
produces a power factor of better than 0.99 with low
input current THD. An overvoltage protection comparator
inhibits the PFC section in the event of a lamp out or lamp
failure condition.
The ballast controller section provides for programmable
starting sequence with individually adjustable preheat and
lamp out-of-socket interrupt times. The IC controls lamp
output power through feedback. The ML4833 provides a
power down input which reduces power to the lamp, for
GFI, end of life, etc.
■
■
■
■
■
■
■
■
■
Complete power factor correction and dimming
ballast control in one IC
Low distortion, high efficiency continuous boost,
peak current sensing PFC section
Programmable start scenario for rapid or
instant start lamps
Lamp current feedback for dimming control
Variable frequency dimming and starting
Programmable restart for lamp out condition to
reduce ballast heating
Internal over-temperature shutdown replaces
external heat sensor
PFC overvoltage comparator eliminates output
“runaway” due to load removal
Low start-up current <0.5mA
Power reduction pin for end of life and GFI detectors
(* Indicates part is End Of Life as of July 1, 2000)
BLOCK DIAGRAM
INTERRUPT
6
7
RSET
RT /CT
LAMP FB
VARIABLE FREQUENCY
OSCILLATOR
LFB OUT
8
4
5
OUTPUT
DRIVERS
9
RX/CX
PRE-HEAT
AND INTERRUPT
TIMERS
OUT A
CONTROL
&
GATING LOGIC
OUT B
3
PDWN
PFC OUT
10
2
1
18
14
13
15
CRAMP
PIFB
PEAO
PVFB/OVP
PGND
POWER
FACTOR
CONTROLLER
VCC
UNDER-VOLTAGE
AND THERMAL
SHUTDOWN
VREF
GND
12
16
17
11
1
ML4833
PIN CONFIGURATION
ML4833
18-Pin DIP (P18)
PEAO
PIFB
PDWN
LAMP FB
LFB OUT
RSET
RT/CT
INTERRUPT
RX/CX
1
18
2
17
3
16
4
15
5
14
6
13
7
12
8
11
9
10
ML4833
18-Pin SOIC (S18)
PEAO
1
18
PVFB/OVP
PIFB
2
17
VREF
PDWN
3
16
VCC
LAMP FB
4
15
PFC OUT
LFB OUT
5
14
OUT A
OUT B
RSET
6
13
OUT B
P GND
RT/CT
7
12
P GND
INTERRUPT
8
11
GND
RX/CX
9
10
CRAMP
PVFB/OVP
VREF
VCC
PFC OUT
OUT A
GND
CRAMP
TOP VIEW
TOP VIEW
PIN DESCRIPTION
PIN# NAME
1
PEAO
PFC error amplifier output and
compensation node.
2
PIFB
Sensing of the inductor current and
peak current sense point of the PFC
cycle by cycle current limit
comparator.
3
PDWN
A one volt comparator threshold that
switches the operating frequency to
the preheat frequency when exceeded.
4
LAMP FB
Inverting input of an error amplifier
used to sense (and regulate) lamp arc
current. Also the input node for
dimming control.
5
2
FUNCTION
LFB OUT
PIN# NAME
FUNCTION
8
INTERRUPT Input used for lamp-out detection and
restart. A voltage less than 1.25 volts
resets the chip and causes a restart
after a programmable interval.
9
RX/CX
Sets the timing for the preheat,
dimming lockout, and interrupt.
10 CRAMP
Integrated voltage of the error
amp out.
11 GND
Ground.
12 P GND
Power ground for the IC.
13 OUT B
Ballast MOSFET drive output.
14 OUT A
Ballast MOSFET drive output.
Output of the lamp current error
transconductance amplifier used for
lamp current loop compensation.
15 PFC OUT
Power Factor MOSFET drive output.
16 VCC
Positive supply for the IC.
6
RSET
External resistor which sets oscillator
FMAX, and R(X)/C(X) charging current.
17 VREF
Buffered output for the 7.5V voltage
reference.
7
RT/CT
Oscillator timing components.
18 PVFB/OVP
Inverting input to PFC error amplifier
and OVP comparator input.
ML4833
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Supply Current (ICC) ............................................... 60mA
Output Current, Source or Sink
(OUT A, OUT B, PFC OUT) DC ......................... 250mA
Output Energy (capacitive load per cycle).............. 1.5 mJ
Analog Inputs
(LAMP FB, INTERRUPT, VCC) ........... –0.3V to VCC –2V
PIFB input voltage ......................................... –1.5V to 2V
Maximum Forced Voltage
(PEAO, LFB OUT) ................................... –0.3V to 7.7V
Maximum Forced Current (PEAO, LFB OUT) ........ ±20mA
Junction Temperature ............................................ 150°C
Storage Temperature Range ..................... –65°C to 150°C
Lead Temperature (Soldering 10 sec.) .................... 260°C
Thermal Resistance (qJA)
ML4833CP ...................................................... 70°C/W
ML4833CS .................................................... 100°C/W
OPERATING CONDITIONS
Temperature Range ........................................ 0°C to 85°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, RSET = 22.1ký, RT = 15.8kW, CT = 1.5nF, CVCC = 1µF, VCC = 12.5V. (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
–0.3
–1.0
µA
65
105
µW
5.0
V
0.2
0.4
V
7.1
7.5
7.8
V
Lamp Current Amplifier (LAMP FB, LFB OUT)
Small Signal Transconductance
35
Input Voltage Range
–0.3
W
Input Bias Current
Output Low
Voltage at LAMP FB = 3V, RL =
Output High
Voltage at LAMP FB = 2V, RL =
Source Current
Voltage at LAMP FB = 0V,
LFB OUT = 7V, TA = 25°C
–0.05
–0.15
–0.25
mA
Voltage at LAMP FB = 5V,
LFB OUT = 0.3V, TA = 25°C
0.05
0.12
0.22
mA
–0.3
–1.0
µA
65
105
µW
5.0
V
0.2
0.4
V
6.5
6.8
7.1
V
Sink Current
PFC Voltage Feedback Amplifier (PEAO, PVFB/OVP)
Small Signal Transconductance
35
Input Voltage Range
–0.3
W
Input Bias Current
Output Low
Voltage at PVFB = 3V, RL =
Output High
Voltage at PVFB = 2V, RL =
Source Current
Voltage at PVFB/OVP = 0V,
PEAO = 6V, TA = 25°C
–0.05
–0.15
–0.25
mA
Voltage at PVFB/OVP = 3V,
PEAO = 0.3V, TA = 25°C
0.03
0.07
0.16
mA
–0.90
–1.05
–1.15
V
Sink Current
PFC Current — Limit Comparator (PIFB)
Current-Limit Threshold
Propagation Delay
100mV step and 100mV overdrive
100
ns
Oscillator
Initial Accuracy
TA = 25°C
Voltage Stability
VCCZ – 4.5V < VCC <VCCZ – 0.5V
72
Temperature Stability
Total Variation
Ramp Valley to Peak
Line, temperature
76
80
kHz
1
%
2
%
69
83
2.5
kHz
V
3
ML4833
ELECTRICAL CHARACTERISTICS
PARAMETER
(Continued)
CONDITIONS
MIN
TYP
MAX
UNITS
Voltage at LAMP FB = 3V,
RT/CT = 2.5V, RX/CX = 0.9V (Preheat)
–90
–110
–130
µA
LAMP FB = 3V, RT/CT = 2.5V,
RX/CX = Open
–180
–220
–260
µA
4.0
5.5
7.0
mA
0.65
1
1.35
µs
7.4
7.5
7.6
V
Oscillator (Continued)
CT Charging Current
CT Discharge Current
Voltage at RT/CT = 2.5V
Output Drive Deadtime
Reference Section
Output Voltage
TA = 25°C, IO = 1mA
Line regulation
VCCZ – 4.5V < VCC < VCCZ – 0.5V
2
35
mV
Load regulation
1mA < IO < 5mA
2
15
mV
Temperature stability
0.4
7.35
%
Total Variation
Line, load, temp
7.65
V
Output Noise Voltage
10Hz to 10kHz
50
µV
Long Term Stability
TJ = 125°C, 1000 hrs
5
mV
Initial Preheat Period
0.8
s
Subsequent Preheat Period
0.7
s
Start Period
1.2
s
Interrupt Period
5.7
s
Preheat and Interrupt Timer (RX/CX where RX = 680ký, CX = 4.7µF)
RX/CX Charging Current
RX/CX Open Circuit Voltage
VCC < Start-up threshold
RX/CX Maximum Voltage
Input Bias Current
–24
–28
–33
µA
0.4
0.7
1.0
V
7.0
7.3
7.7
V
0.1
µA
Voltage at CRAMP = 1.2V
Preheat Lower Threshold
1.05
1.22
1.36
V
Preheat Upper Threshold
4.2
4.7
5.1
V
Interrupt Recovery Threshold
1.05
1.22
1.36
V
Start Period End Threshold
6.05
6.6
7.35
V
1.1
1.22
1.4
V
0.1
µA
Interrupt Input (INTERRUPT)
Interrupt Threshold
Input Bias Current
RSET Voltage
2.4
2.5
2.6
V
OVP Threshold
2.63
2.73
2.83
V
Hysteresis
0.18
0.23
0.27
V
OVP Comparator (PVFB/OVP)
Propagation Delay
4
1.4
µs
ML4833
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IOUT = 20mA
0.1
0.2
V
IOUT = 200mA
1.0
2.0
V
Outputs (OUT A, OUT B, PFC OUT)
Output Voltage Low
Output Voltage High
IOUT = –20mA
VCC – 0.2
VCC – 0.1
V
IOUT = –200mA
VCC – 2.0
VCC – 1.0
V
Output Voltage Low in UVLO
IOUT = 10mA, VCC < Start-up threshold
Output Rise/Fall Time
CL = 1000pF
0.2
20
V
ns
Under-Voltage Lockout and Bias Circuits
IC Shunt Protection Voltage (VCCZ)
ICC = 15mA
Start-up Current
Operating Current
14.2
15.0
15.8
V
VCC - Start-up threshold
0.34
0.48
mA
VCC = 12.5V,
Voltage at LAMP FB = 0V,
LFB OUT = 2.3, PVFB/OVP = 2.3V
PIFB = Open
5.5
8.0
mA
Start-up Threshold
VCC – 1.2 VCCZ – 1.0 VCC – 0.8
V
Shutdown Threshold
VCC – 5.3 VCCZ – 4.8 VCC – 4.3
V
130
°C
30
°C
Shutdown Temperature (TDWN)
(Note 2)
Hysteresis (TDWN)
PDWN
PDWN Threshold
Note 1:
Note 2:
0.9
1.0
1.1
V
Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.
Junction temperature.
5
ML4833
FUNCTIONAL DESCRIPTION
compensation is needed), an integrator, a comparator, and
a logic control block. In the boost topology, power factor
correction is achieved by sensing the output voltage and
the current flowing through the current sense resistor. Duty
cycle control is achieved by comparing the integrated
voltage signal of the error amplifier and the voltage
across RSENSE. The duty cycle control timing is shown in
Figure 2. Setting minimum input voltage for output
regulation can be achieved by selecting CRAMP according
to equation 1.
OVERVIEW
The ML4833 consists of peak current controlled
continuous boost power factor front end section with a
flexible ballast control section. Start-up and lamp-out
retry timing are controlled by the selection of external
timing components, allowing for control of a wide variety
of different lamp types. The ballast section controls the
lamp power using frequency modulation (FM) with
additional programmability provided to adjust the VCO
frequency range. This allows for the IC to be used with a
variety of different output networks. Figure 1 depicts a
detailed block diagram of ML4833.
CRAMP =
LFB OUT
RSET
RT/CT
OSC
+
CLK
9
16
17
11
RX/CX
VCC
VREF
18
1
10
+
PREHEAT
TIMER
–
1.25V
GND
S
PDWN
4
8
3
1.0V
Q
+
–
V TO I
PVFB/OVP
LAMP FB
+
–
5
2.5V
INTERRUPT
–
UNDER-VOLTAGE
THERMAL SHUTDOWN
REFOK
2.5V
(1)
The OVP pin serves to protect the power circuit from
being subjected to excessive voltages if the load should
change suddenly (lamp removal). A divider from the high
voltage DC bus sets the OVP trip level. When the voltage
on PVFB/OVP exceeds 2.75V, the PFC transistor are
inhibited. The ballast section will continue to operate.
The ML4833 power factor section is a peak current
sensing boost mode PFC control circuit in which only
voltage loop compensation is needed. It is simpler than a
conventional average current control method. It consists
of a voltage error amplifier, a current sense amplifier (no
7
}
OVERVOLTAGE PROTECTION AND INHIBIT
POWER FACTOR SECTION
6
{
PEAOMAX
1
(1− D)Ts − 1.1µs
22K
2P
OUT − VOUT − 2VIN (1− D)Ts 8R
SENSE
2L
VIN
–
R
+
PEAO
CRAMP
PFC OUT
–
2.75V
OVP
S
+
Q
OUT A
15
14
R
T Q
–1.0V
–
+
2
PIFB
ILIM
PGND
ISENSE AMPLIFIER
Figure 1. ML4833 Detailed Block Diagram
6
OUT B
13
12
ML4833
TRANSCONDUCTANCE AMPLIFIERS
The PFC voltage feedback amplifier is implemented as an
operational transconductance amplifier. It is designed to
have low small signal forward transconductance such that
a large value of load resistor (R1) and a low value
ceramic capacitor (<1µF) can be used for AC coupling
(C1) in the frequency compensation network. The
compensation network shown in Figure 3 will introduce a
zero and a pole at:
fZ =
1
2π R1C1
fP =
1
2π R1C2
PVFB/OVP
18
–
2.5V
+
R1
C2
C1
(2)
Figure 3. Compensation Network
L
VOUT
SW2
RA
EMI
FILTER
LAMP
NETWORK
INVERTER
RSENSE
2
PIFB
OUT A
SINE
–A
RB
SW1
14
18
L
A
M
P
L
A
M
P
PVFB/OVP
+
R
Q
–
S
SINE
CLK
OSC
RAMP
PEAO
–
V TO I
+
VREF1
CLK
PFC OUT
10
1
CRAMP
PEAO
R1
CRAMP
C2
C1
Figure 2. ML4833 PFC Controller Section
7
ML4833
Figure 4 shows the output configuration for the
operational transconductance amplifiers.
CURRENT
MIRROR
IN
OUT
IQ +
IQ –
OSCILLATOR
The VCO frequency ranges are controlled by the output
of the LFB amplifier (RSET). As lamp current increases,
LFB OUT falls in voltage, causing the CT charging current
to increase, thereby causing the oscillator frequency to
increase. Since the ballast output network attenuates high
frequencies, the power to the lamp will be decreased.
gmVIN
2
io = gmVIN
gmVIN
2
17
VREF
VREF
IN
OUT
RT/CT
CURRENT
MIRROR
CONTROL
ICHG
RT
+
7
1.25/3.75
–
CT
Figure 4. Output Configuration
5.5mA
A DC path to ground or VCC at the output of the
transconductance amplifiers will introduce an offset error.
The magnitude of the offset voltage that will appear at the
input is given by VOS = io/gm. For an io of 1µA and a gm
of 0.05 µW the input referred offset will be 20mV.
Capacitor C1 as shown in Figure 3 is used to block the
DC current to minimize the adverse effect of offsets.
W
Slew rate enhancement is incorporated into all of the
operational transconductance amplifiers in the ML4833.
This improves the recovery of the circuit in response to
power up and transient conditions. The response to large
signals will be somewhat non-linear as the transconductance
amplifiers change from their low to high transconductance
mode. This is illustrated in Figure 5.
iO
CLOCK
tDIS
tCHG
VTH = 3.75V
CT
VTL = 1.25V
Figure 6. Oscillator Block Diagram and Timing
VIN Differential
0
Linear Slope Region
The oscillator frequency is determined by the following
equations:
FOSC =
1
t CHG + tDIS
(3)
and
Figure 5. Transconductance Amplifier Characteristics
BALLAST OUTPUT SECTION
The IC controls output power to the lamps via frequency
modulation with non-overlapping conduction. This means
that both ballast output drivers will be low during the
discharging time tDIS of the oscillator capacitor CT.
8
V + I R − VTL
t CHG = R T CT In REF CH T
VREF + ICH R T − VTH
(4)
The oscillator’s minimum frequency is set when ICH = 0
where:
FOSC ≅
1
0.51× R T CT
(5)
ML4833
This assumes that tCHG >> tDIS.
TJ ≅ TA + (PD + 65°C / W)
When LFB OUT is high, ICH = 0 and the minimum
frequency occurs. The charging current varies according
to two control inputs to the oscillator:
(9)
VCC VCCZ
1. The output of the preheat timer
V(ON)
2. The voltage at LFB OUT (lamp feedback amplifier
output)
V(OFF)
In preheat condition, charging current is fixed at
ICHG (PREHEAT) = 2.5
RSET
(6)
In running mode, charging current decreases as the
voltage rises from 0V to VOH at the LAMP FB amplifier.
The highest frequency will be attained when ICHG is
highest, which is attained when voltage at LFB OUT
is at 0V:
ICHG(0) =
5
RSET
(7)
Highest lamp power, and lowest output frequency are
attained when voltage at LFB OUT is at its maximum
output voltage (VOH).
5.5mA
0.34mA
t
Figure 7. Typical VCC and ICC Waveforms when
the ML4833 is Started with a Bleed Resistor from
the Rectified AC Line and Bootstrapped from an
Auxiliary Winding.
STARTING, RE-START, PREHEAT AND INTERRUPT
In this condition, the minimum operating frequency of the
ballast is set per equation 5 above.
For the IC to be used effectively in dimming ballasts with
higher Q output networks a larger CT value and lower RT
value can be used, to yield a smaller frequency excursion
over the control range (voltage at LFB OUT). The
discharge current is set to 5mA. Assuming that IDIS >>
IRT:
tDIS(VCO) ≅ 600 × CT
t
ICC
(8)
IC BIAS, UNDER-VOLTAGE LOCKOUT AND
THERMAL SHUTDOWN
The IC includes a shunt clamp which will limit the
voltage at VCC to 15V (VCCZ). The IC should be fed with
a current limited source, typically derived from the
ballast transformer auxiliary winding. When VCC is below
VCCZ – 1.1V, the IC draws less than 0.48mA of quiescent
current and the outputs are off. This allows the IC to start
using a “bleed resistor” from the rectified AC line.
To help reduce ballast cost, the ML4833 includes a
temperature sensor which will inhibit ballast operation if
the IC’s junction temperature exceeds 120°C. In order to
use this sensor in lieu of an external sensor, care should
be taken when placing the IC to ensure that it is sensing
temperature at the physically appropriate point in the
ballast. The ML4833’s die temperature can be estimated
with the following equation:
The lamp starting scenario implemented in the ML4833
is designed to maximize lamp life and minimize ballast
heating during lamp out conditions.
The circuit in Figure 8 controls the lamp starting
scenarios: Filament preheat and lamp out interrupt. CX is
charged with a current of IR(SET)/4 and discharged through
RX. The voltage at CX is initialized to 0.7V (VBE) at power
up. The time for CX to rise to 4.8V is the filament preheat
time. During that time, the oscillator charging current
(ICHG) is 2.5/RSET. This will produce a high frequency for
filament preheat, but will not produce sufficient voltage
to ignite the lamp or cause significant glow current.
After cathode heating, the inverter frequency drops to FMIN
causing a high voltage to appear to ignite the lamp. If
lamp current is not detected when the lamp is supposed
to have ignited, the lamp voltage feedback coming into
pin 8 remains below 1.25V, the CX charging current is
shut off and the inverter is inhibited until CX is discharged
by RX to the 1.2V threshold. Shutting off the inverter in
this manner prevents the inverter from generating
excessive heat when the lamp fails to strike or is out of
socket. Typically this time is set to be fairly long by
choosing a large value of RX.
9
ML4833
A summary of the operating frequencies in the various
operating modes is shown below.
0.625
RSET
RX/CX
+
9
Operating Mode
Operating Frequency
Preheat
[F(MAX) to F(MIN)]
2
Dimming
Lock-out
F(MIN)
Dimming
Control
F(MIN) to F(MAX)
HEAT
CX
1.2/4.8
–
RX
6.8
+
1.2/6.8
–
1.25V
–
INHIBIT
R
INTERRUPT
8
DIMMING
LOCKOUT
Q
S
+
TYPICAL APPLICATIONS
Figure 8. Lamp Preheat and Interrupt Timers
LFB OUT is ignored by the oscillator until CX reaches
6.8V threshold. The lamps are therefore driven to full
power and then dimmed. The CX pin is clamped to
about 7.5V.
Figure 10 shows a schematic for a dimming power-factor
corrected 60W ballast, designed to operate two F32T8
fluorescent lamps connected in series.
6.8
4.8
RX/CX
1.2
.65
0
HEAT
DIMMING
LOCKOUT
>1.25
INT
INHIBIT
Figure 9. Lamp Starting and Restart Timing
10
PDWN
NEUTRAL
220 VAC
HOT
F1
T1
C24
R4
3
4
C7
L2
L1
C3
C1
R8
R3
R1
D4
D3
C4
D2
R5
C4
R2
D6
D5
C6
9
6
D9
R7
R6
D10
Q1
9
8
7
6
5
4
3
2
1
+
R22
C20
Q1
D7
VCC
VREF
PVFB
PGND
RTC T
TP3
RXCX
C2
R5
R15
R23
CRAMP
GND
OUT B
RSET
INTERRUPT
OUT A
LFB OUT
R4
C3
C13
10
11
12
13
14
15
16
17
18
R8
C10
PFC OUT
U1
LAMP FB
PDWN
PIFB
PEAO
ML4833
T1
R10
D12
C5
8
10
C25
D13
R20
C26
D2
D1
DIMMER CONTROL INTERFACE SUBASSEMBLY
D1
C11
R25
R14
C2
C1
D8
R3
R13
R12
R11
6
5
2
3
C14
–
+
–
+
8
4
U2
C15
R16
R7
R6
C16
7
1
R1
C12
C19
7
6
8
1
2
3
R19
C17
T2
TP2
TP1
R18
R17
Q3
U1
R2
Q2
R21
R24
GRAY
C8
7
6
C21
D11
VIOLET
C22
TP4
1
9
8
2
3
4
5
1
T5
6
10
C23
REMOTE MANUAL
DIMMER
0–10VDC
TP5
C9
T4
B
B
Y
Y
R
R
ML4833
Figure 10. 220V Dimming Ballast
11
ML4833
PHYSICAL DIMENSIONS
inches (millimeters)
Package: P18
18-Pin PDIP
0.890 - 0.910
(22.60 - 23.12)
18
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.26)
PIN 1 ID
1
0.045 MIN
(1.14 MIN)
(4 PLACES)
0.050 - 0.065
(1.27 - 1.65)
0.100 BSC
(2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
SEATING PLANE
0.016 - 0.022
(0.40 - 0.56)
0.125 MIN
(3.18 MIN)
0º - 15º
0.008 - 0.012
(0.20 - 0.31)
Package: S18
18-Pin SOIC
0.449 - 0.463
(11.40 - 11.76)
18
0.291 - 0.301 0.398 - 0.412
(7.39 - 7.65) (10.11 - 10.47)
PIN 1 ID
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.095 - 0.107
(2.41 - 2.72)
0º - 8º
0.090 - 0.094
(2.28 - 2.39)
12
0.012 - 0.020
(0.30 - 0.51)
SEATING PLANE
0.005 - 0.013
(0.13 - 0.33)
0.022 - 0.042
(0.56 - 1.07)
0.009 - 0.013
(0.22 - 0.33)
ML4833
ORDERING INFORMATION
PART NUMBER
ML4833CP (End of Life)
ML4833CS (Obsolete)
TEMPERATURE RANGE
PACKAGE
0°C to 85°C
0°C to 85°C
Molded DIP (P18)
SOIC (S18)
© Micro Linear 1997
is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017;
5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or
design. Micro Linear does not assume any liability arising out of the application or use of any product
described herein, neither does it convey any license under its patent right nor the rights of others. The
circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no
warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of
others, and will accept no responsibility or liability for use of any application herein. The customer is urged
to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
DS4833-01
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