MC14016B Quad Analog Switch/ Quad Multiplexer The MC14016B quad bilateral switch is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each MC14016B consists of four independent switches capable of controlling either digital or analog signals. The quad bilateral switch is used in signal gating, chopper, modulator, demodulator and CMOS logic implementation. http://onsemi.com Features • • • • • • • • • Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Linearized Transfer Characteristics Low Noise − 12 nV/√Cycle, f ≥ 1.0 kHz typical Pin−for−Pin Replacements for CD4016B, CD4066B (Note Improved Transfer Characteristic Design Causes More Parasitic Coupling Capacitance than CD4016) For Lower RON, Use The HC4016 High−Speed CMOS Device or The MC14066B This Device Has Inputs and Outputs Which Do Not Have ESD Protection. Antistatic Precautions Must Be Taken NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter Symbol VDD DC Supply Voltage Range SOIC−14 D SUFFIX CASE 751A SOEIAJ−14 F SUFFIX CASE 965 MARKING DIAGRAMS 14 14016BG AWLYWW 1 SOIC−14 14 MC14016B ALYWG 1 Value Unit −0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) −0.5 to VDD + 0.5 V Iin Input Current (DC or Transient) per Control Pin ±10 mA ISW Switch Through Current ±25 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C SOEIAJ−14 A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Indicator ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 11 1 Publication Order Number: MC14016B/D MC14016B PIN ASSIGNMENT BLOCK DIAGRAM IN 1 1 14 VDD OUT 1 2 13 CONTROL 1 OUT 2 3 12 CONTROL 4 IN 2 4 11 IN 4 CONTROL 2 5 10 OUT 4 CONTROL 3 6 9 OUT 3 CONTROL 1 IN 1 CONTROL 2 IN 2 CONTROL 3 VSS 7 8 IN 3 IN 3 CONTROL 4 IN 4 LOGIC DIAGRAM (1/4 OF DEVICE SHOWN) 13 2 OUT 1 1 5 3 OUT 2 4 6 9 OUT 3 8 12 10 OUT 4 11 VDD = PIN 14 VSS = PIN 7 OUT CONTROL Control LOGIC DIAGRAM RESTRICTIONS VSS ≤ Vin ≤ VDD VSS ≤ Vout ≤ VDD IN Switch 0 = VSS Off 1 = VDD On ORDERING INFORMATION Package Shipping† MC14016BDG SOIC−14 (Pb−Free) 55 Units / Rail MC14016BDR2G SOIC−14 (Pb−Free) 2500 / Tape & Reel NLV14016BDR2G* SOIC−14 (Pb−Free) 2500 / Tape & Reel SOEIAJ−14 (Pb−Free) 2000 / Tape & Reel Device MC14016BFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 2 MC14016B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) −55_C Characteristic Input Voltage Control Input VDD Vdc Min Max Min VIL 5.0 10 15 − − − − − − − − − 1.5 1.5 1.5 0.9 0.9 0.9 − − − − − − Vdc VIH 5.0 10 15 − − − − − − 3.0 8.0 13 2.0 6.0 11 − − − − − − − − − Vdc 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc − − − − − − − − − − − − − − − − 5.0 5.0 5.0 0.2 − − − − − − − − − − − − 5.0 10 15 − − − 0.25 0.5 1.0 − − − 0.0005 0.0010 0.0015 0.25 0.5 1.0 − − − 7.5 15 30 Figure Symbol 1 − Iin Input Capacitance Control Switch Input Switch Output Feed Through − Cin “ON” Resistance (VC = VDD, RL = 10 kW) 2,3 IDD 4,5,6 RON (Vin = +10 Vdc) (Vin = +0.25 Vdc) VSS = 0 Vdc (Vin = +5.6 Vdc) (Vin = +15 Vdc) (Vin = +0.25 Vdc) VSS = 0 Vdc (Vin = +9.3 Vdc) D “ON” Resistance Between any 2 circuits in a common package (VC = VDD) (Vin = +5.0 Vdc, VSS = −5.0 Vdc) (Vin = +7.5 Vdc, VSS = −7.5 Vdc) − Input/Output Leakage Current (VC = VSS) (Vin = +7.5, Vout = −7.5 Vdc) (Vin = −7.5, Vout = +7.5 Vdc) − 125_C Typ (Note 2) Input Current Control Quiescent Current (Per Package) (Note 3) 25_C Max Min Max Unit pF mAdc W 10 − − − 600 600 600 − − − 260 310 310 660 660 660 − − − 840 840 840 15 − − − 360 360 360 − − − 260 260 300 400 400 400 − − − 520 520 520 DRON W − − 5.0 7.5 − − − − 15 10 − − − − − − mAdc − 7.5 7.5 − − ±0.1 ±0.1 − − ±0.0015 ±0.0015 ±0.1 ± 0.1 − − ±1.0 ±1.0 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. For voltage drops across the switch (DVswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e., the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14. http://onsemi.com 3 MC14016B ELECTRICAL CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25_C) Characteristic VDD Vdc Min Typ (Note 5) Max Unit 5.0 10 15 − − − 15 7.0 6.0 45 20 15 ns 5.0 10 15 − − − 34 20 15 120 110 100 − 5.0 10 15 − − − 30 50 100 − − − mV − − 5.0 − – 80 − dB 10,11 − 5.0 10 15 − − − 24 25 30 − − − nV/√Cycle 5.0 10 15 − − − 12 12 15 − − − − 0.16 − Figure Symbol Propagation Delay Time (VSS = 0 Vdc) Vin to Vout (VC = VDD, RL = 10 kW) 7 tPLH, tPHL Control to Output (Vin ≤ 10 Vdc, RL = 10 kW) 8 tPHZ, tPLZ, tPZH, tPZL Crosstalk, Control to Output (VSS = 0 Vdc) (VC = VDD, Rin = 10 kW, Rout = 10 kW, f = 1.0 kHz) 9 Crosstalk between any two switches (VSS = 0 Vdc) (RL = 1.0 kW, f = 1.0 MHz, V crosstalk + 20 log10 out1) Vout2 Noise Voltage (VSS = 0 Vdc) (VC = VDD, f = 100 Hz) (VC = VDD, f = 100 kHz) ns Second Harmonic Distortion (VSS = – 5.0 Vdc) (Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc, RL = 10 kW, f = 1.0 kHz) − − 5.0 Insertion Loss (VC = VDD, Vin = 1.77 Vdc, VSS = −5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz) V Iloss + 20 log10 out) Vin (RL = 1.0 kW) (RL = 10 kW) (RL = 100 kW) (RL = 1.0 MW) 12 − 5.0 Bandwidth (−3.0 dB) (VC = VDD, Vin = 1.77 Vdc, VSS = −5.0 Vdc, RMS centered @ 0.0 Vdc) (RL = 1.0 kW) (RL = 10 kW) (RL = 100 kW) (RL = 1.0 MW) OFF Channel Feedthrough Attenuation (VSS = −5.0 Vdc) Vout + –50 dB) (VC = VSS, 20 log10 Vin (RL = 1.0 kW) (RL = 10 kW) (RL = 100 kW) (RL = 1.0 MW) dB − − − − 12,13 BW − 2.3 0.2 0.1 0.05 − − − − 5.0 MHz − − − − − 54 40 38 37 − − − − 5.0 kHz − − − − 1250 140 18 2.0 − − − − 4. The formulas given are for typical characteristics only at 25_C. 5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 4 % MC14016B VC IS Vin Vout VIL: VC is raised from VSS until VC = VIL. VIL: at VC = VIL: IS = ±10 mA with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS. VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met. Figure 1. Input Voltage Test Circuit 10,000 VDD ID PULSE GENERATOR TO ALL 4 CIRCUITS VDD Vout 10 k CONTROL INPUT fc VSS PD , POWER DISSIPATION (μW) VDD = 15 Vdc Vin TA = 25°C Figure 2. Quiescent Power Dissipation Test Circuit 5.0 Vdc 1000 100 10 1.0 5.0k 10k PD = VDD x ID 100k 1.0M fc, FREQUENCY (Hz) R ON, “ON” RESISTANCE (OHMS) 700 VSS = 0 Vdc RL = 10 kW TA = 25°C 600 500 VC = VDD = 10 Vdc 300 200 VC = VDD = 15 Vdc 100 0 0 2.0 10M 50M Figure 3. Typical Power Dissipation per Circuit (1/4 of device shown) TYPICAL RON versus INPUT VOLTAGE 400 10 Vdc 6.0 10 14 Vin, INPUT VOLTAGE (Vdc) Figure 4. VSS = 0 V http://onsemi.com 5 18 20 MC14016B Vout RL CL Vin Vout 20 ns RL 20 ns 90% 50% Vin VC tPLH tPHL Figure 5. RON Characteristics Test Circuit VSS 50% Vout Vin VDD 10% Figure 6. Propagation Delay Test Circuit and Waveforms Vout VC RL CL VX Vin 20 ns 50% VC tPZH Vout VDD 90% 10% tPHZ 90% 10% tPZL 10 k VC VSS Vin = VDD Vx = VSS 15 pF Vin tPLZ 1k 90% Vout Vout 10% Vin = VSS Vx = VDD Figure 7. Turn−On Delay Time Test Circuit and Waveforms Figure 8. Crosstalk Test Circuit 35 OUT VC = VDD IN NOISE VOLTAGE (nV/ CYCLE) 30 QUAN-TECH MODEL 2283 OR EQUIV VDD = 15 Vdc 25 10 Vdc 20 5.0 Vdc 15 10 5.0 0 10 Figure 9. Noise Voltage Test Circuit 100 1.0k f, FREQUENCY (Hz) 10 k Figure 10. Typical Noise Characteristics http://onsemi.com 6 100 k MC14016B 2.0 TYPICAL INSERTION LOSS (dB) RL = 1 MW AND 100 kW 0 10 kW - 2.0 - 4.0 1.0 kW- 3.0 dB (R = 1.0 MW ) L - 6.0 - 3.0 dB (RL = 10 kW ) - 3.0 dB (RL = 1.0 kW ) - 8.0 - 10 - 12 10 k 100 k 1.0M 10 M fin, INPUT FREQUENCY (Hz) 100 M Figure 11. Typical Insertion Loss/Bandwidth Characteristics Vout RL VC + 2.5 Vdc 0.0 Vdc - 2.5 Vdc Vin Figure 12. Frequency Response Test Circuit ON SWITCH CONTROL SECTION OF IC LOAD V SOURCE Figure 13. DV Across Switch http://onsemi.com 7 MC14016B APPLICATIONS INFORMATION Figure A illustrates use of the Analog Switch. The 0−to−5 V Digital Control signal is used to directly control a 5 Vp−p analog signal. The digital control logic levels are determined by VDD and VSS. The VDD voltage is the logic high voltage; the VSS voltage is logic low. For the example, VDD = +5 V logic high at the control inputs; VSS = GND = 0 V logic low. The maximum analog signal level is determined by VDD and VSS. The analog voltage must not swing higher than VDD or lower than VSS. The example shows a 5 Vp−p signal which allows no margin at either peak. If voltage transients above VDD and/or below VSS are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between VDD and VSS is 18.0 V. Most parameters are specified up to 15 V which is the recommended maximum difference between VDD and VSS. +5 V VSS VDD +5 V 5 Vp-p ANALOG SIGNAL EXTERNAL CMOS DIGITAL CIRCUITRY + 5.0 V SWITCH IN SWITCH OUT 5 Vp-p + 2.5 V ANALOG SIGNAL 0-TO-5 V DIGITAL GND CONTROL SIGNALS MC14016B Figure A. Application Example VDD VDD Dx Dx SWITCH IN SWITCH OUT Dx Dx VSS VSS Figure B. External Germanium or Schottky Clipping Diodes http://onsemi.com 8 MC14016B PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE K D A B 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 8 A3 E H L 1 0.25 M DETAIL A 7 B 13X M b 0.25 M C A S B S e DETAIL A h A X 45 _ M A1 C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ SOLDERING FOOTPRINT* 6.50 14X 1.18 1 1.27 PITCH 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 9 INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ MC14016B PACKAGE DIMENSIONS SOEIAJ−14 CASE 965 ISSUE B 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 8 Q1 M_ E HE L 7 1 DETAIL P Z D VIEW P A e c A1 b 0.13 (0.005) M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --1.42 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.056 ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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