CXD3408GA
Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
Description
The CXD3408GA is a timing generator and CCD
signal processor IC for the ICX406 CCD image sensor.
Features
• Timing generator functions
• Horizontal drive frequency 18MHz
(base oscillation frequency 36MHz)
• Supports frame readout/draft (quadruple speed)
/AF (auto-focus)
• High-speed/low-speed shutter function
• Horizontal and vertical drivers for CCD image
sensor
• CCD signal processor functions
• Correlated double sampling
• Programmable gain amplifier (PGA) allows gain
adjustment over a wide range (–6 to +42dB)
• 10-bit A/D converter
• Chip Scale Package (CSP):
CSP allows vast reduction in the CCD camera
block footprint
96 pin LFLGA (Plastic)
Absolute Maximum Ratings
• Supply voltage
VSS – 0.3 to +7.0
VDDa, VDDb, VDDc, VDDd
VDDe, VDDf, VDDg
VSS – 0.3 to +4.0
VL
–10.0 to VSS
VH
VL – 0.3 to +26.0
• Input voltage (analog)
VIN
VSS – 0.3 to VDD + 0.3
• Input voltage (digital)
VI
• Output voltage
VO1
VO2
VO3
• Operating temperature
Topr
• Storage temperature
Tstg
Applications
Digital still cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX406 (1/1.8", 3980K pixels)
V
V
V
V
V
VSS – 0.3 to VDD + 0.3
V
VSS – 0.3 to VDD + 0.3
VL – 0.3 to VSS + 0.3
VL – 0.3 to VH + 0.3
V
V
V
–20 to +75
°C
–55 to +125
°C
Recommended Operating Conditions
• Supply voltage
VDDb
3.0 to 5.25
V
VDDa, VDDc, VDDd, VDDe, VDDf, VDDg
3.0 to 3.6
V
VM
0.0
V
VH
14.5 to 15.5
V
VL
–7.0 to –8.0
V
• Operating temperature
Topr
–20 to +75
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01341A26
CXD3408GA
DVSS2
E2 F2 F3
DVSS1
B5
DVDD2
DVDD1
A3 A4 B4
DVSS3
TEST5
TEST3
A5 C4
SEN2
SSI2
SCK2
AVSS5
AVSS4
AVSS3
B8 B6 B9 A6 C5
TEST4
A1 A2 C7 D8 D7
AVDD4
AVDD3
C1
C2
C3
NC
NC
Block Diagram
E3 F1
C4 C8
AVDD5 A9
Serial Port
Register
DAC
AVSS6 A8
C7 B7
C8 A7
B3
D0 (LSB)
B2
D1
B1
D2
C3 D3
C9 C6
C2 D4
CDS
CCDIN C9
PGA
ADC
Latch
C1 D5
AVDD1 E9
D3 D6
AVDD2 E8
D2 D7
AVSS1 D9
D1 D8
AVSS2 E7
XSHPI
F9
XSHDI
F8
PBLKI
F7
XSHP
G9
XSHD
G8
PBLK
G7
E1
Dummy Pixel
Auto Zero
Preblanking
Black Level
Auto Zero
G1
G2
G3
L3
H1
XRS H7
H2
VDD4 H8
H3
VDD2 K7
J3
RG K8
VSS2 K9
L1
VDD3 H9
K1
Pulse Generator
H1 J8
J1
H2 J9
1/2
VSS3 J7
ID/EXP N9
Latch
D9 (MSB)
ADCLKI
CLPOBI
CLPDMI
VSS4
ADCLK
CLPOB
CLPDM
VSS5
OSCI
OSCO
CKI
J2
CKO
K2
MCKO
N8 SNCSL
Selector
WEN M9
L2
Serial Port
Register
VH M5
SSI1
M1 SCK1
V Driver
N1 SEN1
Selector
VM L4
–2–
L8
K3 L7
N3
VDD5
VSS6
VSS1
L9
VD
N2 M2
VDD1
SSG
HD
SUB
V4
V3B
V3A
N6 N4 N7
V2
L5 N5 M4 L6
V1B
TEST2
TEST1
RST
M8 M3 M7
V1A
VL M6
SSGSL
CXD3408GA
Pin Configuration (Top View)
A
NC
NC
SCK2
SSI2
TEST3
AVSS4
C8
AVSS6
AVDD5
B
D2
D1
D0
SEN2
TEST5
AVDD4
C7
AVDD3
AVSS3
C
D5
D4
D3
TEST4
AVSS5
C9
C3
C4
CCDIN
D
D8
D7
D6
C1
C2
AVSS1
E
D9
DVDD1
DVSS1
AVSS2
AVDD2
AVDD1
F
DVSS2
DVSS3
DVDD2
PBLKI
XSHDI
XSHPI
G
ADCLKI
CLPOBI
CLPDMI
PBLK
XSHD
XSHP
H
ADCLK
CLPOB
CLPDM
XRS
VDD4
VDD3
J
CKI
CKO
VSS5
VSS3
H1
H2
K
OSCO
MCKO
VDD5
VDD2
RG
VSS2
L
OSCI
SSI1
VSS4
VM
V1A
V3A
VSS1
SSGSL
VDD1
M
SCK1
VD
TEST1
V2
VH
VL
TEST2
RST
WEN
N
SEN1
HD
VSS6
V4
V1B
V3B
SUB
SNCSL
ID/EXP
1
2
3
4
5
6
7
8
9
–3–
CXD3408GA
Pin Description
Pin
No.
Symbol
I/O
Description
A1
NC
—
No connected. (Open)
A2
NC
—
No connected. (Open)
A3
SCK2
I
CCD signal processor block serial interface clock input. (Schmitt trigger)
A4
SSI2
I
CCD signal processor block serial interface data input. (Schmitt trigger)
A5
TEST3
I
CCD signal processor block test input 3. Connect to DVSS.
A6
AVSS4
—
CCD signal processor block analog GND.
A7
C8
—
Capacitor connection.
A8
AVSS6
—
CCD signal processor block analog GND.
A9
AVDD5
—
CCD signal processor block analog power supply.
B1
D2
O
ADC output.
B2
D1
O
ADC output.
B3
D0
O
ADC output (LSB).
B4
SEN2
I
CCD signal processor block serial interface enable input. (Schmitt trigger)
B5
TEST5
I
CCD signal processor block test input 5. Connect to DVDD.
B6
AVDD4
—
CCD signal processor block analog power supply.
B7
C7
—
Capacitor connection.
B8
AVDD3
—
CCD signal processor block analog power supply.
B9
AVSS3
—
CCD signal processor block analog GND.
C1
D5
O
ADC output.
C2
D4
O
ADC output.
C3
D3
O
ADC output.
C4
TEST4
I
CCD signal processor block test input 4. Connect to DVSS.
C5
AVSS5
—
CCD signal processor block analog GND.
C6
C9
—
Capacitor connection.
C7
C3
—
Capacitor connection.
C8
C4
—
Capacitor connection.
C9
CCDIN
I
CCD output signal input.
D1
D8
O
ADC output.
D2
D7
O
ADC output.
D3
D6
O
ADC output.
D7
C1
—
Capacitor connection.
D8
C2
—
Capacitor connection.
D9
AVSS1
—
CCD signal processor block analog GND.
E1
D9
O
ADC output (MSB).
E2
DVDD1
—
CCD signal processor block digital power supply. (Power supply for ADC)
–4–
CXD3408GA
Pin
No.
Symbol
I/O
Description
E3
DVSS1
—
CCD signal processor block digital GND.
E7
AVSS2
—
CCD signal processor block analog GND.
E8
AVDD2
—
CCD signal processor block analog power supply.
E9
AVDD1
—
CCD signal processor block analog power supply.
F1
DVSS2
—
CCD signal processor block digital GND.
F2
DVSS3
—
CCD signal processor block digital GND.
F3
DVDD2
—
CCD signal processor block digital power supply.
F7
PBLKI
I
Pulse input for horizontal and vertical blanking period pulse cleaning. (Schmitt trigger)
F8
XSHDI
I
CCD data level sample-and-hold pulse input. (Schmitt trigger)
F9
XSHPI
I
CCD precharge level sample-and-hold pulse input. (Schmitt trigger)
G1
ADCLKI
I
Clock input for analog/digital conversion. (Schmitt trigger)
G2
CLPOBI
I
CCD optical black signal clamp pulse input. (Schmitt trigger)
G3
CLPDMI
I
CCD dummy signal clamp pulse input. (Schmitt trigger)
G7
PBLK
O
Pulse output for horizontal and vertical blanking period pulse cleaning.
G8
XSHD
O
CCD data level sample-and-hold pulse output.
G9
XSHP
O
CCD precharge level sample-and-hold pulse output.
H1
ADCLK
O
Clock output for analog/digital conversion.
H2
CLPOB
O
CCD optical black signal clamp pulse output.
H3
CLPDM
O
CCD dummy signal clamp pulse output.
H7
XRS
O
Sample-and-hold pulse output for analog/digital conversion phase alignment.
H8
VDD4
—
Timing generator block digital power supply. (Power supply for CDS block)
H9
VDD3
—
Timing generator block 3.0 to 5.0V power supply. (Power supply for H1/H2)
J1
CKI
I
Inverter input.
J2
CKO
O
Inverter output.
J3
VSS5
—
Timing generator block digital GND.
J7
VSS3
—
Timing generator block digital GND.
J8
H1
O
CCD horizontal register clock output.
J9
H2
O
CCD horizontal register clock output.
K1
OSCO
O
Inverter output for oscillation. When not used, leave open or connect a capacitor.
K2
MCKO
O
System clock output for signal processor IC.
K3
VDD5
—
Timing generator block digital power supply. (Power supply for common logic block)
K7
VDD2
—
Timing generator block digital power supply. (Power supply for RG)
K8
RG
O
CCD reset gate pulse output.
K9
VSS2
—
Timing generator block digital GND.
L1
OSCI
I
Inverter input for oscillation. When not used, fix to low.
–5–
CXD3408GA
Pin
No.
Symbol
I/O
Description
Timing generator block serial interface data input.
Schmitt trigger input/No protective diode on power supply side.
L2
SSI1
I
L3
VSS4
—
Timing generator block digital GND.
L4
VM
—
Timing generator block digital GND. (GND for vertical driver)
L5
V1A
O
CCD vertical register clock output.
L6
V3A
O
CCD vertical register clock output.
L7
VSS1
—
Timing generator block digital GND.
L8
SSGSL
L9
VDD1
—
M1
SCK1
I
Timing generator block serial interface clock input.
Schmitt trigger input/No protective diode on power supply side.
M2
VD
I
Vertical sync signal input.
M3
TEST1
I
Timing generator block test input 1.
Normally fix to GND.
M4
V2
O
CCD vertical register clock output.
M5
VH
—
Timing generator block 15.0V power supply. (Power supply for vertical driver)
M6
VL
—
Timing generator block –7.5V power supply. (Power supply for vertical driver)
M7
TEST2
I
Internal SSG enable.
High: Internal SSG valid, Low: External sync valid
(With pull-down resistor)
Timing generator block digital power supply. (Power supply for common logic block)
I
Timing generator block test input 2.
Normally fix to GND.
(With pull-down resistor)
(With pull-down resistor)
M8
RST
I
Timing generator block reset input.
High: Normal operation, Low: Reset control
Normally apply reset during power-on.
Schmitt trigger input/No protective diode on power supply side
M9
WEN
O
Memory write timing pulse output.
N1
SEN1
I
Timing generator block serial interface strobe input.
Schmitt trigger input/No protective diode on power supply side
N2
HD
I
Horizontal sync signal input.
N3
VSS6
—
Timing generator block digital GND.
N4
V4
O
CCD vertical register clock output.
N5
V1B
O
CCD vertical register clock output.
N6
V3B
O
CCD vertical register clock output.
N7
SUB
O
CCD electronic shutter pulse output.
N8
SNCSL
I
Control input used to switch sync system.
High: CKI sync, Low: MCKO sync
N9
ID/EXP
O
Vertical direction line identification pulse output/exposure time identification pulse
output.
Switching possible using the serial interface data. (Default: ID)
–6–
(With pull-down resistor)
CXD3408GA
Electrical Characteristics
Timing Generator Block Electrical Characteristics
DC Characteristics
Item
(Within the recommended operating conditions)
Pins
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply voltage 1 VDD2
VDDa
3.0
3.3
3.6
V
Supply voltage 2 VDD3
VDDb
3.0
3.3
5.25
V
Supply voltage 3 VDD4
VDDc
3.0
3.3
3.6
V
Supply voltage 4 VDD1, VDD5
VDDd
3.0
3.3
3.6
V
Input
voltage 1∗1
RST, SCK1,
SSI1, SEN1
VI +
Input
voltage 2∗2
TEST1, TEST2 VIH1
SNCSL, SSGSL VIL1
0.7VDDd
VIH2
0.8VDDd
Input/Output
voltage
VD, HD
VI –
VOL1
Pull-in current where IOL = 2.4mA
VOH2
Feed current where IOH = –22.0mA VDDb – 0.8
VOL2
Pull-in current where IOL = 14.4mA
VOH3
Feed current where IOH = –3.3mA
VOL3
Pull-in current where IOL = 2.4mA
Output
voltage 2
RG
Output
voltage 3
XSHP, XSHD,
VOH4
XRS, PBLK,
CLPOB,
CLPDM,
VOL4
ADCLK
CKO
Output
voltage 5
MCKO
Output
voltage 6
ID/EXP,
WEN
Output
current 1
V1A, V1B,
V3A, V3B,
V2, V4
Output
current 2
SUB
Feed current where IOH = –3.3mA
VDDd – 0.8
VOH5
Feed current where IOH = –6.9mA
VOL5
Pull-in current where IOL = 4.8mA
VOH6
Feed current where IOH = –3.3mA
VOL6
Pull-in current where IOL = 2.4mA
VOH7
Feed current where IOH = –2.4mA
VOL7
Pull-in current where IOL = 4.8mA
IOL
V1A/B, V2, V3A/B, V4 = –8.25V
IOM1
V1A/B, V2, V3A/B, V4 = –0.25V
IOM2
V1A/B, V3A/B = 0.25V
IOH
V1A/B, V3A/B = 14.75V
IOSL
SUB = –8.25V
IOSH
SUB = 14.75V
V
V
0.4
V
V
0.4
VDDa – 0.8
V
V
0.4
V
V
VDDc – 0.8
Pull-in current where IOL = 2.4mA
V
V
0.2VDDd
Feed current where IOH = –1.2mA
V
V
0.3VDDd
VOH1
H1, H2
Output
voltage 4
0.2VDDd
VIL2
Output
voltage 1
V
0.8VDDd
0.4
VDDd – 0.8
V
V
0.4
VDDd – 0.8
V
V
0.4
VDDd – 0.8
V
V
0.4
10.0
V
mA
–5.0
5.0
mA
mA
–7.2
5.4
mA
mA
–4.0
mA
∗1 This input pin is a schmitt trigger input and it does not have protective diode of the power supply side in the IC.
∗2 These input pins are with pull-down resistor in the IC.
Note) This table indicates conditions at 3.3V drive.
–7–
CXD3408GA
Inverter I/O Characteristics for Oscillation
Item
Pins
Symbol
Logical Vth
OSCI
Input
voltage
OSCI
Output
voltage
OSCO
Feedback
resistor
OSCI, OSCO RFB
Oscillation
frequency
OSCI, OSCO f
(Within the recommended operating conditions)
Min.
Conditions
Typ.
LVth
Max.
VDDd/2
VIH
V
0.7VDDd
V
VIL
0.3VDDd
VOH
Feed current where IOH = –3.6mA
VOL
Pull-in current where IOL = 2.4mA
VIN = VDDd or VSS
VDDd – 0.8
500k
Unit
V
V
2M
20
0.4
V
5M
Ω
50
MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Item
Pins
Logical Vth
Input
voltage
Symbol
Conditions
Min.
LVth
CKI
Input
amplitude
Typ.
VDDd/2
VIH
V
0.3VDDd
fmax 50MHz sine wave
Unit
V
0.7VDDd
VIL
VIN
Max.
0.3
V
Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude
is the input amplitude characteristics in the case of input through a capacitor.
Switching Characteristics
Item
Rise time
Fall time
Output noise voltage
(VH = 15.0V, VM = GND, VL = –7.5V)
Symbol
Conditions
Min.
Typ.
Max.
Unit
TTLM
VL to VM
200
350
500
ns
TTMH
VM to VH
200
350
500
ns
TTLH
VL to VH
30
60
90
ns
TTML
VM to VL
200
350
500
ns
TTHM
VH to VM
200
350
500
ns
TTHL
VH to VL
30
60
90
ns
VCLH
1.0
V
VCLL
1.0
V
VCMH
1.0
V
VCML
1.0
V
Notes)
1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between
each power supply pin (VH, VL) and GND.
3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.
–8–
CXD3408GA
Switching Waveforms
TTMH
TTHM
VH
V1A (V1B, V3A, V3B)
TTLM
90%
90%
10%
10%
TTML
VM
90%
90%
10%
10%
TTML
TTLM
VL
VM
90%
90%
V2 (V4)
10%
10%
TTLH
TTHL
90%
VL
VH
90%
SUB
10%
10%
VL
Waveform Noise
VM
VCMH
VCML
VCLH
VCLL
VL
–9–
– 10 –
C1
R1
R1
C2
R1
C1
C2
C2 C2
C1 C2
3300pF
30Ω
C2
C1
C2
C2
C1
C2
C2
R2
C2
R2
C1
C2
C1
C2
560pF
10Ω
R1
C2
R1
C3
820pF
C3
C4
D2
AVDD5
AVSS6
C8
AVSS4
TEST3
SSI2
SCK2
NC
NC
C6
CXD3408GA
PBLKI
V3A
L6
VSS1
8pF
N9 ID/EXP
N8 SNCSL
L7
N7 SUB
V1A
VM
L5
L4
N2 HD
N1 SEN1
M9 WEN
M8 RST
M7 TEST2
N6 V3B
N5 V1B
N4 V4
M3 TEST1
180pF
C6
10pF
A2 A1 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B9 B8 C1 C2 C3 C4 C5 C6
C5
F2
F3
F7
F8
F9
E9
E2
E8
D8
D7
D3
D2
D1
C9
C8
C7
AVDD2
C2
C1
D6
D7
D8
CCDIN
C4
C3
DVSS1
DVDD1
F1
E3
DVSS2
E7
D9
AVSS2
AVSS1
AVDD1
ADCLKI G1
DVSS3
AVDD4
M2 VD
D1
C2
C7
DVDD2
AVSS3
M1 SCK1
D0
C2
VSS6
VDD1
SSI1
L9
MCKO
XSHDI
RG
SSGSL
VSS2
L8
VDD2
H1
OSCI
XSHPI
OSCO
ADCLK
H2
E1 D9
VDD5
CLPOBI G2
H1
M6 VL
VSS3
CLPDMI G3
CKI
M5 VH
VDD3
M4 V2
VSS5
SEN2
R1
C6
CKO
TEST5
R1
C5 C5
VDD4
N3 L2 K2 K9 K8 K7 K1 L1 K3 J9 J8 J7 J3 J2 J1 H9 H8 H7 H3 H2 L3 G9 G8 G7
C4
XRS
AVDD3
–7.5V
C6
CLPDM
D5
+3.3V
CLPOB
D4
+15.0V
VSS4
D3
VD
CKI
XSHP
TEST4
HD
Serial interface data
XSHD
AVSS5
PBLK
C9
Measurement Circuit
CXD3408GA
CXD3408GA
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDDd
SSI1
0.2VDDd
0.8VDDd
SCK1
ts1
SEN1
th1
0.2VDDd
ts3
0.8VDDd
SEN1
ts2
(Within the recommended operating conditions)
Symbol
ts1
th1
ts2
ts3
Definition
Min.
Typ.
Max.
Unit
SSI1 setup time, activated by the rising edge of SCK1
20
ns
SSI1 hold time, activated by the rising edge of SCK1
20
ns
SCK1 setup time, activated by the rising edge of SEN1
20
ns
SEN1 setup time, activated by the rising edge of SCK1
20
ns
Serial interface clock internal loading characteristics (1)
Example: During frame mode
VD
HD
V1A
Enlarged view
HD
0.2VDDd
V1A
ts1
SEN1
th1
0.8VDDd
0.2VDDd
∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal period
during which V1A/B and V3A/B values take the ternary value and during that horizontal period.
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
SEN1 setup time, activated by the falling edge of HD
0
ns
SEN1 hold time, activated by the falling edge of HD
110
µs
– 11 –
CXD3408GA
Serial interface clock internal loading characteristics (2)
Example: During frame mode
VD
HD
Enlarged view
VD
0.2VDDd
HD
ts1
SEN1
th1
0.8VDDd
0.2VDDd
∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD.
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
SEN1 setup time, activated by the falling edge of VD
0
ns
SEN1 hold time, activated by the falling edge of VD
200
ns
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD3408GA at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD3408GA and controlled at the rising edge of SEN1. See "Description of Operation".
SEN1
0.8VDDd
Output signal
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
Min.
tpdPULSE Output signal delay, activated by the rising edge of SEN1
– 12 –
5
Typ.
Max.
Unit
100
ns
CXD3408GA
RST loading characteristics
RST
0.8VDDd
0.2VDDd
tw1
(Within the recommended operating conditions)
Symbol
tw1
Definition
Min.
RST pulse width
Typ.
Max.
Unit
ns
25
VD and HD phase characteristics
VD
0.2VDDd
0.2VDDd
ts1
th1
HD
0.2VDDd
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
VD setup time, activated by the falling edge of HD
Typ.
Max.
Unit
ns
100
VD hold time, activated by the falling edge of HD
20
ns
HD loading characteristics
HD
0.2VDDd
0.2VDDd
ts1
th1
0.8VDDd
MCKO
MCKO load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
HD setup time, activated by the rising edge of MCKO
20
ns
HD hold time, activated by the rising edge of MCKO
5
ns
– 13 –
CXD3408GA
Output variation characteristics
0.8VDDd
MCKO
WEN, ID/EXP
tpd1
WEN and ID/EXP load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpd1
Definition
Min.
Time until the above outputs change after the rise of MCKO
20
– 14 –
Typ.
Max.
Unit
60
ns
CXD3408GA
CCD Signal Processor Block Electrical Characteristics
DC Characteristics
Item
(Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Pins
Conditions
Symbol
Min.
Typ. Max. Unit
Supply voltage 1 DVDD1
VDDe
3.0
3.3
3.6
V
Supply voltage 2 DVDD2
VDDf
3.0
3.3
3.6
V
AVDD1,
AVDD2,
Supply voltage 3 AVDD3,
AVDD4,
AVDD5
VDDg
3.0
3.3
3.6
V
Analog input
capacitance
CCDIN
CIN
15
pF
1.8
V
Input voltage
SCK2, SSI2,
VI +
SEN2, TEST3,
TEST4, XSHDI,
XSHPI, ADCLKI, VI –
CLPOBI,
CLPDMI, PBLKI
1.1
V
A/D clock duty
ADCLKI
50
%
Output voltage D0 to D9
VOH
Feed current where IOH = –2.0mA
VOL
Pull-in current where IOL = 2.0mA
Analog Characteristics
Item
VDDe – 0.9
V
0.4
V
(Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Symbol
Conditions
Min. Typ. Max. Unit
CCDIN input voltage amplitude
VIN
PGA gain = 0dB, output full scale
PGA maximum gain
Gmax
PGA gain setting data = "3FFh"
42
dB
PGA minimum gain
Gmin
PGA gain setting data = "000h"
–6
dB
10
bit
900
ADC resolution
1100 mV
ADC maximum conversion rate
Fc max
ADC integral non-linearity error
EL
PGA gain = 0dB
±1.0 ±5.0 LSB
ADC differential non-linearity error
ED
PGA gain = 0dB
±0.5 ±1.0 LSB
Signal-to-noise ratio
SNR∗1
CCDIN input connected to GND
via a coupling capacitor
PGA gain = 0dB
CCDIN input voltage clamp level
CLP
CCD optical black signal clamp
level
OB
18
OBLVL = "8h"
PGA gain = 0dB
∗1 SNR = 20 log (full-scale voltage/rms noise)
– 15 –
MHz
62
dB
1.5
V
32
LSB
CXD3408GA
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDD
SSI2
0.2VDD
0.8VDD
SCK2
ts1
SEN2
th1
0.2VDD
ts3
0.8VDD
SEN2
ts2
∗ The setting values are reflected to the operation 6 ADCLKI clocks after the serial data is loaded at the rise of
SEN2.
(Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Symbol
tp1
ts1
th1
ts2
ts3
Definition
Min.
Typ.
Max.
Unit
SCK2 clock period
100
ns
SSI2 setup time, activated by the rise of SCK2
30
ns
SSI2 hold time, activated by the rise of SCK2
30
ns
SCK2 setup time, activated by the rise of SEN2
30
ns
SEN2 setup time, activated by the rise of SCK2
30
ns
– 16 –
CXD3408GA
CDS/ADC Timing Chart
N
N+1
N+2
N+3
CCDIN
XSHPI
XSHDI
tw1
ADCLKI
DL
D0 to D9
N – 10
N–9
N–8
N–7
∗ Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0".
(Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Definition
Symbol
tw1
DL
Min.
ADCLKI clock period
Typ.
54
Max.
Unit
ns
ADCLKI clock duty
50
%
Data latency
9
clocks
Preblanking Timing Chart
PBLKI
11 Clocks
ADCLKI
11 Clocks
All "0"
D0 to D9
– 17 –
CXD3408GA
Description of Operation
Pulses output from the CXD3408GA's timing generator block are controlled mainly by the RST pin and by the
serial interface data. The Pin Status Table is shown below, and the details of serial interface control are
described on page 20 and thereafter.
Pin Status Table
Pin
No.
Symbol
—
D3
D6
—
NC
—
D7
C1
—
A3
SCK2
—
D8
C2
—
A4
SSI2
—
D9
AVSS1
—
A5
TEST3
—
E1
D9
—
A6
AVSS4
—
E2
DVDD1
—
A7
C8
—
E3
DVSS1
—
A8
AVSS6
—
E7
AVSS2
—
A9
AVDD5
—
E8
AVDD2
—
B1
D2
—
E9
AVDD1
—
B2
D1
—
F1
DVSS2
—
B3
D0
—
F2
DVSS3
—
B4
SEN2
—
F3
DVDD2
—
B5
TEST5
—
F7
PBLKI
—
B6
AVDD4
—
F8
XSHDI
—
B7
C7
—
F9
XSHPI
—
B8
AVDD3
—
G1
ADCLKI
—
B9
AVSS3
—
G2
CLPOBI
—
C1
D5
—
G3
CLPDMI
—
C2
D4
—
G7
PBLK
ACT
C3
D3
—
G8
XSHD
C4
TEST4
—
G9
C5
AVSS5
—
C6
C9
C7
Pin
No.
Symbol
A1
NC
A2
CAM
SLP
STB
RST
STB
RST
L
L
H
ACT
L
L
ACT
XSHP
ACT
L
L
ACT
H1
ADCLK
ACT
L
L
ACT
—
H2
CLPOB
ACT
L
L
H
C3
—
H3
CLPDM
ACT
L
L
H
C8
C4
—
H7
XRS
ACT
L
L
ACT
C9
CCDIN
—
H8
VDD4
—
D1
D8
—
H9
VDD3
—
D2
D7
—
J1
CKI
ACT
ACT
– 18 –
CAM
ACT
SLP
ACT
CXD3408GA
Pin
No.
Symbol
CAM
SLP
STB
RST
Pin
No.
Symbol
J2
CKO
ACT
ACT
L
ACT
L9
VDD1
J3
VSS5
—
M1
J7
VSS3
—
M2
SCK1
VD∗1
J8
H1
ACT
L
L
ACT
M3
TEST1
J9
H2
ACT
L
L
ACT
M4
V2
K1
OSCO
ACT
ACT
ACT
ACT
M5
VH
—
K2
MCKO
ACT
ACT
L
ACT
M6
VL
—
K3
VDD5
—
M7
TEST2
—
K7
VDD2
—
M8
RST
ACT
K8
RG
M9
WEN
K9
VSS2
N1
L1
OSCI
ACT
ACT
ACT
ACT
N2
SEN1
HD∗1
L2
SSI1
ACT
ACT
ACT
DIS
N3
VSS6
L3
VSS4
—
N4
V4
ACT
L4
VM
—
N5
V1B
L5
V1A
ACT
VH
VH
VM
N6
L6
V3A
ACT
VH
VH
VL
L7
VSS1
L8 SSGSL
ACT
L
L
ACT
—
—
ACT
ACT
ACT
ACT
CAM
SLP
STB
RST
—
ACT
ACT
ACT
DIS
ACT
L
L
H
VM
VM
ACT
ACT
L
ACT
L
L
L
ACT
ACT
ACT
DIS
ACT
L
L
H
VM
VM
VL
ACT
VH
VH
VM
V3B
ACT
VH
VH
VL
N7
SUB
ACT
VH
VH
VL
N8
SNCSL
ACT
ACT
ACT
ACT
N9
ID/EXP
ACT
L
L
L
—
ACT
VM
—
∗1 It is for output. For input, all items are "ACT".
Note) ACT means that the circuit is operating, and DIS means that loading is stopped.
L indicates a low output level, and H a high output level in the controlled status.
Also, VH, VM and VL indicate the voltage levels applied to VH (Pin M5), VM (Pin L4) and VL (Pin M6),
respectively, in the controlled status.
– 19 –
CXD3408GA
Timing Generator Block Serial Interface Control
The CXD3408GA's timing generator block basically loads and reflects the timing generator block serial
interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion
specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value.
Note that some items reflect the timing generator block serial interface data at the falling edge of VD or the
rising edge of SEN1.
SSI1
00
01
02
03
04
05
06
07
41
42
43
44
45
46
47
SCK1
SEN1
There are two categories of timing generator block serial interface data: CXD3408GA timing generator block
drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data").
The details of each data are described below.
– 20 –
CXD3408GA
Control Data
Data
D00
to
D07
Symbol
Function
Data = 0
Data = 1
RST
Chip enable
10000001 → Enabled
Other values → Disabled
All
0
D08,
CTG
D09
Category switching
See D08 to D09 CTG.
All
0
D10
to
D12
MODE
Drive mode switching
See D10 to D12 MODE.
All
0
D13
SMD
Electronic shutter mode switching∗1
OFF
ON
0
D14
HTSG
HTSG control switching∗1
OFF
ON
0
—
—
All
0
NTSC
PAL
0
—
—
—
All
0
OFF
ON
0
ID
EXP
0
CHIP
D15,
D16
D17
—
NTPL
D18
to
D31
—
SSG function switching
—
D32
FGOB
Wide OBCLP generation switching
D33
EXP
ID/EXP output switching
D34,
PTOB
D35
OBCLP waveform patterm switching
See D34 to D35 PTOB.
All
0
D36,
LDAD
D37
ADCLK logic phase adjustment
See D36 to D37 LDAD.
1
0
D38,
STB
D39
Standby control
See D38 to D39 STB.
All
0
D40
to
D47
—
—
—
∗1 See D13 SMD.
– 21 –
—
All
0
CXD3408GA
Shutter Data
Data
D00
to
D07
Symbol
Function
Data = 0
Data = 1
RST
Chip enable
10000001 → Enabled
Other values → Disabled
All
0
D08,
CTG
D09
Category switching
See D08 to D09 CTG.
All
0
D10
to
D19
SVD
Electronic shutter vertical period
specification
See D10 to D19 SVD.
All
0
D20
to
D31
SHD
Electronic shutter horizontal period
specification
See D20 to D31 SHD.
All
0
D32
to
D41
SPL
High-speed shutter position
specification
See D32 to D41 SPL.
All
0
D42
to
D47
CHIP
—
—
—
– 22 –
—
All
0
CXD3408GA
Detailed Description of Each Data
Shared data: D08 , D09 CTG [Category]
Of the data provided to the CXD3408GA by the serial interface, the CXD3408GA loads D10 and subsequent
data to each data register as shown in the table below according to the combination of D08 and D09 .
D09
D08
Description of operation
0
0
Loading to control data register
0
1
Loading to shutter data register
1
X
Test mode
Note that the CXD3408GA can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Control data: D10 to D12 MODE [Drive mode]
The CXD3408GA timing generator block drive mode can be switched as follows. However, the drive mode bits
are located to the CXD3408GA and reflected at the falling edge of VD.
D12
D11
D10
0
0
0
0
0
0
0
Description of operation
D12
D11
D10
Description of operation
Draft mode (default)
1
0
0
Draft mode
1
AF1 mode
1
0
1
Frame mode (A field read out)
1
0
AF2 mode
1
1
0
Frame mode (B field read out)
1
1
Frame mode
1
1
1
Test mode
Draft mode is the pulse eliminator drive mode called octuple speed mode in the ICX406. This is a high frame
rate drive mode that can be used for purposes such as monitoring and auto focus (AF).
AF1 and AF2 modes are the pulse eliminator drive modes called by the same names in the ICX406. These
drive modes are based on draft mode, and are used to increase the frame rate for auto focus (AF). In these
modes, the screen is swept in the vertical direction and the center portion lines are cut out.
Frame mode is the ICX406 drive mode in which the data for all lines are read. This drive mode is comprised of
A and B Fields, so when it is established, repeated drive is performed in the manner of A → B → A → and so
on.
Frame mode (A or B Field) is the drive mode in which each field can be specified separately.
Control data: D17 NTPL [SSG function switching]
The CXD3408GA internal SSG output pattern can be switched as follows. However, the SSG function switching
bits are loaded to the CXD3408GA and reflected at the falling edge of VD.
D17
Description of Operation
0
NTSC equivalent pattern output
1
PAL equivalent pattern output
VD period in each pattern is defined as follows.
NTSC equivalent pattern
PAL equivalent pattern
Frame mode
Draft mode
AF1 mode
AF2 mode
1012H + 1672ck
224H + 1372ck × 2
112H + 1372ck
56H + 686ck
944H + 464ck
269H + 2039ck
134H + 2354ck
67H + 1178ck
See the Timing Charts for the actual operation.
– 23 –
CXD3408GA
Control data: D32 FGOB [Wide CLPOB generation]
This controls wide CLPOB generation during the vertical OPB period. See the Timing Charts for the actual
operation. The default is "OFF".
D32
Description of operation
0
Wide CLPOB generation OFF
1
Wide CLPOB generation ON
Control data: D34 , D35 PTOB [CLPOB waveform pattern]
This indicates the CLPOB waveform pattern. The default is "Normal".
D35
D34
Waveform pattern
0
0
(Normal)
0
1
(Shifted rearward)
1
0
(Shifted forward)
1
1
(Wide)
Control data: D36 , D37 LOAD [ADCLK logical phase]
This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO.
D37
D36
Degree of adjustment (°)
0
0
0
0
1
90
1
0
180
1
1
270
Control data: D38 , D39 STB [Standby]
The operating mode is switched as follows. However, the standby bits are loaded to the CXD3408GA and
control is applied immediately at the rising edge of SEN1.
D39
D38
Symbol
Operating mode
X
0
CAM
Normal operating mode
0
1
SLP
Sleep mode
1
1
STB
Standby mode
See the Pin Status Table for the pin status in each mode.
– 24 –
CXD3408GA
Control data/shutter data: [Electronic shutter]
The CXD3408GA realizes various electronic shutter functions by using control data D13 SMD and D14 HTSG
and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL.
These functions are described in detail below.
First, the various modes are shown below.
These modes are switched using control data D13 SMD.
D13
Description of operation
0
Electronic shutter stopped mode
1
Electronic shutter mode
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example.
However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC.
MSB
LSB
D31
D30
X
0
↓
1
D29
D28
D27
D26
0
1
1
1
↓
C
D25
D24
D23
D22
0
0
0
0
D21
D20
1
1
↓
3
SHD is expressed as 1C3h .
[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[Electronic shutter mode]
During this mode, the shutter data items have the following meanings.
Symbol
Data
Description
SVD
D10 to D19
Number of vertical periods specification (000h ≤ SVD ≤ 3FFh)
SHD
D20 to D31
Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh)
SPL
D32 to D41
Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh)
Note) The bit data definition area is assured in terms of the CXD3408GA functions, and does not assure the
CCD characteristics.
The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure
time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the
operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors.
(Exposure time) = SVD + {(number of HD per 1V) – (SHD + 1)}
Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed
shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this
period is finished.
The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of
horizontal periods applied to SHD can be considered as (number of SUB pulses – 1).
– 25 –
CXD3408GA
VD
SVD
SHD
V1A
SUB
WEN
EXP
SMD
1
1
SVD
002h
000h
SHD
10Fh
050h
Exposure time
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the
low-speed shutter period.
In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
SPL
000
001
VD
002
SVD
SHD
V1A
SUB
WEN
EXP
SMD
1
SPL
001h
000h
SVD
002h
000h
SHD
10Fh
0A3h
1
Exposure time
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD.
Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed
shutter to high-speed shutter or vice versa.
– 26 –
CXD3408GA
[HTSG control mode]
This mode controls the V1A/B and V3A/B ternary level outputs (readout pulse block) using D14 HTSG.
D14
Description of operation
0
Readout pulse (SG) normal operation
1
HTSG control mode
VD
V1A
SUB
Vck
WEN
EXP
HTSG
0
1
0
SMD
1
0
1
Exposure time
[EXP pulse]
The ID/EXP pin (N9) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The
default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time
when it is high. The transition point is the last SUB pulse falling edge, and midpoint value (1338ck) of each
V1A/B and V3A/B ternary out put falling edge. When there is no SUB pulse, the later ternary output falling
edge (1416ck) is used. See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for
an image of operation.
Note that the above specification is based on draft mode. For frame mode, the former value is 1260ck and the
latter value is 1416ck.
– 27 –
– 28 –
WEN
ID/EXP
CLPDM
CLPOB
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HD
VD
C
High-speed sweep block
1013 1
A
75
82
1 3 5 7 9 11 1 3 5 7 9 11
A Field
MODE
Frame mode
1719
1547
1715
1713
1709
1711
1718
1716
1714
1712
943
C
1013 1
High-speed sweep block
• ICX406
B
74
B Field
82
2 4 6 8 10 12 2 4 6 8
Applicable CCD image sensor
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗ VD of this chart is NTSC equivalent pattern (1012H + 1672ck units). For PAL equivalent pattern, it is 944H + 464ck units.
943
Vertical Direction Timing Chart
1720
Chart-1
CXD3408GA
– 29 –
WEN
ID/EXP
CLPDM
CLPOB
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HD
VD
D
3
10 5 14 21 30 37 46
1 6 1 10 17 26 33 42
226 1
MODE
Draft mode
1713 1717
1706 1710
1706 1710
218
D
3
10 5 14 21 30 37 46
1 6 1 10 17 26 33 42
226 1
• ICX406
Applicable CCD image sensor
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗ VD of this chart is NTSC equivalent pattern (224H + 1372ck + 1372ck units). For PAL equivalent pattern, it is 269H + 2039ck units.
218
Vertical Direction Timing Chart
1713 1717
Chart-2
CXD3408GA
– 30 –
WEN
ID/EXP
CLPDM
CLPOB
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HD
VD
Chart-3
∗
∗
∗
∗
High-speed
sweep block
E
113
10
6
F Frame shift block
2
9
MODE
AF1 mode
G
High-speed
sweep block
106
E
113
10
6
F Frame shift block
2
• ICX406
9
Applicable CCD image sensor
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
240 stages are fixed for high-speed sweep block; 232 stages are fixed for frame shift block.
VD of this chart is NTSC equivalent pattern (112H + 1372ck units). For PAL equivalent pattern, it is 134H + 2354ck units.
G
106
Vertical Direction Timing Chart
CXD3408GA
– 31 –
WEN
ID/EXP
CLPDM
CLPOB
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HD
VD
Chart-4
∗
∗
∗
∗
High-speed sweep block
E
57
10
6
F
2
Frame shift block
12
MODE
AF2 mode
57
G High-speed sweep block E
47
10
6
F
2
Frame shift block
• ICX406
12
Applicable CCD image sensor
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
360 stages are fixed for high-speed sweep block; 360 stages are fixed for frame shift block.
VD of this chart is NTSC equivalent pattern (56H + 686ck units). For PAL equivalent pattern, it is 67H + 1178ck units.
G
47
Vertical Direction Timing Chart
CXD3408GA
HD
– 32 –
∗
∗
∗
∗
∗
4
(2669)
0
16
16
24
32
42
50
50
58
58
58
60
60
60
92
100
124
124
124
Horizontal Direction Timing Chart
156
150
168
188
200
220
232
252
250
MODE
Frame mode
284
300
319
317
343
347
343
345 361 365
350
400
• ICX406
450
Applicable CCD image sensor
500
The HD of this chart indicates the actual CXD3408GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1.
WEN
ID/EXP
CLPDM
CLPOB (wide)
CLPOB (4)
CLPOB (3)
CLPOB (2)
CLPOB (1)
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
Chart-5
550
CXD3408GA
– 33 –
∗
∗
∗
∗
∗
4
(2669)
0
16
16
24
32
42
50
50
58
58
58
60
60
60
68
76
84
124
124
168
200
204
212
232
308
300
300
292
284
276
268
260
252
244
236
228
220
250
319
317
MODE
Draft mode, AF1 mode, AF2 mode
196
188
180
172
164
156
150
148
140
132
124
116
108
100
92
100
Horizontal Direction Timing Chart
343
347
343
345 361 365
350
400
• ICX406
450
500
Applicable CCD image sensor
The HD of this chart indicates the actual CXD3408GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4.
WEN
ID/EXP
CLPDM
CLPOB (wide)
CLPOB (4)
CLPOB (3)
CLPOB (2)
CLPOB (1)
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HD
Chart-6
550
CXD3408GA
– 34 –
∗
∗
∗
∗
∗
∗
4
(2669)
0
50
60
60
60
88
88
100
#1
116
116
Horizontal Direction Timing Chart
(High-speed sweep: C)
144
144
150
168
172
172
200
200
200
232
#2
228
228
256
256
250
MODE
Frame mode
284
284
300
312
312
317
#3
340
340
368
368
345 361 365
350
396
396
400
424
424
• ICX406
#4
452
452
450
480
480
508
508
500
Applicable CCD image sensor
536
536
The HD of this chart indicates the actual CXD3408GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID.
High-speed sweep of V1A/B, V2, V3A/B, V4 is performed up to 72H of 2660ck (#1739).
WEN
ID/EXP
CLPDM
CLPOB
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HD
Chart-7
#5
550
564
564
CXD3408GA
– 35 –
∗
∗
∗
∗
∗
∗
4
(2669)
0
24
50
50
60
60
60
68
76
84
#1
124
#2
168
204
232
#4
350
#5
#6
#7
500
556
550
#8
548
540
532
524
516
508
500
492
484
476
468
460
452
450
444
436
428
420
412
404
400
• ICX406
Applicable CCD image sensor
396
388
380
372
364
356
348
345 361 365
340
332
324
317
316
308
300
300
292
284
276
268
260
252
244
236
228
#3
212
220
250
MODE
AF1 mode, AF2 mode
200
196
188
180
172
164
156
150
148
140
132
124
116
108
100
92
100
Horizontal Direction Timing Chart
(Frame shift: F)
(High-speed sweep: G)
The HD of this chart indicates the actual CXD3408GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. PBLK, CLPOB, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4.
Frame shift of V1A/B, V2, V3A/B and V4 is performed up to 7H 1563ck (#232) in AF1 mode and 10H 1688ck (#360) in AF2 mode.
In addition, high-speed sweep is performed up to 111H 2015ck (#240) in AF1 mode and 55H 1688ck (#360) in AF2 mode.
WEN
ID/EXP
CLPDM
CLPOB
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HD
Chart-8
CXD3408GA
– 36 –
V4
V3B
V3A
V2
V1B
V1A
V4
V3B
V3A
V2
V1B
V1A
HD
B
A
• ICX406
(2669)
0
124
1168
1136
1104
Applicable CCD image sensor
284
252
220
1292
1260
∗ The HD of this chart indicates the actual CXD3408GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
[B Field]
[A Field]
(2669)
0
1200 1202
MODE
Frame mode
156
Horizontal Direction Timing Chart
188
Chart-9
CXD3408GA
– 37 –
D
1416
1356 1358
1324
1292
1260
1136
1104
(2669)
0
• ICX406
Applicable CCD image sensor
∗ The HD of this chart indicates the actual CXD3408GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
V4
V3B
V3A
V2
V1B
V1A
HD
(2669)
0
1168
MODE
Draft mode
1200 1202
Horizontal Direction Timing Chart
68
84
100
116
132
148
164
180
60
76
92
108
124
140
156
172
Chart-10
CXD3408GA
– 38 –
E
1448
1464 1456
1480 1472
1496 1488
1512 1504
1528 1520
1544 1536
1560 1552
1568
1416
1292
1260
1200 1202
1168
1136
1104
(2669)
0
• ICX406
Applicable CCD image sensor
∗ The HD of this chart indicates the actual CXD3408GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
V4
V3B
V3A
V2
V1B
V1A
HD
(2669)
0
1324
MODE
AF1 mode, AF2 mode
1356 1358
Horizontal Direction Timing Chart
68
84
100
116
132
148
164
180
196
212
228
244
260
276
292
308
60
76
92
108
124
140
156
172
188
204
220
236
252
268
284
300
Chart-11
CXD3408GA
– 39 –
XRS
XSHD
XSHP
RG
H2
H1
MCKO
ADCLK
CKO
CKI
HD'
HD
Chart-12
MODE
60
• ICX406
317
Applicable CCD image sensor
∗ HD' indicates the HD which is the actual CXD3408GA load timing.
∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse.
∗ The logical phase of ADCLK can be specified by the serial interface data.
1
High-Speed Phase Timing Chart
CXD3408GA
– 40 –
1
050h
SMD
SHD
∗
∗
∗
∗
0
0
MODE
B
050h
1
0
B
C
050h
1
0
C
D
050h
1
0
E
Close
000h
0
3
E
MODE
Draft → Frame → Draft
This chart is a drive timing chart example of electronic shutter normal operation.
Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet.
The CXD3408GA does not generate the pulse to control mechanical shutter operation.
The switching timing of drive mode and electronic shutter data is not the same.
050h
1
A
A
Vertical Direction Sequence Chart
CCD OUT
Exposure
time
Mechanical
shutter
SUB
V4
V3B
V3A
V2
V1B
V1A
VD
Chart-13
0
000h
3
E
• ICX406
1
0
050h
Open
F
Applicable CCD image sensor
050h
1
0
F
CXD3408GA
CXD3408GA
CCD Signal Processor Block Serial Interface Control
The CXD3408GA's CCD signal processor block basically loads the CCD signal processor block serial interface
data sent in the following format at the rising edge of SEN2, and the setting values are then reflected to the
operation 6 ADCLKI clocks after that.
CCD signal processor block serial interface control requires clock input to ADCLKI in order to load and reflect
the serial interface data to operation, so this should normally be performed when the timing generator block is
in the normal operation mode.
00
SSI2
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
SCK2
SEN2
There are four categories of CCD signal processor block serial interface data: standby control data, PGA gain
setting data, OB clamp level setting data, and input pulse polarity setting data.
Note that when data from multiple categories is loaded consecutively, the data for the category loaded last is
valid and data from other categories is lost. When transferring data from multiple categories, raise SEN2 for
each category and wait until the setting value 6 ADCLKI clocks after that has been reflected to operation, then
transmit the next category.
The detail of each data are described below.
Standby Control Data
Data
Symbol
Function
D00
TEST
Test code
D01
to
D03
CTG
Category switching
D04
to
D14
FIXED
D15
STB
Data = 0
Data = 1
Set to 0.
D01 to D03 CTG
—
Set to All 0.
Standby control
Normal operating mode
Standby mode
Data = 0
Data = 1
PGA Gain Setting Data
Data
Symbol
Function
D00
TEST
Test code
D01
to
D03
CTG
Category switching
D04,
FIXED
D05
D06
to
D15
GAIN
Set to 0.
D01 to D03 CTG
—
Set to All 0.
PGA gain setting data
See D06 to D15 GAIN.
– 41 –
CXD3408GA
OB Clamp Level Setting Data
Data
Symbol
Function
D00
TEST
Test code
D01
to
D03
CTG
Category switching
D04
to
D11
FIXED
D12
to
D15
OBLVL
Data = 0
Data = 1
Set to 0.
D01 to D03 CTG
—
Set to All 0.
OB clamp level setting data
See D12 to D15 OBLVL.
Input Pulse Polarity Setting Data
Data
Symbol
Function
D00
TEST
Test code
D01
to
D03
CTG
Category switching
D04
to
D12
FIXED
D13
to
D15
POL
Data = 0
Data = 1
Set to 0.
D01 to D03 CTG
—
Set to All 0.
Input pulse polarity setting data
Set to All 0.
– 42 –
CXD3408GA
Detailed Description of Each Data
Shared data: D01 to D03 CTG [Category]
Of the data provided to the CXD3408GA by the CCD signal processor block serial interface, the CXD3408GA
loads D04 and subsequent data to each data register as shown in the table below according to the combination
of D01 to D03 .
D01
D02
D03
Description of operation
0
0
0
Loading to standby control data register
0
0
1
Loading to PGA gain setting data register
0
1
0
Loading to OB clamp level setting data register
0
1
1
Loading to input pulse polarity setting data register
1
X
X
Access prohibited
Standby control data: D15 STB [Standby]
The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor
block is in standby mode, only the serial interface is valid.
D15
Description of operation
0
Normal operating mode
1
Standby mode
PGA gain setting data: D06 to D15 GAIN [PGA gain]
The CXD3408GA can set the programmable gain amplifier (PGA) gain from –6dB to +42dB in 1024 steps by
using PGA gain setting data D06 to D15 GAIN.
The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN.
MSB
LSB
D06
0
↓
1
D07
D08
D09
1
1
1
↓
C
D10
D11
D12
D13
0
0
0
0
↓
3
D14
D15
1
1
GAIN is expressed as 1C3h .
For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting
values are –6dB, 0dB, +20dB, +34dB and +42dB.
– 43 –
CXD3408GA
OB clamp level setting data: D12 to D15 OBLVL [OB clamp level]
The CXD3408GA can set the OPB clamp output value from 0 to 60LSB in 4LSB steps by using CCD signal
processor block control data D12 to D15 OBLVL.
The OPB clamp output setting data is expressed as shown in the table below using D12 to D15 OBLVL.
MSB
LSB
D12
D13
0
1
↓
6
D14
D15
1
0
OBLVL is expressed as 6h .
For example, when OBLVL is set to "0h", "1h", "8h" and "Fh", the respective OPB clamp output setting values
are 0LSB, 4LSB, 32LSB and 60LSB.
– 44 –
SUB
V4
V3B
V3A
V2
V1B
V1A
RG
H2
H1
C4
C3
C2
N7
N4
N6
L5
M4
N5
L5
K8
J9
J8
C8
C7
D8
D7
J1
XSHPI
OSCO
XSHDI
K1
PBLKI
L1
CLPOB
CLPDM
PBLK
XSHP
M3 M7 A5 C4 B5
TG/CDS/PGA/ADC
CXD3408GA
ADCLKI
B7
A7
C6
L2 N1 M1 A4 B4 A3
G1
C9 0.1µF
CLPOBI
SNCSL
SSGSL
L8
Controller
RST
N8
WEN
ID/EXP
HD
VD
MCKO
CKO
D9 (MSB)
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
NC
NC
M8
M9
N9
N2
M2
K2
J2
E1
D1
D2
D3
C1
C2
C3
B1
B2
B3
A1
A2
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
This block diagram illustrates connections with each circuit
block, and is not an actual circuit diagram. See the CCD
image sensor data sheet for an example of specific circuit
connections with the CCD image sensor.
240pF
390pF
390pF
1µF
C1
CKI
C9
TEST2
CLPDMI
OSCI
XSHD
TEST3
1µF
TEST1
ADCLK
G9 G8 G7 H3 H2 H1
SSI1
F9 F8 F7 G3 G2
SEN1
CCDIN
TEST4
C7 0.1µF
SCK1
CCDOUT
TEST5
C8 0.1µF
SSI2
CCD
ICX406
SEN2
– 45 –
SCK2
Application Circuit Block Diagram
Signal
Processor
Block
CXD3408GA
CXD3408GA
Notes on Operation
1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the
figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In
addition, start up the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pin and CCD signal processor
block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin power supplies at the same time either
before or at the same time as the VH pin power supply is started up.
15.0V
t1
20%
0V
20%
t2
–7.5V
t2 ≥ t1
2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator
block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by
initializing the serial data.
3. Separate the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins from the CCD signal processor
block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pins.
Also, the ADC output driver stage is connected to the dedicated power supply pin DVDD1. Separating this
pin from other power supplies is recommended to avoid affecting the internal analog circuits.
4. The difference in potential between the timing generator block VDD4 pin supply voltage 3 VDDc and the CCD
signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin supply voltages 1 VDDe,
2 VDDf and 3 VDDg should be 0.1V or less.
5. The timing generator block and CCD signal processor block ground pins should use a shared ground which
is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the
timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to
the analog ground. The difference in potential between the timing generator block VSS1, VSS2, VSS3, VSS4,
VSS5, VSS6 and VM and the CCD signal processor block DVSS1, DVSS2, DVSS3, AVSS1, AVSS2, AVSS3, AVSS4,
AVSS5 and AVSS6 should be 0.1V or less.
6. Do not perform serial communication with the CCD signal processor block during the effective image
period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which
are used by the CCD signal processor block, use of the dedicated ports is recommended. When using
these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the
effects on picture quality before use.
– 46 –
CXD3408GA
Package Outline
Unit: mm
0.2
Oita Ass'y
96PIN LFLGA
S A
8.0
1.3 MAX
0.2
0.2
S
S B
12.0
0.10MAX
0.10 S
X
PIN 1 INDEX
x4
S
0.15
0.5
96 -φ0.45 ± 0.05
0.8
A
φ0.08 M S A B
N
M
L
K
J
H
G
F
E
D
C
B
A
0.5
(0.3)
0.8
B
3 – φ0.50
1 2 3 4 5 6 7 8 9
0.8
0.5
1.2
(0.3)
0.5
0.9
0.9
(0.3)
DETAIL X
(0.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL
ORGANIC SUBSTRATE
SONY CODE
LFLGA-96P-02
TERMINAL TREATMENT
EIAJ CODE
P-LFLGA96-12X8-0.8
TERMINAL MATERIAL
JEDEC CODE
0.2
HITACHI TOKYO Ass'y
GOLD PLATING
NICKEL PLATING
0.3 g
PACKAGE MASS
96PIN LFLGA
S A
8.0
1.3 MAX
0.2
0.2
S
S B
12.0
0.10MAX
0.10 S
X
PIN 1 INDEX
x4
0.9
(0.3)
S
0.5
96 -φ0.45 ± 0.05
0.8
A
N
M
L
K
J
H
G
F
E
D
C
B
DETAIL X
φ0.08 M S A B
B
0.8
0.9
(0.3)
0.15
3 – φ0.50
0.5
(0.3)
1 2 3 4 5 6 7 8 9
0.8
0.5
1.2
(0.3)
0.5
A
PACKAGE STRUCTURE
PACKAGE MATERIAL
ORGANIC SUBSTRATE
SONY CODE
LFLGA-96P-051
TERMINAL TREATMENT NICKEL & GOLD PLATING
EIAJ CODE
P-LFLGA96-12.0X8.0-0.8
TERMINAL MATERIAL
JEDEC CODE
PACKAGE MASS
– 47 –
COPPER
0.3g
Sony Corporation