CY14B256K
256 Kbit (32K x 8) nvSRAM with Real Time Clock
Features
■
High reliability
❐ Endurance to 200K cycles
❐ Data retention: 20 years at 55°C
■
25 ns, 35 ns, and 45 ns access times
■
Pin compatible with STK17T88
■
Single 3V operation with tolerance of +20%, -10%
■
Data integrity of Cypress nvSRAM combined with full featured
Real Time Clock
❐ Low power, 350 nA RTC current
❐ Capacitor or battery backup for RTC
■
Commercial and industrial temperature
■
48-Pin SSOP (ROHS compliant)
■
Watchdog timer
■
Clock alarm with programmable interrupts
■
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap™ initiated by software, device pin, or
on power down
■
RECALL to SRAM initiated by software or on power up
■
Infinite READ, WRITE, and RECALL cycles
Functional Description
The Cypress CY14B256K combines a 256 Kbit nonvolatile static
RAM with a full-featured real time clock in a monolithic integrated
circuit. The embedded nonvolatile elements incorporate
QuantumTrap technology producing the world’s most reliable
nonvolatile memory. The SRAM is read and written an infinite
number of times, while independent, nonvolatile data resides in
the nonvolatile elements.
The real time clock function provides an accurate clock with leap
year tracking and a programmable high accuracy oscillator. The
alarm function is programmable for one time alarms or periodic
seconds, minutes, hours, or days. There is also a programmable
watchdog timer for process control.
Logic Block Diagram
VCC
QuantumTrap
512 X 512
A5
A9
A 11
A 12
A 13
POWER
CONTROL
STORE
ROW DECODER
A6
A7
A8
STATIC RAM
ARRAY
512 X 512
RECALL
DQ 4
DQ 5
DQ 6
HSB
A13
- A0
COLUMN IO
INPUT BUFFERS
DQ 2
VRTCcap
SOFTWARE
DETECT
DQ 0
DQ 3
VRTCbat
STORE/
RECALL
CONTROL
A 14
DQ 1
VCAP
COLUMN DEC
RTC
x1
x2
MUX
A14
INT
A 0 A 1 A 2 A 3 A 4 A 10
DQ 7
- A0
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-06431 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 24, 2009
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CY14B256K
Pin Configurations
Figure 1. 48-Pin SSOP
V CAP
1
48
V CC
NC
A 14
2
47
NC
3
46
HSB
4
45
5
44
WE
A 13
A 12
A7
A6
6
43
A5
7
42
A9
INT
8
41
NC
A4
9
NC
10
NC
11
NC
V SS
12
NC
14
13
A8
48-SSOP
40
A 11
39
NC
38
NC
Top View
37
NC
36
(Not To Scale)
V SS
35
NC
V RTCcap
V RTCbat
15
34
DQ0
16
33
DQ 6
A3
17
32
A2
18
31
OE
A 10
A1
19
30
A0
CE
20
29
DQ7
DQ5
DQ1
21
28
DQ2
22
27
DQ4
X1
23
26
DQ3
X2
24
25
V CC
Pin Definitions
Pin Name
Alt
A0–A14
IO Type
Input
DQ0-DQ7
Description
Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Input or Output Bidirectional Data IO lines. Used as input or output lines depending on operation.
NC
No Connect
WE
W
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
CE
E
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
G
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE high causes the IO pins to tri-state.
X1
Output
No Connects. This pin is not connected to the die.
Crystal Connection. Drives crystal on start up.
X2
Input
VRTCcap
Power Supply
Crystal Connection for 32.768 kHz Crystal.
Capacitor Supplied Backup RTC Supply Voltage. (Left unconnected if VRTCbat is used)
VRTCbat
Power Supply
Battery Supplied Backup RTC Supply Voltage. (Left unconnected if VRTCcap is used)
INT
Output
Interrupt Output. It is programmed to respond to the clock alarm, the watchdog timer, and the
power monitor. Programmable to either active HIGH (push or pull) or LOW (open drain).
Ground for the Device. It is connected to ground of the system.
VSS
Ground
VCC
Power Supply
HSB
Input or Output Hardware Store Busy (HSB). When low, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin HIGH if not connected (connection optional).
VCAP
Power Supply
Power Supply Inputs to the Device.
AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
Document Number: 001-06431 Rev. *H
Page 2 of 28
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CY14B256K
Device Operation
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
The CY14B256K nvSRAM consists of two functional
components paired in the same physical cell. The components
are SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM READ and WRITE operations are inhibited. The
CY14B256K supports infinite reads and writes similar to a typical
SRAM. In addition, it provides infinite RECALL operations from
the nonvolatile cells and up to 200K STORE operations.
Figure 2. AutoStore Mode
V CC
0.1UF
10k Ohm
V CAP
V CAP
V CC
WE
See the “Truth Table For SRAM Operations” on page 22 for a
complete description of read and write modes.
SRAM READ
The CY14B256K performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A0-14 determines which of the 32,752 data bytes are
accessed. When the READ is initiated by an address transition,
the outputs are valid after a delay of tAA (see the section Figure
8 on page 17). If the READ is initiated by CE or OE, the outputs
are valid at tACE or at tDOE, whichever is later (see the section
Figure 9 on page 17). The data outputs repeatedly respond to
address changes within the tAA access time without the need for
transitions on any control input pins. This remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs are stable before entering the
WRITE cycle and must remain stable until either CE or WE goes
HIGH at the end of the cycle. The data on the common IO pins
DQ0–7 is written into the memory if the data is valid tSD before
the end of a WE controlled WRITE or before the end of a CE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common IO lines. If OE is left
LOW, internal circuitry turns off the output buffers tHZWE after WE
goes LOW.
AutoStore® Operation
The CY14B256K stores data to nvSRAM using one of the three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B256K.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to DC Electrical
Characteristics on page 15 for the size of the VCAP. The voltage
on the VCAP pin is driven to 5V by a charge pump internal to the
chip. A pull up should be placed on WE to hold it inactive during
power up. This pull up is only effective if the WE signal is tri-state
during power up. Many MPUs tri-state their controls on power up.
Verify this when using the pull up. When the nvSRAM comes out
of power-on-recall, the MPU must be active or the WE held
inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B256K provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
low, the CY14B256K conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a WRITE to
the SRAM takes place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internally
driven low to indicate a busy condition, while the STORE
(initiated by any means) is in progress. This pin is externally
pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations, that are in progress when
HSB is driven low by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14B256K continues SRAM operations for tDELAY. During
Document Number: 001-06431 Rev. *H
Page 3 of 28
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CY14B256K
tDELAY, multiple SRAM READ operations take place. If a WRITE
is in progress when HSB is pulled LOW, it allows a time, tDELAY,
to complete. However, any SRAM WRITE cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
It is important to use READ cycles and not WRITE cycles in the
sequence, although it is not necessary that OE be LOW for a
valid sequence. After the tSTORE cycle time is fulfilled, the SRAM
is activated again for READ and WRITE operations.
During any STORE operation, regardless of how it is initiated,
the CY14B256K continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. After completing the
STORE operation, the CY14B256K remains disabled until the
HSB pin returns HIGH.
Software RECALL
If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition
(VCC<VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B256K software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed, followed by a program of the nonvolatile
elements. After a STORE cycle is initiated, further READs and
WRITEs are inhibited untill the cycle is completed.
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared and then the nonvolatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for READ and WRITE operations. The RECALL operation
in no way alters the data in the nonvolatile elements.
Data Protection
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If it intervenes, the
sequence is aborted and no STORE or RECALL takes place.
The CY14B256K protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when VCC is less than VSWITCH.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
If the CY14B256K is in a WRITE mode (both CE and WE are low)
at power up after a RECALL, or after a STORE, the WRITE is
inhibited until a negative transition on CE or WE is detected. This
protects against inadvertent writes during power up or brown out
conditions.
The software sequence is clocked with CE controlled READs or
OE controlled READs. After the sixth address in the sequence is
entered, the STORE cycle commences and the chip is disabled.
Document Number: 001-06431 Rev. *H
Noise Considerations
The CY14B256K is a high speed memory and must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Page 4 of 28
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CY14B256K
Low Average Active Power
Best Practices
CMOS technology provides the CY14B256K the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 3 shows the relationship between ICC and
READ and/or WRITE cycle time. Worst case current
consumption is shown for commercial temperature range, VCC =
3.6V, and chip enable at maximum frequency. Only standby
current is drawn when the chip is disabled. The overall average
current drawn by the CY14B256K depends on the following
items:
1. 1The duty cycle of chip enable
2. The overall cycle rate for accesses
3. The ratio of READs to WRITEs
4. The operating temperature
5. The VCC level
6. IO loading
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
The end product’s firmware should not assume that an NV array
is in a set programmed state. Routines that check memory
content values to determine first time system configuration and
cold or warm boot status must always program a unique NV
pattern (for example, complex 4-byte pattern of 46 E6 49 53
hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
Figure 3. Current versus Cycle Time
■
The OSCEN bit in the Calibration register at 0x7FF8 should be
set to 1 to preserve battery life when the system is in storage
(see Stopping and Starting the Oscillator on page 7).
■
The Vcap value specified in this data sheet includes a minimum
and a maximum value size. The best practice is to meet this
requirement and not exceed the maximum Vcap value because
the higher inrush currents may reduce the reliability of the
internal pass transistor. Customers who want to use a larger
Vcap value to make sure there is extra store charge should
discuss their Vcap size selection with Cypress.
Document Number: 001-06431 Rev. *H
Page 5 of 28
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CY14B256K
Table 1. Mode Selection
CE
H
WE
X
OE
X
A13–A0
Mode
IO
Power
X
Not Selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[1, 2, 3]
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[1, 2, 3]
Notes
1. The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 15 address lines on the CY14B256K, only the lower 14 lines are used to control software modes.
3. IO state depends on the state of OE. The IO table shown is based on OE Low.
Document Number: 001-06431 Rev. *H
Page 6 of 28
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CY14B256K
Real Time Clock Operation
nvTIME Operation
The CY14B256K consists of internal registers that contain clock,
alarm, watchdog, interrupt, and control functions. RTC registers
use the last 16 address locations of the SRAM. Internal double
buffering of the clock and the clock and timer information
registers prevent accessing transitional internal clock data
during a read or write operation. Double buffering also
circumvents disrupting normal timing counts or clock accuracy of
the internal clock while accessing clock data. Clock and Alarm
registers store data in BCD format.
The RTC register addresses for CY14B256K range from 0x7FF0
to 0x7FFF. Refer to RTC Register Map[5, 6] on page 11 and
Register Map Detail on page 12 for detailed description.
clock operation with the primary source removed, the data stored
in the nvSRAM is secure, having been stored in the nonvolatile
elements when power was lost.
During backup operation, the CY14B256K consumes a
maximum of 300 nanoamps at 2 volts. The user should choose
capacitor or battery values according to the application. Backup
time values based on maximum current specifications are shown
in the following table. Nominal backup times are approximately
three times longer.
Table 2. RTC Backup Time
Capacitor Value
Backup Time
0.1F
72 hours
0.47F
14 days
1.0F
30 days
Clock Operations
The Clock registers maintain time up to 9,999 years in one
second increments. The user sets the time to any calendar time
and the clock automatically keeps track of days of the week,
month, leap years, and century transitions. There are eight
registers dedicated to the clock functions that are used to set
time with a write cycle and to read time during a read cycle.
These registers contain the time of day in BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
Reading the Clock
The double buffered RTC register structure reduces the chance
of reading incorrect data from the clock. The user should stop
internal updates to the CY14B256K time keeping registers
before reading clock data, to prevent reading of data in transition.
Stopping the internal register updates does not affect clock
accuracy.
The updating process is stopped by writing a ‘1’ to the read bit
‘R’ (in the flags register at 0x7FF0), and does not restart until a
‘0’ is written to the read bit. The RTC registers are then read while
the internal clock continues to run. After a ‘0’ is written to the read
bit (‘R’), all CY14B256K registers are simultaneously updated
within 20 ms.
Setting the Clock
Setting the write bit ‘W’ (in the flags register at 0x7FF0) to a ‘1’
stops updates to the time keeping registers and enables the time
to be set. The correct day, date, and time is then written into the
registers in 24 hour BCD format. The time written is referred to
as the “Base Time”. This value is stored in nonvolatile registers
and used in the calculation of the current time. Resetting the
write bit to ‘0’ transfers the register values to the actual clock
counters, after which the clock resumes normal operation.
Backup Power
The RTC in the CY14B256K is intended for permanently
powered operation. The VRTCcap or VRTCbat pin is connected
depending on whether a capacitor or battery is chosen for the
application. When the primary power, VCC, fails and drops below
VSWITCH the device switches to the backup power supply.
Using a capacitor has the advantage of recharging the backup
source each time the system is powered up. If a battery is used,
a 3V lithium is recommended and the CY14B256K sources
current only from the battery when the primary power is removed.
The battery is not, however, recharged at any time by the
CY14B256K. The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x7FF8 controls the
enable and disable of the oscillator. This active LOW bit is
nonvolatile and is shipped to customers in the “enabled” (set to
0) state. To preserve the battery life when the system is in
storage, OSCEN bit must be set to ‘1’. This turns off the oscillator
circuit, extending the battery life. If the OSCEN bit goes from
disabled to enabled, it takes approximately 5 seconds (10
seconds maximum) for the oscillator to start.
While system power is off, if the voltage on the backup supply
(VRTCcap or VRTCbat) falls below their respective minimum level,
the oscillator may fail.The CY14B256K has the ability to detect
oscillator failure when system power is restored. This is recorded
in the OSCF (Oscillator Failed bit) of the Flags register at
address 0x7FF0. When the device is powered on (VCC goes
above VSWITCH), the OSCEN bit is checked for “enabled” status.
If the OSCEN bit is enabled and the oscillator is not active within
the first 5 ms, the OSCF bit is set to “1”. The system must check
for this condition and then write ‘0’ to clear the flag. Note that in
addition to setting the OSCF flag bit, the time registers are reset
to the “Base Time” (see “Setting the Clock” on page 7), which is
the value last written to the time keeping registers. The Control
or Calibration registers and the OSCEN bit are not affected by
the “oscillator failed” condition.
The value of OSCF must be reset to ‘0’ when the time registers
are written for the first time. This initializes the state of this bit
which may have become set when the system was first powered
on.
To reset OSCF, set the write bit “W” (in the flags register at
0x7FF0) to “1” to enable writes to the Flag register. Write a “0” to
the OSCF bit and then reset the write bit to “0” to disable writes.
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of the
Document Number: 001-06431 Rev. *H
Page 7 of 28
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CY14B256K
Calibrating the Clock
The RTC is driven by a quartz controlled oscillator with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal and calibration. The crystal oscillators typically
have an error of +20ppm to +35ppm. However, CY14B256K
employs a calibration circuit that improves the accuracy to +1/–2
ppm at 25°C. This implies an error of +2.5 seconds to -5 seconds
per month.
The calibration circuit adds or subtracts counts from the oscillator
divider circuit to achieve this accuracy. The number of pulses that
are suppressed (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five
calibration bits found in Calibration register at 0x7FF8. The
calibration bits occupy the five lower order bits in the Calibration
register. These bits are set to represent any value between ‘0’
and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates
positive calibration and a ‘0’ indicates negative calibration.
Adding counts speeds the clock up and subtracting counts slows
the clock down. If a binary ‘1’ is loaded into the register, it corresponds to an adjustment of 4.068 or –2.034 ppm offset in oscillator error, depending on the sign.
Calibration occurs within a 64 minute cycle. The first 62 minutes
in the cycle may, once per minute, have one second shortened
by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is
loaded into the register, only the first two minutes of the 64
minute cycle is modified. If a binary 6 is loaded, the first 12 are
affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm
of adjustment per calibration step in the Calibration register.
To determine the required calibration, the CAL bit in the Flags
register (0x7FF0) must be set to ‘1’. This causes the INT pin to
toggle at a nominal frequency of 512 Hz. Any deviation
measured from the 512 Hz indicates the degree and direction of
the required correction. For example, a reading of 512.01024 Hz
indicates a +20 ppm error. Hence, a decimal value of –10
(001010b) must be loaded into the Calibration register to offset
this error.
Note Setting or changing the Calibration register does not affect
the test output frequency.
To set or clear CAL, set the write bit “W” (in the flags register at
0x7FF0) to “1” to enable writes to the Flag register. Write a value
to CAL, and then reset the write bit to “0” to disable writes.
Alarm
The alarm function compares user programmed values of alarm
time and date (stored in the registers 0x7FF1-5) with the corresponding time of day and date values. When a match occurs, the
alarm internal flag (AF) is set and an interrupt is generated on
INT pin if Alarm Interrupt Enable (AIE) bit is set.
There are four alarm match fields - date, hours, minutes, and
seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding field is used in
Document Number: 001-06431 Rev. *H
the match process. Depending on the match bits, the alarm
occurs as specifically as once a month or as frequently as once
every minute. Selecting none of the match bits (all 1s) indicates
that no match is required and therefore, alarm is disabled.
Selecting all match bits (all 0s) causes an exact time and date
match.
There are two ways to detect an alarm event: by reading the AF
flag or monitoring the INT pin. The AF flag in the flags register at
0x7FF0 indicates that a date or time match has occurred. The
AF bit is set to “1” when a match occurs. Reading the flags or
control register clears the alarm flag bit (and all others). A
hardware interrupt pin may also be used to detect an alarm
event.
Note CY14B256K requires the alarm match bit for seconds
(0x7FF2 - D7) to be set to ‘0’ for proper operation of Alarm Flag
and Interrupt.
Alarm registers are not nonvolatile and, therefore, need to be
reinitialized by software on power up. To set, clear or enable an
alarm, set the ‘W’ bit (in Flags Register - 0x7FF0) to ‘1’ to enable
writes to Alarm Registers. After writing the alarm value, clear the
‘W’ bit back to “0” for the changes to take effect.
Watchdog Timer
The Watchdog Timer is a free running down counter that uses
the 32 Hz clock (31.25 ms) derived from the crystal oscillator.
The oscillator must be running for the watchdog to function. It
begins counting down from the value loaded in the Watchdog
Timer register.
The timer consists of a loadable register and a free running
counter. On power up, the watchdog time out value in register
0x7FF7 is loaded into the Counter Load register. Counting
begins on power up and restarts from the loadable value any time
the Watchdog Strobe (WDS) bit is set to ‘1’. The counter is
compared to the terminal value of ‘0’. If the counter reaches this
value, it causes an internal flag and an optional interrupt output.
You can prevent the time out interrupt by setting WDS bit to ‘1’
prior to the counter reaching ‘0’. This causes the counter to
reload with the watchdog time out value and to be restarted. As
long as the user sets the WDS bit prior to the counter reaching
the terminal value, the interrupt and WDF flag never occur.
New time out values are written by setting the watchdog write bit
to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out
value bits D5-D0 are enabled to modify the time out value. When
WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function
enables a user to set the WDS bit without concern that the
watchdog timer value is modified. A logical diagram of the
watchdog timer is shown in Figure 4. Note that setting the
watchdog time out value to ‘0’ disables the watchdog function.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to time out. The flag is set upon a
watchdog time out and cleared when the user reads the Flags or
Control registers. If the watchdog time out occurs, the user also
enables an optional interrupt source to drive the INT pin.
Page 8 of 28
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CY14B256K
Figure 4. Watchdog Timer Block Diagram
Clock
Divider
Oscillator
32,768 KHz
1 Hz
32 Hz
Counter
Zero
Compare
WDF
register is enabled (set to ‘1’). After an interrupt source is active,
two programmable bits, H/L and P/L, determine the behavior of
the output pin driver on INT pin. These two bits are located in the
Interrupt register and can be used to drive level or pulse mode
output from the INT pin. In pulse mode, the pulse width is
internally fixed at approximately 200 ms. This mode is intended
to reset a host microcontroller. In the level mode, the pin goes to
its active polarity until the Flags register is read by the user. This
mode is used as an interrupt to a host microcontroller. The
control bits are summarized in the following section.
Interrupt Register
Load
Register
WDS
D
Q
WDW
Q
write to
Watchdog
Register
Watchdog
Register
Power Monitor
The CY14B256K provides a power management scheme with
power fail interrupt capability. It also controls the internal switch
to backup power for the clock and protects the memory from low
VCC access. The power monitor is based on an internal band gap
reference circuit that compares the VCC voltage to VSWITCH
threshold.
As described in the “AutoStore® Operation” on page 3, when
VSWITCH is reached as VCC decays from power loss, a data store
operation is initiated from SRAM to the nonvolatile elements,
securing the last SRAM data state. Power is also switched from
VCC to the backup supply (battery or capacitor) to operate the
RTC oscillator.
When operating from the backup source, read and write operations to nvSRAM are inhibited and the clock functions are not
available to the user. The clock continues to operate in the
background. The updated clock data is available to the user
tHRECALL delay after VCC is restored to the device (see
“AutoStore or Power Up RECALL” on page 19).
Interrupts
The CY14B256K has a Flags register, Interrupt register and
Interrupt logic that can signal interrupt to the microcontroller.
There are three potential sources for interrupt: watchdog timer,
power monitor, and alarm timer. Each of these can be individually
enabled to drive the INT pin by appropriate setting in the Interrupt
register (0x7FF6). In addition, each has an associated flag bit in
the Flags register (0x7FF0) that the host processor uses to
determine the cause of the interrupt. The INT pin driver has two
bits that specify its behavior when an interrupt occurs.
An Interrupt is raised only if both a flag is raised by one of the
three sources and the respective interrupt enable bit in Interrupts
Document Number: 001-06431 Rev. *H
Watchdog Interrupt Enable - WIE. When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog time out occurs. When WIE is set to ‘0’, the watchdog
timer only affects the WDF flag in Flags register.
Alarm Interrupt Enable - AIE. When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When AIE is set to ‘0’, the
alarm match only affects the AF flagin Flags register.
Power Fail Interrupt Enable - PFE. When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When PFE is set
to ‘0’, the power fail monitor only affects the PF flag in Flags
register.
High/Low - H/L. When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin drives high only
when VCC is greater than VSWITCH. When set to a ‘0’, the INT pin
is active LOW and the drive mode is open drain. Active LOW
(open drain) is operational even in battery backup mode.
Pulse/Level - P/L. When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven high or low (determined by H/L) until the
Flags or Control register is read.
When an enabled interrupt source activates the INT pin, an
external host reads the Flags registers to determine the cause.
Remember that all flags are cleared when the register is read. If
the INT pin is programmed for Level mode, then the condition
clears and the INT pin returns to its inactive state. If the pin is
programmed for Pulse mode, then reading the flag also clears
the flag and the pin. The pulse does not complete its specified
duration if the Flags register is read. If the INT pin is used as a
host reset, then the Flags or Control register is not read during a
reset.
Flags Register
The Flag register has three flag bits: WDF, AF, and PF, which can
be used to generate an interrupt. These flags are set by the
watchdog timeout, alarm match, or power fail monitor respectively. The processor can either poll this register or enable interrupts to be informed when a flag is set. These flags are automatically reset once the register is read. The flags register is
automatically loaded with the value 00h on power up (except for
the OSCF bit. See “Stopping and Starting the Oscillator” on
page 7.)
Page 9 of 28
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CY14B256K
Figure 5. Interrupt Block Diagram
WDF
Watchdog
Timer
WIE
P/L
PF
Power
Monitor
VCC
Pin
Driver
PFE
INT
VINT
H/L
VSS
AF
Clock
Alarm
WDF - Watchdog Timer Flag
WIE - Watchdog Interrupt
Enable
PF - Power Fail Flag
PFE - Power Fail Enable
AF - Alarm Flag
AIE - Alarm Interrupt Enable
P/L - Pulse Level
H/L - High/Low
AIE
Figure 6. RTC Recommended Component Configuration
DQ 0
A3
A2
A1
C2
Y1
RF
C1
A0
X1
X2
Recommended Values:
Y1 = 32.768KHz
RF = 10M Ohm
C1 = 0 (install cap footprint, but leave unloaded)
C2 = 56 pF + 10% (do not vary from this value)
Note
4. Schottky diodes, (VF < 0.4V with IF at 100mA) are recommended at pins A0 - A3 and DQ0 in applications where undershoot exceeds -0.5V. Please see application note
AN49947 for further details.
Document Number: 001-06431 Rev. *H
Page 10 of 28
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CY14B256K
Table 3. RTC Register Map[5, 6]
Register
BCD Format Data [5]
D7
D6
0x7FFF
D5
D4
D3
D2
10s Years
D0
Function/Range
Years
Years: 00–99
Months
Months: 01–12
Day Of Month
Day of Month: 01–31
0x7FFE
0
0
0x7FFD
0
0
0x7FFC
0
0
0x7FFB
0
0
0x7FFA
0
0x7FF9
0
0x7FF8
OSCEN
(0)
0
0x7FF7
WDS (0)
WDW (0)
0x7FF6
WIE (0)
AIE (0)
0x7FF5
M (1)
0
10s Alarm Date
Alarm Day
Alarm, Day of Month: 01–31
0x7FF4
M (1)
0
10s Alarm Hours
Alarm Hours
Alarm, Hours: 00–23
0x7FF3
M (1)
10 Alarm Minutes
Alarm Minutes
Alarm, Minutes: 00–59
0x7FF2
M (1)
10 Alarm Seconds
Alarm, Seconds
Alarm, Seconds: 00–59
0x7FF1
0x7FF0
0
D1
10s Months
10s Day of Month
0
0
0
Day of Week
10s Hours
Hours: 00–23
10s Minutes
Minutes
Minutes: 00–59
10s Seconds
Seconds
Seconds: 00–59
Cal Sign
(0)
AF
Calibration Values [7]
Calibration (00000)
Watchdog [7]
WDT (000000)
PFE (0)
0
H/L (1)
10s Centuries
WDF
Day of Week: 01–07
Hours
PF
P/L (0)
0
0
Centuries
OSCF
0
CAL (0)
W (0)
Interrupts [7]
Centuries: 00–99
R (0)
Flags [7]
Note
5. ( ) designates values shipped from the factory.
6. The unused bits of RTC registers are reserved for future use and should be set to ‘0’.
7. Is a binary value, not a BCD value.
Document Number: 001-06431 Rev. *H
Page 11 of 28
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CY14B256K
Table 4. Register Map Detail
Time Keeping - Years
D7
D6
0x7FFF
D5
D4
D3
D2
10s Years
D1
D0
Years
Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four
bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99.
Time Keeping - Months
0x7FFE
D7
D6
D5
D4
0
0
0
10s Month
D3
D2
D1
D0
Months
Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper
nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1–12.
Time Keeping - Date
0x7FFD
D7
D6
0
0
D5
D4
D3
10s Day of Month
D2
D1
D0
Day of Month
Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit and operates from 0
to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3. The range for the register is 1–31. Leap
years are automatically adjusted for.
Time Keeping - Day
0x7FFC
D7
D6
D5
D4
D3
0
0
0
0
0
D2
D1
D0
Day of Week
Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a ring counter that counts
from 1 to 7 then returns to 1. The user must assign meaning to the day value, because the day is not integrated with the
date.
Time Keeping - Hours
0x7FFB
D7
D6
0
0
D5
D4
D3
D2
10s Hours
D1
D0
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower digit and operates from
0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0–23.
Time Keeping - Minutes
D7
0x7FFA
D6
0
D5
D4
D3
D2
10s Minutes
D1
D0
Minutes
Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper
nibble (three bits) contains the upper minutes digit and operates from 0 to 5. The range for the register is 0–59.
Time Keeping - Seconds
D7
0x7FF9
D6
0
D5
10s Seconds
D4
D3
D2
D1
D0
Seconds
Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper
nibble (three bits) contains the upper digit and operates from 0 to 5. The range for the register is 0–59.
Document Number: 001-06431 Rev. *H
Page 12 of 28
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CY14B256K
Table 4. Register Map Detail (continued)
Calibration/Control
0X7FF8
OSCEN
D7
D6
D5
OSCEN
0
Calibration
Sign
D4
D3
D2
D1
D0
Calibration
Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator
saves battery or capacitor power during storage.
Calibration Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base.
Sign
Calibration These five bits control the calibration of the clock.
WatchDog Timer
0x7FF7
D7
D6
WDS
WDW
D5
D4
D3
D2
D1
D0
WDT
WDS
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no effect. The bit
is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0.
WDW
Watchdog Write Enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value (D5–D0). This allows
the user to set the watchdog strobe bit without disturbing the timeout value. Setting this bit to 0 allows bits D5–D0 to be
written to the watchdog register when the next write cycle is complete. This function is explained in detail in the “Watchdog
Timer” on page 8.
WDT
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a
multiplier of the 32 Hz count (31.25 ms). The range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting of
3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit was set
to 0 on a previous cycle.
Interrupt Status/Control
0x7FF6
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFIE
0
H/L
P/L
0
0
WIE
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives the INT pin and
the WDF flag. When set to 0, the watchdog timeout affects only the WDF flag.
AIE
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When set to 0, the alarm
match only affects the AF flag.
PFIE
Power Fail Enable. When set to 1, the alarm match drives the INT pin and the PF flag. When set to 0, the power fail
monitor affects only the PF flag.
0
Reserved for future use
H/L
High/Low. When set to 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open drain, active LOW.
P/L
Pulse/Level. When set to 1, the INT pin is driven active (determined by H/L) by an interrupt source for approximately
200 ms. When set to 0, the INT pin is driven to an active level (as set by H/L) until the flags register is read.
Alarm - Day
0x7FF5
D7
D6
M
0
D5
D4
10s Alarm Date
D3
D2
D1
D0
Alarm Date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
M
Match. When this bit is set to 0, the date value is used in the alarm match. Setting this bit to 1 causes the match circuit
to ignore the date value.
Document Number: 001-06431 Rev. *H
Page 13 of 28
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CY14B256K
Table 4. Register Map Detail (continued)
Alarm - Hours
0x7FF4
D7
D6
D5
M
D4
D3
D2
10s Alarm Hours
D1
D0
Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
M
Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit
to ignore the hours value.
Alarm - Minutes
0x7FF3
D7
D6
D5
M
D4
D3
10s Alarm Minutes
D2
D1
D0
Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
M
Match. When this bit is set to 0, the minutes value is used in the alarm match. Setting this bit to 1 causes the match
circuit to ignore the minutes value.
Alarm - Seconds
0x7FF2
D7
D6
M
D5
D4
D3
10s Alarm Seconds
D2
D1
D0
Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
M
Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to 1 causes the match
circuit to ignore the seconds value.
Time Keeping - Centuries
D7
D6
0x7FF1
D5
D4
D3
D2
10s Centuries
D1
D0
Centuries
Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains
the upper digit and operates from 0 to 9. The range for the register is 0-99 centuries.
Flags
0x7FF0
D7
D6
D5
D4
D3
D2
D1
D0
WDF
AF
PF
OSCF
0
CAL
W
R
WDF
Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset
by the user. It is cleared to 0 when the Flags register is read or on power-up.
AF
Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the
match bits = 0. It is cleared when the Flags register is read or on power-up.
PF
Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold VSWITCH. It is cleared to
0 when the Flags register is read or on power-up.
OSCF
Oscillator Fail Flag. Set to 1 on power up if the oscillator is enabled and not running in the first 5 ms of operation. This
indicates that RTC backup power failed and clock value is no longer valid. The user must reset this bit to 0 to clear this
condition (Flag). The chip does not clear this flag. This bit survives power cycles.
CAL
Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0, the INT pin resumes
normal operation. This bit defaults to 0 (disabled) on power up.
W
Write Enable: Setting the W bit to 1 freezes updatesof the RTC registers. The user can then write to RTC registers, Alarm
registers, Calibration register, Interrupt register and Flags register. Setting the W bit to 0 causes the contents of the RTC
registers to be transferred to the time keeping counters if the time has been changed (a new base time is loaded). This
bit defaults to 0 on power up.
R
Read Enable: Setting R bit to 1, stops clock updates to user RTC registers so that clock updates are not seen during
the reading process. Set R bit to 0 to resume clock updates to the holding register. Setting this bit does not require W
bit to be set to 1. This bit defaults to 0 on power up.
Document Number: 001-06431 Rev. *H
Page 14 of 28
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CY14B256K
Maximum Ratings
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Surface Mount Pb Soldering
Temperature (3 Seconds).......................................... +260°C
Storage Temperature ................................. –65°C to +150°C
DC Output Current (1 output at a time, 1s duration) ... 15 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Supply Voltage on VCC Relative to GND ..........–0.5V to 4.1V
Latch Up Current ................................................... > 200 mA
Voltage Applied to Outputs
in High Z State ....................................... –0.5V to VCC + 0.5V
Operating Range
Range
Input Voltage.............................................–0.5V to Vcc+0.5V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V
Commercial
Industrial
Ambient Temperature
VCC
0°C to +70°C
2.7V to 3.6V
–40°C to +85°C
2.7V to 3.6V
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V) [8, 9]
Parameter
ICC1
Description
Test Conditions
Average VCC Current tRC = 25 ns
tRC = 35 ns
tRC = 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads.
IOUT = 0 mA.
Min
Max
Unit
Commercial
65
55
50
mA
mA
Industrial
70
60
55
mA
mA
ICC2
Average VCC Current All Inputs Do Not Care, VCC = Max
during STORE
Average current for duration tSTORE
3
mA
ICC3
Average VCC Current WE > (VCC – 0.2V). All other inputs cycling.
at tAVAV = 200 ns, 3V, Dependent on output loading and cycle rate.
Values obtained without output loads.
25°C Typical
10
mA
ICC4
Average VCAP
Current during
AutoStore Cycle
All Inputs Do Not Care, VCC = Max
Average current for duration tSTORE
3
mA
ISB
VCC Standby Current WE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
3
mA
IIX
Input Leakage
Current
VCC = Max, VSS < VIN < VCC
-1
+1
μA
IOZ
Off State Output
Leakage Current
VCC = Max, VSS < VIN < VCC, CE or OE > VIH
-1
+1
μA
VIH
Input HIGH Voltage
2.0
VCC + 0.5
V
VIL
Input LOW Voltage
VSS – 0.5
0.8
V
VOH
Output HIGH Voltage IOUT = –2 mA
VOL
Output LOW Voltage IOUT = 4 mA
VCAP
Storage Capacitor
Between VCAP pin and VSS, 5V Rated
2.4
17
V
0.4
V
120
μF
Notes
8. The HSB pin has IOUT = –10 μA for VOH of 2.4V, this parameter is characterized but not tested.
9. The INT pin is open drain and does not source or sink current when Interrupt register bit D3 is low.
Document Number: 001-06431 Rev. *H
Page 15 of 28
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CY14B256K
Data Retention and Endurance
Parameter
Description
Min
Unit
DATAR
Data Retention
20
Years
NVC
Nonvolatile STORE Operations
200
K
Capacitance
These parameters are guaranteed but not tested.
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0 V
Max
Unit
7
pF
7
pF
48-SSOP
Unit
32.9
°C/W
25.56
°C/W
Thermal Resistance
These parameters are guaranteed but not tested.
Parameter
ΘJA
ΘJC
Description
Test Conditions
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA / JESD51.
Figure 7. AC Test Loads
R1 577Ω
R1 577Ω
For Tri-state Specs
3.0V
3.0V
Output
Output
30 pF
R2
789Ω
5 pF
R2
789Ω
AC Test Conditions
Input Pulse Levels ..................................................0 V to 3 V
Input Rise and Fall Times (10% - 90%) ........................ <5 ns
Input and Output Timing Reference Levels ................... 1.5 V
Document Number: 001-06431 Rev. *H
Page 16 of 28
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CY14B256K
AC Switching Characteristics
Parameter
Cypress
Parameter
25 ns
Description
Alt.
Parameter
Min
35 ns
Max
Min
45 ns
Max
Min
Max
Unit
SRAM Read Cycle
tACE
tRC
tELQV
[10]
Chip Enable Access Time
25
tAVAV, tELEH Read Cycle Time
25
tAA [11]
tAVQV
Address Access Time
tDOE
tGLQV
Output Enable to Data Valid
tOHA [11]
tAXQX
Output Hold After Address Change
3
[12]
tELQX
Chip Enable to Output Active
3
tHZCE [12]
tEHQZ
Chip Disable to Output Inactive
tLZOE [12]
tGLQX
Output Enable to Output Active
tHZOE [12]
tGHQZ
Output Disable to Output Inactive
tPU [13]
tELICCH
Chip Enable to Power Active
tPD [13]
tEHICCL
Chip Disable to Power Standby
tLZCE
35
45
35
25
45
35
12
15
3
0
0
0
20
ns
ns
ns
15
ns
15
ns
45
ns
0
13
0
25
ns
3
13
10
ns
45
3
3
10
ns
0
35
ns
ns
Figure 8. SRAM Read Cycle 1: Address Controlled [10, 11, 14]
W5&
$''5(66
W $$
W2+$
'4 '$7$287
'$7$9$/,'
Figure 9. SRAM Read Cycle 2: CE and OE Controlled [10, 14]
W5&
$''5(66
W$&(
W3'
W/=&(
&(
W+=&(
2(
W+=2(
W'2(
W/=2(
'4 '$7$287
'$7$9$/,'
W 38
,&&
$&7,9(
67$1'%<
Notes
10. WE is HIGH during SRAM Read Cycles.
11. Device is continuously selected with CE and OE both Low.
12. Measured ±200 mV from steady state output voltage.
13. These parameters are guaranteed by design and are not tested.
14. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-06431 Rev. *H
Page 17 of 28
[+] Feedback
CY14B256K
AC Switching Characteristics (continued)
Parameter
Cypress
Parameter
25 ns
Description
Alt.
Parameter
Min
35 ns
Max
Min
45 ns
Max
Min
Max
Unit
SRAM Write Cycle
tWC
tAVAV
Write Cycle Time
25
35
45
ns
tPWE
tWLWH, tWLEH
Write Pulse Width
20
25
30
ns
tSCE
tELWH, tELEH
Chip Enable To End of Write
20
25
30
ns
tSD
tDVWH, tDVEH
Data Setup to End of Write
10
12
15
ns
tHD
tWHDX, tEHDX
Data Hold After End of Write
0
0
0
ns
tAW
tAVWH, tAVEH
Address Setup to End of Write
20
25
30
ns
tSA
tAVWL, tAVEL
Address Setup to Start of Write
0
0
0
ns
tHA
tWHAX, tEHAX
Address Hold After End of Write
0
tHZWE [12, 15]
tWLQZ
Write Enable to Output Disable
tLZWE [12]
tWHQX
Output Active After End of Write
0
0
10
3
13
3
ns
15
3
ns
ns
Figure 10. SRAM Write Cycle 1: WE Controlled [14, 16]
tWC
ADDRESS
tHA
tSCE
CE
tAW
tSA
tPWE
WE
tHD
tSD
DATA VALID
DATA IN
tHZWE
DATA OUT
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
Figure 11. SRAM Write Cycle 2: CE Controlled
tWC
ADDRESS
CE
WE
tHA
tSCE
tSA
tAW
tPWE
tSD
DATA IN
DATA OUT
tHD
DATA VALID
HIGH IMPEDANCE
Notes
15. If WE is Low when CE goes Low, the outputs remain in the High Impedance State.
16. CE or WE are greater than VIH during address transitions.
Document Number: 001-06431 Rev. *H
Page 18 of 28
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CY14B256K
AutoStore or Power Up RECALL
Parameter
tHRECALL [17]
tSTORE
CY14B256K
Description
Min
Max
Power Up RECALL Duration
[18, 19]
STORE Cycle Duration
VSWITCH
Low Voltage Trigger Level
tVCCRISE
VCC Rise Time
Unit
40
ms
Commercial
12.5
ms
Industrial
15
ms
2.65
V
μs
150
Figure 12. AutoStore/Power Up RECALL
No STORE occurs
without atleast one
SRAM write
STORE occurs only
if a SRAM write
has happened
VCC
VSWITCH
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
tHRECALL
Read & Write Inhibited
Notes
17. tHRECALL starts from the time VCC rises above VSWITCH.
18. If an SRAM Write does not taken place since the last nonvolatile cycle, no STORE takes place.
19. Industrial Grade Devices require 15 ms Max.
Document Number: 001-06431 Rev. *H
Page 19 of 28
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CY14B256K
Software Controlled STORE/RECALL Cycles [20, 21]
Parameter
Alt.
Parameter
Description
25 ns
Min
35 ns
Max
Min
Max
45 ns
Min
Max
Unit
tRC
tAVAV
STORE/RECALL Initiation Cycle Time
25
35
45
ns
tSA
tAVEL
Address Setup Time
0
0
0
ns
tCW
tELEH
Clock Pulse Width
20
25
30
ns
tHA
tEHAX
Address Hold Time
1
1
1
ns
tRECALL
RECALL Duration
170
170
170
μs
Figure 13. CE Controlled Software STORE/RECALL Cycle [21]
tRC
tRC
ADDRESS # 1
ADDRESS
tSA
ADDRESS # 6
tSCE
CE
tHA
OE
t STORE / t RECALL
DATA VALID
DATA VALID
DQ (DATA)
HIGH IMPEDANCE
Figure 14. OE Controlled Software STORE/RECALL Cycle [21]
tRC
tRC
ADDRESS # 1
ADDRESS
ADDRESS # 6
CE
tSA
tSCE
OE
tHA
DQ (DATA)
DATA VALID
t STORE / t RECALL
DATA VALID
HIGH IMPEDANCE
Notes
20. The software sequence is clocked with CE controlled or OE controlled READs.
21. The six consecutive addresses are read in the order listed in the Mode Selection on page 6. WE is HIGH during all six consecutive cycles.
Document Number: 001-06431 Rev. *H
Page 20 of 28
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CY14B256K
Hardware STORE Cycle
Parameter
Alt.
Parameter
tDELAY [22]
tPHSB
tHLHX
CY14B256K
Description
Min
Max
Time Allowed to Complete SRAM Cycle
1
70
Hardware STORE Pulse Width
15
Unit
μs
ns
Figure 15. Hardware STORE Cycle
W3+6%
+/+;
+6% ,1
W6725(
W+/%/
+6% 287
+,*+,03('$1&(
+,*+,03('$1&(
W '(/$<
'$7$9$/,'
'4 '$7$287
'$7$9$/,'
Soft Sequence Commands
Parameter
tSS [23, 24]
CY14B256K
Description
Min
Max
Soft Sequence Processing Time
70
Unit
μs
Figure 16. Soft Sequence Processing [23, 24]
6RIW6HTXHQFH
&RPPDQG
$GGUHVV
$GGUHVV
W6$
$GGUHVV
W&:
W66
6RIW6HTXHQFH
&RPPDQG
$GGUHVV
W66
$GGUHVV
W&:
&(
9&&
Notes
22. Read and Write cycles in progress before HSB are given this amount of time to complete.
23. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
24. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See specific command.
Document Number: 001-06431 Rev. *H
Page 21 of 28
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CY14B256K
RTC Characteristics
Parameter
IBAK
[25]
Description
Test Conditions
RTC Backup Current
Min
Max
Unit
Commercial
300
nA
Industrial
350
nA
VRTCbat
[26]
RTC Battery Pin Voltage
1.8
3.3
V
VRTCcap
[27]
RTC Capacitor Pin Voltage
1.2
2.7
V
10
sec
5
sec
tOCS
RTC Oscillator Time to Start At Min Temperature from Power up or Enable
At 25°C Temperature from Power up or Enable
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
CE
WE
OE
H
X
X
Inputs and Outputs
High Z
Mode
Deselect/Power down
Power
Standby
L
H
L
Data Out (DQ0–DQ7);
Read
Active
L
H
H
High Z
Output Disabled
Active
L
L
X
Data in (DQ0–DQ7);
Write
Active
Notes
25. From either VRTCcap or VRTCbat.
26. Typical = 3.0V during normal operation.
27. Typical = 2.4V during normal operation.
Document Number: 001-06431 Rev. *H
Page 22 of 28
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CY14B256K
Part Numbering Nomenclature
CY 14 B 256 K - SP 25 X C T
Option:
T-Tape and Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Pb-Free
Package:
SP - 48-SSOP
Voltage:
B - 3.0V
Speed:
25 - 25 ns
35 - 35 ns
45 - 45 ns
Data Bus:
K - x8 + RTC
Density:
256 - 256 Kb
nvSRAM
14 - AutoStore + Software Store + Hardware Store
Cypress
Document Number: 001-06431 Rev. *H
Page 23 of 28
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CY14B256K
Ordering Information
All the below mentioned parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.
Speed
(ns)
25
Ordering Code
CY14B256K-SP25XC
Package
Diagram
Package Type
Operating
Range
51-85061
48-pin SSOP
Commercial
51-85061
48-pin SSOP
Industrial
51-85061
48-pin SSOP
Commercial
51-85061
48-pin SSOP
Industrial
51-85061
48-pin SSOP
Commercial
51-85061
48-pin SSOP
Industrial
CY14B256K-SP25XCT
CY14B256K-SP25XI
CY14B256K-SP25XIT
35
CY14B256K-SP35XC
CY14B256K-SP35XCT
CY14B256K-SP35XI
CY14B256K-SP35XIT
45
CY14B256K-SP45XC
CY14B256K-SP45XCT
CY14B256K-SP45XI
CY14B256K-SP45XIT
Document Number: 001-06431 Rev. *H
Page 24 of 28
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CY14B256K
Package Diagrams
Figure 17. 48-Pin Shrunk Small Outline Package (51-85061)
51-85061-*C
Document Number: 001-06431 Rev. *H
Page 25 of 28
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CY14B256K
Document History Page
Document Title: CY14B256K 256 Kbit (32K x 8) nvSRAM with Real Time Clock
Document Number: 001-06431
Rev.
ECN
Orig. of Change
Submission
Date
**
425138
TUP
See ECN
Description of Change
New data sheet
*A
437321
TUP
See ECN
Show data sheet on external Web
*B
471966
TUP
See ECN
Changed VIH(min) from 2.2V to 2.0V
Changed tRECALL from 60 μs to 100 μs
Changed Endurance from one million cycles to 500K cycles
Changed Data Retention from 100 years to 20 years
Added Soft Sequence Processing Time Waveform
Updated Part Numbering Nomenclature and Ordering Information
Added RTC Characteristics Table
Added RTC Recommended Component Configuration
*C
503277
PCI
See ECN
Changed from “Advance” to “Preliminary”
Changed the term “Unlimited” to “Infinite”
Changed endurance from 500K cycles to 200K cycles
Device operation: Tolerance limit changed from +20% to +15% in
the
Features Section and Operating Range Table
Removed Icc1 values from the DC table for 25 ns and 35 ns
industrial grade
Changed VSWITCH(min) from 2.55V to 2.45V
Added temperature specifications to data retention - 20 years at
55°C
Updated Part Nomenclature Table and Ordering Information Table
*D
597004
TUP
See ECN
Removed VSWITCH(min) specification from AutoStore/Power Up RECALL table
Changed tGLAX specification from 20 ns to 1 ns
Added tDELAY(max) specification of 70 μs in the Hardware STORE
Cycle table
Removed tHLBL specification
Changed tSS specification from 70 μs(min) to 70 μs(max)
Changed VCAP(max) from 57 μF to 120 μF
*E
696097
VKN
See ECN
Added footnote 7 related to HSB
Added footnote 8 related to INT pin
Changed tGLAX to tGHAX
Removed ABE bit from Interrupt register
*F
1349963
UHA/SFV
See ECN
Changed from Preliminary to Final
Added Note 5 regarding the W bit in the Flag register
Updated Ordering Information Table
*G
2483006
GVCH/PYRS
05/05/08
Changed tolerance from +15%, -10% to +20%, -10%
Changed Operating voltage range from 2.7V-3.45V to 2.7V-3.6V
Document Number: 001-06431 Rev. *H
Page 26 of 28
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CY14B256K
Document Title: CY14B256K 256 Kbit (32K x 8) nvSRAM with Real Time Clock
Document Number: 001-06431
Rev.
ECN
Orig. of Change
Submission
Date
*H
2663934
GVCH/PYRS
02/24/09
Document Number: 001-06431 Rev. *H
Description of Change
Updated Features section
Updated pin definition of WE pin
Updated “Reading the clock”, “Backup Power”, “Stopping and
starting the Oscillator” and “Alarm” descriptions under RTC
operation
Modified “Figure 4. RTC Recommended Component Configuration”
Added footnote 4
Added footnote 6
Added default values to RTC Register Map” table
Updated flag register description in Register Map Detail” table
Added Industrial specs for 25ns and 35ns speed
Changed VIH from vcc+0.3 to Vcc+0.5
Added “Data Retention and Endurance” table on page 15
Added thermal resistance values
Added alternate parameters in the AC switching characteristics
table
Renamed tOH to tOHA
Changed tHRECALL from 20 to 40ms
Changed tRECALL spec from 100μs to 170μs (Including tss of 70us)
Renamed tAS to tSA
Renamed tGHAX to tHA
Renamed tHLHX to tPHSB
Updated Figure 16
Added truth table for SRAM operations
Page 27 of 28
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CY14B256K
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC Solutions
PSoC
psoc.cypress.com
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clocks.cypress.com
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Low Power/Low Voltage
psoc.cypress.com/solutions
psoc.cypress.com/low-power
Wireless
wireless.cypress.com
Precision Analog
Memories
memory.cypress.com
LCD Drive
psoc.cypress.com/lcd-drive
image.cypress.com
CAN 2.0b
psoc.cypress.com/can
USB
psoc.cypress.com/usb
Image Sensors
psoc.cypress.com/precision-analog
© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06431 Rev. *H
Revised February 24, 2009
Page 28 of 28
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