IDT IDT70T3319S166BC High-speed 2.5v 512/256/128k x 18 synchronous dual-port static ram with 3.3v or 2.5v interface Datasheet

HIGH-SPEED 2.5V
PRELIMINARY
512/256/128K X 18
IDT70T3339/19/99S
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
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◆
◆
◆
◆
◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
◆
◆
◆
◆
◆
◆
◆
◆
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA), a 144-pin Thin
Quad Flatpack (TQFP) and 208-pin fine pitch Ball Grid Array
(fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Due to limited pin count JTAG, Collision Detection and
Interrupt are not supported on the 144-pin TQFP package
Functional Block Diagram
UBL
UB R
LBL
LBR
FT/PIPEL
1/0
0a 1a
0b 1b
1b 0b
1a 0a
a
b
b
a
FT/PIPE R
1/0
R/WL
R/WR
CE 0L
CE0R
CE1R
1
1
CE 1L
B B
WW
0 1
L L
0
1/0
B B
WW
1 0
R R
Dout0-8_L
Dout9-17_L
OE L
0
1/0
OE R
Dout0-8_R
Dout9-17_R
0a 1a 0b
1b
1b 0b 1a 0a
FT/PIPE L
0/1
512/256/128K x 18
MEMORY
ARRAY
ab
Din_L
I/O0L - I/O17L
,
FT/PIPER
0/1
ba
I/O 0R - I/O17R
Din_R
CLK R
CLK L
Counter/
Address
Reg.
A0L
REPEATL
ADSL
CNTENL
,
A 18R(1)
A 18L(1)
Counter/
Address
Reg.
ADDR_R
ADDR_L
A0R
REPEATR
ADSR
CNTENR
TDI
INTERRUPT
COLLISION
DETECTION
LOGIC
CE 0 L
CE1L
R/W L
JTAG
CE0 R
CE1 R
TDO
TCK
TMS
TRST
R/W R
COL L
INTL
COLR
INTR
(2)
ZZ L
ZZ
CONTROL
LOGIC
ZZR
(2)
NOTES:
1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
5652 drw 01
NOVEMBER 2003
1
©2003 Integrated Device Technology, Inc.
DSC-5652/3
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Description:
The IDT70T3339/19/99 is a high-speed 512/256/128k x 18 bit
synchronous Dual-Port RAM. The memory array utilizes Dual-Port
memory cells to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup and
hold times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70T3339/19/99 has been optimized for applications having unidirec-
tional or bidirectional data flow in bursts. An automatic power down feature,
controlled by CE0 and CE1, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The IDT70T3339/19/99 can support an operating voltage of either
3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power
supply for the core of the device (VDD) is at 2.5V.
6.42
2
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Pin Configuration (3,4,5,6,9)
70T3339/19/99BC
BC-256(8)
256-Pin BGA
Top View(9)
01/13/03
A1
NC
B1
INTL
C1
A2
TDI
B2
NC
C2
COLL I/O9L
D1
NC
E1
D2
I/O9R
E2
I/O10R I/O10L
F1
I/O11L
G1
NC
H1
NC
J1
F2
NC
G2
NC
H2
I/O12R
J2
A3
NC
B3
A4
A5
A 17L(2) A14L
B4
B5
TDO A18L(1) A15L
C3
VSS
D3
NC
E3
NC
F3
C4
A 16L
D4
C5
A13L
D5
E4
E5
VDDQL VDD
F4
G4
I/O12L VDDQR
H3
F5
H4
G5
VSS
H5
NC V DDQR VSS
J3
J4
J5
I/O13L I/O14R I/O13R VDDQL ZZR
K1
NC
L1
I/O15L
M1
K2
NC
L2
NC
M2
I/O16R I/O16L
N1
NC
P1
N2
I/O17R
P2
K3
INT R
T1
NC
R2
NC
T2
TCK
K5
L4
L5
I/O15R VDDQR VDD
M3
M4
NC VDDQR
N3
B6
A 12L
C6
A 10L
D6
A7
A8L
B7
A9L
C7
A7L
D7
A8
A9
NC
CE1L
B9
B8
UBL
NC
LB L
D9
D8
A11
A12
OEL CNTENL A 5L
B10
B11
CE0L R/WL REPEATL
C9
C8
A10
C10
C11
CLKL ADSL
D10
D11
B12
A4L
C12
A6L
D12
N4
M5
VDD
N5
E6
VDD
E7
NC
F7
F6
NC
G6
VSS
H6
VSS
J6
NC
G7
VSS
H7
VSS
J7
VSS
K6
V SS
L6
NC
M6
VDD
N6
E9
E8
VSS
F9
F8
VSS
K7
VSS
L7
NC
M7
NC
N7
VSS
G9
G8
V SS
H8
VSS
H9
V SS
J8
VSS
VSS
VSS
J9
VSS
K8
VSS
K9
V SS
L8
VSS
L9
V SS
VSS
M9
M8
VSS
N8
VSS
N9
E10
VSS
F10
VSS
G10
VSS
H10
VSS
J10
VSS
K10
VSS
L10
VSS
M10
VSS
N10
E11
VDD
F11
VSS
G11
VSS
H11
VSS
J11
VSS
K11
VSS
L11
VSS
M11
VDD
N11
E12
P3
R3
P4
A16R
R4
P5
A13R
R5
TRST A18R(1) A15R
T3
NC
A13
A2L
B13
A1L
C13
A3L
D13
T4
T5
A17R(2) A14R
P6
A 10R
R6
A12R
T6
A11R
P7
A7R
R7
A9R
T7
A8R
P9
P8
NC
R8
LB R
R9
UBR
F12
NC
P11
CLKR ADSR
R10
R11
CE1R
T10
T11
F13
A14
A0L
B14
V DD
C14
OPTL
D14
NC
E14
NC
F14
VDD VDDQR I/O6R
G12
V SS
H12
VSS
J12
G13
G14
VDDQL I/O5L
H13
VDDQL
J13
H14
NC
J14
A15
A16
NC
B15
NC
B16
NC
NC
C16
C15
NC
I/O8L
D16
D15
NC
I/O8R
E16
E15
I/O7L I/O7R
F16
F15
NC
G15
I/O6L
G16
NC
NC
H16
H15
NC
I/O5R
J16
J15
ZZ L VDDQR I/O4R I/O3R I/O4L
K12
V SS
L12
VDD
M12
VDD
N12
P12
A 6R
R12
CE0R R/WR REPEATR A 4R
T9
T8
P10
E13
V DD VDDQR
NC PIPE/ FT R VDDQR VDDQR V DDQL VDDQL VDDQR VDDQR VDDQL VDDQL
COLR I/O17L TMS
R1
K4
I/O14L VDDQL VSS
L3
A11L
PIPE/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD
I/O11R VDDQL VDD
G3
A6
T12
OER CNTENR A5R
K13
K14
VDDQR NC
L13
L14
VDDQL I/O2L
M13
M14
VDDQL I/O1R
N13
VDD
P13
A3R
R13
A1R
T13
A2R
N14
NC
P14
NC
R14
OPTR
T14
A0R
K16
K15
NC
I/O3L
L16
L15
NC
I/O2R
M16
M15
I/O1L
NC
N16
N15
I/O0R
P15
NC
P16
NC
I/O0L
R16
R15
NC
T15
NC
,
T16
NC
NC
5652 drw 02d
NOTES:
1. Pin is a NC for IDT70T3319 and IDT70T3399.
2. Pin is a NC for IDT70T3399.
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to V SS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins A15 and T15 will be V REFL and VREFR respectively for future HSTL device.
6.42
3
,
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
PL/FTL
NC
NC
A18L(1)
A17L(2)
A16L
A15L
A14L
A13L
A12L
A11L
A10L
A9L
A8L
A7L
UBL
LBL
CE1L
CE0L
VDD
VSS
CLKL
OEL
R/WL
ADSL
CNTENL
REPEATL
A6L
A5L
A4L
A3L
A2L
A1L
A0L
VDD
NC
Pin Configuration(con't)(3,4,5,6,9,10)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
70T3339/19/99DD
DD-144(7)
144-Pin TQFP
Top View(8)
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
OPTL
VDDQR
VSS
I/O8L
I/O8R
I/O7L
I/O7R
I/O6L
I/O6R
VSS
VDDQL
I/O5L
I/O5R
VSS
VDDQR
VDD
VDD
VSS
VSS
ZZL
VDDQL
I/O4R
I/O4L
I/O3R
I/O3L
VSS
VDDQR
I/O2R
I/O2L
I/O1R
I/O1L
I/O0R
I/O0L
VSS
VDDQL
OPTR
,
PL/FTR
NC
NC
A18R(1)
A17R(2)
A16R
A15R
A14R
A13R
A12R
A11R
A10R
A9R
A8R
A7R
UBR
LBR
CE1R
CE0R
VDD
VSS
CLKR
OER
R/WR
ADSR
CNTENR
REPEATR
A6R
A5R
A4R
A3R
A2R
A1R
A0R
VDD
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
VDDQR
VSS
I/O9L
I/O9R
I/O10L
I/O10R
I/O11L
I/O11R
VDDQL
VSS
I/O12L
I/O12R
VDDQR
ZZR
VDD
VDD
VSS
VSS
VDDQL
VSS
I/O13R
I/O13L
I/O14R
I/O14L
VDDQR
VSS
I/O15R
I/O15L
I/O16R
I/O16L
I/O17R
I/O17L
VSS
VDDQL
NC
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
01/07/03
5652 drw 02a
NOTES:
1. Pin is a NC for IDT70T3319 and IDT70T3399.
2. Pin is a NC for IDT70T3399.
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DD (2.5V), and 2.5V if OPT pin for that port is set to V SS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 20mm x 20mm x 1.4mm.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Due to limited pin count, JTAG, Collison Detection and Interrupt are not supported in the DD-144 package.
10. Pins 109 and 72 will be VREFL and VREFR respectively for future HSTL device.
6.42
4
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Pin Configurations(con't)(3,4,5,6,9)
01/13/03
1
2
3
4
5
6
7
8
9
10 11
12
13 14
15
16 17
I/O9L
INTL
VSS
TDO
NC
A16L
A12L
A8L
NC
VDD
CLKL
CNTEN L
A4L
A0L
OPT L
NC
VSS
A
NC
VSS
COLL
TDI
A17L(2)
A13L
A9L
NC
CE0L
VSS
ADSL
A5L
A1L
NC
VDDQR
I/O8L
NC
B
VDDQL
I/O9R
VDDQR PIPE/FTL A18L(1)
A14L
A10L
UBL
CE1L
VSS
R/WL
A6L
A2L
VDD
I/O8R
NC
VSS
C
NC
VSS
I/O10L
A11L
A7L
LBL
VDD
A3L
VDD
NC
VDDQL
I/O7L
I/O7R
D
I/O11L
NC
VDDQR I/O10R
I/O6L
NC
VSS
NC
E
VDDQL I/O11R
NC
A15L
OEL REPEAT L
NC
VSS
VSS
I/O6R
NC
VDDQR
F
NC
NC
VDDQL
I/O5L
NC
G
VDD
NC
VSS
I/O5R
H
ZZL
VDD
VSS
VDDQR
J
I/O3R
VDDQL
I/O4R
VSS
K
NC
VSS
I/O12L
VDD
NC
VDDQR I/O12R
VDDQL
VDD
VSS
ZZR
I/O14R
VSS
I/O13R
VSS
NC
I/O14L
VDDQR
I/O13L
NC
I/O3L
VSS
I/O4L
L
VDDQL
NC
I/O15R
VSS
VSS
NC
I/O2R
VDDQR
M
NC
VSS
NC
I/O15L
I/O1R
VDDQL
NC
I/O2L
N
I/O16R
I/O16L
VSS
NC
NC
VSS
70T3339/19/99BF
BF-208(7)
208-Pin fpBGA
Top View(8)
VDDQR COLR
TRST
A16R
A12R
A8R
NC
VDD
CLKR CNTEN R
A4R
NC
I/O1L
VSS
NC
P
I/O17R
TCK
A17R(2)
A13R
A9R
NC
CE0R
VSS
ADSR
A5R
A1R
NC
VDDQL
I/O0R
VDDQR
R
I/O17L
VDDQL
TMS
A18R(1)
A14R
A10R
UBR
CE1R
VSS
R/WR
A6R
A2R
VSS
NC
VSS
NC
T
INTR
PIPE/FTR
NC
A15R
A11R
A7R
LBR
VDD
OER REPEAT R
A3R
A0R
VDD
OPT R
NC
I/O0L
U
5652 drw 02c
NOTES:
1. Pin is a NC for IDT70T3319 and IDT70T3399.
2. Pin is a NC for IDT70T3399.
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins B14 and R14 will be VREFL and VREFR respectively for future HSTL device.
6.42
5
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables (Input)(7)
R/WL
R/WR
Read/Write Enable (Input)
OEL
OER
A0L - A18L
(6)
Output Enable (Input)
(6)
A0R - A18R
Address (Input)
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
CLKL
CLKR
Clock (Input)
PL/FTL
PL/FTR
Pipeline/Flow-Through (Input)
ADSL
ADSR
Address Strobe Enable (Input)
CNTENL
CNTENR
Counter Enable (Input)
REPEATL
REPEATR
Counter Repeat(3)
UBL
UBR
Upper Byte Enable (I/O9 - I/O17)(7)
LBL
LBR
Lower Byte Enable (I/O0 - I/O8)(7)
VDDQL
VDDQR
Power (I/O Bus) (3.3V or 2.5V)(1) (Input)
OPTL
OPTR
Option for selecting V DDQX(1,2) (Input)
ZZL
ZZR
Sleep Mode pin(4) (Input)
VDD
Power (2.5V)(1) (Input)
VSS
Ground (0V) (Input)
(5)
Test Data Input
TDI
TDO(5)
TCK
Test Data Output
(5)
TMS
Test Logic Clock (10MHz) (Input)
(5)
Test Mode Select (Input)
TRST(5)
Reset (Initialize TAP Controller) (Input)
INTL(5)
INTR(5)
Interrupt Flag (Output)
COLL(5)
COLR(5)
Collision Alert (Output)
5652 tbl 01
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPT X is set to VSS (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADS X.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode.
5. Due to limited pin count, JTAG, Collision Detection and Interrupt are not supported
in the DD-144 package.
6. Address A18x is a NC for the IDT70T3319. Also, Addresses A18x and A17x are
NC's for the IDT70T3399.
7. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
6.42
6
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control
(1,2,3,4)
OE
CLK
CE0
CE1
UB
LB
R/W
ZZ
Upper Byte
I/O9-17
Lower Byte
I/O0-8
X
↑
H
X
X
X
X
L
High-Z
High-Z
Deselected–Power Down
X
↑
X
L
X
X
X
L
High-Z
High-Z
Deselected–Power Down
X
↑
L
H
H
H
X
L
High-Z
High-Z
Both Bytes Deselected
X
↑
L
H
H
L
L
L
High-Z
DIN
Write to Lower Byte Only
X
↑
L
H
L
H
L
L
DIN
High-Z
Write to Upper Byte Only
X
↑
L
H
L
L
L
L
DIN
DIN
Write to Both Bytes
L
↑
L
H
H
L
H
L
High-Z
DOUT
Read Lower Byte Only
L
↑
L
H
L
H
H
L
DOUT
High-Z
Read Upper Byte Only
L
↑
L
H
L
L
H
L
DOUT
DOUT
Read Both Bytes
H
↑
L
H
L
L
X
L
High-Z
High-Z
Outputs Disabled
X
X
X
X
X
X
X
H
High-Z
High-Z
Sleep Mode
MODE
NOTES:
1. "H" = V IH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = VIH.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table II—Address Counter Control
Address
Previous
Internal
Address
Internal
Address
Used
CLK
An
X
An
↑
ADS
L(4)
CNTEN
REPEAT(6)
I/O(3)
X
H
DI/O (n)
5652 tbl 02
(1,2)
MODE
External Address Used
X
An
An + 1
↑
H
L
H
DI/O(n+1)
Counter Enabled—Internal Address generation
X
An + 1
An + 1
↑
H
H
H
DI/O(n+1)
External Address Blocked—Counter disabled (An + 1 reused)
An
↑
X
(4)
X
X
X
(5)
L
DI/O(n)
Counter Set to last valid ADS load
5652 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE 1, UB, LB and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE 0, CE1, UB and LB.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.42
7
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Maximum Operating
Temperature and Supply Voltage(1)
Grade
Commercial
Industrial
Ambient
Temperature
GND
VDD
0OC to +70OC
0V
2.5V + 100mV
-40OC to +85OC
0V
2.5V + 100mV
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
5652 tbl 04
Recommended DC Operating
Conditions with VDDQ at 2.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Core Supply Voltage
2.4
2.5
2.6
V
VDDQ
I/O Supply Voltage (3)
2.4
2.5
2.6
V
VSS
Ground
0
0
0
V
VIH
Input High Volltage
(Address, Control &
Data I/O Inputs)(3)
1.7
____
VDDQ + 100mV (2)
V
VIH
Input High Voltage
JTAG
1.7
____
VDD + 100mV (2)
V
VIH
Input High Voltage ZZ, OPT, PIPE/FT
VDD - 0.2V
____
VDD + 100mV (2)
V
(1)
_
VIL
Input Low Voltage
-0.3
____
0.7
V
VIL
Input Low Voltage ZZ, OPT, PIPE/FT
-0.3(1)
____
0.2
V
5652 tbl 05a
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC /2 or 5ns, whichever is less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT
pin for that port must be set to Vss(0V), and VDDQX for that port must be supplied as
indicated above.
Recommended DC Operating
Conditions with VDDQ at 3.3V
Symbol
V DD
Parameter
Min.
Typ.
Max.
Unit
2.4
2.5
2.6
V
3.15
3.3
3.45
V
0
0
0
V
2.0
____
VDDQ + 150mV(2)
V
1.7
____
VDD + 100mV(2)
V
VDD - 0.2V
____
VDD + 100mV(2)
V
Core Supply Voltage
(3)
V DDQ
I/O Supply Voltage
V SS
Ground
V IH
Input High Voltage
(Address, Control
&Data I/O Inputs)(3)
V IH
Input High Voltage
JTAG
V IH
Input High Voltage ZZ, OPT, PIPE/FT
VIL
Input Low Voltage
-0.3(1)
____
0.8
V
VIL
Input Low Voltage ZZ, OPT, PIPE/FT
-0.3(1)
____
0.2
V
_
5652 tbl 05b
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT
pin for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied
as indicated above.
6.42
8
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM
(VDD)
V DD Terminal Voltage
with Respect to GND
VTERM(2)
(VDDQ)
V DDQ Terminal Voltage
with Respect to GND
-0.3 to VDDQ + 0.3
V
VTERM(2)
(INPUTS and I/O's)
Input and I/O Terminal
Voltage with Respect to GND
-0.3 to VDDQ + 0.3
V
TBIAS(3)
Temperature Under Bias
TSTG
-0.5 to 3.6
Storage Temperature
TJN
V
-55 to +125
o
C
-65 to +150
o
C
+150
o
C
Junction Temperature
IOUT(For V DDQ = 3.3V) DC Output Current
50
IOUT(For V DDQ = 2.5V) DC Output Current
40
mA
mA
5652 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage on
any Input or I/O pin cannot exceed VDDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
Capacitance(1)
(TA = +25°C, f = 1.0MHz) PQFP ONLY
Symbol
CIN
Parameter
Conditions(2)
Max.
Unit
VIN = 3dV
8
pF
VOUT = 3dV
10.5
Input Capacitance
(3)
COUT
Output Capacitance
pF
5652 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T3339/19/99S
Symbol
|ILI|
|ILI|
|ILO|
VOL (3.3V)
Parameter
Test Conditions
Input Leakage Current(1)
(1,2)
JTAG & ZZ Input Leakage Current
(1,3)
Output Leakage Current
Output Low Voltage
(1)
(1)
Min.
Max.
Unit
VDDQ = Max., VIN = 0V to VDDQ
___
10
µA
VDD = Max., VIN = 0V to VDD
___
±30
µA
CE0 = V IH or CE 1 = VIL, VOUT = 0V to VDDQ
___
10
µA
IOL = +4mA, VDDQ = Min.
___
0.4
V
V
IOH = -4mA, VDDQ = Min.
2.4
___
VOL (2.5V)
Output Low Voltage
(1)
IOL = +2mA, VDDQ = Min.
___
0.4
V
VOH (2.5V)
Output High Voltage (1)
IOH = -2mA, VDDQ = Min.
2.0
___
V
VOH (3.3V)
Output High Voltage
5652 tbl 08
NOTES:
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.6 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
6.42
9
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (3)(VDD = 2.5V ± 100mV)
Symbol
IDD
ISB1(6)
ISB2(6)
ISB3
ISB4(6)
Izz
Parameter
Test Condition
Dynamic Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled,
f = fMAX(1)
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(1)
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Version
70T3339/19/99
S200
Com'l Only(8)
70T3339/19/99
S166
Com'l
& Ind(7)
70T3339/19/99
S133
Com'l
& Ind
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
COM'L
S
375
525
320
450
260
370
IND
S
___
___
320
510
260
450
COM'L
S
205
270
175
230
140
190
IND
S
___
___
175
275
140
235
COM'L
S
300
375
250
325
200
250
IND
S
___
___
250
365
200
310
Both Ports CEL and
CER > VDDQ - 0.2V, VIN > VDDQ - 0.2V
or VIN < 0.2V, f = 0(2)
COM'L
S
5
15
5
15
5
15
IND
S
___
___
5
20
5
20
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V(5)
VIN > VDDQ - 0.2V or VIN < 0.2V
Active Port, Outputs Disabled, f = fMAX(1)
COM'L
S
300
375
250
325
200
250
IND
S
___
___
250
365
200
310
Sleep Mode Current
(Both Ports - TTL
Level Inputs)
ZZL = ZZR = VIH
f=fMAX(1)
COM'L
S
5
15
5
15
5
15
S
___
___
5
20
5
20
Unit
mA
mA
mA
mA
mA
mA
IND
5652 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS".
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 15mA (Typ).
5. CEX = V IL means CE 0X = V IL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.
7. 166MHz I-Temp is not available in the BF-208 package.
8. 200Mhz is not available in the BF-208 and DD-144 packages.
6.42
10
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels (Address & Controls)
GND to 3.0V/GND to 2.4V
Input Pulse Levels (I/Os)
GND to 3.0V/GND to 2.4V
Input Rise/Fall Times
2ns
Input Timing Reference Levels
1.5V/1.25V
Output Reference Levels
1.5V/1.25V
Output Load
Figures 1 and 2
5652 tbl 10
50Ω
50Ω
DATAOUT
1.5V/1.25
10pF
(Tester)
5652 drw 03
Figure 1. AC Output Test load.
∆ tCD
(Typical, ns)
∆ Capacitance (pF) from AC Test Load
6.42
11
5652 drw 04
,
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C)
Symbol
Parameter
70T3339/19/99
S200
Com'l Only(5)
70T3339/19/99
S166
Com'l
& Ind(4)
70T3339/19/99
S133
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tCYC1
Clock Cycle Time (Flow-Through)(1)
15
____
20
____
25
____
ns
tCYC2
Clock Cycle Time (Pipelined)(1)
5
____
6
____
7.5
____
ns
ns
(1)
tCH1
Clock High Time (Flow-Through)
6
____
8
____
10
____
tCL1
Clock Low Time (Flow-Through)(1)
6
____
8
____
10
____
ns
tCH2
Clock High Time (Pipelined)(2)
2
____
2.4
____
3
____
ns
tCL2
Clock Low Time (Pipelined)(1)
2
____
2.4
____
3
____
ns
tSA
Address Setup Time
1.5
____
1.7
____
1.8
____
ns
ns
tHA
Address Hold Time
0.5
____
0.5
____
0.5
____
tSC
Chip Enable Setup Time
1.5
____
1.7
____
1.8
____
ns
tHC
Chip Enable Hold Time
0.5
____
0.5
____
0.5
____
ns
tSB
Byte Enable Setup Time
1.5
____
1.7
____
1.8
____
ns
tHB
Byte Enable Hold Time
0.5
____
0.5
____
0.5
____
ns
ns
tSW
R/W Setup Time
1.5
____
1.7
____
1.8
____
tHW
R/W Hold Time
0.5
____
0.5
____
0.5
____
ns
tSD
Input Data Setup Time
1.5
____
1.7
____
1.8
____
ns
tHD
Input Data Hold Time
0.5
____
0.5
____
0.5
____
ns
tSAD
ADS Setup Time
1.5
____
1.7
____
1.8
____
ns
tHAD
ADS Hold Time
0.5
____
0.5
____
0.5
____
ns
tSCN
CNTEN Setup Time
1.5
____
1.7
____
1.8
____
ns
tHCN
CNTEN Hold Time
0.5
____
0.5
____
0.5
____
ns
tSRPT
REPEAT Setup Time
1.5
____
1.7
____
1.8
____
ns
tHRPT
REPEAT Hold Time
0.5
____
0.5
____
0.5
____
ns
tOE
Output Enable to Data Valid
____
4.4
____
4.4
____
4.6
ns
1
____
1
____
1
____
ns
ns
tOLZ(6)
(6)
Output Enable to Output Low-Z
tOHZ
Output Enable to Output High-Z
1
3.4
1
3.6
1
4.2
tCD1
Clock to Data Valid (Flow-Through)(1)
____
10
____
12
____
15
ns
tCD2
Clock to Data Valid (Pipelined)(1)
____
3.4
____
3.6
____
4.2
ns
tDC
Data Output Hold After Clock High
1
____
1
____
1
____
ns
tCKHZ(6)
Clock High to Output High-Z
1
3.4
1
3.6
1
4.2
ns
tCKLZ(6)
Clock High to Output Low-Z
1
____
1
____
1
____
ns
7
____
7
____
7
ns
tINS
Interrupt Flag Set Time
____
tINR
Interrupt Flag Reset Time
____
7
____
7
____
7
ns
tCOLS
Collision Flag Set Time
____
3.4
____
3.6
____
4.2
ns
tCOLR
Collision Flag Reset Time
____
3.4
____
3.6
____
4.2
ns
cycles
tZZSC
Sleep Mode Set Cycles
2
____
2
____
2
____
tZZRC
Sleep Mode Recovery Cycles
3
____
3
____
3
____
cycles
4
____
5
____
6
____
ns
Port-to-Port Delay
tCO
Clock-to-Clock Offset
tOFS
Clock-to-Clock Offset for Collision Detection
Please refer to Collision Detection Timing Table on Page 21
5652 tbl 11
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1)
apply when FT/PIPE = Vss (0V) for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be
treated as DC signals, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.
4. 166MHz I-Temp is not available in the BF-208 package.
5. 200Mhz is not available in the BF-208 and DD-144 packages.
6. Guaranteed by design (not production tested).
6.42
12
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
tHC
(3)
CE1
tSB
tSB
tHB
UB, LB
R/W
tSW tHW
tSA
ADDRESS
(4)
tHA
An
An + 1
An + 2
(1 Latency)
An + 3
tDC
tCD2
DATAOUT
Qn
tCKLZ
OE
tHB
(5)
Qn + 1
Qn + 2
(5)
(1)
tOHZ
tOLZ
(1)
,
tOE
5652 drw 05
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(2,6)
tCYC1
tCH1
tCL1
CLK
CE 0
tSC
tSC
tHC
CE1
tSB
tHB
UB, LB
tSB
R/W
tHB
tSW tHW
tSA
ADDRESS
tHC
(3)
(4)
tHA
An
An + 1
tCD1
DATAOUT
An + 2
tCKHZ
Qn
Qn + 2(5)
Qn + 1
tCKLZ
OE
An + 3
tDC
tOHZ
tOLZ
tDC
(1)
tOE
,
5652 drw 06
NOTES:
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB, LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42
13
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Timing Waveform of a Multi-Device Pipelined Read(1,2)
tCYC2
tCH2
tCL2
CLK
tSA
tHA
A0
ADDRESS(B1)
tSC
tHC
CE0(B1)
tSC
tHC
tCD2
tCD2
Q0
DATAOUT(B1)
tCKHZ
tSA
Q3
tCKLZ
tDC
tCKHZ
tHA
A0
tSC
A6
A5
A4
A3
A2
A1
tSC
CE0(B2)
tCD2
Q1
tDC
ADDRESS(B2)
A6
A5
A4
A3
A2
A1
tHC
tHC
tCD2
tCKHZ
tCD2
,
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
5652 drw 07
Timing Waveform of a Multi-Device Flow-Through Read(1,2)
tCH1
tCYC1
tCL1
CLK
tSA
tH
A
A0
ADDRESS(B1)
CE0(B1)
tSC tHC
tSC tHC
tCD1
tCD1
D0
DATAOUT(B1)
tDC
tSA
ADDRESS(B2)
A6
A5
A4
A3
A2
A1
tCKHZ
(1)
tCD1
tCD1
D3
D1
tDC
tCKLZ
(1)
D5
tCKHZ(1)
tCKLZ
(1)
tHA
A0
A1
A6
A5
A4
A3
A2
tSC tHC
CE0(B2)
tSC tHC
tCD1
DATAOUT(B2)
tCKLZ
(1)
tCKHZ
(1)
tCD1
D2
tCKLZ
(1)
tCKHZ
(1)
D4
,
5652 drw 08
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3339/19/99 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE 1(B2), R/W, CNTEN, and REPEAT = VIH.
6.42
14
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4)
CLK"A"
tSW
tHW
tSA
tHA
R/W"A
"
ADDRESS"A"
tSD
DATAIN"A"
NO
MATC
H
MATC
H
tHD
VALID
tCO(3)
CLK"B"
tCD2
R/W"B"
ADDRESS"B"
tSW
tHW
tSA
tHA
NO
MATCH
MATC
H
DATAOUT"B"
VALID
,
tDC
5652 drw 09
NOTES:
1. CE 0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH .
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2 ). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + t CYC2 + t CD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
CLK "A"
tSW tHW
R/W "A"
tSA
ADDRESS "A"
NO
MATCH
MATCH
tSD
DATAIN "A"
tHA
tHD
VALID
tCO
(3)
CLK "B"
tCD1
R/W "B"
ADDRESS "B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
tCD1
DATAOUT "B"
VALID
VALID
tDC
tDC
,
5652 drw 10
NOTES:
1. CE 0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH .
2. OE = V IL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be t CO + t CD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42
15
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read
tCYC2
(OE = VIL)(2)
tCH2
tCL2
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
tSW tHW
R/W
tSW tHW
(3)
An
tSA tHA
ADDRESS
An +1
An + 2
An + 3
An + 2
An + 4
tSD tHD
DATAIN
Dn + 2
tCD2
(1)
tCKHZ
tCD2
tCKLZ
Qn + 3
Qn
DATAOUT
(4)
READ
NOP
WRITE
READ
5652 drw 11
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = V IL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
,
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(2)
tCH2
tCYC2
tCL2
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
tSW tHW
R/W
(3)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
tSD
DATAIN
Qn
DATAOUT
An + 4
An + 5
tHD
Dn + 2
tCD2
(1)
An + 3
Dn + 3
tCKLZ
tCD2
Qn + 4
(4)
tOHZ
OE
READ
WRITE
READ
,
NOTES:
5652 drw 12
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = V IH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
16
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2)
tCH1
tCYC1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
tSW tHW
R/W
tSW tHW
(3)
ADDRESS
tSA
An
tHA
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD1
(1)
tCD1
Qn
DATAOUT
tCD1
tCD1
Qn + 1
tDC
tCKLZ
tCKHZ
READ
NOP
(4)
Qn + 3
tDC
READ
WRITE
,
5652 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
tSW tHW
R/W
tSW tHW
(3)
An
tSA tHA
ADDRESS
An +1
DATAIN
(1)
DATAOUT
An + 2
tSD tHD
An + 3
Dn + 2
Dn + 3
tDC
tCD1
An + 4
tOE
tCD1
Qn
tCKLZ
tOHZ
An + 5
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
,
5652 drw 14
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = V IH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
17
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2
tCYC2
tCL2
CLK
tSA tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT
Qx - 1(2)
,
Qn + 2(2)
Qn + 1
Qn
Qx
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5652 drw 15
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
tCYC1
tCH1
tCL1
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD1
DATAOUT
Qx(2)
Qn
Qn + 1
Qn + 2
Qn + 3(2)
,
Qn + 4
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
5652 drw 16
NOTES:
1. CE0, OE, UB, LB = VIL; CE1, R/W, and REPEAT = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
18
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
tSCN tHC
N
CNTEN
tSD tHD
Dn + 1
Dn
DATAIN
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 4
Dn + 3
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
,
5652 drw 17
Timing Waveform of Counter Repeat(2)
tCH2
tCYC2
tCL2
CLK
tSA tHA
(4)
An
ADDRESS
INTERNAL(3)
ADDRESS
LAST ADS LOAD
Ax
An + 2
An + 1
LAST ADS +1
An
An + 1
tSW tHW
R/ W
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tSRPT tHRPT
REPEAT
tSD
tHD
D0
DATAIN
(5)
QLAST
DATAOUT
EXECUTE
REPEAT
(6)
WRITE
LAST ADS
ADDRESS
READ
LAST ADS
ADDRESS
READ
LAST ADS
ADDRESS + 1
QLAST+1
READ
ADDRESS n
READ
ADDRESS n+1
Qn
,
NOTES:
5652 drw 18
1. CE 0, UB, LB, and R/W = V IL; CE 1 and REPEAT = VIH.
2. CE 0, UB, LB = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6.42
19
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Waveform of Interrupt Timing
PRELIMINARY
Industrial and Commercial Temperature Ranges
(2)
CLKL
tSW
tHW
tSA
tHA
R/WL
ADDRESS
L(3)
CE
L(1)
7FFFF
tSC
tHC
tINS
INTR
tINR
CLKR
tSC
tHC
CER(1)
R/WR
ADDRESSR(3)
tSW
tHW
tSA
tHA
7FFFF
NOTES:
1. CE0 = VIL and CE1 = VIH
2. All timing is the same for Left and Right ports.
3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
5652 drw 19
Truth Table III — Interrupt Flag (1)
Left Port
CLKL
R/WL
(2)
CEL
(2)
Right Port
A18L-A0L
(3,4,5)
(2)
INTL
CLKR
R/WR
CER(2)
A18R-A0R(3,4,5)
INTR
Function
↑
L
L
7FFFF
X
↑
X
X
X
L
Set Right INTR Flag
↑
X
X
X
X
↑
H
L
7FFFF
H
Reset Right INTR Flag
↑
X
X
X
L
↑
L
L
7FFFE
X
Set Left INTL Flag
↑
H
L
7FFFE
H
↑
X
X
X
X
Reset Left INTL Flag
NOTES:
1. INT L and INTR must be initialized at power-up by Resetting the flags.
2. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
3. A18X is a NC for IDT70T3319, therefore Interrupt Addresses are 3FFFF and 3FFFE.
4. A18X and A17X are NC's for IDT70T3399, therefore Interrupt Addresses are 1FFFF and 1FFFE.
5. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
20
5652 tbl 12
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Waveform of Collision Timing (1,2)
Both Ports Writing with Left Port Clock Leading
CLKL
tOFS
tSA
(4)
tHA
A2
A1
A0
ADDRESSL
A3
tCOLR
tCOLS
COLL
(3)
tOFS
CLKR
tSA
tHA
(4)
ADDRESSR
A0
A3
A2
A1
tCOLR
tCOLS
COLR
5652 drw 20
NOTES:
1. CE0 = VIL, CE1 = VIH.
2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3. Leading Port Output flag might output 3tCYC 2 + tCOLS after Address match.
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Collision Detection Timing(3,4)
tOFS (ns)
Cycle Time
Region 1 (ns)
(1)
Region 2 (ns)
5ns
0 - 2.8
2.81 - 4.6
6ns
0 - 3.8
3.81 - 5.6
7.5ns
0 - 5.3
5.31 - 7.1
NOTES:
1. Region 1
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.
2. Region 2
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.
3. All the production units are tested to midpoint of each region.
4. These ranges are based on characterization of a typical device.
(2)
5652 tbl 13
Truth Table IV — Collision Detection Flag
Left Port
Right Port
CLKL
R/WL(1)
CEL(1)
A18L-A0L(2)
COLL
CLKR
R/WR(1)
CE R(1)
A18R-A0R(2)
COLR
Function
↑
H
L
MATCH
H
↑
H
L
MATCH
H
Both ports reading. Not a valid collision.
No flag output on either port.
↑
H
L
MATCH
L
↑
L
L
MATCH
H
Left port reading, Right port writing.
Valid collision, flag output on Left port.
↑
L
L
MATCH
H
↑
H
L
MATCH
L
Right port reading, Left port writing.
Valid collision, flag output on Right port.
↑
L
L
MATCH
L
↑
L
L
MATCH
L
Both ports writing. Valid collision. Flag
output on both ports.
NOTES:
1. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
21
5652 tbl 14
6.42
22
(4)
NOTES:
1. CE 1 = V IH.
2. All timing is same for Left and Right ports.
3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = VIH).
4. CE0 has to be deactivated (CE0 = VIH) two cycles prior to de-asserting ZZ (ZZx = VIL) and held for three cycles after de-asserting ZZ (ZZx = VIL).
(3)
Timing Waveform of Sleep Mode (1,2)
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Functional Description
The IDT70T3339/19/99 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse width is independent of the cycle time.
An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70T3339/19/99s for depth
expansion configurations. Two cycles are required with CE0 LOW and
CE1 HIGH to re-activate the outputs.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
7FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location 7FFFE when CEL = VIL and R/WL = VIH. Likewise, the
right port interrupt flag (INT R ) is asserted when the left
port writes to memory location 7FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 7FFFF (3FFFF
or 3FFFE for IDT70T3319 and 1FFFF or 1FFFE for IDT70T3399). The
message (18 bits) at 7FFFE or 7FFFF (3FFFF or 3FFFE for IDT70T3319
and 1FFFF or 1FFFE for IDT70T3399) is user-defined since it is an
addressable SRAM location. If the interrupt function is not used, address
locations 7FFFE and 7FFFF (3FFFF or 3FFFE for IDT70T3319 and
1FFFF or 1FFFE for IDT70T3399) are not used as mail boxes, but as
part of the random access memory. Refer to Truth Table III for the interrupt
operation.
Collision Detection
Collision is defined as an overlap in access between the two ports
resulting in the potential for either reading or writing incorrect data to a
specific address. For the specific cases: (a) Both ports reading - no
data is corrupted, lost, or incorrectly output, so no collision flag is output
on either port. (b) One port writing, the other port reading - the end
result of the write will still be valid. However, the reading port might
capture data that is in a state of transition and hence the reading port’s
collision flag is output. (c) Both ports writing - there is a risk that the two
ports will interfere with each other, and the data stored in memory will
not be a valid write from either port (it may essentially be a random
combination of the two). Therefore, the collision flag is output on both
ports. Please refer to Truth Table IV for all of the above cases.
The alert flag (COLX) is asserted on the 2nd or 3rd rising clock
edge of the affected port following the collision, and remains low for
one cycle. Please refer to Collision DetectionTiming table on Page 21.
During that next cycle, the internal arbitration is engaged in resetting
the alert flag (this avoids a specific requirement on the part of the user
to reset the alert flag). If two collisions occur on subsequent clock
cycles, the second collision may not generate the appropriate alert
flag. A third collision will generate the alert flag as appropriate. In the
event that a user initiates a burst access on both ports with the same
starting address on both ports and one or both ports writing during
each access (i.e., imposes a long string of collisions on contiguous
clock cycles), the alert flag will be asserted and cleared every other
cycle. Please refer to the Collision Detection timing waveform on page
21.
Collision detection on the IDT70T3339/19/99 represents a
significant advance in functionality over current sync multi-ports, which
have no such capability. In addition to this functionality the
IDT70T3339/19/99 sustains the key features of bandwidth and
flexibility. The collision detection function is very useful in the case of
bursting data, or a string of accesses made to sequential addresses, in
that it indicates a problem within the burst, giving the user the option of
either repeating the burst or continuing to watch the alert flag to see
whether the number of collisions increases above an acceptable
threshold value. Offering this function on chip also allows users to
reduce their need for arbitration circuits, typically done in CPLD’s or
FPGA’s. This reduces board space and design complexity, and gives
the user more flexibility in developing a solution.
Sleep Mode
The IDT70T3339/19/99 is equipped with an optional sleep or low
power mode on both ports. The sleep mode pin on both ports is
asynchronous and active high. During normal operation, the ZZ pin is
pulled low. When ZZ is pulled high, the port will enter sleep mode where
it will meet lowest possible power conditions. The sleep mode timing
diagram shows the modes of operation: Normal Operation, No Read/Write
Allowed and Sleep Mode.
For normal operation all inputs must meet setup and hold times prior
to sleep and after recovering from sleep. Clocks must also meet cycle high
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx = VIH) and three cycles after de-asserting ZZ (ZZx = VIL), new reads
or writes are not allowed. If a write or read operation occurs during these
periods, the memory array may be corrupted. Validity of data out from the
RAM cannot be guaranteed immediately after ZZ is asserted (prior to being
in sleep).
During sleep mode the RAM automatically deselects itself. The RAM
disconnects its internal clock buffer. The external clock may continue to run
without impacting the RAMs sleep current (IZZ). All outputs will remain in
high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM
will not be selected and will not perform any reads or writes.
6.42
23
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
The IDT70T3339/19/99 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70T3339/19/99 can also be used in applications requiring
expanded width, as indicated in Figure 4. Through combining the control
signals, the devices can be grouped as necessary to accommodate
applications needing 36-bits or wider.
A19/A18/A17(1)
IDT70T3339/19/99
CE0
CE1
IDT70T3339/19/99
CE1
VDD
VDD
Control Inputs
Control Inputs
IDT70T3339/19/99
CE0
IDT70T3339/19/99
CE1
CE1
CE0
CE0
Control Inputs
Control Inputs
Figure 4. Depth and Width Expansion with IDT70T3339/19/99
5652 drw 22
NOTE:
1. A19 is for IDT70T3339, A18 is for IDT70T3319, A17 is for IDT70T3399.
6.42
24
UB, LB,
R/W,
OE,
CLK,
ADS,
REPEAT,
CNTEN
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
JTAG Timing Specifications
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST
,
5652 drw 23
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics (1,2,3,4)
70T3339/19/99
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
JTAG Clock Low
40
____
ns
JTAG Clock Rise Time
____
(1)
ns
tJF
JTAG Clock Fall Time
____
(1)
3
ns
tJRST
JTAG Reset
50
____
ns
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
25
ns
0
____
ns
ns
ns
tJCL
tJR
tJDC
JTAG Data Output Hold
3
tJS
JTAG Setup
15
____
tJH
JTAG Hold
15
____
5652 tbl 15
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
6.42
25
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Revision Number (31:28)
Description
0x0
Reserved for version number
IDT Device ID (27:12)
0x333(1)
IDT JEDEC ID (11:1)
0x33
ID Register Indicator Bit (Bit 0)
Defines IDT part number
Allows unique identification of device vendor as IDT
1
Indicates the presence of an ID register
5652 tbl 16
NOTE:
1. Device ID for IDT70T3319 is 0x334. Device ID for IDT70T3399 is 0x335.
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
Identification (IDR)
32
Boundary Scan (BSR)
Note (3)
5652 tbl 17
System Interface Parameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs (1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
1111
Places the bypass register (BYR) between TDI and TDO.
IDCODE
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state except COLx & INTx outputs.
HIGHZ
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
0011
SAMPLE/PRELOAD
0001
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs (2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
0101, 0111, 1000, 1001,
1010, 1011, 1100
Several combinations are reserved. Do not use codes other than those
identified above.
RESERVED
PRIVATE
0110,1110,1101
For internal use only.
5652 tbl 18
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
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IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Ordering Information
IDT
XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BC
DD
BF
256-pin BGA (BC-256)
144-pin TQFP (DD-144)
208-pin fpBGA (BF-208)
200
166
133
Commercial Only(2)
Commercial & Industrial(1)
Commercial & Industrial
S
Standard Power
Speed in Megahertz
,
70T3339 9Mbit (512K x 18-Bit) Synchronous Dual-Port RAM
70T3319 4Mbit (256K x 18-Bit) Synchronous Dual-Port RAM
70T3399 2Mbit (128K x 18-Bit) Synchronous Dual-Port RAM
5652 drw 24
NOTES:
1. 166MHz I-Temp is not available in the BF-208 package.
2. 200Mhz is not available in the BF-208 and DD-144 packages.
IDT Clock Solution for IDT70T3339/19/99 Dual-Port
Dual-Port I/O Specitications
IDT Dual-Port
Part Number
Voltage
70T3339/19/99
2.5
Clock Specifications
I/O
Input
Capacitance
Input Duty
Cycle
Requirement
Maximum
Frequency
Jitter
Tolerance
IDT
PLL
Clock Device
IDT
Non-PLL
Clock Device
LVTTL
8pF
40%
200
75ps
5T2010
5T9010
5T905, 5T9050
5T907, 5T9070
5652 tbl 19
Preliminary Datasheet: Definition
"PRELIMINARY' datasheets contain descriptions for products that are in early release.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-5166
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
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for Tech Support:
831-754-4613
[email protected]
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Datasheet Document History:
01/20/03:
04/25/03:
11/11/03:
Initial Datasheet
Page 11 Added Capacitance Derating drawing
Page 12 Changed tINS and tINR specs in AC Electrical Characteristics table
Page 10 Updated power numbers in DC Electrical Characteristics table
Page 12 Added tOFS symbol and parameter to AC Electrical Characteristics table
Page 21 Updated Collision Timing waveform
Page 22 Added Collision Detection Timing table and footnotes
Page 26 Updated HIGHZ function in System Interface Parameters table
Page 27 Added IDT Clock Solution table
6.42
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