ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 ADC0831-N/ADC0832-N/ADC0834-N/ADC0838-N 8-Bit Serial I/O A/D Converters with Multiplexer Options Check for Samples: ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N FEATURES KEY SPECIFICATIONS • • • • • • 1 2 • • • • • • • • • • • TI MICROWIRE Compatible—Direct Interface to COPS Family Processors Easy Interface to All Microprocessors, or Operates “Stand-Alone” Operates Ratiometrically or with 5 VDC Voltage Reference No Zero or Full-Scale Adjust Required 2-, 4- or 8-Channel Multiplexer Options with Address Logic Shunt Regulator Allows Operation with High Voltage Supplies 0V to 5V Input Range with Single 5V Power Supply Remote Operation with Serial Digital Data Link TTL/MOS Input/Output Compatible 0.3 in. Standard Width, 8-, 14- or 20-Pin PDIP Package 20 Pin PLCC Package (ADC0838-N Only) SOIC Package Resolution: 8 Bits Total Unadjusted Error: ±½ LSB and ±1 LSB Single Supply: 5 VDC Low Power: 15 mW Conversion Time: 32 μs DESCRIPTION The ADC0831 series are 8-bit successive approximation A/D converters with a serial I/O and configurable input multiplexers with up to 8 channels. The serial I/O is configured to comply with the TI MICROWIRE serial data exchange standard for easy interface to the COPS family of processors, and can interface with standard shift registers or μPs. The 2-, 4- or 8-channel multiplexers are software configured for single-ended or differential inputs as well as channel assignment. The differential analog voltage input allows increasing the common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. Typical Application 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N SNAS531B – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Connection Diagrams Figure 4. ADC0831-N Single Differential Input PDIP Package (P) Top View Figure 1. ADC0838-N 8-Channel Mux SOIC/PDIP Package (DW or NFH) Top View COM internally connected to GND. VREF internally connected to VCC. Top View Figure 5. ADC0832-N 2-Channel MUX PDIP Package (P) Top View Figure 2. ADC0832-N 2-Channel MUX SOIC Package (NPA) Top View Figure 6. ADC0831-N Single Differential Input SOIC Package (NPA) Top View COM internally connected to A GND Top View Figure 3. ADC0834-N 4-Channel MUX SOIC/PDIP (NPA or NFF) Top View Figure 7. ADC0838-N 8-Channel MUX PLCC Package (FN) These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) Current into V+ (4) 15 mA Supply Voltage, VCC (4) 6.5V Voltage Logic Inputs −0.3V to VCC + 0.3V Analog Inputs −0.3V to VCC + 0.3V Pin Input Current per (5) ±5 mA Package ±20 mA −65°C to +150°C Storage Temperature Package Dissipation at TA = 25°C (Board Mount) Lead Temperature (Soldering 10 sec.) PDIP Package 260°C Vapor Phase (60 sec.) 215°C PLCC Package 0.8W Infrared (15 sec.) 220°C ESD Susceptibility (6) (1) (2) (3) (4) (5) (6) 2000V All voltages are measured with respect to the ground plugs. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Internal zener diodes (6.3 to 8.5V) are connected from V+ to GND and VCC to GND. The zener at V+ can operate as a shunt regulator and is connected to VCC via a conventional diode. Since the zener voltage equals the A/D's breakdown voltage, the diode insures that VCC will be below breakdown when the device is powered from V+. Functionality is therefore ensured for V+ operation even though the resultant voltage at VCC may exceed the specified Absolute Max of 6.5V. It is recommended that a resistor be used to limit the max current into V+. (See Figure 24 in Functional Description) When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V− or VIN > V+) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four. Human body model, 100 pF discharged through a 1.5 kΩ resistor. Operating Ratings (1) (2) Supply Voltage, VCC 4.5 VDC to 6.3 VDC Temperature Range (TMIN ≤ TA ≤ TMAX) ADC0832/8CIWM ADC0834BCN, ADC0838BCV, ADC0831/2/4/8CCN, ADC0838CCV ADC0831/2/4/8CCWM (1) (2) −40°C to +85°C 0°C to +70°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. All voltages are measured with respect to the ground plugs. Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N 3 ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N SNAS531B – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Converter and Multiplexer Electrical Characteristics The following specifications apply for VCC = V+ = VREF = 5V, VREF ≤ VCC +0.1V, TA = Tj = 25°C, and fCLK = 250 kHz unless otherwise specified. Boldface limits apply from TMIN to TMAX. BCV, CCV, CCWM, BCN and CCN Devices CIWM Devices Parameter Conditions Tested Limit (2) Design Limit (3) ADC0838BCV ±½ ±½ ADC0834BCN ±½ ±½ ADC0838CCV ±1 ±1 ±1 ±1 ±1 ±1 Typ (1) Tested Limit (2) Design Limit (3) Typ (1) Units CONVERTER AND MULTIPLEXER CHARACTERISTICS Total Unadjusted Error ADC0831/2/4/8CCN VREF = 5.00 V (4) ADC0831/2/4/8CCWM ADC0832/8CIWM LSB (Max) ±1 Minimum Reference Input Resistance (5) 3.5 1.3 3.5 1.3 1.3 kΩ Maximum Reference Input Resistance (5) 3.5 5.9 3.5 5.4 5.9 kΩ Maximum Common-Mode Input Range (6) VCC +0.05 VCC +0.05 VCC+0.05 V Minimum Common-Mode Input Range (6) GND −0.05 GND −0.05 GND −0.05 V ±¼ ±¼ LSB 1 1 1 LSB 6.3 6.3 6.3 8.5 8.5 V ±¼ ±¼ LSB −0.2 −1 μA +0.2 +1 μA −0.2 −1 μA +0.2 +1 μA DC Common-Mode Error ±1/16 Change in zero error from VCC=5V to internal zener operation (7) VZ, internal diode breakdown (at V+) (7) 15 mA into V+, VCC = N.C., VREF = 5V MIN 15 mA into V+ MAX Power Supply Sensitivity On Channel = 5V ION, On Channel Leakage Current (8) (1) (2) (3) (4) (5) (6) (7) (8) 4 ±1/16 8.5 VCC = 5V ± 5% IOFF, Off Channel Leakage Current (8) ±¼ ±1/16 ±¼ ±¼ ±1/16 −0.2 Off Channel = 0V −1 On Channel = 0V +0.2 Off Channel = 5V +1 On Channel = 0V −0.2 Off Channel = 5V −1 On Channel = 5V +0.2 Off Channel = 0V +1 Typicals are at 25°C and represent most likely parametric norm. Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level). Ensured but not 100% production tested. These limits are not used to calculate outgoing quality levels. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. Cannot be tested for ADC0832-N. For VIN(−) ≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Functional Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Internal zener diodes (6.3 to 8.5V) are connected from V+ to GND and VCC to GND. The zener at V+ can operate as a shunt regulator and is connected to VCC via a conventional diode. Since the zener voltage equals the A/D's breakdown voltage, the diode insures that VCC will be below breakdown when the device is powered from V+. Functionality is therefore ensured for V+ operation even though the resultant voltage at VCC may exceed the specified Absolute Max of 6.5V. It is recommended that a resistor be used to limit the max current into V+. (See Figure 24 in Functional Description) Leakage current is measured with the clock not switching. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 Converter and Multiplexer Electrical Characteristics (continued) The following specifications apply for VCC = V+ = VREF = 5V, VREF ≤ VCC +0.1V, TA = Tj = 25°C, and fCLK = 250 kHz unless otherwise specified. Boldface limits apply from TMIN to TMAX. CIWM Devices Parameter Conditions Typ (1) Tested Limit (2) Design Limit (3) BCV, CCV, CCWM, BCN and CCN Devices Typ (1) Tested Limit (2) Design Limit (3) Units DIGITAL AND DC CHARACTERISTICS VIN(1), Logical “1” Input Voltage (Min) VCC = 5.25V 2.0 2.0 2.0 V VIN(0), Logical “0” Input Voltage (Max) 0.8 0.8 0.8 V VCC = 4.75V IIN(1), Logical “1” Input Current (Max) VIN = 5.0V 0.005 1 0.005 1 1 μA IIN(0), Logical “0” Input Current (Max) VIN = 0V −0.005 −1 −0.00 5 −1 −1 μA VCC = 4.75V VOUT(1), Logical “1” Output Voltage (Min) IOUT = −360 μA 2.4 2.4 2.4 V IOUT = −10 μA 4.5 4.5 4.5 V VOUT(0), Logical “0” Output Voltage (Max) VCC = 4.75V, IOUT = 1.6 mA 0.4 0.4 0.4 V IOUT, TRI-STATE Output Current (Max) VOUT = 0V −0.1 −3 −0.1 −3 −3 μA VOUT = 5V 0.1 3 0.1 +3 +3 μA ISOURCE, Output Source Current (Min) VOUT = 0V −14 −6.5 −14 −7.5 −6.5 mA ISINK, Output Sink Current (Min) VOUT = VCC 16 8.0 16 9.0 8.0 mA 0.9 2.5 0.9 2.5 2.5 mA 2.3 6.5 2.3 6.5 6.5 mA ICC, Supply Current (Max) ADC0832-N ADC0831-N, ADC0834-N, ADC0838-N Includes Ladder Current Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N 5 ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N SNAS531B – AUGUST 1999 – REVISED MARCH 2013 www.ti.com AC Characteristics The following specifications apply for VCC = 5V, tr = tf = 20 ns and 25°C unless otherwise specified. Parameter Conditions Typ (1) Min fCLK, Clock Frequency Tested Limit (2) 10 Max tC, Conversion Time Design Limit (3) kHz 400 Not including MUX Addressing Time Limit Units 8 kHz 1/fCLK Min 40 % Max 60 % tSET-UP, CS Falling Edge or Data Input Valid to CLK Rising Edge 250 ns tHOLD, Data Input Valid after CLK Rising Edge 90 ns Clock Duty Cycle (4) CL=100 pF tpd1, tpd0—CLK Falling Edge to Output Data Valid (5) t1H, t0H,—Rising Edge of CS to Data Output and SARS Hi–Z Data MSB First 650 1500 ns Data LSB First 250 600 ns CL=10 pF, RL=10k (See TRI-STATE Test Circuits and Waveforms) 125 250 ns CL=100 pf, RL=2k 500 ns CIN, Capacitance of Logic Input 5 pF COUT, Capacitance of Logic Outputs 5 pF (1) (2) (3) (4) (5) 6 Typicals are at 25°C and represent most likely parametric norm. Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level). Ensured but not 100% production tested. These limits are not used to calculate outgoing quality levels. A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the minimum, time the clock is high or the minimum time the clock is low must be at least 1 μs. The maximum time the clock can be high is 60 μs. The clock can be stopped when low so long as the analog input voltage remains stable. Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see ADC0838-N Functional Block Diagram) to allow for comparator response time. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 Typical Performance Characteristics Unadjusted Offset Error vs. VREF Voltage Linearity Error vs. VREFVoltage Figure 8. Figure 9. Linearity Error vs. Temperature Linearity Error vs. fCLK Figure 10. Figure 11. Power Supply Current vs. Temperature (ADC0838-N, ADC0831-N, ADC0834-N) Output Current vs. Temperature Note: For ADC0832-N add IREF. Figure 12. Copyright © 1999–2013, Texas Instruments Incorporated Figure 13. Submit Documentation Feedback Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N 7 ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N SNAS531B – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Power Supply Current vs. fCLK Figure 14. Leakage Current Test Circuit TRI-STATE Test Circuits and Waveforms 8 t1H t1H t0H t0H Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 Timing Diagrams Figure 15. Data Input Timing Figure 16. Data Output Timing Figure 17. ADC0831-N Start Conversion Timing *LSB first output not available on ADC0831-N. Figure 18. ADC0831-N Timing Figure 19. ADC0832-N Timing Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N 9 ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N SNAS531B – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Figure 20. ADC0834-N Timing 10 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 *Make sure clock edge #18 clocks in the LSB before SE is taken low Figure 21. ADC0838-N Timing Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N 11 ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N SNAS531B – AUGUST 1999 – REVISED MARCH 2013 www.ti.com ADC0838-N Functional Block Diagram *Some of these functions/pins are not available with other options. Note 1: For the ADC0834-N, D1 is input directly to the D input of SELECT 1. SELECT 0 is forced to a “1”. For the ADC0832-N, DI is input directly to the DI input of ODD/SIGN. SELECT 0 is forced to a “0” and SELECT 1 is forced to a “1”. 12 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 Functional Description Multiplexer Addressing The design of these converters utilizes a sample-data comparator structure which provides for a differential analog input to be converted by a successive approximation routine. The actual voltage converted is always the difference between an assigned “+” input terminal and a “−” input terminal. The polarity of each input terminal of the pair being converted indicates which line the converter expects to be the most positive. If the assigned “+” input is less than the “−” input the converter responds with an all zeros output code. A unique input multiplexing scheme has been utilized to provide multiple analog channels with softwareconfigurable single-ended, differential, or a new pseudo-differential option which will convert the difference between the voltage at any analog input and a common terminal. The analog signal conditioning required in transducer-based data acquisition systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals with some arbitrary reference voltage. A particular input configuration is assigned during the MUX addressing sequence, prior to the start of a conversion. The MUX address selects which of the analog inputs are to be enabled and whether this input is single-ended or differential. In the differential case, it also assigns the polarity of the channels. Differential inputs are restricted to adjacent channel pairs. For example channel 0 and channel 1 may be selected as a different pair but channel 0 or 1 cannot act differentially with any other channel. In addition to selecting differential mode the sign may also be selected. Channel 0 may be selected as the positive input and channel 1 as the negative input or vice versa. This programmability is best illustrated by the MUX addressing codes shown in the following tables for the various product options. The MUX address is shifted into the converter via the DI line. Because the ADC0831-N contains only one differential input channel with a fixed polarity assignment, it does not require addressing. The common input line on the ADC0838-N can be used as a pseudo-differential input. In this mode, the voltage on this pin is treated as the “−” input for any of the other input channels. This voltage does not have to be analog ground; it can be any reference potential which is common to all of the inputs. This feature is most useful in single-supply application where the analog circuitry may be biased up to a potential other than ground and the output signals are all referred to this potential. Table 1. Multiplexer/Package Options Single-Ended MUX Mode Number of Analog Channels Part Number Number of Package Pins Single-Ended Differential ADC0831-N 1 1 8 ADC0832-N 2 1 8 ADC0834-N 4 2 14 ADC0838-N 8 4 20 Table 2. MUX Addressing: ADC0838-N Single-Ended MUX Mode MUX Address Analog Single-Ended Channel # SGL/ ODD/ DIF SIGN SELECT 0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 2 3 4 5 6 7 COM 0 Copyright © 1999–2013, Texas Instruments Incorporated − + − + − + − + − + − + − + + Submit Documentation Feedback Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N − 13 ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N SNAS531B – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Table 3. MUX Addressing: ADC0838-N Differential MUX Mode MUX Address Analog Differential Channel-Pair # SGL/ ODD/ SELECT 0 DIF SIGN 1 0 0 1 0 0 0 0 + − 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 − 1 2 2 3 + − 3 4 5 + − 6 7 + − − + + − + − + Table 4. MUX Addressing: ADC0834-N Single-Ended MUX Mode MUX Address Channel # SELECT SGL / DIF ODD / SIGN 1 0 0 1 0 1 1 1 0 1 1 1 1 0 1 2 3 + + + + Table 5. MUX Addressing: ADC0834-N Differential MUX Mode MUX Address Channel # SELECT SGL / DIF ODD / SIGN 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 + − − + 2 3 + − − + Table 6. MUX Addressing: ADC0832-N Single-Ended MUX Mode MUX Address Channel # SGL / DIF ODD / SIGN 0 1 0 + 1 1 1 + Table 7. MUX Addressing: ADC0832-N Differential MUX Mode MUX Address Channel # SGL / DIF ODD / SIGN 0 1 0 0 + − 0 1 − + Since the input configuration is under software control, it can be modified, as required, at each conversion. A channel can be treated as a single-ended, ground referenced input for one conversion; then it can be reconfigured as part of a differential channel for another conversion. Figure 22 illustrates the input flexibility which can be achieved. The analog input voltages for each channel can range from 50 mV below ground to 50 mV above VCC (typically 5V) without degrading conversion accuracy. 14 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 THE DIGITAL INTERFACE A most important characteristic of these converters is their serial data link with the controlling processor. Using a serial communication format offers two very significant system improvements; it allows more function to be included in the converter package with no increase in package size and it can eliminate the transmission of low level analog signals by locating the converter right at the analog sensor; transmitting highly noise immune digital data back to the host processor. To understand the operation of these converters it is best to refer to the Timing Diagrams and Functional Block Diagram and to follow a complete conversion sequence. For clarity a separate diagram is shown of each device. 1. A conversion is initiated by first pulling the CS (chip select) line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its MUX assignment word. 2. A clock is then generated by the processor (if not provided continuously) and output to the A/D clock input. 8 Single-Ended 8 Pseudo-Differential 4 Differential Mixed Mode Figure 22. Analog Input Multiplexer Options for the ADC0838-N 3. On each rising edge of the clock the status of the data in (DI) line is clocked into the MUX address shift register. The start bit is the first logic “1” that appears on this line (all leading zeros are ignored). Following the start bit the converter expects the next 2 to 4 bits to be the MUX assignment word. 4. When the start bit has been shifted into the start location of the MUX register, the input channel has been assigned and a conversion is about to begin. An interval of ½ clock period (where nothing happens) is automatically inserted to allow the selected MUX channel to settle. The SAR status line goes high at this time to signal that a conversion is now in progress and the DI line is disabled (it no longer accepts data). 5. The data out (DO) line now comes out of TRI-STATE and provides a leading zero for this one clock period of MUX settling time. 6. When the conversion begins, the output of the SAR comparator, which indicates whether the analog input is greater than (high) or less than (low) each successive voltage from the internal resistor ladder, appears at the DO line on each falling edge of the clock. This data is the result of the conversion being shifted out (with the MSB coming first) and can be read by the processor immediately. Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N 15 ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N SNAS531B – AUGUST 1999 – REVISED MARCH 2013 www.ti.com 7. After 8 clock periods the conversion is completed. The SAR status line returns low to indicate this ½ clock cycle later. 8. If the programmer prefers, the data can be provided in an LSB first format [this makes use of the shift enable (SE) control line]. All 8 bits of the result are stored in an output shift register. On devices which do not include the SE control line, the data, LSB first, is automatically shifted out the DO line, after the MSB first data stream. The DO line then goes low and stays low until CS is returned high. On the ADC0838-N the SE line is brought out and if held high, the value of the LSB remains valid on the DO line. When SE is forced low, the data is then clocked out LSB first. The ADC0831-N is an exception in that its data is only output in MSB first format. 9. All internal registers are cleared when the CS line is high. If another conversion is desired, CS must make a high to low transition followed by address information. The DI and DO lines can be tied together and controlled through a bidirectional processor I/O bit with one wire. This is possible because the DI input is only “looked-at” during the MUX addressing interval while the DO line is still in a high impedance state. Reference Considerations The voltage applied to the reference input to these converters defines the voltage span of the analog input (the difference between VIN(MAX) and VIN(MIN)) over which the 256 possible output codes apply. The devices can be used in either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a voltage source capable of driving the reference input resistance of typically 3.5 kΩ. This pin is the top of a resistor divider string used for the successive approximation conversion. In a ratiometric system, the analog input voltage is proportional to the voltage used for the A/D reference. This voltage is typically the system power supply, so the VREF pin can be tied to VCC (done internally on the ADC0832N). This technique relaxes the stability requirements of the system reference as the analog input and A/D reference move together maintaining the same output code for a given input condition. For absolute accuracy, where the analog input varies between very specific voltage limits, the reference pin can be biased with a time and temperature stable voltage source. The LM385 and LM336 reference diodes are good low current devices to use with these converters. The maximum value of the reference is limited to the VCC supply voltage. The minimum value, however, can be quite small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals VREF/256). a) Ratiometric b) Absolute with a reduced Span Figure 23. Reference Examples 16 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 The Analog Inputs The most important feature of these converters is that they can be located right at the analog signal source and through just a few wires can communicate with a controlling processor with a highly noise immune serial bit stream. This in itself greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup. However, a few words are in order with regard to the analog inputs should the input be noisy to begin with or possibly riding on a large common-mode voltage. The differential input of these converters actually reduces the effects of common-mode input noise, a signal common to both selected “+” and “−” inputs for a conversion (60 Hz is most typical). The time interval between sampling the “+” input and then the “−” input is ½ of a clock period. The change in the common-mode voltage during this short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is: where • • • fCM is the frequency of the common-mode signal VPEAK is its peak voltage value fCLK, is the A/D clock frequency (1) For a 60 Hz common-mode signal to generate a ¼ LSB error (≈5 mV) with the converter running at 250 kHz, its peak value would have to be 6.63V which would be larger than allowed as it exceeds the maximum analog input limits. Due to the sampling nature of the analog inputs short spikes of current enter the “+” input and exit the “−” input at the clock edges during the actual conversion. These currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents and cause an effective DC current to flow through the output resistance of the analog signal source. Bypass capacitors should not be used if the source resistance is greater than 1 kΩ. This source resistance limitation is important with regard to the DC leakage currents of input multiplexer as well. The worst-case leakage current of ±1 μA over temperature will create a 1 mV input error with a 1 kΩ source resistance. An op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance signal source be required. Optional Adjustments Zero Error The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VIN(MIN), is not ground a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing any VIN (−) input at this VIN(MIN) value. This utilizes the differential mode operation of the A/D. The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the VIN(−) input and applying a small magnitude positive voltage to the VIN(+) input. Zero error is the difference between the actual DC input voltage which is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal ½ LSB value (½ LSB=9.8 mV for VREF=5.000 VDC). Full-Scale The full-scale adjustment can be made by applying a differential input voltage which is 1 ½ LSB down from the desired analog full-scale voltage range and then adjusting the magnitude of the VREF input (or VCC for the ADC0832) for a digital output code which is just changing from 1111 1110 to 1111 1111. Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N 17 ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N SNAS531B – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference should be properly adjusted first. A VIN (+) voltage which equals this desired zero reference plus ½ LSB (where the LSB is calculated for the desired analog span, using 1 LSB= analog span/256) is applied to selected “+” input and the zero reference voltage at the corresponding “−” input should then be adjusted to just obtain the 00HEX to 01HEX code transition. The full-scale adjustment should be made [with the proper VIN(−) voltage applied] by forcing a voltage to the VIN(+) input which is given by: where • • VMAX = the high end of the analog input range VMIN = the low end (the offset zero) of the analog range. (Both are ground referenced.) (2) The VREF (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the adjustment procedure. Power Supply A unique feature of the ADC0838-N and ADC0834-N is the inclusion of a zener diode connected from the V+ terminal to ground which also connects to the VCC terminal (which is the actual converter supply) through a silicon diode, as shown in Figure 24 (1). Figure 24. An On-Chip Shunt Regulator Diode This zener is intended for use as a shunt voltage regulator to eliminate the need for any additional regulating components. This is most desirable if the converter is to be remotely located from the system power source. Figure 25 and Figure 27 illustrate two useful applications of this on-board zener when an external transistor can be afforded. An important use of the interconnecting diode between V+ and VCC is shown in Figure 26 and Figure 28. Here, this diode is used as a rectifier to allow the VCC supply for the converter to be derived from the clock. The low current requirements of the A/D and the relatively high clock frequencies used (typically in the range of 10k–400 kHz) allows using the small value filter capacitor shown to keep the ripple on the VCC line to well under ¼ of an LSB. The shunt zener regulator can also be used in this mode. This requires a clock voltage swing which is in excess of VZ. A current limit for the zener is needed, either built into the clock generator or a resistor can be used from the CLK pin to the V+ pin. (1) 18 Internal zener diodes (6.3 to 8.5V) are connected from V+ to GND and VCC to GND. The zener at V+ can operate as a shunt regulator and is connected to VCC via a conventional diode. Since the zener voltage equals the A/D's breakdown voltage, the diode insures that VCC will be below breakdown when the device is powered from V+. Functionality is therefore ensured for V+ operation even though the resultant voltage at VCC may exceed the specified Absolute Max of 6.5V. It is recommended that a resistor be used to limit the max current into V+. (See Figure 24 in Functional Description) Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 APPLICATIONS *4.5V ≤ VCC ≤ 6.3V Figure 25. Operating with a Temperature Compensated Reference Figure 26. Generating VCC from the Converter Clock *4.5V ≤ VCC ≤ 6.3V Figure 27. Using the A/D as the System Supply Regulator Figure 28. Remote Sensing— Clock and Power on 1 Wire Figure 29. Digital Link and Sample Controlling Software for the Serially Oriented COP420 and the Bit Programmable I/O INS8048 Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N 19 ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N SNAS531B – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Cop Coding Example Mnemonic LEI SC OGI CLR A AISC 1 XAS LDD NOP XAS XAS XIS CLER A RC XAS XIS OGI LEI Instruction ENABLES SIO's INPUT AND OUTPUT C = 1 G0 = 0 (CS = 0) CLEARS ACCUMULATOR LOADS ACCUMULATOR WITH 1 EXCHANGES SIO WITH ACCUMULATOR AND STARTS SK CLOCK LOADS MUX ADDRESS FROM RAM INTO ACCUMULATOR LOADS MUX ADDRESS FROM ACCUMULATOR ↑ 8 INSTRUCTIONS ↓ READS HIGH ORDER NIBBLE (4 BITS) INTO ACCUMULATOR PUTS HIGH ORDER NIBBLE INTO RAM CLEARS ACCUMULATOR C = 0 READS LOW ORDER NIBBLE INTO ACCUMULATOR AND STOPS SK PUTS LOW ORDER NIBBLE INTO RAM G0 = 1 (CS = 1) DISABLES SIO's INPUT AND OUTPUT 8048 Coding Example Mnemonic START: ANL MOV MOV LOOP 1: RRC JC ZERO: ANL JMP ONE: CONT: ORL CALL DJNZ CALL LOOP 2: MOV CALL IN RRC RRC MOV RLC MOV DJNZ Instruction P1, #0F7H ;SELECT A/D (CS = 0) B, #5 ;BIT COUNTER←5 A, #ADDR ;A←MUX ADDRESS A ;CY←ADDRESS BIT ONE ;TEST BIT ;BIT=0 P1, #0FEH ;DI←0 CONT ;CONTINUE ;BIT=1 P1, #1 ;DI←1 PULSE ;PULSE SK 0→1→0 B, LOOP 1 ;CONTINUE UNTIL DONE PULSE ;EXTRA CLOCK FOR SYNC B, #8 ;BIT COUNTER←8 PULSE ;PULSE SK 0→1→0 A, P1 ;CY←DO A A A, C ;A←RESULT A ;A(0)←BIT AND SHIFT C, A ;C←RESULT B, LOOP 2 ;CONTINUE UNTIL DONE RETR PULSE: 20 ORL NOP ANL RET P1, #04 P1, #0FBH ;PULSE SUBROUTINE ;SK←1 ;DELAY ;SK←0 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 *Pinouts shown for ADC0838-N. For all other products tie to pin functions as shown. Figure 30. A “Stand-Alone” Hook-Up for ADC0838-N Evaluation Figure 31. Low-Cost Remote Temperature Sensor Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N 21 ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N SNAS531B – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Figure 32. Digitizing a Current Flow *VIN(−) = 0.15 VCC 15% of VCC ≤ VXDR ≤ 85% of VCC Figure 33. Operating with Ratiometric Transducers Figure 34. Span Adjust: 0V≤VIN≤3V 22 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 Figure 35. Zero-Shift and Span Adjust: 2V ≤ VIN ≤ 5V Figure 36. Obtaining Higher Resolution - 9-Bit A/D Controller performs a routine to determine which input polarity (9-bit example) or which channel pair (10-bit example) provides a non-zero output code. This information provides the extra bits. Figure 37. Obtaining Higher Resolution - 10-Bit A/D Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N 23 ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N SNAS531B – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Diodes are 1N914 Figure 38. Protecting the Input DO = all 1s if +VIN > −VIN DO = all 0s if +VIN < −VIN Figure 39. High Accuracy Comparators 24 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 •Uses one more wire than load cell itself •Two mini-DIPs could be mounted inside load cell for digital output transducer •Electronic offset and gain trims relax mechanical specs for gauge factor and offset •Low level cell output is converted immediately for high noise immunity Figure 40. Digital Load Cell •All power supplied by loop •1500V isolation at output Figure 41. 4 mA-20 mA Current Loop Converter Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N 25 ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N SNAS531B – AUGUST 1999 – REVISED MARCH 2013 www.ti.com •No power required remotely •1500V isolation Figure 42. Isolated Data Converter 26 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 Figure 43. Two Wire Interface for 8 Channels Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N 27 ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N SNAS531B – AUGUST 1999 – REVISED MARCH 2013 www.ti.com Figure 44. Two Wire 1-Channels Interface 28 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N www.ti.com SNAS531B – AUGUST 1999 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision A (March 2013) to Revision B • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 28 Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC0831-N ADC0832-N ADC0834-N ADC0838-N 29 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADC0831CCN NRND PDIP P 8 40 TBD Call TI Call TI -40 to 85 ADC 0831CCN ADC0831CCN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) SN | CU SN Level-1-NA-UNLIM -40 to 85 ADC 0831CCN ADC0831CCWM/NOPB ACTIVE SOIC NPA 14 50 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC0831 CCWM ADC0831CCWMX/NOPB ACTIVE SOIC NPA 14 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC0831 CCWM ADC0832CCN NRND PDIP P 8 40 TBD Call TI Call TI -40 to 85 ADC 0832CCN ADC0832CCN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) SN | CU SN Level-1-NA-UNLIM -40 to 85 ADC 0832CCN ADC0832CCWM NRND SOIC NPA 14 50 TBD Call TI Call TI -40 to 85 ADC0832 CCWM ADC0832CCWM/NOPB ACTIVE SOIC NPA 14 50 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC0832 CCWM ADC0832CCWMX NRND SOIC NPA 14 1000 TBD Call TI Call TI -40 to 85 ADC0832 CCWM ADC0832CCWMX/NOPB ACTIVE SOIC NPA 14 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC0832 CCWM ADC0834CCN/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS & no Sb/Br) SN | CU SN Level-1-NA-UNLIM -40 to 85 ADC0834CCN ADC0834CCWM NRND SOIC NPA 14 50 TBD Call TI Call TI -40 to 85 ADC0834 CCWM ADC0834CCWM/NOPB ACTIVE SOIC NPA 14 50 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC0834 CCWM ADC0834CCWMX/NOPB ACTIVE SOIC NPA 14 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC0834 CCWM ADC0838CCN NRND PDIP NFH 20 18 TBD Call TI Call TI -40 to 85 ADC0838CCN ADC0838CCN/NOPB ACTIVE PDIP NFH 20 18 Green (RoHS & no Sb/Br) SN Level-1-NA-UNLIM -40 to 85 ADC0838CCN ADC0838CCWM NRND SOIC DW 20 36 TBD Call TI Call TI -40 to 85 ADC0838 CCWM Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 1-Nov-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADC0838CCWM/NOPB ACTIVE SOIC DW 20 36 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC0838 CCWM ADC0838CCWMX NRND SOIC DW 20 1000 TBD Call TI Call TI -40 to 85 ADC0838 CCWM ADC0838CCWMX/NOPB ACTIVE SOIC DW 20 1000 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC0838 CCWM ADC0838CIWM/NOPB ACTIVE SOIC DW 20 36 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC0838 CIWM ADC0838CIWMX NRND SOIC DW 20 1000 TBD Call TI Call TI -40 to 85 ADC0838 CIWM ADC0838CIWMX/NOPB ACTIVE SOIC DW 20 1000 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC0838 CIWM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC0831CCWMX/NOPB SOIC NPA 14 1000 330.0 16.4 10.9 9.5 3.2 12.0 16.0 Q1 ADC0832CCWMX SOIC NPA 14 1000 330.0 16.4 10.9 9.5 3.2 12.0 16.0 Q1 ADC0832CCWMX/NOPB SOIC NPA 14 1000 330.0 16.4 10.9 9.5 3.2 12.0 16.0 Q1 ADC0834CCWMX/NOPB SOIC NPA 14 1000 330.0 16.4 10.9 9.5 3.2 12.0 16.0 Q1 ADC0838CCWMX SOIC DW 20 1000 330.0 24.4 10.9 13.3 3.25 12.0 24.0 Q1 ADC0838CCWMX/NOPB SOIC DW 20 1000 330.0 24.4 10.9 13.3 3.25 12.0 24.0 Q1 ADC0838CIWMX SOIC DW 20 1000 330.0 24.4 10.9 13.3 3.25 12.0 24.0 Q1 ADC0838CIWMX/NOPB SOIC DW 20 1000 330.0 24.4 10.9 13.3 3.25 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC0831CCWMX/NOPB SOIC NPA 14 1000 367.0 367.0 38.0 ADC0832CCWMX SOIC NPA 14 1000 367.0 367.0 38.0 ADC0832CCWMX/NOPB SOIC NPA 14 1000 367.0 367.0 38.0 ADC0834CCWMX/NOPB SOIC NPA 14 1000 367.0 367.0 38.0 ADC0838CCWMX SOIC DW 20 1000 367.0 367.0 45.0 ADC0838CCWMX/NOPB SOIC DW 20 1000 367.0 367.0 45.0 ADC0838CIWMX SOIC DW 20 1000 367.0 367.0 45.0 ADC0838CIWMX/NOPB SOIC DW 20 1000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA NFF0014A N0014A N14A (Rev G) www.ti.com MECHANICAL DATA NFH0020A N0020A N20A (Rev G) www.ti.com MECHANICAL DATA NPA0014B www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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