AVAGO MGA-638P8 High linearity low noise amplifi er Datasheet

MGA-638P8
High Linearity Low Noise Amplifier
Data Sheet
Description
Features
Avago Technologies’ MGA-638P8 is an economical, easyto-use GaAs MMIC Low Noise Amplifier (LNA). This LNA
has low noise and high linearity achieved through the
use of Avago Technologies’ proprietary 0.25 m GaAs
Enhancement-mode pHEMT process. It is housed in the
miniature 2.0 x 2.0 x 0.75 mm3 8-pin Dual-Flat-Non-Lead
(DFN) package. The device is designed for optimum use
from 2.5 GHz up to 4.0 GHz. The compact footprint and
low profile coupled with low noise, high gain and high
linearity make this an ideal choice as a low noise amplifier
for cellular infrastructure applications such as LTE, GSM,
CDMA, W-CDMA, CDMA2000 & TD-SCDMA. For optimum
performance at lower frequency from 450 MHz up to 1.5
GHz, MGA-636P8 is recommended. For optimum performance from 1.5 GHz up to 2.5 GHz, MGA-637P8 is recommended. All these 3 products, MGA-636P8, MGA-637P8
and MGA-638P8 share the same package and pinout configuration.
 High linearity performance.
Pin Configuration and Package Marking
[2]
[3]
[8]
38X
[7]
[6]
[5]
[4]
TOP VIEW
Pin 1 – Not Used
Pin 2 – RFinput
Pin 3 – Vbias2
Pin 4 – Not Used
Center paddle – GND
[8]
[7]
[6]
[5]
[1]
[2]
GND
 GaAs E-pHEMT Technology[1].
 Low cost small package size.
 Integrated with active bias and option to access FET
gate.
 Integrated power down control pin.
Specifications
2.5 GHz; 4.8 V, 84 mA
 17.3 dB Gain
 0.87 dB Noise Figure
 14 dB Input Return Loss
 22.6 dBm Input IP3
 22.2 dBm Output Power at 1 dB gain compression
Applications
2.0 x 2.0 x 0.75 mm3 8-lead DFN
[1]
 Low Noise Figure.
[3]
[4]
BOTTOM VIEW
 Cellular infrastructure applications such as LTE, GSM,
CDMA, W-CDMA, CDMA2000 & TD-SCDMA.
 Other low noise applications.
Note:
1. Enhancement mode technology employs positive Vgs, thereby
eliminating the need of negative gate voltage associated with conventional depletion mode devices.
Pin 5 – Vbias1
Pin 6 – PwrDwn
Pin 7 – RFoutput
Pin 8 – Not Used
Note:
Package marking provides orientation and identification
“38” = Product Code
“X” = Month Code
It is recommended to ground Pin1, 4 and 8 which are Not Used.
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 100 V
ESD Human Body Model = 350 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Simplified Schematic [1]
Vdd
C6
R2
C4
L3
C1
RFin
L1
[8]
[NU]
[2]
[RFinput]
[7]
[RFoutput]
[3]
[Vbias2]
Bias
[4]
[NU]
C3
L2
[1]
[NU]
C2
RFout
[6]
[PwrDwn]
[5]
[Vbias1]
R1
Rb
C7
C5
C8
PwrDwn
Vbias1
Note:
1. Device is turned ON when PwrDwn pin is applied with 0 V or left
open. Device is turned OFF when PwrDwn pin is applied with 3.3 V
Absolute Maximum Rating [1] TA=25° C
Thermal Resistance
Symbol
Parameter
Units
Absolute Maximum
Vdd
Device Voltage,
RF output to ground
V
5.5
Idd
Drain Current
mA
125
Vbias1
Bias Voltage
V
5.5
VpwrDwn
Power Down Voltage
V
5.5
Pin,max
CW RF Input Power
dBm
+24
Pdiss
Total Power Dissipation
W
0.61
Tj
Junction Temperature
°C
150
TSTG
Storage Temperature
°C
-65 to 150
2
Thermal Resistance [2]
(Vdd = 4.8 V, Idd = 84 mA)
jc = 67°C/W
Notes:
1. Operation of this device in excess of any of
these limits may cause permanent damage.
2. Thermal resistance measured using Infra-Red
Measurement Technique.
3. Power dissipation with unit turned on. Board
temperature TC is 25° C. Derate at 14.9 mW/°C
for Tc > 105.8° C.
Electrical Specifications[1,4]
TA = 25° C, Vdd = Vbias1 = 4.8 V, RF measurement at 2.5 GHz, measured on demo board in Figure 5 with component listed
in Table1.
Symbol
Parameter and Test Condition
Units
Min.
Typ.
Max.
Idd
Bias Current
mA
60
84
110
IPwrDwn
Current at VPwrDwn pin when VPwrDwn = 3.3 V
(Power Down mode)
mA
–
0.15
–
Gain
Gain
dB
16
17.3
19
NF[2]
Noise Figure
dB
–
0.87
1.15
IIP3[3]
Input Third Order Intercept Point
dBm
21
22.6
–
OP1dB
Output Power at 1dB Gain Compression
dBm
–
22.2
–
IRL
Input Return Loss, 50  source
dB
–
14
–
ORL
Output Return Loss, 50  load
dB
–
10
–
Notes:
1. Measurements at 2.5 GHz obtained using demo board described in Figure 5.
2. For NF data, board losses of the input have not been de-embedded.
3. IIP3 test condition: FRF1 = 2.500 GHz, FRF2 = 2.501 GHz with input power of -10 dBm per tone.
4. Use proper bias, heatsink and derating to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and application
note for more details.
Product Consistency Distribution Charts [1, 2]
LSL
50
USL
70
60
80
90
100
110
Figure 1. Idd, LSL = 60 mA , nominal = 84 mA, USL = 110 mA
21
0.7
0.9
0.8
1
1.1
LSL
22
23
Figure 3. IIP3, LSL = 21 dBm, nominal = 22.6 dBm
24
1.2
Figure 2. NF, nominal = 0.87 dB, USL = 1.15 dB
LSL
20
USL
25
16
USL
17
18
19
Figure 4. Gain, LSL = 16 dB, nominal = 17.3 dB, USL = 19 dB
Notes:
1. Distribution data sample size is 500 samples taken from 3 different wafer lots. Future wafers allocated to this product may have nominal values
anywhere between the upper and lower limits.
2. Circuit trace losses have not been de-embedded from measurements above.
3
Demo Board Layout
Demo Board Schematic
Avago
Technologies
BTS LNA
Nov 2010
Vdd
C6
R2
RFin
C4
L3
C1
C2
L1
RFout
L3
L2
C4
C6
C3
Rb
C1
RFin
R1
L1
C5
C8
C7
[8]
[NU]
[2]
[RFinput]
[7]
[RFoutput]
[3]
[Vbias2]
Bias
[4]
[NU]
C3
L2
[1]
[NU]
C2
RFout
[6]
[PwrDwn]
[5]
[Vbias1]
R1
Rb
C7
Vbias1
C8
PwrDwn
Vdd
PwrDwn
Vbias1
C5
Truth Table
Figure 5. Demo Board Layout Diagram
– Recommended PCB material is 10 mils Rogers RO4350.
– Suggested component values may vary according to
layout and PCB material.
VPwrDwn(V)
LNA Mode
0 or open
Power Down Mode
3.3
Figure 6. Demo Board Schematic Diagram
Notes:
 The schematic is shown with the assumption that similar PCB is used
for all MGA-636P8, MGA-637P8 and MGA-638P8.
 Detail of the components needed for this product is shown in Table 1.
Table 1. Component list for 2.5 GHz matching
Part
Size
Value
Detail Part Number
C1
0402
1.8 pF (Murata)
GRM1555C1H1R8CB01D
C2
0402
100 pF (Murata)
GRM1555C1H101JD01D
C5, C6, C7, C8
0603
4.7 F (Murata)
GRM188R60J475KE19D
C3, C4
0402
Not Used
L1
0402
8.2 nH (Toko)
LLP1005-FH8N2C
L2
0402
5.6 nH (Toko)
LLP1005-FH5N6C
L3
0402
1.8 nH (Toko)
LLP1005-FH1N8C
Rb
0402
680 ohm (Rohm)
MCR004YZPJ680
R1
0402
51 ohm (Rohm)
MCR004YZPJ510
R2
0402
0 ohm (Rohm)
MCR01MZPJ000
Notes:
C1, C2 are DC blocking capacitors
C1, L1, L3 input match for NF
L2 output match for IP3
C5, C6, C7, C8 are bypass capacitors
R1 is a stabilizing resistor
Rb is the biasing resistor
4
Typical Performance
0.9
0.9
0.8
0.8
0.7
0.7
Fmin (dB)
Fmin (dB)
RF performance at TA = 25° C, Vdd = 4.8 V, Idd = 84 mA, measured using 50 ohm input and output board unless stated
otherwise. IIP3 test condition: FRF1-FRF2 = 1 MHz with input power of -10 dBm per tone.
0.6
0.5
0.5
0.4
0.4
0.3
0.3
60
80
84
Idd (mA)
90
60
80
84
Idd (mA)
90
100
22
20
18
16
14
12
10
8
6
4
2
0
35
35
30
30
25
25
20
15
5
5
84
Idd (mA)
100
90
100
Figure 11. IIP3 vs Idd at 4.8 V Tuned for Optimum IIP3 and Fmin at 2.5 GHz
60
80
84
Idd (mA)
90
100
15
10
80
90
20
10
60
84
Idd (mA)
Figure 10. Gain vs Idd at 4.8 V Tuned for Optimum IIP3 and Fmin at 2 GHz
IIP3 (dBm)
IIP3 (dBm)
Figure 9. Gain vs Idd at 4.8 V Tuned for Optimum IIP3 and Fmin at 2.5 GHz
0
80
Figure 8. Fmin vs Idd at 4.8 V at 2 GHz
Gain(dB)
Gain(dB)
22
20
18
16
14
12
10
8
6
4
2
0
60
100
Figure 7. Fmin vs Idd at 4.8 V at 2.5 GHz
5
0.6
0
60
80
84
Idd (mA)
90
100
Figure 12. IIP3 vs Idd at 4.8 V Tuned for Optimum IIP3 and Fmin at 2 GHz
1.2
1.1
Gain (dB)
Fmin (dB)
1
0.9
0.8
0.7
100 mA
84 mA
70 mA
0.6
0.5
1.9
2
2.2
2.5
2.7
Frequency (GHz)
3.3
3.5
Figure 13. Fmin vs Frequency and Idd at 4.8 V
30
IIP3 (dBm)
25
20
15
10
5
0
2
2.2
2.5
2.7
Frequency (GHz)
3.3
3.5
Figure 15. IIP3 vs Frequency for Optimum IIP3 and Fmin at 4.8 V 84 mA
6
1.9
2
2.2
2.5
2.7
Frequency (GHz)
3.3
3.5
Figure 14. Gain vs Frequency for Optimum IIP3 and Fmin at 4.8 V 84 mA
35
1.9
22
20
18
16
14
12
10
8
6
4
2
0
Below is the table showing the MGA-638P8 Reflection Coefficient Parameters
tuned for Maximum IIP3, Vdd = 4.8 V, Idd = 84 mA.
Gamma Load position
Frequency
(GHz)
Magnitude
Angle
IIP3
(dBm)
1.9
0.45
-69.6
26.8
2
0.54
-68.1
28.2
2.2
0.45
-69.8
31
2.5
0.45
-58
30
2.7
0.36
-57.7
31.4
3.3
0.18
-89.9
32.1
3.5
0.18
-59.9
34
RFinput
Reference Plane
[1]
[NU]
[8]
[NU]
[2]
[RFinput]
[7]
[RFoutput]
[3]
[Vbias2]
Bias
[4]
[NU]
RFoutput
Reference Plane
[6]
[PwrDwn]
[5]
[Vbias1]
Figure 16. RFinput and RFoutput Reference Plane
Notes:
1. The Maximum IIP3 values are calculated based on Load pull measurements
on approximately 100 different impedances using Focus Load pull test
system.
2. Measurements are conducted on 0.010 inch thick ROGER 4350. The input
reference plane is at the end of the RFin pin and the output reference
plane is at the end of the RFout pin as shown in Figure 16.
7
Typical Performance
RF performance at TA = 25° C, Vdd = Vbias1 = 4.8 V, Idd = 84 mA, LNA mode, measured on demo board in Figure 5.
Signal = CW unless stated otherwise. Application Test Circuit is shown in Figure 6 and Table 1. IIP3 test condition: FRF1-FRF2
= 1 MHz with input power of -10 dBm per tone.
2.0
20
1.8
19
18
Gain (dB)
NF (dB)
1.6
1.4
1.2
1.0
1.9
2.1
2.3
2.5
2.7 2.9 3.1 3.3
Frequency (GHz)
3.5
3.7
12
1.9
3.9
2.1
2.3
2.5
2.7
2.9
Frequency (GHz)
3.1
3.3
3.5
Figure 18. Gain vs Frequency vs Temperature
24
23
OP1dB(dBm)
IIP3 (dBm)
15
25
85° C
25° C
-40° C
22
21
20
19
85° C
25° C
-40° C
18
17
16
2.1
2.3
2.5
2.7
2.9
Frequency (GHz)
Figure 19. IIP3 vs Frequency vs Temperature
8
16
13
Figure 17. NF vs Frequency vs Temperature
32
30
28
26
24
22
20
18
16
14
12
1.9
17
14
85° C
25° C
-40° C
0.8
0.6
85° C
25° C
-40° C
3.1
3.3
3.5
1.9
2.1
2.3
2.5
2.7
2.9
3.1
Frequency (GHz)
Figure 20. OP1dB vs Frequency vs Temperature
3.3
3.5
2.0
0.5
0.0
2.0
2.5
3.0
Frequency (GHz)
3.5
0
4.0
Figure 21. Input Return Loss, Output Return Loss, Gain, Reverse Isolation vs
Frequency
2
4
6
8 10 12 14
Frequency (GHz)
16
18
20
Figure 22. k-factor vs Frequency vs Temperature
90
120
85° C
25° C
-40° C
80
100
70
60
Idd (mA)
80
Idd (mA)
1.5
1.0
1.5
60
50
40
30
40
20
20
10
0
0
0
200
Figure 23. Idd vs Rb
9
100° C
85° C
25° C
-40° C
2.5
k-factor
dB(S(1,2))
dB(S(2,2))
dB(S(1,1))
dB(S(2,1))
3.0
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
-35
400
600
Rb (ohm)
800
1000
1200
0.0
0.5
1.0
Figure 24. Idd vs VPwrDwn
1.5
2.0
2.5
VPwrDwn (V)
3.0
3.5
4.0
Typical Scattering Parameters, Vdd = 4.8 V, Idd = 84 mA
LNA SPAR (100 MHz – 20 GHz)
Freq
(GHz)
S11
(dB)
S11
(ang)
S21
(dB)
S21
(ang)
S12
(dB)
S12
(ang)
S22
(dB)
S22
(ang)
0.1
0.5
0.7
0.9
1.0
1
1.5
1.7
1.9
2.0
2.5
3
3.5
4
4.5
5
5.5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0.052
-3.786
-4.926
-5.619
-5.94
-6.855
-6.979
-7.065
-7.111
-7.134
-7.136
-7.142
-7.139
-7.089
-6.942
-6.655
-6.451
-5.788
-5.04
-4.687
-4.53
-4.256
-3.95
-3.737
-3.546
-3.424
-3.498
-3.526
-3.178
-2.789
-2.6
0.052
-25.318
-94.894
-113.237
-126.296
-130.828
-149.182
-155.224
-160.403
-162.698
-172.674
179.587
173.225
167.248
161.143
155.016
148.942
142.125
130.272
122.162
113.451
100.173
84.617
69.227
53.796
40.2
31.813
23.38
11.48
-0.579
-13.818
-28.557
-25.318
34.68
28.92
26.654
24.794
24.002
20.776
19.732
18.78
18.329
16.343
14.633
13.156
11.896
10.78
9.656
8.55
7.548
5.404
3.238
1.055
-0.705
-3.251
-6.332
-10.138
-12.417
-16.055
-20.865
-28.925
-41.317
-28.286
-24.254
34.68
152.786
107.281
95.227
85.752
81.827
64.411
57.966
51.816
48.898
34.267
20.497
7.35
-4.959
-17.688
-30.521
-43.17
-55.893
-80.204
-102.483
-123.348
-145.751
-170.507
165.37
151.871
132.898
116.123
103.357
85.718
-143.263
-139.464
-152.264
152.786
-47.737
-37.408
-35.752
-34.427
-33.793
-31.307
-30.494
-29.76
-29.413
-27.955
-26.738
-25.665
-24.685
-23.859
-23.2
-22.633
-22.01
-21.138
-20.538
-19.722
-18.579
-18.185
-17.868
-18.239
-16.923
-16.237
-15.662
-15.097
-15.974
-16.249
-16.13
-47.737
91.863
58.237
55.654
54.436
54.206
51.726
50.16
48.458
47.834
42.754
37.613
32.748
27.439
21.999
16.433
11
5.398
-5.826
-15.36
-23.213
-35.202
-49.114
-64.111
-71.411
-83.447
-95.104
-105.573
-123.669
-133.494
-148.305
-161.015
91.863
-4.011
-9.104
-10.055
-10.498
-10.523
-10.416
-10.335
-10.19
-10.067
-9.537
-8.876
-8.157
-7.477
-7.005
-6.443
-5.941
-5.508
-4.575
-3.749
-3.697
-2.821
-2.62
-2.273
-3.688
-2.495
-2.974
-3.854
-3.569
-3.394
-2.439
-2.919
-4.011
-28.89
-52.056
-57.82
-62.723
-63.981
-74.85
-80.854
-86.86
-89.923
-104.635
-118.233
-130.639
-143.5
-155.432
-167.299
-178.746
169.605
148.209
131.73
119.517
101.483
75.099
51.688
41.604
39.518
25.468
8.667
-9.967
-14.401
-20.145
-18.344
-28.89
RFinput
Reference Plane
[1]
[NU]
[8]
[NU]
[2]
[RFinput]
[7]
[RFoutput]
[3]
[Vbias2]
Bias
[4]
[NU]
Figure 25. RFinput and RFoutput Reference Plane
10
[6]
[PwrDwn]
[5]
[Vbias1]
RFoutput
Reference Plane
Typical Noise Parameters, Vdd = 4.8 V, Idd = 84 mA
Freq
GHz
Fmin
dB
opt
Mag.
opt
Ang.
1.9
0.656
0.193
2
0.664
0.206
2.2
0.678
2.5
2.7
Part Number Ordering Information
Part Number
No. of Devices
Container
Rn/50
MGA-638P8-BLKG
100
Antistatic Bag
152.8
0.044
MGA-638P8-TR1G
3000
7 inch Reel
156.4
0.040
0.234
163.5
0.035
0.704
0.274
174.2
0.034
0.736
0.301
181.4
0.036
3.3
0.958
0.383
202.8
0.045
3.5
1.12
0.41
209.9
0.045
Notes:
1. The Fmin values are based on noise figure measurements at 100
different impedances using Focus source pull test system. From
these measurements a true Fmin is calculated.
2. Scattering and noise parameters are measured on coplanar waveguide
made on 0.010 inch thick ROGER 4350. The input reference plane is
at the end of the RFinput pin and the output reference plane is at the
end of the RFoutput pin as shown in Figure 25.
DFN2X2 Package Dimensions
PIN 1 DOT
BY MARKING
2.00±0.10
0.20 Ref.
2.00±0.10
38X
0.0–0.05
0.75±0.10
TOP VIEW
SIDE VIEW
0.60±0.05
Exp. DAP
PIN #1 IDENTIFICATION
R0.10
0.35±0.05
1.20±0.05
Exp. DAP
0.50 Bsc
0.25±0.05
BOTTOM VIEW
11
1.50
Ref.
Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating.
3. Dimensions are exclusive of mold ash and metal burr.
Recommended PCB Land Pattern and Stencil Design
2.20
2.16
1.75
0.563x
0.502x
1.75
0.00
0.80
0.506x
1.50
0.258x
0.21
0.228x
0.1702x
0.458x
0.05
(all SM gaps)
0.303x
0.408x
R0.154x
PCB Land Pattern
Stencil Design
1.75
0.563x
0.506x
0.50
Metal surface
0.21
1.50
Soldermask Open
R0.154x
0.172x
Combines PCB & Stencil Design
All Dimension are in millimeters
Notes:
1. Stencil thickness is 0.1 mm (4 mils).
2. All dimensions are in mm unless otherwise specified.
12
1.72
0.482x
1.50
1.20
0.50
0.506x
Device Orientation
REEL
4 mm
8 mm
38X
CARRIER
TAPE
USER FEED
DIRECTION
38X
COVER TAPE
Tape Dimensions
D
P
PO
P2
E
F
W
+
+
D1
t1
Tt
KO
10° MAX
AO
DESCRIPTION
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
PERFORATION DIAMETER
PITCH
POSITION
CARRIER TAPE WIDTH
CAVITY
COVER TAPE
DISTANCE
13
10° MAX
BO
THICKNESS
WIDTH
TAPE THICKNESS
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
SYMBOL
A0
B0
K0
P
D1
D
P0
E
W
t1
C
Tt
F
SIZE (mm)
2.30 ± 0.05
2.30 ± 0.05
1.00 ± 0.05
4.00 ± 0.10
1.00 + 0.25
1.50 ± 0.10
4.00 ± 0.10
1.75 ± 0.10
8.00 ± 0.30
8.00 ± 0.10
0.254 ± 0.02
5.4 ± 0.10
0.062 ± 0.001
3.50 ± 0.05
SIZE (INCHES)
0.091 ± 0.004
0.091 ± 0.004
0.039 ± 0.002
0.157 ± 0.004
0.039 + 0.002
0.060 ± 0.004
0.157 ± 0.004
0.069 ± 0.004
0.315 ± 0.012
0.315 ± 0.004
0.010 ± 0.0008
0.205 ± 0.004
0.0025 ± 0.0004
0.138 ± 0.002
P2
2.00 ± 0.05
0.079 ± 0.002
38X
38X
Reel Dimensions – 7 inch
6.25mm EMBOSSED LETTERS
LETTERING THICKNESS: 1.6mm
SLOT HOLE "a"
SEE DETAIL "X"
Ø178.0±0.5
SLOT HOLE "b"
FRONT
BACK
6
PS
SLOT HOLE(2x)
180° APART.
6
PS
RECYCLE LOGO
SLOT HOLE "a": 3.0±0.5mm(1x)
SLOT HOLE "b": 2.5±0.5mm(1x)
FRONT VIEW
12.4
45°
1.5 MIN.
+1.5*
-0.0
+0.5
Ø13.0 -0.2
Ø20.2 MIN.
°
R10.65
120
65°
R5.2
45°
EMBOSSED RIBS
RAISED: 0.25mm, WIDTH: 1.25mm
Ø178.0±0.5
Ø51.2±0.3
BACK VIEW
For product information and a complete list of distributors, please go to our web site:
DETAIL "X"
18.0*
MAX.
SEE DETAIL "Y"
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-2993EN - September 29, 2011
3.5
DETAIL "Y"
(Slot Hole)
1.0
Ø55.0±0.5
BACK
Ø178.0±0.5
FRONT