Maxim MAX5883 3.3v, 12-bit, 200msps high dynamic performance dac with cmos input Datasheet

19-2824; Rev 1; 12/03
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
♦ Single 3.3V Supply Operation
♦ Excellent SFDR and IMD Performance
SFDR = 77dBc at fOUT = 10MHz (to Nyquist)
IMD = -86dBc at fOUT = 10MHz
ACLR = 71dB at fOUT = 30.72MHz
♦ 2mA to 20mA Full-Scale Output Current
♦ CMOS-Compatible Digital and Clock Inputs
♦ On-Chip 1.2V Bandgap Reference
♦ Low Power Dissipation
♦ 48-Pin QFN-EP Package
Ordering Information
PART
MAX5883EGM
B5
B6
B7
37
38
39
40
DGND
B3
B4
41
42
43
B1
B2
DVDD
44
45
46
N.C.
N.C.
B0
36
2
35
3
34
4
33
5
32
CLKN
CLKGND
VCLK
PD
7
9
28
10
27
AVDD
11
26
AGND
12
25
31
6
30
B11
DGND
DVDD
SEL0
N.C.
N.C.
N.C.
N.C.
N.C.
24
23
22
21
B8
B9
B10
AGND
AVDD
AGND
20
29
AGND
AVDD
19
18
16
8
17
MAX5883
15
Instrumentation
1
DACREF
N.C.
AGND
IOUTN
IOUTP
Automated Test Equipment (ATE)
N.C.
N.C.
XOR
VCLK
CLKGND
CLKP
14
Digital Signal Synthesis
47
TOP VIEW
48
Pin Configuration
13
Communications: LMDS, MMDS, Point-to-Point
Microwave
PIN-PACKAGE
48 QFN-EP*
*EP = Exposed paddle.
Applications
Base Stations: Single/Multicarrier UMTS,
CDMA
TEMP RANGE
-40°C to +85°C
REFIO
The digital and clock inputs of the MAX5883 are
designed for CMOS-compatible voltage levels. The
MAX5883 is available in a 48-pin QFN package with an
exposed paddle (EP) and is specified for the extended
industrial temperature range (-40°C to +85°C).
Refer to the MAX5884 and MAX5885 data sheets for
pin-compatible 14- and 16-bit versions of the MAX5883.
For LVDS high-speed versions, refer to the MAX5886,
MAX5887, and MAX5888 data sheets.
♦ 200Msps Output Update Rate
FSADJ
The MAX5883 utilizes a current-steering architecture,
which supports a full-scale output current range of 2mA
to 20mA, and allows a differential output voltage swing
between 0.1VP-P and 1VP-P.
The MAX5883 features an integrated 1.2V bandgap
reference and control amplifier to ensure high accuracy
and low noise performance. Additionally, a separate
reference input pin enables the user to apply an external reference source for optimum flexibility and to
improve gain accuracy.
Features
QFN
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX5883
General Description
The MAX5883 is an advanced, 12-bit, 200Msps digitalto-analog converter (DAC) designed to meet the
demanding performance requirements of signal synthesis applications found in wireless base stations and
other communications applications. Operating from a
single 3.3V supply, this DAC offers exceptional dynamic
performance such as 77dBc spurious-free dynamic
range (SFDR) at f OUT = 10MHz. The DAC supports
update rates of 200Msps at a power dissipation of less
than 200mW.
MAX5883
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
ABSOLUTE MAXIMUM RATINGS
Continuous Power Dissipation (TA = +70°C)
48-Pin QFN (derate 27mW/°C above +70°C)............2162.2mW
Thermal Resistance (θJA) ..............................................+37°C/W
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
AVDD, DVDD, VCLK to AGND................................-0.3V to +3.9V
AVDD, DVDD, VCLK to DGND ...............................-0.3V to +3.9V
AVDD, DVDD, VCLK to CLKGND ...........................-0.3V to +3.9V
AGND, CLKGND to DGND....................................-0.3V to +0.3V
DACREF, REFIO, FSADJ to AGND.............-0.3V to AVDD + 0.3V
IOUTP, IOUTN to AGND................................-1V to AVDD + 0.3V
CLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3V
B0–B11, SEL0, PD, XOR to DGND.............-0.3V to DVDD + 0.3V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, fCLK =
200Msps, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and
characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
12
Bits
Integral Nonlinearity
INL
Measured differentially
±0.3
LSB
Differential Nonlinearity
DNL
Measured differentially
±0.2
LSB
Offset Error
OS
-0.025
Full-Scale Gain Error
GEFS
Gain Drift
Full-Scale Output Current
±0.003
+0.025
±50
Offset Drift
IOUT
External reference, TA ≥ +25°C
-3.5
+1.3
Internal reference
±100
External reference
±50
(Note 1)
2
%FS
ppm/°C
%FS
ppm/°C
20
mA
Min Output Voltage
Single ended
-0.5
Max Output Voltage
Single ended
1.1
V
V
Output Resistance
ROUT
1
MΩ
Output Capacitance
COUT
5
pF
DYNAMIC PERFORMANCE
Output Update Rate
fCLK
Noise Spectral Density
Spurious-Free Dynamic Range to
Nyquist
2
SFDR
1
200
fCLK = 100MHz
fOUT = 16MHz, -12dB FS
-150
fCLK = 200MHz
fOUT = 80MHz, -12dB FS
-148
fCLK = 100MHz
fOUT = 1MHz, 0dB FS
87
fOUT = 1MHz, -6dB FS
81
fOUT = 1MHz, -12dB FS
80
_______________________________________________________________________________________
Msps
dB FS/
Hz
dBc
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
(AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, fCLK =
200Msps, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and
characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
fCLK = 100MHz
Spurious-Free Dynamic Range to
Nyquist
SFDR
fCLK = 200MHz
fCLK = 100MHz
Two-Tone IMD
TTIMD
fCLK = 200MHz
MIN
TYP
fOUT = 10MHz, -12dB
77
fOUT = 30MHz, -12dB
73
fOUT = 10MHz, -12dB
70
fOUT > 16MHz, -12dB FS,
TA = +25°C
68
fOUT = 30MHz, -12dB
66
68
UNITS
dBc
74
fOUT = 50MHz, -12dB
fOUT1 = 9MHz, -6dB
MAX
-86
fOUT2 = 10MHz, -6dB
dBc
fOUT1 = 29MHz, -6dB
-74
fOUT2 = 30MHz, -6dB
Four-Tone IMD, 1MHz Frequency
Spacing
FTIMD
fCLK = 150MHz
fOUT = 32MHz, -12dB FS
-82
dBc
Adjacent Channel Leakage
Power Ratio, 4.1MHz Bandwidth,
W-CDMA Model
ACLR
fCLK =
184.32MHz
fOUT = 30.72MHz
71
dB
450
MHz
Output Bandwidth
BW-1dB
(Note 2)
REFERENCE
Internal Reference Voltage Range
Reference Input Compliance
Range
VREFIO
1.1
VREFIOCR
0.125
1.22
1.34
V
1.25
V
Reference Input Resistance
RREFIO
10
kΩ
Reference Voltage Drift
TCOREF
±50
ppm/°C
ANALOG OUTPUT TIMING
Output Fall Time
tFALL
90% to 10% (Note 3)
375
ps
Output Rise Time
tRISE
10% to 90% (Note 3)
375
ps
Output settles to 0.025% FS (Note 3)
11
ns
(Note 3)
1.8
ns
1
pV-s
Output Voltage Settling Time
Output Propagation Delay
tSETTLE
tPD
Glitch Energy
Output Noise
NOUT
IOUT = 2mA
30
IOUT = 20mA
30
pA/√Hz
TIMING CHARACTERISTICS
Data to Clock Setup Time
tSETUP
Referenced to rising edge of clock (Note 4)
0.4
ns
Data to Clock Hold Time
tHOLD
Referenced to rising edge of clock (Note 4)
1.25
ns
_______________________________________________________________________________________
3
MAX5883
ELECTRICAL CHARACTERISTICS (continued)
MAX5883
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, fCLK =
200Msps, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and
characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Data Latency
3.5
Clock
cycles
Minimum Clock Pulse Width High
tCH
CLKP, CLKN
Minimum Clock Pulse Width Low
tCL
CLKP, CLKN
CMOS LOGIC INPUTS (B0–B11, PD, SEL0, XOR)
1.5
1.5
ns
ns
Input Logic High
VIH
Input Logic Low
VIL
Input Leakage Current
IIN
Input Capacitance
CIN
0.7 x
DVDD
V
0.3 x
DVDD
-15
+15
5
V
µA
pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave
≥1.5
Square wave
≥0.5
(Note 5)
>100
V/µs
VCOM
1.5
±20%
V
Input Resistance
RCLK
5
kΩ
Input Capacitance
CCLK
5
pF
Differential Input Voltage Swing
Differential Input Slew Rate
Common-Mode Voltage Range
VCLK
SRCLK
VP-P
POWER SUPPLIES
Analog Supply Voltage Range
AVDD
3.135
3.3
3.465
V
Digital Supply Voltage Range
DVDD
3.135
3.3
3.465
V
Clock Supply Voltage Range
VCLK
3.135
3.3
3.465
V
Analog Supply Current
IAVDD
Digital Supply Current
IDVDD
Clock Supply Current
IVCLK
Power Dissipation
PDISS
Power-Supply Rejection Ratio
PSRR
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
4
fCLK = 100Msps, fOUT = 1MHz
27
Power-down
0.3
fCLK = 100Msps, fOUT = 1MHz
7.5
mA
Power-down
10
µA
fCLK = 100Msps, fOUT = 1MHz
5.5
mA
Power-down
10
µA
fCLK = 100Msps, fOUT = 1MHz
132
Power-down
AVDD = VCLK = DVDD = 3.3V ±5% (Note 5)
mA
mW
1
-0.1
+0.1
Nominal full-scale current IOUT = 32 ✕ IREF.
This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5883.
Parameter measured single ended into a 50Ω termination resistor.
Parameter guaranteed by design.
Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
_______________________________________________________________________________________
%FS/V
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
-12dB FS
80
100
-12dB FS
80
90
70
-6dB FS
50
40
SFDR (dBc)
60
-6dB FS
60
0dB FS
50
40
30
20
20
10
10
10
0
0
15
25
20
0dB FS
40
20
10
-12dB FS
50
30
0
0
10
20
30
40
0
50
15
30
45
60
75
fOUT (MHz)
fOUT (MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 200MHz)
2-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, fCLK = 100MHz)
2-TONE INTERMODULATION DISTORTION
(fCLK = 100MHz)
-12dB FS
-90
2-TONE IMD (dBc)
60
50
-6dB FS
0dB FS
40
30
20
-80
-70
-6dB FS
-60
fT1 = 28.9429MHz
fT2 = 29.8706MHz
AOUT = -6dB FS
BW = 12MHz
-10
-20
OUTPUT POWER (dBm)
-12dB FS
70
0
MAX5883 toc05
MAX5883 toc04
90
80
-100
fT1
-30
MAX5883 toc06
fOUT (MHz)
100
fT2
-40
-50
-60
-70
2 x fT1 - fT2
2 x fT2 - fT1
-80
-50
-90
10
-100
-40
0
10 20 30 40 50 60 70 80 90 100
0
10
20
30
40
24 25 26 27 28 29 30 31 32 33 34 35 36
50
fOUT (MHz)
fOUT(MHz)
fOUT (MHz)
2-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, fCLK = 200MHz)
4-TONE POWER RATIO PLOT
(fCLK = 150MHz, fCENTER = 31.9885MHz)
SFDR vs. OUTPUT FREQUENCY
(fCLK = 200MHz, AOUT = -6dB FS)
-12dB FS
-70
-6dB FS
-60
-20
fT1 fT2 fT3
IOUT = 20mA
80
fT4
-30
-40
-50
-60
60
IOUT = 5mA
IOUT = 10mA
40
-70
20
-80
-50
100
SFDR (dBc)
-80
-10
OUTPUT POWER (dBm)
-90
AOUT = -12dB FS fT1 = 29.9744MHz fT3 = 32.9773MHz
BW = 12MHz
fT2 = 30.9998MHz fT4 = 33.8196MHz
MAX5883 toc08
0
MAX5883 toc07
-100
MAX5883 toc09
0
2-TONE IMD (dBc)
60
30
5
-6dB FS
80
70
0dB FS
0
SFDR (dBc)
90
SFDR (dBc)
SFDR (dBc)
70
100
MAX5883 toc02
90
MAX5883 toc01
100
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 150MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 100MHz)
MAX5883 toc03
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 50MHz)
-90
0
-100
-40
0
10
20
30
40
50
fOUT (MHz)
60
70
80
26
28
30
32
fOUT (MHz)
34
36
38
0
10 20 30 40 50 60 70 80 90 100
fOUT (MHz)
_______________________________________________________________________________________
5
MAX5883
Typical Operating Characteristics
(AVDD = DVDD = VCLK = 3.3V, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(AVDD = DVDD = VCLK = 3.3V, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
TA = +25°C
80
0.3
0.2
70
0.15
MAX5883 toc11
90
MAX5883 toc10
100
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
0.10
TA = -40°C
0.05
DNL (LSB)
TA = +85°C
50
INL (LSB)
0.1
60
0
40
30
20
MAX5883 toc12
SFDR vs. fOUT AND TEMPERATURE
(fCLK = 200MHz, AOUT = -6dB FS, IFS = 20mA)
SFDR (dBc)
0
-0.1
-0.05
-0.2
-0.10
10
-0.3
0
-0.15
0
10 20 30 40 50 60 70 80 90 100
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL INPUT CODE
fOUT (MHz)
DIGITAL INPUT CODE
POWER DISSIPATION vs. CLOCK FREQUENCY
(fOUT = 10MHz, AOUT = 0dB FS, IOUT = 20mA)
160
MAX5883 toc13
180
POWER DISSIPATION vs. SUPPLY VOLTAGE
(fCLK = 100MHz, fOUT = 10MHz, IFS = 20mA)
POWER DISSIPATION (mW)
170
160
150
140
130
120
MAX5883 toc14
0
POWER DISSIPATION (mW)
MAX5883
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
152
EXTERNAL REFERENCE
144
136
INTERNAL REFERENCE
128
110
100
25
50
75
100
125
fCLK (MHz)
6
150
175
200
120
3.135
3.190
3.245
3.300
3.355
3.410
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
3.465
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
PIN
NAME
1, 2, 16,
25–29, 47,
48
FUNCTION
N.C.
No connection. Do not connect to these pins. Do not tie these pins together.
3
XOR
XOR Input Pin.
XOR = 1 inverts the digital input data.
XOR = 0 leaves the digital input data unchanged.
XOR has an internal pulldown resistor and may be left unconnected if not used.
4, 9
VCLK
Clock Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest CLKGND.
5, 8
CLKGND
Clock Ground
6
CLKP
Converter Clock Input. Positive input terminal for the converter clock.
7
CLKN
Complementary Converter Clock Input. Negative input terminal for the converter clock.
10
PD
11, 21, 23
AVDD
Analog Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest AGND.
12, 17, 20,
22, 24, EP
AGND
Analog Ground. Exposed paddle (EP) must be connected to AGND.
13
REFIO
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 0.1µF
capacitor to AGND. Can be driven with an external reference source.
14
FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For 20mA full-scale
output current, connect a 2kΩ resistor between FSADJ and DACREF.
15
DACREF
Return Path for the Current Set Resistor. For 20mA full-scale output current, connect a 2kΩ resistor
between FSADJ and DACREF.
18
IOUTN
Complementary DAC Output. Negative terminal for differential current output. The full-scale output
current range can be set from 2mA to 20mA.
19
IOUTP
DAC Output. Positive terminal for differential current output. The full-scale output current range can
be set from 2mA to 20mA.
30
SEL0
Mode Select Input SEL0. This pin has an internal pulldown resistor; it can be left open to disable the
segment-shuffling function (see the Segment Shuffling section).
31, 43
DVDD
Digital Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest DGND.
32, 42
DGND
33
B11
Data Bit 11 (MSB)
34
B10
Data Bit 10
35
B9
Data Bit 9
36
B8
Data Bit 8
37
B7
Data Bit 7
Power-Down Input. PD pulled high enables the DAC’s power-down mode. PD pulled low allows for
normal operation of the DAC.
Digital Ground
_______________________________________________________________________________________
7
MAX5883
Pin Description
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
MAX5883
Pin Description (continued)
PIN
NAME
FUNCTION
38
B6
Data Bit 6
39
B5
Data Bit 5
40
B4
Data Bit 4
41
B3
Data Bit 3
44
B2
Data Bit 2
45
B1
Data Bit 1
46
B0
Data Bit 0 (LSB)
DVDD
DGND
SEL0
PD
FUNCTION
SELECTION
BLOCK
1.2V
REFERENCE
AGND
AVDD
MAX5883
REFIO
FSADJ
CLKN
CLKP
CURRENT-STEERING
DAC
SEGMENT SHUFFLING/LATCH
DECODER
CMOS RECEIVER/INPUT LATCH
12
DIGITAL INPUTS B0 THROUGH B11
Figure 1. Simplified MAX5883 Block Diagram
8
_______________________________________________________________________________________
IOUTP
IOUTN
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
Architecture
The MAX5883 is a high-performance, 12-bit, currentsteering DAC (Figure 1) capable of operating with
clock speeds up to 200MHz. The converter consists of
separate input and DAC registers, followed by a current-steering circuit. This circuit is capable of generating differential full-scale currents in the range of 2mA to
20mA. An internal current-switching network in combination with external 50Ω termination resistors convert
the differential output currents into a differential output
voltage with a peak-to-peak output voltage range of
0.1V to 1V. An integrated 1.2V bandgap reference,
control amplifier, and user-selectable external resistor
determine the data converter’s full-scale output range.
RSET is the reference resistor, which determines the
amplifier’s output current for the DAC. See Table 1 for a
matrix of different IOUT and RSET selections.
Analog Outputs (IOUTP, IOUTN)
The MAX5883 outputs two complementary currents
(IOUTP, IOUTN) that can be operated in a singleended or differential configuration. A load resistor can
convert these two output currents into complementary
single-ended output voltages. The differential voltage
existing between IOUTP and IOUTN can also be converted to a single-ended voltage using a transformer or
a differential amplifier configuration. If no transformer is
used, the output should have a 50Ω termination to the
analog ground and a 50Ω resistor between the outputs.
Reference Architecture and Operation
The MAX5883 supports operation with the on-chip 1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, lowimpedance reference source, and as the output if the
DAC is operating with the internal reference. For stable
operation with the internal reference, REFIO should be
decoupled to AGND with a 0.1µF capacitor. Due to its
limited output drive capability, REFIO must be buffered
with an external amplifier, if heavier loading is required.
The MAX5883’s reference circuit (Figure 2) employs a
control amplifier, designed to regulate the full-scale
current IOUT for the differential current outputs of the
DAC. Configured as a voltage-to-current amplifier, the
output current can be calculated as follows:
AVDD
1.2V
REFERENCE
10kΩ
REFIO
0.1µF
IOUTP
FSADJ
CURRENT-STEERING
DAC
IREF
RSET
IOUT = 32 ✕ IREFIO - 1 LSB
IOUT = 32 ✕ IREFIO - (IOUT / 212)
where IREFIO is the reference output current (IREFIO =
VREFIO/RSET) and IOUT is the full-scale output current
of the DAC. Located between FSADJ and DACREF,
IOUTN
DACREF
IREF = VREFIO/RSET
Figure 2. Reference Architecture, Internal Reference
Configuration
Table 1. IOUT and RSET Selection Matrix Based on a Typical 1.200V Reference Voltage
FULL-SCALE CURRENT
IOUT (mA)
REFERENCE CURRENT
IREF (µA)
RSET (kΩ)
CALCULATED
1% EIA STD
OUTPUT VOLTAGE
VIOUTP/N* (mVP-P)
2
62.5
19.2
19.1
100
5
156.26
7.68
7.5
250
10
312.5
3.84
3.83
500
15
468.75
2.56
2.55
750
20
625
1.92
1.91
1000
*Terminated into a 50Ω load.
_______________________________________________________________________________________
9
MAX5883
Detailed Description
MAX5883
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
Although not recommended because of additional
noise pickup from the ground plane, for single-ended
operation IOUTP should be selected as the output, with
IOUTN connected to AGND. Note that a single-ended
output configuration has a higher 2nd-order harmonic
distortion at high output frequencies than a differential
output configuration.
Figure 3 displays a simplified diagram of the
MAX5883’s internal output structure.
Clock Inputs (CLKP, CLKN)
The MAX5883 features a flexible differential clock input
(CLKP, CLKN) operating from separate supplies
(VCLK, CLKGND) to achieve the best possible jitter
performance. The two clock inputs can be driven from
a single-ended or a differential clock source. For singleended operation, CLKP should be driven by a logic
source, while CLKN should be bypassed to AGND with
a 0.1µF capacitor.
The CLKP and CLKN pins are internally biased to
VCLK/2. This allows the user to AC-couple clock
sources directly to the device without external resistors
to define the DC level. The input resistance of CLKP and
CLKN is >5kΩ.
See Figure 4 for a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP 8662A signal generator) and a wideband
transformer. These inputs can also be driven from a
CMOS-compatible clock source; however, it is recommended to use sinewave or AC-coupled ECL drive for
best performance.
Data Timing Relationship
Figure 5 shows the timing relationship between differential, digital CMOS data, clock, and output signals.
The MAX5883 features a 1.25ns hold, a 0.4ns setup,
AVDD
and a 1.8ns propagation delay time. There is a 3.5
clock-cycle latency between CLKP/CLKN transitioning
high/low and IOUTP/IOUTN.
CMOS-Compatible Digital Inputs (B0–B11)
The MAX5883 features single-ended, CMOS-compatible
receivers on the bus input interface. These CMOS inputs
(B0–B11) allow for a voltage swing of 3.3V.
Segment Shuffling (SEL0)
Segment shuffling can improve the SFDR of the
MAX5883 at higher output frequencies and amplitudes.
Note that an improvement in SFDR can only be
achieved at the cost of a slight increase in the DAC’s
noise floor.
Pin SEL0 controls the segment-shuffling function. If
SEL0 is pulled low, the segment-shuffling function of
the DAC is disabled. SEL0 can also be left open,
because an internal pulldown resistor helps to deactivate the segment-shuffling feature. To activate the
MAX5883 segment-shuffling function, SEL0 must be
pulled high.
XOR Function (XOR)
The MAX5883 is equipped with a single-ended, CMOScompatible XOR input, which may be left open (XOR
provides an internal pulldown resistor) or pulled down
to DGND, if not used. Input data is XORed with the bit
applied to the XOR pin. Pulling XOR high inverts the
input data. Pulling XOR low leaves the input data noninverted. By applying a pseudorandom bit stream to XOR
and applying inverted data when XOR is high, the bit
transitions of the digital input data can be decorrelated
from the DAC output. This allows the user to troubleshoot possible spurious or harmonic distortion
degradation due to digital feedthrough on the PC
board.
0.1µF
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED TO
DIFFERENTIAL CONVERSION.
CURRENT
SOURCES
CLKP
25Ω
CURRENT
SWITCHES
TO
DAC
1:1
SINGLE-ENDED
CLOCK SOURCE
(e.g., HP 8662A)
25Ω
0.1µF
IOUT
IOUT
IOUTN
Figure 3. Simplified Analog Output Structure
10
IOUTP
CLKGND
Figure 4. Differential Clock Signal Generation
______________________________________________________________________________________
CLKN
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
B0 TO B15
OUTPUT DATA IS UPDATED ON
THE FALLING EDGE OF CLKP
N+1
N
N-1
tSETUP
MAX5883
DIGITAL DATA IS LATCHED ON
THE RISING EDGE OF CLKP
tHOLD
N+2
tCH
tCL
CLKP
CLKN
tPD
IOUT
N-5
N-4
N-3
N-2
N-1
Figure 5. Detailed Timing Relationship
Power-Down Operation (PD)
The MAX5883 also features an active-high power-down
mode, which allows the user to cut the DAC’s current
consumption. A single pin (PD) is used to control the
power-down mode (PD = 1) or reactivate the DAC (PD
= 0) after power-down.
Enabling the power-down mode of this 12-bit CMOS
DAC allows the overall power consumption to be
reduced to less than 1mW. The MAX5883 requires
10ms to wake up from power-down and enter a fully
operational state.
Applications Information
Differential Coupling Using a
Wideband RF Transformer
The differential voltage existing between IOUTP and
IOUTN can also be converted to a single-ended voltage using a transformer (Figure 6) or a differential
amplifier configuration. Using a differential transformercoupled output, in which the output power is limited to
0dBm, can optimize the dynamic performance.
However, make sure to pay close attention to the transformer core saturation characteristics when selecting a
transformer for the MAX5883. Transformer core saturation can introduce strong 2nd-harmonic distortion,
especially at low output frequencies and high signal
amplitudes. It is also recommended to center tap the
transformer to ground. If no transformer is used, each
DAC output should be terminated to ground with a 50Ω
resistor. Additionally, a 100Ω resistor should be placed
between the outputs.
If a single-ended unipolar output is desirable, IOUTP
should be selected as the output, with IOUTN grounded. However, driving the MAX5883 single ended is not
recommended since additional noise is added (from
the ground plane) in such configurations.
The distortion performance of the DAC depends on the
load impedance. The MAX5883 is optimized for a 50Ω
double termination. It can be used with a transformer
output as shown in Figure 7 or just one 50Ω resistor
from each output to ground and one 50Ω resistor
between the outputs. This produces a full-scale output
power of up to 0dBm, depending on the output current
setting. Higher termination impedance can be used at
the cost of degraded distortion performance and
increased output noise voltage.
Adjacent Channel Leakage Power Ratio
(ACLR) Testing for CDMA- and
W-CDMA-Based Base Station
Transceiver Systems (BTS)
The transmitter sections of BTS applications serving
CDMA and W-CDMA architectures must generate carriers with minimal coupling of carrier energy into the adjacent channels. A transmit mask (Tx mask) exists for this
application. The spread-spectrum modulation function
applied to the carrier frequency generates a spectral
response, which is uniform over a given bandwidth (up
to 4MHz) for a W-CDMA-modulated carrier.
______________________________________________________________________________________
11
MAX5883
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
AVDD
DVDD
VCLK
50Ω
T2, 1:1
VOUT, SINGLE ENDED
IOUTP
B0–B11
100Ω
MAX5883
IOUTN
12
T1, 1:1
AGND
DGND
WIDEBAND RF TRANSFORMER T2
PERFORMS THE DIFFERENTIAL TO
SINGLE-ENDED CONVERSION.
50Ω
CLKGND
Figure 6. Differential to Single-Ended Conversion Using a Wideband RF Transformer
AVDD
DVDD
VCLK
50Ω
OUTP
IOUTP
B0–B11
100Ω
MAX5883
IOUTN
12
AGND
DGND
CLKGND
OUTN
50Ω
Figure 7. MAX5883 Differential Output Configuration
A dominant specification is ACLR, a parameter which
reflects the ratio of the power in the desired carrier
band to the power in an adjacent carrier band. The
specification covers the first two adjacent bands, and is
measured on both sides of the desired carrier.
According to the transmit mask for CDMA and WCDMA architectures, the power ratio of the integrated
carrier channel energy to the integrated adjacent channel energy must be >45dB for the first adjacent carrier
slot (ACLR 1) and >50dB for the second adjacent carrier slot (ACLR 2). This specification applies to the output
of the entire transmitter signal chain. The requirement
for only the DAC block of the transmitter must be
tighter, with a typical margin of >15dB, requiring the
DAC’s ACLR 1 to be better than 60dB.
Adjacent channel leakage is caused by a single spreadspectrum carrier, which generates intermodulation (IM)
products between the frequency components located
within the carrier band. The energy at one end of the
carrier band generates IM products with the energy
from the opposite end of the carrier band. For singlecarrier W-CDMA modulation, these IMD products are
spread 3.84MHz over the adjacent sideband. Four contiguous W-CDMA carriers spread their IM products over
a bandwidth of 20MHz on either side of the 20MHz total
carrier bandwidth. In this four-carrier scenario, only the
energy in the first adjacent 3.84MHz sideband is considered for ACLR 1. To measure ACLR, drive the converter with a W-CDMA pattern. Make sure that the
signal is backed off by the peak-to-average ratio, such
that the DAC is not clipping the signal. ACLR can then
be measured with the ACLR measurement function built
into your spectrum analyzer.
Figure 8 shows the ACLR performance for a single
W-CDMA carrier (fCLK = 184.32MHz, fOUT = 30.72MHz)
applied to the MAX5883 (including measurement system
limitations*).
Figure 9 illustrates the ACLR test results for the
MAX5883 with a four-carrier W-CDMA signal at an output frequency of 30.72MHz and a sampling frequency
of 184.32MHz. Considerable care must be taken to
ensure accurate measurement of this parameter.
Grounding, Bypassing, and Power-Supply
Considerations
Grounding and power-supply decoupling can strongly
influence the performance of the MAX5883. Unwanted
digital crosstalk may couple through the input, reference, power supply, and ground connections, affecting
dynamic performance. Proper grounding and power-
*Note that due to their own IM effects and noise limitations, spectrum analyzers introduce ACLR errors, which can falsify the measurement. For a single-carrier ACLR measurement greater than 70dB, these measurement limitations are significant, becoming even more
restricting for multicarrier measurement. Before attempting an ACLR measurement, it is recommended consulting application notes provided by major spectrum analyzer manufacturers that provide useful tips on how to use their instruments for such tests.
12
______________________________________________________________________________________
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
-40
-20
fCLK = 184.32MHz
fCENTER = 30.72MHz
ACLR = 71dB
-50
-60
-70
-80
-90
-100
-30
ANALOG OUTPUT POWER (dBm)
ANALOG OUTPUT POWER (dBm)
-30
ACLR = 67dB
-40
-50
-60
-70
-80
-90
-100
-110
-110
-120
-120
3.5MHz/div
fCLK = 184.32MHz
fCENTER = 30.72MHz
MAX5883
-20
4MHz/div
Figure 8. ACLR for W-CDMA Modulation, Single Carrier
Figure 9. ACLR for W-CDMA Modulation, Four Carriers
supply decoupling guidelines for high-speed, high-frequency applications should be closely followed. This
reduces EMI and internal crosstalk that can significantly affect the dynamic performance of the MAX5883.
point they enter the PC board with tantalum or electrolytic capacitors. Ferrite beads with additional decoupling capacitors forming a pi network could also
improve performance.
The analog and digital power-supply inputs AV DD ,
VCLK, and DVDD of the MAX5883 allow a supply voltage range of 3.3V ±5%.
Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended. High-speed signals should run on lines directly
above the ground plane. Since the MAX5883 has separate analog and digital ground buses (AGND,
CLKGND, and DGND, respectively), the PC board
should also have separate analog and digital ground
sections with only one point connecting the two planes.
Digital signals should be run above the digital ground
plane and analog/clock signals above the analog/clock
ground plane. Digital signals should be kept as far
away from sensitive analog inputs, reference input
sense lines, common-mode input, and clock inputs as
practical. A symmetric design of clock input and analog output lines is recommended to minimize 2nd-order
harmonic distortion components and optimize the
DAC’s dynamic performance. Digital signal paths
should be kept short and run lengths matched to avoid
propagation delay and data skew mismatches.
The MAX5883 supports three separate power-supply
inputs for analog (AVDD), digital (DVDD), and clock
(VCLK) circuitry. Each AVDD, DVDD, and VCLK input
should at least be decoupled with a separate 0.1µF
capacitor as close to the pin as possible and their
opposite ends with the shortest possible connection to
the corresponding ground plane (Figure 10). All three
power-supply voltages should also be decoupled at the
The MAX5883 is packaged in a 48-pin QFN-EP
(package code: G4877-1), providing greater design
flexibility, increased thermal efficiency**, and optimized
AC performance of the DAC. The exposed pad (EP)
enables the user to implement grounding techniques,
which are necessary to ensure highest performance
operation. The EP must be soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PC board
side of the package. This allows a solid attachment of
the package to the PC board with standard infrared (IR)
flow soldering techniques. A specially created land pattern on the PC board, matching the size of the EP (5mm
✕ 5mm), ensures the proper attachment and grounding
of the DAC. Designing vias*** into the land area and
implementing large ground planes in the PC board
design allow for highest performance operation of the
DAC. An array of at least 3 ✕ 3 vias (≤0.3mm diameter
per via hole and 1.2mm pitch between via holes) is recommended for this 48-pin QFN-EP package.
**Thermal efficiency is not the key factor, since the MAX5883 features low-power operation. The exposed pad is the key element to
ensure a solid ground connection between the DAC and the PC board’s analog ground layer.
***Vias connect the land pattern to internal or external copper planes. It is important to connect as many vias as possible to the analog
ground plane to minimize inductance.
______________________________________________________________________________________
13
MAX5883
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For
a DAC, the deviations are measured at every individual
step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.
Glitch Energy
A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011...111 to 100...000. The glitch energy is found by integrating the voltage of the glitch at the
midscale transition over time. The glitch energy is usually specified in pV-s.
14
Dynamic Performance Parameter
Definitions
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog output (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical maximum SNR
can be derived from the DAC’s resolution (N bits):
SNRdB = 6.02dB ✕ N + 1.76dB
However, noise sources such as thermal noise, reference noise, clock jitter, etc., affect the ideal reading;
therefore, SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four
harmonics, and the DC offset.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal components) to the RMS
value of their next-largest distortion component. SFDR
is usually measured in dBc and with respect to the carrier frequency amplitude or in dB FS with respect to the
DAC’s full-scale range. Depending on its test condition,
SFDR is observed within a predefined window or
to Nyquist.
Two-/Four-Tone Intermodulation
Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc (or dB FS)
of either input tone to the worst 3rd-order (or higher) IMD
products. Note that 2nd-order IMD products usually fall at
frequencies that can be easily removed by digital filtering;
therefore, they are not as critical as 3rd-order IMDs. The
two-tone IMD performance of the MAX5883 was tested
with the two individual input tone levels set to at least
-6dB FS and the four-tone performance was tested at an
output frequency of 32MHz and amplitude of -12dB FS.
______________________________________________________________________________________
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
Commonly used in combination with W-CDMA, ACLR
reflects the leakage power ratio in dB between the
measured power within a channel relative to its adjacent channel. ACLR provides a quantifiable method of
determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited
RF signal passes through a nonlinear device.
Chip Information
TRANSISTOR COUNT: 10,721
PROCESS: CMOS
BYPASSING—DAC LEVEL
BYPASSING—BOARD LEVEL
AVCC
AVDD
VCLK
FERRITE BEAD
1µF
0.1µF
0.1µF
10µF
47µF
ANALOG POWER-SUPPLY
SOURCE
47µF
DIGITAL POWER-SUPPLY
SOURCE
47µF
CLOCK POWER-SUPPLY
SOURCE
CLKGND
AGND
DVCC
OUTP
B0–B11
FERRITE BEAD
MAX5883
1µF
12
10µF
OUTN
0.1µF
VCLK
FERRITE BEAD
DGND
1µF
10µF
DVDD
Figure 10. Recommended Power-Supply Decoupling and Bypassing Circuitry
______________________________________________________________________________________
15
MAX5883
Adjacent Channel Leakage
Power Ratio (ACLR)
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
32, 44, 48L QFN.EPS
MAX5883
3.3V, 12-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
PACKAGE OUTLINE
32,44,48L QFN, 7x7x0.90 MM
21-0092
H
1
2
U
PACKAGE OUTLINE,
32,44,48L QFN, 7x7x0.90 MM
21-0092
H
2
2
MAX5883 Package Code: G4877-1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.