Burr-Brown OPA678AU Wideband switched-input operational amplifier Datasheet

®
OPA678
OPA
678
OPA
678
Wideband Switched-Input
OPERATIONAL AMPLIFIER
FEATURES
APPLICATIONS
● FAST SETTLING: 11ns (1%)
● VIDEO AMPLIFICATION AND SWITCHING
● WIDE BANDWIDTH: 200MHz
● FAST 2-INPUT MULTIPLEXER
● TWO LOGIC SELECTABLE INPUTS
● PULSE/RF AMPLIFIERS
● LOW OFFSET VOLTAGE: ±380µV
● PROGRAMMABLE-GAIN AMPLIFIER
● FAST INPUT SWITCHING: 4ns
● ACTIVE FILTERS
● ACCEPTS TTL/ECL SWITCHING SIGNALS
● SYNCHRONOUS DEMODULATOR
● UNITY GAIN STABLE
● LOW COST REPLACEMENT FOR OPA675/676
● 16-PIN DIP AND SO-16 PACKAGES
DESCRIPTION
The OPA678 is a wideband monolithic operational
amplifier with two independent differential inputs.
Either input can be selected by an external TTL or
ECL logic signal. The amplifier is externally compensated and features a very fast input selection speed, 4ns
for either ECL or TTL. This amplifier features fully
symmetrical differential inputs due to its “classical”
operational amplifier circuit architecture. Unlike “current-feedback” amplifier designs, the OPA678 may be
used in all op amp applications requiring high speed
and precision.
Low distortion and crosstalk make this amplifier suitable for RF and video applications.
The OPA678 is available in plastic DIP and SO-16
packages.
–
Input A
A
+
Enable
A
A/B Channel
Select Input
(TTL or ECL)
Output
Enable
B
–
B
Input B
Compensation
+
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
©
1992 Burr-Brown Corporation
PDS-1136E
1
OPA678
Printed in U.S.A. March, 1998
SPECIFICATIONS
ELECTRICAL
At VCC = ±5VDC, RL = 150Ω, CCOMP = 5pF, and TA = +25°C, unless otherwise noted.
OPA678AP, AU
PARAMETER
CONDITIONS
INPUT NOISE(1)
Voltage: fO = 100Hz
fO = 1kHz
fO = 10kHz
fO = 100kHz
fB = 10Hz to 10MHz
Current: fO = 10Hz to 1MHz
OFFSET VOLTAGE(1)
Input Offset Voltage
Offset Voltage Drift
Supply Rejection
MIN
TYP
MAX
UNITS
RS = 0Ω
55
21
7.8
4.9
18
2.1
VCM = 0VDC
TA = T MIN to TMAX
±VCC = 4.5V to 5.5V
±380
±3
71
±1.5mV
±15
µV
µV/°C
dB
65
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µVrms
pA/√Hz
BIAS CURRENT(1)
Input Bias Current
VCM = 0VDC
14
50
µA
OFFSET CURRENT(1)
Input Offset Current
VCM = 0VDC
0.2
2
µA
INPUT IMPEDANCE(1)
Differential
Common-Mode
25k  2
106 5
Ω  pF
Ω  pF
2.0
75
±2.5
85
V
dB
50
60
dB
140
200
100
70
–102
–83
–64
–44
MHz
MHz
MHz
dBC(2)
dBC
dBC
dBC
4.5MHz, Gain = +2V/V, CC = 2.2pF
4.5MHz, Gain = +2V/V, CC = 2.2pF
–71
–82
45
350
11
22
30
0.02
0.02
dBC(3)
dBC
MHz
V/µs
ns
ns
ns
%
Degrees
INPUT SELECTION(5)
Transition Time
50% In to 50% Out
ECL: Operation
TTL: Operation
4
4
DIGITAL INPUT
TTL Logic Levels: VIL
VIH
IIL
IIH
ECL Logic Levels: VIL
VIH
IIL
IIH
Logic “LO”
Logic “HI”
Logic “LO”, VIL = 0V
Logic “HI”, VIH = +2.7V
Logic “LO”
Logic “HI”
Logic “LO”, VIL = –1.6V
Logic “HI”, VIH = –1.0V
INPUT VOLTAGE RANGE(1)
Common-Mode Input Range
Common-Mode Rejection
VIN = ±0.5VDC, VO = ±1.25V
OPEN-LOOP GAIN, DC(1)
Open-Loop Voltage Gain
FREQUENCY RESPONSE
Closed-Loop Bandwidth
Crosstalk
Harmonic Distortion: 5MHz
Large Signal Response(4)
Slew Rate
Settling Time: 1%
0.1%
0.01%
Differential Gain (0V to 0.7V)
Differential Phase (0V to 0.7V)
RATED OUTPUT
Voltage Output
Gain = +1V/V, CC = 9pF
Gain = +2V/V, CC = 7pF
Gain = +5V/V, CC = 1pF
Gain = +1V/V, f = 100kHz
f = 1MHz
f = 10MHz
f = 100MHz
G = +1V/V, RL= 150Ω, VO = 0.25Vp-p
Second Harmonic
Third Harmonic
VO = 2.5Vp-p, Gain = +1V/V
Gain = +1V/V
Gain = –1V/V, 1VOUT Step
1MHz, Open-Loop, CC = 5pF
RF = 100Ω, Gain = +1V/V, CC = 10pF
Continuous to Gnd
®
OPA678
0
+2.0
–0.05
1
–1.81
–1.15
–50
–50
±2.5
±1.7
±30
RL = 150Ω
RL = 50Ω
Current Output
Output Resistance
Load Capacitance Stability
Short Circuit Current
32
250
2
±3.75
±2.2
±44
5
17
+45
8
8
ns
ns
+0.8
+5
–0.2
20
–1.475
– 0.88
–100
–100
V
V
mA
µA
V
V
µA
µA
V
V
mA
Ω
pF
mA
SPECIFICATIONS
(CONT)
ELECTRICAL
At VCC = ±5VDC, RL = 150Ω, CCOMP = 5pF, and TA = +25°C, unless otherwise noted.
OPA678AP, AU
PARAMETER
POWER SUPPLY
Rated Voltage
Derated Performance
Current, Quiescent
TEMPERATURE RANGE
Specification
Thermal Impedance
AP
AU
CONDITIONS
MIN
±VCC
±VCC
IO = 0mADC
4.5
TYP
MAX
UNITS
5.5
30
VDC
VDC
mA
+85
°C
5
26
Ambient Temp AP, AU
Junction-to-Ambient
–40
°C/W
°C/W
90
100
NOTES: (1) Specifications are for both inputs (A and B). (2) dBC = Level referred to carrier-input signal. (3) Harmonic distortion will typically be improved significantly
SR
in the inverting mode. (4) Large Signal Response is calculated from the formula LSBW =
. (5) Switching time from application of digital logic signal to
2πV PEAK
input signal selection.
ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS)
At VCC = ±5VDC, RL = 150Ω, CCOMP = 5pF, and TA = TMIN to TMAX, unless otherwise noted.
OPA678AP, AU
PARAMETER
TEMPERATURE RANGE
Specification
OFFSET VOLTAGE
Input Offset Voltage
Offset Voltage Drift
Supply Rejection
CONDITIONS
MIN
Ambient Temp AP/AU
–40
TA = TMIN to TMAX
TA = TMIN to TMAX
±VCC = 4.5V to 5.5V
60
TYP
MAX
UNITS
+85
°C
600
±3
70
±2.4mV
±15
µV
µV/°C
dB
BIAS CURRENT
Input Bias Current
VCM = 0VDC
15
85
µA
OFFSET CURRENT
Input Offset Current
VCM = 0VDC
0.5
5
µA
INPUT VOLTAGE RANGE
Common-Mode Input Range
Common-Mode Rejection
VIN = ±0.5VDC, VO = ±1.25V
OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain
DIGITAL INPUT
TTL Logic Levels: VIL
VIH
IIL
IIH
ECL Logic Levels: VIL
VIH
IIL
IIH
RATED OUTPUT
Voltage Output
Logic “LO”
Logic “HI”
Logic “LO", VIL = 0V
Logic “HI”, VIH = +2.7V
Logic “LO”
Logic “HI”
Logic “LO”, VIL = –1.6V
Logic “HI”, VIH = –1.0V
±2.5
80
V
dB
50
60
dB
0
+2.0
IO = 0mADC
–50
–50
V
V
mA
µA
V
V
µA
µA
±3.75
±2.0
44
V
V
mA
–0.08
5
–1.81
–1.15
±2.5
±1.5
RL = 150Ω
RL = 50Ω
Output Current
POWER SUPPLY
Current, Quiescent
±2.0
60
25
+0.8
+5
–0.4
50
–1.475
–0.88
35
mA
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
OPA678
Pin Assignments for Differential ECL Channel Switching
Pin Assignments for TTL Channel Switching
+In A
1
16 +In B
+In A
1
16 +In B
–In A
2
15 –In B
–In A
2
15 –In B
NC
3
14 DNC
NC
3
–
+
A
+
–
B
–
+
A
+
–
14 Short to pin 13
B
NC
4
13 CHA (ECL)
NC
4
13 Short to pin 14
Compensation
Capacitor
5
12 CHA (ECL)
Compensation
Capacitor
5
12 CHA (TTL)
NC
6
11 Common
NC
6
11 Common
+VCC
7
10 –VCC
+VCC
7
10 –VCC
Output
8
9
Output
8
9
NC
ABSOLUTE MAXIMUM RATINGS
NC
ORDERING INFORMATION
OPA678
Supply ............................................................................................. ±7VDC
Differential Input Voltage .............................................................. Total VCC
Input Voltage Range (Analog and Digital) ........................................... ±VCC
Storage Temperature Range ....................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
Output Short Circuit to Ground (+25°C) ................... Continuous to ground
Junction Temperature .................................................................... +175°C
Package Code
P: 16-Pin Plastic DIP
U: 16-Lead SOIC
ELECTROSTATIC
DISCHARGE SENSITIVITY
PACKAGE INFORMATION
PRODUCT
PACKAGE
PACKAGE DRAWING
NUMBER(1)
OPA678AP
OPA678AU
16-Pin Plastic DIP
16-Pin SOIC
180
211
( )( )
Basic Model Number
Performance Grade Code
A: –40°C to +85°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
®
OPA678
4
TYPICAL PERFORMANCE CURVES
AV = +1V/V CLOSED-LOOP
SMALL SIGNAL BANDWIDTH
0
10
Gain
4
2
–4
–60
–5
–80
–6
–100
–7
–120
–8
–140
–9
–160
4
2
6
8 10
20
40
1MHz
60 80 100
10MHz
AV = +2V/V CLOSED-LOOP
SMALL SIGNAL BANDWIDTH
AV = +5V/V CLOSED-LOOP
SMALL SIGNAL BANDWIDTH
60
15
7
40
14
20
13
0
φ
–20
4
BW = 103MHz
φ = 103°
CC = 3pF
3
2
–40
–60
60
Gain
40
20
12
Gain (dB)
Gain
Phase (°)
8
5
–180
16Hz
Frequency (Hz)
Noise Gain (V/V)
6
100MHz
0
φ
–20
11
BW = 69MHz
φ = 119°
CC = 1pF
10
9
–40
–60
1
–80
8
–80
0
–100
7
–100
–1
–120
6
–120
–2
–140
16Hz
5
1MHz
10MHz
100MHz
1MHz
Frequency (Hz)
0.4
0.4
Differential Phase (°)
0.5
0.3
VO = 0V to 2.1V
0.2
VO = 0V to 2.1V
VO = 0V to 1.4V
VO = 0V to 0.7V
0
VO = 0V to 0.7V
0
2
3
Closed-Loop Gain
–140
16Hz
0.3
0.1
VO = 0V to 1.4V
1
100MHz
DIFFERENTIAL PHASE vs CLOSED-LOOP GAIN
(f = 4.5MHz)
0.5
0.1
10MHz
Frequency (Hz)
DIFFERENTIAL GAIN vs CLOSED-LOOP GAIN
(f = 4.5MHz)
0.2
Phase (°)
1
Gain (dB)
–40
–10
0
Differential Gain (%)
–20
BW = 200MHz
φ = 57°
CC = 8.5pF
–3
6
0
φ
–2
8
Gain (dB)
Compensation Capacitor (pF)
–1
Phase (°)
NOMINAL FREQUENCY COMPENSATION vs NOISE GAIN
4
5
1
2
4
3
5
Closed-Loop Gain
NOTE: For the gain of +2V/V, CC = 2.2pF; for the gain of +5V/V, CC = 0.
NOTE: For the gain of +2V/V, CC = 2.2pF; for the gain of +5V/V, CC = 0.
®
5
OPA678
TYPICAL PERFORMANCE CURVES (CONT)
OPEN-LOOP GAIN, CMR, AND PSR vs TEMPERATURE
CHANNEL-TO-CHANNEL CROSSTALK vs FREQUENCY
0
110
–15
100
Crosstalk (dBc)
–30
90
(dBc)
–45
–60
–75
CMR
80
70
PSR
60
AOL
–90
–105
–120
1
0.1
10
50
–50
1000
100
–25
0
Frequency (MHz)
1MHz HARMONIC DISTORTION vs POWER OUTPUT
75
100
125
5MHz HARMONIC DISTORTION vs POWER OUTPUT
AV = +1V/V
CC = 5pF
RL = 150Ω
fc = 1MHz
–40
–50
–60
AV = +1V/V
CC = 5pF
RL = 150Ω
fc = 5MHz
–30
Distortion (dBc)
–30
Distortion (dBc)
50
–20
–20
2f
–40
–50
2f
–60
–70
–70
3f
–80
–15
–10
1Vp-p
–5
0
5
Power Output (dBm)
2Vp-p
10
0.125Vp-p 0.25Vp-p 0.5Vp-p
–90
–20
15
10MHz HARMONIC DISTORTION vs POWER OUTPUT
–5
1Vp-p
0
5
2Vp-p
10
15
20MHz HARMONIC DISTORTION vs POWER OUTPUT
AV = +1V/V
CC = 5pF
RL = 150Ω
fc = 10MHz
–30
–50
2f
–60
3f
–70
–40
AV = +1V/V
CC = 5pF
RL = 150Ω
fc = 20MHz
–50
2f
–60
–70
3f
–80
–80
0.125Vp-p 0.25Vp-p 0.5Vp-p
–90
–20
–10
–20
Distortion (dBc)
–40
–15
Power Output (dBm)
–20
–30
3f
–80
0.125Vp-p 0.25Vp-p 0.5Vp-p
–90
–20
Distortion (dBc)
25
Temperature (°C)
–15
–10
–5
1Vp-p
0
5
2Vp-p
10
0.125Vp-p 0.25Vp-p 0.5Vp-p
–90
–20
15
Power Output (dBm)
–10
–5
0
Power Output (dBm)
®
OPA678
–15
1Vp-p
6
5
2Vp-p
10
15
THEORY OF OPERATION
The simplified circuit of the ECL compatible OPA678 is
shown in Figure 1. It is a “classical” high-speed op amp
architecture with one important exception—the amplifier
has two ECL logic selectable differential input stages. An
appropriate differential ECL logic signal on A and A will
turn on either Q5 or Q6, steering operating (tail) current to
either differential input pair Q1 and Q2 or Q3 and Q4. The
input pair receiving the tail current operates as a conventional op-amp input stage while the de-selected input pair
receiving no tail current appears as an open circuit. The deselected inputs have only a few pF parasitic capacitance and
in the off condition exhibit only a very low leakage (bias)
current of about 100pA. Two feedback networks can be
connected to each input separately allowing a wide range of
circuit applications. The feedback network connected to the
selected input operates in a normal op amp fashion while the
feedback network connected to the de-selected input is
totally inactive, appearing only as an additional load to the
amplifier’s output stage.
Standard TTL and ECL logic levels may be applied to each
input selection circuit but only 350mV is typically required
to switch between inputs. This logic input sensitivity allows
simpler high-speed logic driver circuitry and it minimizes
digital noise coupling into adjacent wideband analog circuitry and allows single ended ECL inputs to be used with
VBB applied to the other input.
The OPA678 is designed to be frequency compensated by a
single capacitor connected from pin 5 to ground. Recommended compensation is shown in the Typical Performance
Curve section. A small variable capacitor may be trimmed
for best bandwidth, settling time, and gain peaking. Closedloop gain/phase (Bode) plots are shown in the Typical
Performance Curves.
OFFSET TRIM
The laser trimmed input offset voltage is low enough for
many video and RF applications. Independent control of
input offset will require that trim adjust current be summed
into one or both inputs.
For TTL operation, “A select” is held to an internal reference level by tying pins 13 and 14 together. This allows “A”
to become the single-ended TTL input.
+VCC
Bias
Q7
A
Select
Q8
A
Select
–
A
Q1
B
Q2
+ –
Q3
Q4
+
Comp
Out
Q5
Q6
ITAIL
–VCC
FIGURE 1. OPA678 Simplified Circuit Diagram.
®
7
OPA678
APPLICATION TIPS
Wideband amplifier circuits require good layout techniques
to be successful. The use of short, direct signal paths and
heavy (2oz copper recommended) ground planes are absolutely necessary to achieve the performance level inherent in
the OPA678. Oscillation, ringing, poor bandwidth and settling, gain peaking, and instability are typical problems that
plague all high-speed amplifiers when they are used in poor
layouts. The OPA678 is no different in this respect—any
amplifier with a gain bandwidth product of a few GHz
requires some care be taken in its application.
7.
8.
Avoid overloading the output. Remember that output
current must be provided by the amplifier to drive its
own feedback network as well as to drive its “load.”
Lowest distortion is achieved with high impedance
loads.
9. PC board traces for signal and power lines should be
wide to reduce impedance or inductance.
10. Don’t forget that these amplifiers use ±5V supplies.
Although they will operate perfectly well with +5V and
–5.2V, the use of ±15V supplies will result in destruction.
Points to remember:
1. Use a heavy copper ground plane on the component side
of your PC board. This provides a low inductance
ground and it also conducts heat from active circuit
package pins into ambient air by convection.
2. Bypass power supply pins directly at the active device.
The use of monoblock or tantalum capacitors with very
short leads is highly recommended. A 0.1µF in parallel
with a 1.0µF will be optimum in most applications. The
0.1µF should be placed directly at the device’s power
supply leads.
3.
When using the OPA678 in the unity gain voltage
follower configuration it is recommended that a 100Ω
resistor be connected from the output to the inverting
input for optimum performance.
4.
Signal paths should be short and direct. Feedback resistors, compensation capacitors, termination resistors, etc.
should have lead lengths no longer than 1/4 inch (6cm).
Surface mount components (chip resistors, capacitors,
etc.) have low inductance and are therefore recommended. Parasitic inductance and capacitance should be
avoided if best performance is to be achieved.
5.
6.
11. Standard commercial test equipment has not been designed to test devices in the OPA678 speed range.
Benchtop op amp testers and ATE systems will require
a special test head to successfully test these amplifiers.
12. High-speed amplifiers can drive only a limited amount
of capacitance. If the load exceeds 10 to 20pF consider
using a fast buffer or a small resistor to isolate the
capacitance from the amplifier’s output. Capacitive loads
will cause loop instability if not compensated for.
13. Terminate transmission line loads. Unterminated lines,
such as coaxial cable, can appear to the amplifier to be
a capacitive or inductive load. By terminating a transmission line with its characteristic impedance, the
amplifier’s load then appears as a purely resistive impedance.
14. For clean, fast input selection the logic input pins
should be terminated with appropriate resistors. Resistors should be connected from input selection pins to
ground plane with short leads. Failure to terminate long
lines will result in ringing and poor high frequency
switching.
Resistors used in feedback networks should have values
of a few hundred ohms for best performance. Shunt
capacitance problems limit the acceptable range to about
1kΩ or on the high resistance end and to a value that is
within the amplifier’s output drive limits on the low
end. Metal film and carbon compensation resistors will
be satisfactory.
15. Plug-in prototype boards and wire-wrap boards will not
be satisfactory. A clean layout using RF techniques is
required; there is no shortcut.
®
OPA678
Wirewound resistors (even “noninductive” types) are
absolutely unacceptable in high frequency circuits.
8
301Ω
301Ω
NC
TEK 11402
D.S.O.
154Ω
(1)
3
2
–
+ A
1
NC
4
5
7
6
15
14
9
10
+ B
–
TEK 11402
D.S.O.
NC
11
12
Output
3
OPA678
16
1µF
Tantalum
(2)
NC
Input
50Ω
+5V
1 to 4.5pF
1:1 HP
Probe
1MHz
Square Wave
50Ω
13
(1)
1µF
Tantalum
–5V
NOTES: (1) 0.1µF to 1.0µF, ceramic mono-block, located at package pin. (2) 1 to 4.5pF Johanson Thin-Trim® Capacitor.
FIGURE 2. OPA678 Settling Time Test Circuit.
100Ω
4.4pF +5V
NC
NC
2
+1Vdc
1
50Ω
–1Vdc
50Ω
1µF
3
–
+ A
4
NC
5
7
6
16
+ B
11
–
12
15
13
14
10:1 Probe
8
OPA678
10
Scope
9
150Ω
NC
1µF
–5.2V
50:1 Probe
Scope
20MHz sq. wave
0 to 4V, 50Ω source
50Ω
FIGURE 3. OPA678 (TTL) Input Selection Transition Time Test Circuit.
®
9
OPA678
FIGURE 4. OPA678 (TTL) Input Selection Time. Input A to
B. Larger output voltages will have slightly
slower switching times due to more slewing of
the op amp.
FIGURE 5. OPA678 (ECL) Input Selection Time. Input A
to B. Larger output voltages will have slightly
slower switching times due to more slewing of
the op amp.
100Ω
4.4pF +5V
NC
NC
2
0Vdc
1
50Ω
0Vdc
50Ω
1µF
3
–
+ A
4
NC
5
6
8
OPA678
16
+ B
11
–
12
15
13
14
7
10
Scope
9
150Ω
NC
1µF
–5.2V
20MHz sq. wave
0 to 4V, 50Ω source
50Ω
FIGURE 6. Channel Select Switching Transient Test Schematic.
FIGURE 7. OPA678 Switching Transient. The switching
transient levels will be lower for switching
signals with slower rising edges.
®
OPA678
10
R2
R1
+5V
NC
CC
NC
2
Input
1
(1)
VOLTAGE GAIN
V/V
dB
1µF
Tantalum
3
–
+ A
4
7
6
16
10
+ B
11
–
12
15
13
14
75Ω
8
OPA678
75Ω
+1
+2
NC
5
Output
0
6
R1
Ω
R2
Ω
CC
pF
∞
500
100
500
8
3
NOTE: (1) 0.1µF, Ceramic Mono-block,
Located at Package Pin.
9
NC
(1)
1µF
Tantalum
–5V
FIGURE 8. OPA678 used as Conventional Op Amp. A wideband video amplifier with 75Ω input and output impedance.
R1
R2
+5V
NC
CC
NC
2
Input 1
1
3
–
+ A
4
NC
5
6
16
+ B
11
–
12
15
13
14
10
TTL
R1
R2
7
Output
8
OPA678
Input 2
(1)
1µF
Tantalum
9
VOLTAGE GAIN
V/V
R1
Ω
R2
Ω
CC
pF
+1
+2
+4
+8
∞
300
100
50
100
300
300
350
8
3
1
0
NOTE: (1) 0.1µF, Ceramic Mono-block,
Located at Package Pin.
NC
(1)
1µF
Tantalum
–5V
FIGURE 9. Two Input Multiplexer with Gain. This circuit can be used to multiplex I & Q signals into one sampling ADC.
®
11
OPA678
300Ω
150Ω
–
+5V
Input 1
150Ω
NC
+
(1)
3
2
300Ω
–
+ A
1
4
NC
5
7
6
16
+ B
11
–
12
15
13
14
150Ω
Output
8
OPA678
300Ω
1µF
Tantalum
5pF
NC
10
9
NC
(1)
1µF
Tantalum
+
TTL
–5V
Input 2
150Ω
300Ω
–
NOTE: (1) 0.1µF to 1.0µF, ceramic mono-block, located at package pin.
FIGURE 10. Differential Input Multiplexer with Gain of +2V/V.
R2
R1
+5V
NC
CC
NC
50Ω RF or IF
Input
2
1
(1)
1µF
Tantalum
3
–
+ A
4
6
16
+ B
11
–
12
15
13
49.9Ω
14
7
49.9Ω
8
OPA678
49.9Ω
50Ω RF or IF
Output
NC
5
10
9
NC
(1)
1µF
Tantalum
–5V
49.9Ω
TTL
R1
R2
VOLTAGE GAIN
V/V
R1
Ω
R2
Ω
CC
pF
+1
+2
∞
500
100
500
8
3
NOTE: (1) 0.1µF, Ceramic Mono-block,
Located at Package Pin.
FIGURE 11. Receiver Noise Blanker: A Wideband Gated Video Amplifier.
®
OPA678
12
R1
R2
+5V
NC
CC
NC
2
R1 || R2
1
3
–
+ A
4
NC
5
6
16
+ B
11
–
12
15
13
14
7
Output
8
OPA678
Output
1µF
Tantalum
(1)
10
9
NC
(1)
1µF
Tantalum
–5V
TTL
R3
R4
VOLTAGE GAIN
V/V
R1
Ω
R2
Ω
R3
Ω
R4
Ω
CC
pF
±2
±5
100
40
200
200
200
50
200
200
4
1
NOTE: (1) 0.1µF, Ceramic Mono-block, Located at Package Pin.
FIGURE 12. Synchronous Modulator/Demodulator (with Gain).
R2
R1
+5V
NC
3 to
5pF
NC
(1)
1µF
Tantalum
3
2
–
+ A
Input
1
4
5
NC
6
16
+ B
–
15
14
13
Output
8
OPA678
300Ω
7
9
10
NC
11
12
(1)
DNC
1µF
Tantalum
–5V
300Ω
A
A
Diff ECL
300Ω
300Ω
NOTE: (1) 0.1µF to 1.0µF, ceramic mono-block, located at package pin.
FIGURE 13. Very Fast Programmable Gain Amplifier with Voltage Gains of +1V/V and +2V/V (0dB and 6dB).
®
13
OPA678
3
+
1/2
OPA2680
6
–
2
400Ω
Differential
Input
1
200Ω
400Ω
500Ω
500Ω
2
+
1/2
OPA2680
500Ω
6
–
TTL
3
2
500Ω
1
16
15
3
1/2
OPA2680
+ B
–
13
–
2
500Ω
500Ω
400Ω
Differential
Input
2
200Ω
2
400Ω
+
1/2
OPA2680
6
–
3
FIGURE 14. High Input Impedance Differential Input Multiplexer with Gain of 5V/V (14dB).
®
OPA678
14
8
5
11
14
500Ω
6
12
OPA678
500Ω
+
–
+ A
3 to 5pF
Output