TI1 INA231AIYFDR High- or low-side measurement, bidirectional current and power monitor with 1.8-v i2c interface Datasheet

Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
INA231 High- or Low-Side Measurement, Bidirectional Current and Power Monitor
With 1.8-V I2C Interface
1 Features
3 Description
•
•
•
•
The INA231 is a current-shunt and power monitor
with a 1.8-V compliant I2C interface that features 16
programmable addresses. The INA231 monitors both
shunt voltage drops and bus supply voltage.
Programmable calibration value, conversion times,
and averaging combined with an internal multiplier
enable direct readouts of current in amperes and
power in watts.
1
•
•
•
•
•
Bus Voltage Sensing From 0 V to 28 V
High- or Low-Side Sensing
Current, Voltage, and Power Reporting
High Accuracy:
– 0.5% Gain Error (Max)
– 50-μV Offset (Max)
Configurable Averaging Options
Programmable Alert Threshold
1.8-V I2C Compliant
Power-Supply Operation: 2.7 V to 5.5 V
Packages: 1.68-mm × 1.43-mm, WCSP-12
– Low Profile, 0.4-mm Height (YFD Package)
The INA231 senses current on buses that vary from 0
V to 28 V, with the device powered from a single 2.7V to 5.5-V supply, drawing 330 μA (typical) of supply
current. The INA231 is specified over the operating
temperature range of –40°C to +125°C.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
•
•
•
Smartphones
Tablets
Servers
Computers
Power Management
Battery Chargers
Power Supplies
Test Equipment
PACKAGE
BODY SIZE (NOM)
YFF (DSBGA-12)
1.645 mm x 1.388
mm x 0.625 mm
YFD (DSBGA-12)
1.645 mm x 1.388
mm x 0.400 mm
INA231
(1) For all available packages, see the package option addendum
at the end of the datasheet.
High-or Low-Side Sensing
Power Supply
(0 V to 28 V)
HighSide
Shunt
CBYPASS
0.1 mF
VS
(Supply Voltage)
BUS
INA231
SDA
SCL
´
Load
Power Register
V
2
Current Register
ADC
LowSide
Shunt
I
Voltage Register
IC
Interface
ALERT
A0
Alert Register
A1
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Timing Requirements: I2C Bus..................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 14
8.5 Programming .......................................................... 15
8.6 Register Maps ......................................................... 22
9
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
9.2 Typical Applications ................................................ 30
10 Power Supply Recommendations ..................... 32
11 Layout................................................................... 32
11.1 Layout Guidelines ................................................. 32
11.2 Layout Example .................................................... 32
12 Device and Documentation Support ................. 33
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
13 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
Changes from Revision A (June 2017) to Revision B
Page
•
Changed NC pin description from "No internal connection" to "Do not connect, leave floating" .......................................... 3
•
Changed SCL max value from VS + 0.3 V to 6 V in Absolute Maximum Ratings table ......................................................... 4
•
Added text to end of Layout Guidelines section clarifying no connection of NC pins .......................................................... 32
Changes from Original (February 2013) to Revision A
Page
•
Added Device Information, Recommended Operating Conditions, and ESD Ratings tables, and Detailed
Description , Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation
Support , and Mechanical, Packaging, and Orderable Information sections ......................................................................... 1
•
Added new WSCP-12 (YFD) package with 0.4-mm package height and associated content to data sheet......................... 1
•
Added operating ambient temperature, TA to Absolute Maximum Ratings table ................................................................... 4
•
Added new note 1 to Timing Requirements: I2C Bus section ............................................................................................... 6
•
Added test condition to Figure 2 ............................................................................................................................................ 7
2
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
5 Device Comparison Table
DEVICE
DESCRIPTION
INA209
Current and power monitor with watchdog, peak-hold, and fast comparator functions
INA210, INA211, INA212, INA213, INA214,
INA215
Zerø-drift, low-cost, analog current shunt monitor series in small package
INA219
Zerø-drift, bidirectional current power monitor with two-wire interface
INA226
High or Low-side, bidirectional current and power monitor with two-wire interface and programmable alert
6 Pin Configuration and Functions
YFF and YFD Packages
12-Pin WCSP
Top View
ALERT
A0
A1
IN+
SDA
NC
NC
IN-
SCL
VS
GND
BUS
A
B
C
D
Rows
3
2
1
Columns
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
A0
B3
DI
Address pin. Connect to GND, SCL, SDA, or VS. Table 2 shows pin settings and corresponding
addresses.
A1
C3
DI
Address pin. Connect to GND, SCL, SDA, or VS. Table 2 shows pin settings and corresponding
addresses.
ALERT
A3
DO
Multi-functional alert, open-drain output.
GND
C1
A
Ground
NC
B2, C2
—
Do not connect, leave floating.
SCL
A1
DI
Serial bus clock line, open-drain input.
SDA
A2
D I/O
BUS
D1
AI
Bus voltage input
IN–
D2
AI
Negative differential shunt voltage input. Connect to load side of shunt resistor.
IN+
D3
AI
Positive differential shunt voltage input. Connect to supply side of shunt resistor.
VS
B1
A
Power supply pin, 2.7 V to 5.5 V
Serial bus data line, open-drain input/output.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
3
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
6
V
Supply voltage, VS
–30
30
V
–0.3
30
V
SDA
GND – 0.3
6
V
SCL
GND – 0.3
Analog inputs, IN+, IN–
Differential (VIN+) – (VIN–)
(2)
Common-mode
6
V
Input current into any pin
5
mA
Open-drain digital output current
10
mA
125
°C
150
°C
150
°C
Operating ambient temperature, TA
–40
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VIN+ and VIN– may have a differential voltage of –30 V to +30 V; however, the voltage at these pins must not exceed the range –0.3 V to
+30 V.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
Electrostatic
discharge
V(ESD)
(1)
(2)
(1)
UNIT
2500
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
1000
Machine model (MM)
150
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VCM
Common-mode voltage
0
28
VS
Operating supply voltage
2.7
5.5
V
V
TA
Operating ambient temperature
–40
125
°C
7.4 Thermal Information
INA231
THERMAL METRIC (1)
YFD (DSBGA)
YFF (DSBGA)
UNIT
12 PINS
12 PINS
RθJA
Junction-to-ambient thermal resistance
83.8
90.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.4
0.5
°C/W
RθJB
Junction-to-board thermal resistance
19.3
40.0
°C/W
ψJT
Junction-to-top characterization parameter
0.3
3.0
°C/W
ψJB
Junction-to-board characterization parameter
19.4
39.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
7.5 Electrical Characteristics
at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VBUS = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SHUNT INPUT
Shunt voltage input
CMR
Common-mode rejection
VOS
Shunt offset voltage, RTI (1)
PSRR
vs power supply
–81.92
VIN+ = 0 V to 28 V
100
81.9175
mV
120
dB
±10
±50
μV
TA = –40°C to +125°C
0.1
0.5
μV/°C
VS = 2.7 V to 5.5 V
10
μV/V
BUS INPUT
Bus voltage input range (2)
VOS
Bus offset voltage, RTI (1)
PSRR
vs power supply
0
TA = –40°C to +125°C
28
V
±5
±30
mV
10
40
μV/°C
2
BUS pin input impedance
mV/V
830
kΩ
INPUT
IIN+, IIN-
Input bias current
Input leakage (3)
10
μA
(VIN+) + (VIN–), Power-Down mode
0.1
0.5
Shunt voltage
2.5
μV
1.25
mV
μA
DC ACCURACY
ADC native resolution
1 LSB step size
Shunt voltage gain error
Bus voltage gain error
16
Bus voltage
0.2%
TA = –40°C to +125°C
TA = –40°C to +125°C
Differential nonlinearity
ADC conversion time
Bits
0.5%
10
50
0.2%
0.5%
10
50
ppm/°C
ppm/°C
±0.1
LSB
CT bit = 000
140
154
μs
CT bit = 001
204
224
μs
CT bit = 010
332
365
μs
CT bit = 011
588
646
μs
CT bit = 100
1.1
1.21
ms
CT bit = 101
2.116
2.328
ms
CT bit = 110
4.156
4.572
ms
CT bit = 111
8.244
9.068
ms
28
35
ms
2
μA
SMBus
SMBus timeout (4)
DIGITAL INPUT/OUTPUT
Input capacitance
Leakage input current
3
0 ≤ VIN ≤ VS
0.5
pF
VIH
High-level input voltage
1.4
6
V
VIL
Low-level input voltage
–0.5
0.4
V
VOL
Low-level output voltage (SDA, ALERT) IOL = 3 mA
0
0.4
Hysteresis
500
V
mV
POWER SUPPLY
Quiescent current
Power-Down mode
Power-on reset threshold
(1)
(2)
(3)
(4)
330
420
μA
3
7
μA
2
V
RTI = Referred-to-input.
Although the input range is 28 V, the full-scale range of the ADC scaling is 40.96 V. Do not apply more than 28 V. See the Basic
Analog-to-Digital Converter (ADC) Functions section for more details
Input leakage is positive (current flowing into the pin) for the conditions shown at the top of this table. Negative leakage currents can
occur under different input conditions.
SMBus timeout in the INA231 resets the interface any time SCL is low for more than 28 ms.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
5
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
7.6 Timing Requirements: I2C Bus (1)
FAST MODE
MIN
f(SCL) SCL operating frequency
0.001
HIGH-SPEED MODE
MAX
MIN
0.4
0.001
TYP
MAX
2.5
UNIT
MHz
Bus free time between stop
and start conditions
600
260
ns
t(HDSTA)
Hold time after repeated
START condition.
After this period, the first clock
is generated.
100
100
ns
t(SUSTA)
Repeated start condition setup
time
100
100
ns
t(SUSTO) STOP condition setup time
100
100
t(HDDAT) Data hold time, VS ≤ 3.3 V
0
0
130
ns
t(HDDAT) Data hold time, VS > 3.3 V
10
10
130
ns
t(BUF)
t(SUDAT) Data setup time
ns
100
50
ns
t(LOW) SCL clock low period
1300
260
ns
t(HIGH) SCL clock high period
600
60
ns
tF Data fall time
300
80
ns
tR Data rise time
300
80
ns
tF Clock fall time
300
40
ns
tR Clock rise time
300
40
ns
tR
(1)
TYP
Clock/data rise time for SCLK
≤ 100 kHz
1000
ns
Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are specified by design, but not
production tested.
t(LOW)
tF
tR
t(HDSTA)
SCL
t(HDSTA)
t(HIGH)
t(HDDAT)
t(SUSTO)
t(SUSTA)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 1. Bus Timing Diagram
6
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
7.7 Typical Characteristics
at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VBUS = 12 V (unless otherwise noted)
0
−10
Population
Gain (dB)
−20
−30
−40
−60
1
10
100
1k
Frequency (Hz)
10k
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
35
40
45
50
−50
100k
G001
Input Offset Voltage (µV)
G002
Conversion time = 1.1 ms
Figure 3. Shunt Input Offset Voltage Production Distribution
Figure 2. Frequency Response
10
Common-Mode Rejection Ratio (dB)
170
Offset (µV)
0
−10
−20
−50
−25
0
25
50
Temperature (°C)
75
100
160
150
140
−50
125
−25
0
25
50
Temperature (°C)
G003
Figure 4. Shunt Input Offset Voltage vs Temperature
75
100
125
G004
Figure 5. Shunt Input Common-Mode Rejection Ratio
vs Temperature
500
Population
Gain Error (m%)
400
300
200
Shunt Gain Error (m%)
0
−50
500
400
300
200
100
0
−100
−200
−300
−400
−500
100
−25
0
25
50
Temperature (°C)
75
100
125
G006
G005
Figure 7. Shunt Input Gain Error vs Temperature
Figure 6. Shunt Input Gain Error Production Distribution
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
7
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
Typical Characteristics (continued)
at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VBUS = 12 V (unless otherwise noted)
300
250
Population
Gain Error (m%)
200
150
100
50
G007
30
25
27.5
20
22.5
15
17.5
10
12.5
5
7.5
36
0
32
2.5
8
12
16
20
24
28
Common−Mode Input Voltage (V)
−2.5
4
−5
0
−5
−50
−15
0
Input Offset Voltage (mV)
Figure 8. Shunt Input Gain Error vs Common-Mode Voltage
G008
Figure 9. Bus Input Offset Voltage Production Distribution
−0.6
Population
Offset (mV)
−0.8
−1
G009
500
400
300
200
125
100
100
0
75
−100
25
50
Temperature (°C)
−200
0
−300
−25
−400
−1.4
−50
−500
−1.2
Input Gain Error (m%)
G010
Figure 10. Bus Input Offset Voltage vs Temperature
Figure 11. Bus Input Gain Error Production Distribution
500
25
Input Bias Current (µA)
Gain Error (m%)
400
300
200
100
0
−50
−25
0
25
50
Temperature (°C)
75
100
125
20
15
10
5
G011
0
0
Figure 12. Bus Input Gain Error vs Temperature
4
8
12
16
20
24
28
Common-Mode Input Voltage (V)
32
36
G012
Figure 13. Input Bias Current vs Common-Mode Voltage
8
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
Typical Characteristics (continued)
at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VBUS = 12 V (unless otherwise noted)
260
Input Bias Current − Shutdown (nA)
Input Bias Current (µA)
24
22
20
18
16
−50
−25
0
25
50
Temperature (°C)
75
100
180
140
100
60
20
−50
125
−25
0
G013
Figure 14. Input Bias Current vs Temperature
25
50
Temperature (°C)
75
100
125
G014
Figure 15. Input Bias Current vs Temperature, Shutdown
2.6
Quiescent Current − Shutdown (µA)
500
Quiescent Current (µA)
220
400
300
200
100
−50
−25
0
25
50
Temperature (°C)
75
100
2.4
2.2
2
1.8
1.6
−50
125
−25
0
G015
Figure 16. Active IQ vs Temperature
25
50
Temperature (°C)
75
100
125
G016
Figure 17. Shutdown IQ vs Temperature
500
300
250
Shutdown IQ (mA)
IQ (mA)
450
400
200
150
100
350
50
300
0
1
10
100
1,000
10,000
1
10
100
1,000
10,000
Frequency (kHz)
Frequency (kHz)
Figure 18. Active IQ vs I2C Clock Frequency
Figure 19. Shutdown IQ vs I2C Clock Frequency
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
9
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
8 Detailed Description
8.1 Overview
The INA231 is a digital, current-sense amplifier with an I2C- and SMBus-compatible interface. It provides digital
current, voltage, and power readings necessary for accurate decision-making in precisely controlled systems.
Programmable registers allow flexible configuration for measurement resolution, as well as continuous-versustriggered operation. Detailed register information is shown in the Register Maps section. See the Functional
Block Diagram section for a block diagram of the INA231 device.
8.2 Functional Block Diagram
Power
(1)
Bus Voltage
(1)
´
Shunt Voltage
Channel
Current
(1)
ADC
Bus Voltage
Channel
Calibration
(2)
´
Shunt Voltage
(1)
Data Registers
(1)
Read-only
(2)
Read/write
Figure 20. Functional Block Diagram
8.3 Feature Description
8.3.1 Basic Analog-to-Digital Converter (ADC) Functions
The INA231 performs two measurements on the power-supply bus of interest. The voltage developed from the
load current that flows through a shunt resistor creates the shunt voltage signal that is measured at the IN+ and
IN– pins. The device can also measure the power supply bus voltage by connecting this voltage to the BUS pin.
The differential shunt voltage is measured with respect to the IN– pin whereas the bus voltage is measured with
respect to ground.
The INA231 is typically powered by a separate supply that can range from 2.7 V to 5.5 V. The bus that is being
monitored can range in voltage from 0 V to 28 V.
NOTE
Based on the fixed 1.25 mV LSB for the bus voltage register, a full-scale register would
result in a 40.96-V value. However, the actual voltage that is applied to the input pins of
the INA231 should not exceed 28 V.
There are no special considerations for power-supply sequencing because the common-mode input range and
power-supply voltage are independent of each other; therefore, the bus voltage can be present with the supply
voltage off, and vice-versa.
As noted, the INA231 takes two measurements, shunt voltage and bus voltage. It then converts these
measurements to current, based on the Calibration register value, and then calculates power. See the Configure,
Measure, and Calculate Example section for additional information on programming the calibration register.
10
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
Feature Description (continued)
The INA231 has two operating modes, continuous and triggered, that determine how the ADC operates after
these conversions. When the INA231 is in the normal operating mode (that is, the MODE bits of the
Configuration register are set to '111'), it continuously converts a shunt voltage reading followed by a bus voltage
reading. After the shunt voltage reading, the current value is calculated based on Equation 3. This current value
is then used to calculate the power result using Equation 4. These values are subsequently stored in an
accumulator, and the measurement and calculation sequence repeats until the number of averages set in the
Configuration register is reached. Note that the current and power calculations are based on the value
programmed into the Calibration register. If the Calibration register is not programmed, the result of the current
and power calculations is zero. Following every sequence, the present set of measured and calculated values
are appended to the previously collected values. After all of the averaging has been completed, the final values
for shunt voltage, bus voltage, current, and power are updated in the corresponding registers and can then be
read. These values remain in the data output registers until they are replaced by the next fully completed
conversion results. Reading the data output registers does not affect a conversion in progress.
The mode control bits in the Configuration register also permit selecting specific modes to convert only the shunt
voltage or the bus voltage in order to further allow the monitoring function configuration to fit specific application
requirements.
All current and power calculations are performed in the background and do not contribute to conversion time.
In triggered mode, writing any of the triggered convert modes into the Configuration register (that is, the MODE
bits of the Configuration register are set to 001, 010, or 011) triggers a single-shot conversion. This action
produces a single set of measurements. To trigger another single-shot conversion, the Configuration register
must be written to again, even if the mode does not change.
In addition to the two operating modes (continuous and triggered), the INA231 also has a power-down mode that
reduces the quiescent current and turns off current into the INA231 inputs, which reduces the impact of supply
drain when the device is not being used. Full recovery from power-down mode requires 40 ms. The registers of
the INA231 can be written to and read from while the device is in power-down mode. The device remains in
power-down mode until one of the active modes settings are written into the Configuration register.
Although the INA231 can be read at any time, and the data from the last conversion remain available, the
conversion ready flag bit (CVRF bit, Mask/Enable register) is provided to help coordinate single-shot or triggered
conversions. The CVRF bit is set after all conversions, averaging, and multiplication operations are complete for
a single cycle.
The CVRF bit clears under these conditions:
1. Writing to the Configuration register, except when configuring the MODE bits for power-down mode; or
2. Reading the Status register.
8.3.1.1 Power Calculation
The current and power are calculated after shunt voltage and bus voltage measurements, as shown in Figure 21.
The current is calculated after a shunt voltage measurement based on the value set in the Calibration register. If
there is no value loaded into the Calibration register, the current value stored is zero. Power is calculated
following the bus voltage measurement based on the previous current calculation and bus voltage measurement.
If there is no value loaded in the Calibration register, the power value stored is also zero. These calculations are
performed in the background and do not add to the overall conversion time. These current and power values are
considered intermediate results (unless the averaging is set to 1) and are stored in an internal accumulation
register, not the corresponding output registers. Following every measured sample, the newly-calculated values
for current and power are appended to this accumulation register until all of the samples have been measured
and averaged based on the number of averages set in the Configuration register.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
11
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
Feature Description (continued)
Bus and Power Limit Detect
Following Every Bus Voltage Conversion
Current Limit Detect Following
Every Shunt Voltage Conversion
I
V
I
P
V
I
P
V
I
P
V
I
P
V
I
P
V
I
P
V
I
P
V
I
P
V
I
V
P
I
P
V
I
P
V
I
P
V
I
P
V
I
P
V
I
P
V
P
Power Average
Bus Voltage Average
Shunt Voltage Average
Figure 21. Power Calculation Scheme
In addition to the current and power accumulating after every sample, the shunt and bus voltage measurements
are also collected. After all of the samples have been measured and the corresponding current and power
calculations have been made, the accumulated average for each of these parameters is then loaded to the
corresponding output registers where they can then be read.
8.3.1.2 ALERT Pin
The INA231 has a single Alert Limit register (07h) that allows the ALERT pin to be programmed to respond to a
single user-defined event or to a conversion ready notification if desired. The Mask/Enable register allows for
selection from one of the five available functions to monitor and set the conversion ready bit (CNVR,
Mask/Enable register) to control the response of the ALERT pin. Based on the function being monitored, a value
would then be entered into the Alert Limit register to set the corresponding threshold value that asserts the
ALERT pin.
The ALERT pin allows for one of several available alert functions to be monitored to determine if a user-defined
threshold has been exceeded. The five alert functions that can be monitored are:
• Shunt voltage overlimit (SOL)
• Shunt voltage underlimit (SUL)
• Bus voltage overlimit (BOL)
• Bus voltage underlimit (BUL)
• Power overlimit (POL)
The ALERT pin is an open-drain output. This pin is asserted when the alert function selected in the Mask/Enable
register exceeds the value programmed into the Alert Limit register. Only one of these alert functions can be
enabled and monitored at a time. If multiple alert functions are enabled, the selected function in the highest
significant bit position takes priority and responds to the Alert Limit register value. For example, if the SOL and
the SUL are both selected, the ALERT pin asserts when the Shunt Voltage Over Limit register exceeds the value
in the Alert Limit register.
The conversion-ready state of the device can also be monitored at the ALERT pin to inform the user when the
device has completed the previous conversion and is ready to begin a new conversion. The conversion ready
flag (CVRF) bit can be monitored at the ALERT pin along with one of the alert functions. If an alert function and
the CNVR bit are both enabled for monitoring at the ALERT pin, then after the ALERT pin is asserted, the CVRF
bit (D3) and the AFF bit (D4) in the Mask/Enable register must be read following the alert to determine the
source of the alert. If the conversion ready feature is not desired, and the CNVR bit is not set, the ALERT pin
only responds to an exceeded alert limit based on the alert function enabled.
If the alert function is not used, the ALERT pin can be left floating without impacting the operation of the device.
12
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
Feature Description (continued)
Refer to Figure 21 to see the relative timing of when the value in the Alert Limit register is compared to the
corresponding converted value. For example, if the alert function that is enabled is Shunt Voltage Over Limit
(SOL), following every shunt voltage conversion the value in the Alert Limit register is compared to the measured
shunt voltage to determine if the measurements have exceeded the programmed limit. The AFF bit (D4,
Mask/Enable register) asserts high any time the measured voltage exceeds the value programmed into the Alert
Limit register. In addition to the AFF bit being asserted, the ALERT pin is asserted based on the Alert Polarity bit
(APOL, D1, Mask/Enable register). If the Alert Latch is enabled, the AFF bit and ALERT pin remain asserted until
either the Configuration register is written to or the Mask/Enable register is read.
The bus voltage alert functions (BOL and BUL, Mask/Enable register) compare the measured bus voltage to the
Alert Limit register following every bus voltage conversion and assert the AFF bit and ALERT pin if the limit
threshold is exceeded.
The power overlimit alert function (POL, Mask/Enable register) is also compared to the calculated power value
following every bus voltage measurement conversion and asserts the AFF bit and ALERT pin if the limit
threshold is exceeded.
The alert function compares the programmed alert limit value to the result of each corresponding conversion.
Therefore, an alert can be issued during a conversion cycle where the averaged value of the signal does not
exceed the alert limit. Triggering an alert based on this intermediate conversion allows for out-of-range events to
be detected faster than the averaged output data registers are updated. This fast detection can be used to create
alert limits for quickly changing conditions through the use of the alert function, as well as to create limits to
longer-duration conditions through software monitoring of the averaged output values.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
13
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
8.4 Device Functional Modes
8.4.1 Averaging and Conversion Time Considerations
The INA231 has programmable conversion times for both the shunt voltage and bus voltage measurements. The
conversion times for these measurements can be selected from as fast as 140 μs to as long as 8.244 ms. The
conversion time settings, along with the programmable averaging mode, allow the INA231 to be configured to
optimize the available timing requirements in a given application. For example, if a system requires that data be
read every 5 ms, the INA231 can be configured with the conversion times set to 588 μs and the averaging mode
set to 4. This configuration results in the data updating approximately every 4.7 ms. The INA231 can also be
configured with a different conversion time setting for the shunt and bus voltage measurements. This type of
approach is common in applications where the bus voltage tends to be relatively stable. This situation allows for
the time spent measuring the bus voltage to be reduced relative to the shunt voltage measurement. The shunt
voltage conversion time can be set to 4.156 ms with the bus voltage conversion time set to 588 μs, and the
averaging mode set to 1. This configuration also results in data updating approximately every 4.7 ms.
There are trade-offs associated with the conversion time settings and the averaging mode used. The averaging
feature can significantly improve the measurement accuracy by effectively filtering the signal. This approach
allows the INA231 to reduce noise in the measurement that may be caused by noise coupling into the signal. A
greater number of averages enables the INA231 to be more effective in reducing the noise component of the
measurement.
The conversion times selected can also have an impact on the measurement accuracy; this effect can be seen in
Figure 22. Multiple conversion times are shown to illustrate the impact of noise on the measurement. In order to
achieve the highest accuracy measurement possible, use a combination of the longest allowable conversion
times and highest number of averages, based on the timing requirements of the system.
10mV/div
Conversion Time: 140ms
Conversion Time: 1.1ms
Conversion Time: 8.244ms
0
200
400
600
800
1000
Number of Conversions
Figure 22. Noise vs Conversion Time
14
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
8.5 Programming
An important aspect of the INA231 is that it does not necessarily measure current or power. The INA231
measures both the differential voltage applied between the IN+ and IN– input pins and the voltage applied to the
BUS pin. In order for the INA231 to report both current and power values, both the Current register resolution
and the value of the shunt resistor present in the application that resulted in the differential voltage being
developed must be programmed. The Power register is internally set to be 25 times the programmed least
significant bit of the Current register (Current_LSB). Both the Current_LSB and shunt resistor value are used
when calculating the Calibration register value. The INA231 uses this value to calculate the corresponding
current and power values based on the measured shunt and bus voltages.
The Calibration register is calculated based on Equation 1. This equation includes the term Current_LSB, the
programmed value for the LSB for the Current register. This is the value used to convert the value in the Current
register to the actual current in amps. The highest resolution for the Current register can be obtained by using
the smallest allowable Current_LSB based on the maximum expected current, as shown in Equation 2. While this
value yields the highest resolution, it is common to select a value for the Current_LSB to the nearest round
number above this value to simplify the conversion of the Current register and Power register to amps and watts,
respectively. RSHUNT is the value of the external shunt used to develop the differential voltage across the input
pins. The 0.00512 value in Equation 1 is an internal fixed value used to make sure that scaling is properly
maintained.
0.00512
CAL = Current_LSB · R
SHUNT
Current_LSB =
(1)
Maximum Expected Current
215
(2)
After the Calibration register has been programmed, the Current register and Power register are updated
accordingly based on the corresponding shunt voltage and bus voltage measurements. Until the Calibration
register is programmed, the Current and Power registers remain at zero.
8.5.1 Configure, Measure, and Calculate Example
In this example, shown in Figure 29, a nominal 10-A load creates a differential voltage of 20 mV across a 2-mΩ
shunt resistor. The bus voltage for the INA231 is measured at the external BUS input pin; in this example, BUS
is connected to the IN– pin to measure the voltage level delivered to the load. For this example, the BUS pin
measures less than 12 V because the voltage at the IN– pin is 11.98 V as a result of the voltage drop across the
shunt resistor.
For this example, assuming a maximum expected current of 15 A, the Current_LSB is calculated to be 457.7
μA/bit using Equation 2. Using a value of 500 μA/bit or 1 mA/bit for the Current_LSB significantly simplifies the
conversion from the Current register and Power register to amps and watts, respectively. For this example, a
value of 1 mA/bit was chosen for the Current register LSB. Using this value for the Current_LSB trades a small
amount of resolution for a simpler conversion process on the processor side. Using Equation 1 in this example
with a current LSB of 1 mA/bit and a shunt resistor of 2 mΩ results in a Calibration register value of 2560, or
A00h.
The Current register (04h) is then calculated by multiplying the decimal value of the Shunt Voltage register
contents by the decimal value of the Calibration register and then dividing by 2048, as shown in Equation 3. For
this example, the Shunt Voltage register value of 8000 is multiplied by the Calibration register value of 2560 and
then divided by 2048 to yield a decimal value for the Current register of 10000, or 2710h. Multiplying this value
by 1 mA/bit results in the original 10-A level stated in the example.
Current =
ShuntVoltage · CalibrationRegister
2048
(3)
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
15
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
Programming (continued)
The LSB for the Bus Voltage register (02h) is a fixed 1.25 mV/bit. This fixed value means that the 11.98 V
present at the BUS pin results in a register value of 2570h, or a decimal equivalent of 9584. Note that the MSB of
the Bus Voltage register is always zero because the BUS pin is only able to measure positive voltages.
The Power register (03h) is then calculated by multiplying the decimal value of the Current register, 10000, by
the decimal value of the Bus Voltage register, 9584, and then dividing by 20,000, as defined in Equation 4. For
this example, the result for the Power register is 12B8h, or a decimal equivalent of 4792. Multiplying this result by
the power LSB (25 times the [1 × 10–3 Current_LSB]) results in a power calculation of (4792 × 25 mW/bit), or
119.8 W. The Power register LSB has a fixed ratio to the Current register LSB of 25 W/bit to 1 A/bit. For this
example, a programmed Current register LSB of 1 mA/bit results in a Power register LSB of 25 mW/bit. This ratio
is internally programmed to make sure that the scaling of the power calculation is within an acceptable range. A
manual calculation for the power being delivered to the load would use a bus voltage of 11.98 V (12VCM – 20 mV
shunt drop) multiplied by the load current of 10 A to give a result of 119.8 W.
Power =
Current · BusVoltage
20,000
(4)
Table 1 shows the steps for configuring, measuring, and calculating the values for current and power for this
device.
Table 1. Configure, Measure. and Calculate Example (1)
(1)
16
STEP #
REGISTER NAME
ADDRESS
CONTENTS
DEC
LSB
VALUE
Step 1
Configuration
00h
4127h
—
—
—
Step 2
Shunt
01h
1F40h
8000
2.5 µV
20m V
Step 3
Bus
02h
2570h
9584
1.25 mV
11.98 V
Step 4
Calibration
05h
A00h
2560
—
—
Step 5
Current
04h
2710h
10000
1 mA
10 A
Step 6
Power
03h
12B8h
4792
25 mW
119.8 W
Conditions: Load = 10 A, VCM = 12 V, RSHUNT = 2 mΩ, and VBUS =11.98 V.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
8.5.2 Programming the Power Measurement Engine
8.5.2.1 Calibration Register and Scaling
The Calibration register makes it possible to set the scaling of the Current and Power registers to the values that
are most useful for a given application. One strategy may be to set the Calibration register so that the largest
possible number is generated in the Current register or Power register at the expected full-scale point. This
approach yields the highest resolution based on the previously-calculated minimum Current_LSB in the equation
for the Calibration register (Equation 1). The Calibration register can also be selected to provide values in the
Current and Power registers that either provide direct decimal equivalents of the values being measured, or yield
a round LSB value for each corresponding register. After these choices have been made, the Calibration register
also offers possibilities for end-user, system-level calibration. By physically measuring the current with an
external ammeter, the exact current is known. The value of the Calibration register can then be adjusted based
on the measured current result of the INA231 to cancel the total system error, as shown in Equation 5.
Corrected_Full_Scale_Cal = trunc
Cal ´ MeasShuntCurrent
INA231_Current
(5)
8.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)
The INA231 does not require programming to read a shunt voltage drop and the bus voltage when using the
default power-on reset configuration and running continuous conversions of the shunt and bus voltage.
Without programming the INA231 Calibration register, the device is unable to provide either a valid current or
power value because these outputs are both derived using the values loaded into the Calibration register.
8.5.4 Default INA231 Settings
The default power-up states of the registers are shown in the Register Details section of this data sheet. These
registers are volatile, and if programmed to a value other than the default values shown in Table 3, they must be
reprogrammed at every device power-up. Detailed information on programming the Calibration register is given in
the Configure/Measure/Calculate Example section and calculated based on Equation 1.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
17
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
8.5.5 Writing to and Reading from the INA231
8.5.5.1 Bus Overview
The INA231 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are
essentially compatible with one another.
The I2C interface is used throughout this data sheet as the primary example, with SMBus protocol specified only
when a difference between the two systems is discussed. Two bidirectional lines, SCL and SDA, connect the
INA231 to the bus. Both SCL and SDA are open-drain connections.
The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves.
The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access,
and generates start and stop conditions.
To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a
high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge
of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the
slave being addressed responds to the master by generating an Acknowledge bit (ACK) and pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an ACK. During data transfer, SDA must
remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a start or stop condition.
After all data have been transferred, the master generates a stop condition indicated by pulling SDA from low to
high while SCL is high. The INA231 includes a 28-ms timeout on its interface to prevent locking up the bus.
8.5.5.1.1 Serial Bus Address
In order to communicate with the INA231, the master must first address slave devices using a corresponding
slave address byte. The slave address byte consists of seven address bits and a direction bit that indicates
whether the action is to be a read or write operation.
The INA231 has two address pins: A0 and A1. Table 2 describes the pin logic levels for each of the 16 possible
addresses. The state of pins A0 and A1 is sampled on every bus communication. Set these pins before any
activity on the interface occurs.
Table 2. Address Pins and
Slave Addresses
18
A1
A0
SLAVE ADDRESS
GND
GND
1000000
GND
VS
1000001
GND
SDA
1000010
GND
SCL
1000011
VS
GND
1000100
VS
VS
1000101
VS
SDA
1000110
VS
SCL
1000111
SDA
GND
1001000
SDA
VS
1001001
SDA
SDA
1001010
SDA
SCL
1001011
SCL
GND
1001100
SCL
VS
1001101
SCL
SDA
1001110
SCL
SCL
1001111
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
8.5.5.1.2 Serial Interface
The INA231 operates only as a slave device on both the I2C bus and the SMBus. Connections to the bus are
made through the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spikesuppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. Although there is
spike suppression integrated into the digital I/O lines, use proper layout to minimize the amount of coupling into
the communication lines. This noise introduction could occur from capacitively coupling signal edges between the
two communication lines themselves or from other switching noise sources present in the system. Routing traces
in parallel with ground in between layers on a printed circuit board (PCB) typically reduces the effects of coupling
between the communication lines. Shielding communication lines in general is recommended to reduce to
possibility of unintended noise coupling into the digital I/O lines that could be incorrectly interpreted as start or
stop commands.
The INA231 supports the transmission protocol for Fast (1 kHz to 400 kHz) and High-speed (1 kHz to 2.5 MHz)
modes. All data bytes are transmitted most significant byte first.
Accessing a specific register on the INA231 is accomplished by writing the appropriate value to the register
pointer. Refer to Table 3 for a complete list of registers and corresponding addresses. The value for the register
pointer (shown in Figure 26) is the first byte transferred after the slave address byte with the R/W bit low. Every
write operation to the INA231 requires a value for the register pointer.
Writing to a register begins with the first byte transmitted by the master. This byte is the slave address, with the
R/W bit low. The INA231 then acknowledges receipt of a valid address. The next byte transmitted by the master
is the address of the register that data are written to. This register address value updates the register pointer to
the desired register. The next two bytes are written to the register addressed by the register pointer. The INA231
acknowledges receipt of each data byte. The master may terminate data transfer by generating a start or stop
condition.
When reading from the INA231, the last value stored in the register pointer by a write operation determines
which register is read during a read operation. To change the register pointer for a read operation, a new value
must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/W
bit low, followed by the register pointer byte. No additional data are required. The master then generates a start
condition and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is
transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte
is followed by an ACK from the master; then the slave transmits the least significant byte. The master
acknowledges receipt of the data byte. The master may terminate data transfer by generating a NotAcknowledge bit (No ACK) after receiving any data byte, or generating a start or stop condition. If repeated reads
from the same register are desired, it is not necessary to continually send the register pointer bytes; the INA231
retains the register pointer value until it is changed by the next write operation.
Figure 23 and Figure 24 show the write and read operation timing diagrams, respectively. Note that register
bytes are sent most-significant byte first, followed by the least significant byte.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
19
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
1
9
www.ti.com
9
1
9
1
9
1
SCL
SDA
1
0
0
A3
A2
A1
A0
R/W
Start By
Master
P7
P6
P5
P4
P3
P2
P1
Frame 1 Two-Wire Slave Address Byte
(1)
D15 D14
P0
ACK By
INA231
D13
D12 D11 D10
D9
D8
(1)
D7
D6
D5
D4
D3
D2
D1
D0
ACK By
INA231
ACK By
INA231
Frame 2 Register Pointer Byte
ACK By
INA231
Frame 3 Data MSByte
Stop By
Master
Frame 4 Data LSByte
The value of the slave address byte is determined by the settings of the A0 and A1 pins. Refer to Table 2.
Figure 23. Timing Diagram for Write Word Format
1
9
1
1
9
9
SCL
SDA
0
1
0
A3
A2
A1
R/W
A0
Start By
Master
D15 D14
D13
D12
D11 D10
Frame 1 Two-Wire Slave Address Byte
D9
D7
D8
From
INA231
ACK By
INA231
(1)
Frame 2 Data MSByte
D6
D5
D4
D3
D2
D1
From
INA231
ACK By
Master
(2)
D0
No ACK By
Master
Frame 3 Data LSByte
(3)
Stop
(2)
(1)
The value of the slave address byte is determined by the settings of the A0 and A1 pins. Refer to Table 2.
(2)
Read data are from the last register pointer location. If a new register is desired, the register pointer must be updated.
See Figure 26.
(3)
ACK by Master can also be sent.
Figure 24. Timing Diagram for Read Word Format
Figure 25 shows the timing diagram for the SMBus alert response operation. Figure 26 illustrates a typical
register pointer configuration.
ALERT
1
9
1
9
SCL
SDA
0
0
0
1
1
0
0
R/W
Start By
Master
1
0
A3
A2
ACK By
INA231
A1
A0
0
From
INA231
Frame 1 SMBus ALERT Response Address Byte
(1)
0
Frame 2 Slave Address Byte
NACK By
Master
Stop By
Master
(1)
The slave address byte value is determined by the settings of the A0 and A1 pins. Refer to Table 2.
Figure 25. Timing Diagram for SMBus Alert
1
9
1
9
SCL
¼
SDA
1
0
0
A3
A2
A1
A0
R/W
Start By
Master
Frame 1 Two-Wire Slave Address Byte
(1)
P7
P6
P5
P4
P3
P2
P1
ACK By
INA231
(1)
P0
Stop
ACK By
INA231
Frame 2 Register Pointer Byte
The slave address byte value is determined by the settings of the A0 and A1 pins. Refer to Table 2.
Figure 26. Typical Register Pointer Set
20
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
8.5.5.2 High-Speed I2C Mode
When the bus is idle, both the SDA and SCL lines are pulled high by the pull-up devices. The master generates
a start condition followed by a valid serial byte containing High-Speed (HS) master code 00001XXX. This
transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The INA231
does not acknowledge the HS master code, but does recognize it and switches its internal filters to support 2.5MHz operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S mode except that transmission
speeds up to 2.5 MHz are allowed. Instead of using a stop condition, use repeated start conditions to secure the
bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the INA231 to support
the F/S mode. A bus timing diagram is shown in Figure 1.
8.5.6 SMBus Alert Response
The INA231 is designed to respond to the SMBus alert response address. The SMBus alert response provides a
quick fault identification for simple slave devices. When an alert occurs, the master can broadcast the alert
response slave address (0001 100) with the Read/Write bit set high. Following this alert response, any slave
devices that generated an alert identify themselves by acknowledging the alert response and sending their
respective address on the bus.
The alert response can activate several different slave devices simultaneously, similar to the I2C general call. If
more than one slave attempts to respond, bus arbitration rules apply. The losing device does not generate an
acknowledge and continues to hold the ALERT line low until the interrupt is cleared.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
21
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
8.6 Register Maps
The INA231 uses a bank of registers for holding configuration settings, measurement results, minimum/maximum
limits, and status information. Table 3 summarizes the INA231 registers; refer to Figure 20 for an illustration of
the registers.
All 16-bit INA231 registers are two 8-bit bytes through the I2C interface.
Table 3. Summary of Register Set
POINTER
ADDRESS
HEX
(1)
(2)
22
POWER-ON RESET
REGISTER NAME
FUNCTION
BINARY
HEX
TYPE (1)
01000001 00100111
4127
R/W
00
Configuration
This register resets all registers and
controls shunt voltage and bus voltage,
ADC conversion times and averaging,
as well as the device operating mode.
01
Shunt Voltage
Shunt voltage measurement data
00000000 00000000
0000
R
02
Bus Voltage
Bus voltage measurement data
00000000 00000000
0000
R
00000000 00000000
0000
R
03
Power (2)
This register contains the value of the
calculated power being delivered to the
load.
04
Current (2)
This register contains the value of the
calculated current flowing through the
shunt resistor.
00000000 00000000
0000
R
05
Calibration
This register sets the full-scale range
and LSB of the current and power
measurements. This register sets the
overall system calibration.
00000000 00000000
0000
R/W
06
Mask/Enable
This register sets the alert configuration
and conversion ready flag.
00000000 00000000
0000
R/W
07
Alert Limit
This register contains the limit value to
compare to the selected alert function.
00000000 00000000
0000
R/W
Type: R = read-only, R/W = read/write.
The Current register defaults to '0' because the Calibration register defaults to '0', yielding a zero current and power value until the
Calibration register is programmed.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
8.6.1 Configuration Register (00h, Read/Write)
Table 4. Configuration Register (00h, Read/Write) Descriptions
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
RST
—
—
—
AVG2
AVG1
AVG0
VBUSCT2
VBUSCT1
VBUSCT0
VSHCT2
VSHCT1
VSHCT0
MODE3
MODE2
MODE1
POR
VALUE
0
1
0
0
0
0
0
1
0
0
1
0
0
1
1
1
The Configuration register settings control the operating modes for the INA231. This register controls the
conversion time settings for both the shunt and bus voltage measurements, as well as the averaging mode used.
The operating mode that controls which signals are selected to be measured is also programmed in the
Configuration register.
The Configuration register can be read from at any time without impacting or affecting the device settings or a
conversion in progress. Writing to the Configuration register halts any conversion in progress until the write
sequence is complete, resulting in the start of a new conversion based on the new contents of the Configuration
register. This feature prevents any uncertainty in the conditions used for the next completed conversion.
RST:
Reset Bit
Bit 15
Setting this bit to 1 generates a system reset that is the same as a power-on reset; all registers are reset to default
values. This bit self-clears.
AVG:
Averaging Mode
Bits 9–11
These bits set the number of samples that are collected and averaged together. Table 5 summarizes the AVG bit
settings and related number of averages for each bit.
8.6.1.1 AVG Bit Settings [11:9]
Table 5. AVG Bit Settings [11:9] (1) Description
(1)
AVG2
(D11)
AVG1
(D10)
AVG0
(D9)
NUMBER OF
AVERAGES
0
0
0
1
0
0
1
4
0
1
0
16
0
1
1
64
1
0
0
128
1
0
1
256
1
1
0
512
1
1
1
1024
Shaded values are default.
VBUS CT:
Bus Voltage Conversion Time
Bits 6–8
These bits set the conversion time for the bus voltage measurement. Table 6 shows the VBUS CT bit options and
related conversion times for each bit.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
23
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
8.6.1.2 VBUS CT Bit Settings [8:6]
Table 6. VBUS CT Bit Settings [8:6] (1) Description
(1)
VBUS CT2
(D8)
VBUS CT1
(D7)
VBUS CT0
(D6)
CONVERSION TIME
0
0
0
140 µs
0
0
1
204 µs
0
1
0
332 µs
0
1
1
588 µs
1
0
0
1.1 ms
1
0
1
2.116 ms
1
1
0
4.156 ms
1
1
1
8.244 ms
Shaded values are default.
VSH CT:
Shunt Voltage Conversion Time
Bits 3–5
These bits set the conversion time for the shunt voltage measurement. Table 7 shows the
VSH CT bit options and related conversion times for each bit.
8.6.1.3 VSH CT Bit Settings [5:3]
Table 7. Register Description VSH CT Bit Settings [5:3] (1)
(1)
VSH CT2
(D5)
VSH CT1
(D4)
VSH CT0
(D3)
CONVERSION TIME
0
0
0
140 µs
0
0
1
204 µs
0
1
0
332 µs
0
1
1
588 µs
1
0
0
1.1 ms
1
0
1
2.116 ms
1
1
0
4.156 ms
1
1
1
8.244 ms
Shaded values are default.
MODE:
Operating Mode
Bits 0–2
These bits select continuous, triggered, or power-down mode of operation. These bits default to continuous shunt
and bus measurement mode. The mode settings are shown in Table 8.
8.6.1.4 Mode Settings [2:0]
Table 8. Mode Settings [2:0] (1)
(1)
24
MODE3
(D2)
MODE2
(D1)
MODE1
(D0)
MODE
0
0
0
Power-down
0
0
1
Shunt voltage, triggered
0
1
0
Bus voltage, triggered
0
1
1
Shunt and bus, triggered
1
0
0
Power-down
1
0
1
Shunt voltage, continuous
1
1
0
Bus voltage, continuous
1
1
1
Shunt and bus, continuous
Shaded values are default.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
8.6.2 Shunt Voltage Register (01h, Read-Only)
The Shunt Voltage register stores the current shunt voltage reading, VSHUNT. Negative numbers are represented
in twos complement format. Generate the two's complement of a negative number by complementing the
absolute value binary number and adding 1. Extend the sign, denoting a negative number by setting the MSB =
1.
Example: For a value of VSHUNT = –80 mV:
1. Take the absolute value: 80mV
2. Translate this number to a whole decimal number (80 mV ÷ 2.5 µV) = 32000
3. Convert this number to binary = 111 1101 0000 0000
4. Complement the binary result = 000 0010 1111 1111
5. Add '1' to the complement to create the two's complement result = 000 0011 0000 0000
6. Extend the sign and create the 16-bit word: 1000 0011 0000 0000 = 8300h
This register displays the averaged value if averaging is enabled. Full-scale range = 81.9175 mV (decimal =
7FFF); LSB: 2.5 μV.
Table 9. Shunt Voltage Register (01h, Read-Only) Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
SIGN
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8.6.3 Bus Voltage Register (02h, Read-Only)
The Bus Voltage register stores the most recent bus voltage reading, VBUS.
This register displays the averaged value if averaging is enabled. Full-scale range = 40.95875 V (decimal =
7FFF); LSB = 1.25 mV. Do not apply more than 28 V on the BUS pin.
Table 10. Bus Voltage Register (02h, Read-Only) (1) Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
—
BD14
BD13
BD12
BD11
BD10
BD9
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(1)
D15 is always zero because bus voltage can only be positive.
8.6.4 Power Register (03h, Read-Only)
This register displays the averaged value if averaging is enabled.
Table 11. Power Register (03h, Read-Only) Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The Power register LSB is internally programmed to equal 25 times the programmed value of the Current_LSB.
The Power register records power in watts by multiplying the decimal values of the current register with the
decimal value of the bus voltage register according to Equation 4.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
25
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
8.6.5 Current Register (04h, Read-Only)
If averaging is enabled, this register displays the averaged value.
Table 12. Current Register (04h, Read-Only) Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
CSIGN
CD14
CD13
CD12
CD11
CD10
CD9
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The value of the Current register is calculated by multiplying the decimal value in the Shunt Voltage register with
the decimal value of the Calibration register, according to Equation 3.
8.6.6 Calibration Register (05h, Read/Write)
This register provides the INA231 with the shunt resistor value that was present to create the measured
differential voltage. This register also sets the resolution of the Current register. The Current register LSB and
Power register LSB are set through the programming of this register. This register is also used for overall system
calibration. See the Configure, Measure, and Calculate Example for more information on programming this
register.
Table 13. Calibration Register (05h, Read/Write) Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
—
FS14
FS13
FS12
FS11
FS10
FS9
FS8
FS7
FS6
FS5
FS4
FS3
FS2
FS1
FS0
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8.6.7 Mask/Enable Register (06h, Read/Write)
The Mask/Enable register selects the function that controls the ALERT pin, as well as how that pin functions. If
multiple functions are enabled, the highest significant bit position alert function (D15:D11) takes priority and
responds to the Alert Limit register.
Table 14. Mask/Enable Register (06h, Read/Write) Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
SOL
SUL
BOL
BUL
POL
CNVR
—
—
—
—
—
AFF
CVRF
OVF
APOL
LEN
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOL:
Shunt Voltage Overvoltage1
Bit 15
Setting this bit high configures the ALERT pin to be asserted when the shunt voltage conversion exceeds the value
in the Alert Limit register.
SUL:
Shunt Voltage Undervoltage
Bit 14
Setting this bit high configures the ALERT pin to be asserted when the shunt voltage conversion drops below the
value in the Alert Limit register.
BOL:
Bus Voltage Overvoltage
Bit 13
Setting this bit high configures the ALERT pin to be asserted when the bus voltage conversion exceeds the value in
the Alert Limit register.
BUL:
Bus Voltage Undervoltage
Bit 12
Setting this bit high configures the ALERT pin to be asserted when the bus voltage conversion drops below the
value in the Alert Limit register.
26
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
POL:
Power Overlimit
Bit 11
Setting this bit high configures the ALERT pin to be asserted when the power calculation exceeds the value in the
Alert Limit register.
CNVR:
Conversion Ready
Bit 10
Setting this bit high configures the ALERT pin to be asserted when the Conversion Ready Flag bit (CVRF, bit 3) is
asserted, indicating that the device is ready for the next conversion.
AFF:
Alert Function Flag
Bit 4
Although only one alert function at a time can be monitored at the ALERT pin, the Conversion Ready bit (CNVR, bit
10) can also be enabled to assert the ALERT pin. Reading the Alert Function Flag bit after an alert can help
determine if the alert function was the source of the alert.
When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag bit clears only when the Mask/Enable
register is read. When the Alert Latch Enable bit is set to Transparent mode, the Alert Function Flag bit is cleared
after the next conversion that does not result in an alert condition.
CVRF:
Conversion Ready Flag
Bit 3
Although the INA231 can be read at any time, and the data from the last conversion are available, this bit is
provided to help coordinate single-shot or triggered conversions. This bit is set after all conversions, averaging, and
multiplications are complete. This bit clears under the following conditions in single-shot mode:
1) Writing to the Configuration register (except for power-down or disable selections)
2) Reading the Mask/Enable register
OVF:
Math Overflow Flag
Bit 2
This bit is set to 1 if an arithmetic operation results in an overflow error; it indicates that current and power data may
be invalid.
APOL:
Alert Polarity
Bit 1
Configures the latching feature of the ALERT pin and the flag bits.
1 = Inverted (active-high open collector)
0 = Normal (active-low open collector) (default)
LEN:
Alert Latch Enable
Bit 0
Configures the latching feature of the ALERT pin and flag bits.
1 = Latch enabled
0 = Transparent (default)
When the Alert Latch Enable bit is set to Transparent mode, the ALERT pin and flag bits reset to their idle states
when the fault has been cleared. When the Alert Latch Enable bit is set to Latch mode, the ALERT pin and flag bits
remain active following a fault until the Mask/Enable register has been read.
8.6.8 Alert Limit Register (07h, Read/Write)
The Alert Limit register contains the value used to compare to the register selected in the Mask/Enable register
to determine if a limit has been exceeded.
Table 15. Alert Limit Register (07h, Read/Write) Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
AUL15
AUL14
AUL13
AUL12
AUL11
AUL10
AUL9
AUL8
AUL7
AUL6
AUL5
AUL4
AUL3
AUL2
AUL1
AUL0
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
27
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The INA231 is a digital current shunt monitor with an I2C- and SMBus-compatible interface. This device provides
digital current, voltage, and power readings necessary for accurate decision-making in precisely-controlled
systems. Programmable registers allow flexible configuration for measurement resolution, as well as continuousversus-triggered operation. Detailed register information appears towards the end of this data sheet, beginning
with Table 3. See Figure 20 for a block diagram of the INA231.
Figure 27 shows a typical application circuit for the INA231. For power-supply bypassing, place a 0.1-μF ceramic
capacitor as close as possible to the supply and ground pins.
Power Supply
(0 V to 28 V)
CBYPASS
0.1 mF
VS
(Supply Voltage)
BUS
HighSide
Shunt
INA231
SDA
SCL
´
Load
Power Register
V
2
IC
Interface
Current Register
ADC
LowSide
Shunt
I
ALERT
Voltage Register
A0
A1
Alert Register
GND
Figure 27. High- or Low-Side Sensing
9.1.1 Filtering and Input Considerations
Measuring current is often a noisy task, and such noise can be difficult to define. The INA231 offers several
options for filtering by allowing the conversion times and number of averages to be independently selected in the
Configuration register. The conversion times can be independently set for the shunt voltage and bus voltage
measurements to allow added flexibility in configuring the monitoring of the power-supply bus.
The internal ADC is based on a delta-sigma (ΔΣ) front-end with a 500-kHz (±30%) typical sampling rate. This
architecture has good inherent noise rejection; however, transients that occur at or very close to the sampling
rate harmonics can cause problems. These signals are at 1 MHz and higher; therefore, manage them by
incorporating filtering at the input of the INA231. The high frequency enables the use of low-value series resistors
on the filter with negligible effects on measurement accuracy. In general, filtering the INA231 input is only
necessary if there are transients at exact harmonics of the 500-kHz (±30%) sampling rate (greater than 1 MHz).
Filter using the lowest possible series resistance (typically 10 Ω or less) and a ceramic capacitor. Recommended
values for this capacitor are 0.1 μF to 1.0 μF. Figure 28 shows the INA231 with an additional filter added at the
input.
28
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
Application Information (continued)
Power Supply
(0 V to 28 V)
CBYPASS
0.1 mF
VS
(Supply Voltage)
BUS
CFILTER
0.1 mF to 1 mF
Ceramic
Capacitor
SDA
SCL
´
RFILTER
£10 W
IN+
Power Register
V
2
Current Register
ADC
I
Load
RFILTER
£10 W
Voltage Register
IC
Interface
ALERT
A0
INAlert Register
A1
GND
Figure 28. INA231 With Input Filtering
Overload conditions are another consideration for the INA231 inputs. The INA231 inputs are specified to tolerate
30 V across the inputs. A large differential scenario might be a short to ground on the load side of the shunt. This
type of event can result in full power-supply voltage across the shunt (as long as the power supply or energy
storage capacitors support it). Keep in mind that removing a short to ground can result in inductive kickbacks that
could exceed the 30-V differential and common-mode rating of the INA231. Inductive kickback voltages are best
controlled by zener-type transient-absorbing devices (commonly called transzorbs) combined with sufficient
energy storage capacitance.
In applications that do not have large energy-storage electrolytics on one or both sides of the shunt, an input
overstress condition may result from an excessive dV/dt of the voltage applied to the input. A hard physical short
is the most likely cause of this event, particularly in applications with no large electrolytics present. This problem
occurs because an excessive dV/dt can activate the ESD protection in the INA231 in systems where large
currents are available. Testing has demonstrated that the addition of 10-Ω resistors in series with each input of
the INA231 sufficiently protect the inputs against this dV/dt failure up to the 30-V rating of the INA231. Selecting
these resistors in the range noted has minimal effect on accuracy.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
29
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
9.2 Typical Applications
+12-V Supply
CBYPASS
0.1 mF
VS
(Supply Voltage)
BUS
SDA
SCL
´
IN+
Power Register
V
2
IC
Interface
Current Register
ADC
RSHUNT
2 mW
I
ALERT
Voltage Register
A0
IN-
A1
Alert Register
10A
Load
GND
Figure 29. Monitoring a 10-A Load
9.2.1 Design Requirements
The INA231 measures the voltage developed across a current-sensing resistor (RSHUNT) when current passes
through the resistor. The device also measures the bus supply voltage, and calculates power when calibrated.
The INA231 comes with alert capability, where the alert pin can be programmed to respond to a user-defined
event, or to a conversion-ready notification. This design illustrates the ability of the alert pin to respond to a set
threshold. In this case, a 10 A are pulled through a 2-mΩ shunt resistor, generating a 20-mV shunt voltage drop
that is measured by the INA231. The bus supply is 12 V, and the BUS pin is tied to the IN– pin, so that the
power loss through the shunt resistor, however small, is not added to the power calculation performed by the
INA231. This configuration provides an accurate measurement the power dissipated by the load.
9.2.2 Detailed Design Procedure
The ALERT pin can be configured to respond to one of the five alert functions described in the ALERT Pin
section. The ALERT pin must to be pulled up to the VS pin voltage using a pull-up resistor. The Configuration
register is set based on the required conversion time and averaging. The Mask/Enable register is set to identify
the required alert function and the Alert Limit register is set to the limit value used for comparison.
9.2.3 Application Curves
Figure 30 shows the ALERT pin response to a shunt overvoltage of 50 mV for a conversion time (tCT) of 140 μs.
and averaging set to 1. Figure 31 shows the response for the same limit, but with the conversion time reduced to
1.1 ms.
30
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
SHUNT Voltage
(50 mV/div)
SHUNT Voltage
(50 mV/div)
ALERT
(2 V/div)
ALERT
(2 V/div)
Typical Applications (continued)
Time (100 µs/div)
Time (1 ms/div)
Configuration register = 4005h
Mask/Enable register = 8008h
Alert Limit register = 4E20h,
tCT = 140 µs
Configuration register = 4125h
Mask/Enable register = 8008h
Alert Limit register = 4E20h,
tCT = 1.1 ms
Figure 30. Alert Response
Figure 31. Alert Response
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
31
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
10 Power Supply Recommendations
The INA231 input circuitry accurately measures signals on common-mode voltages beyond the device powersupply voltage, VS. For example, the voltage applied to the power-supply pin (VS) can be 5 V; however, the load
power-supply voltage being monitored (the common-mode voltage) can be as high as 28 V. The device can also
withstand the full 0-V to 28-V range at the input terminals, regardless of whether the device has power applied or
not.
Place the required power-supply bypass capacitors as close as possible to the supply and ground pins of the
device. A typical value for this supply bypass capacitor is 0.1 μF. For more accurate results for applications with
noisy or high-impedance power supplies, use additional decoupling capacitors to reject power-supply noise.
11 Layout
11.1 Layout Guidelines
Connect the input pins (IN+ and IN–) to the sensing resistor using a Kelvin or 4-wire connection. These
connection techniques make sure that only the current-sensing resistor impedance is detected between the input
pins. Poor routing of the current-sensing resistor commonly results in additional resistance present between the
input pins. Given the very low ohmic value of the current-sensing resistor, any additional high-current-carrying
impedance causes significant measurement errors. Place the power-supply bypass capacitor as close as
possible to the supply and ground pins. Make sure the NC pins (B2 and C2) are not connected to anything.
11.2 Layout Example
Tie to GND, VS,
SCL, or SDA to set
I2C address
RPULLUP
VIA to another layer
A0
A1
IN+
SDA
NC
NC
IN-
SCL
VS
GND
BUS
RPULLUP
RPULLUP
I2C/SMBUS
interface
ALERT
RSHUNT
Alert output
(Can be left floating
if unused)
VIA to GND
CBYPASS
VIA to another layer
Connect to supply for VS
Figure 32. Layout Example
32
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
INA231
www.ti.com
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: INA231
33
PACKAGE OPTION ADDENDUM
www.ti.com
7-Feb-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
INA231AIYFDR
ACTIVE
DSBGA
YFD
12
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
I231YFD
INA231AIYFDT
ACTIVE
DSBGA
YFD
12
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
I231YFD
INA231AIYFFR
ACTIVE
DSBGA
YFF
12
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
INA231
INA231AIYFFT
ACTIVE
DSBGA
YFF
12
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
INA231
INA231BIYFDR
PREVIEW
DSBGA
YFD
12
3000
TBD
Call TI
Call TI
-40 to 125
INA231BIYFDT
PREVIEW
DSBGA
YFD
12
250
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Feb-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
INA231AIYFDR
DSBGA
YFD
12
3000
180.0
8.4
INA231AIYFDT
DSBGA
YFD
12
250
180.0
INA231AIYFFR
DSBGA
YFF
12
3000
180.0
INA231AIYFFT
DSBGA
YFF
12
250
180.0
1.49
1.76
0.5
4.0
8.0
Q1
8.4
1.49
1.76
0.5
4.0
8.0
Q1
8.4
1.48
1.78
0.69
4.0
8.0
Q1
8.4
1.48
1.78
0.69
4.0
8.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
INA231AIYFDR
DSBGA
YFD
12
3000
182.0
182.0
20.0
INA231AIYFDT
DSBGA
YFD
12
250
182.0
182.0
20.0
INA231AIYFFR
DSBGA
YFF
12
3000
182.0
182.0
20.0
INA231AIYFFT
DSBGA
YFF
12
250
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0012
DSBGA - 0.625 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
0.625 MAX
C
SEATING PLANE
BALL TYP
0.30
0.12
0.05 C
0.8 TYP
0.4 TYP
D
SYMM
C
1.2
TYP
B
D: Max = 1.675 mm, Min =1.614 mm
E: Max = 1.418 mm, Min =1.358 mm
A
12X
0.015
0.3
0.2
C A
1
2
3
0.4 TYP
SYMM
B
4222191/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0012
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
12X ( 0.23)
1
2
3
A
(0.4) TYP
B
SYMM
C
D
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
( 0.23)
METAL
METAL UNDER
SOLDER MASK
0.05 MIN
( 0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222191/A 07/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0012
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
12X ( 0.25)
(R0.05) TYP
1
2
3
A
(0.4) TYP
B
SYMM
METAL
TYP
C
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4222191/A 07/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
YFD0012
DSBGA - 0.4 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
0.4 MAX
C
SEATING PLANE
0.175
0.125
BALL TYP
0.05 C
0.8
TYP
SYMM
D
1.2
TYP
C
SYMM
D: Max = 1.675 mm, Min =1.614 mm
B
0.4
TYP
12X
0.015
0.243
0.226
C A B
E: Max = 1.418 mm, Min =1.358 mm
A
2
1
3
0.4
TYP
4223364/A 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFD0012
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
12X ( 0.225)
A
(0.4) TYP
B
SYMM
C
D
1
2
3
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MAX
( 0.225)
METAL
METAL UNDER
SOLDER MASK
0.05 MIN
( 0.225)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223364/A 10/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFD0012
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
12X ( 0.25)
A
(0.4)
TYP
B
SYMM
METAL
TYP
C
D
1
2
SYMM
3
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4223364/A 10/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated