Preliminary GS816018/32/36T-250/225/200/166/150/133 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect (SCD) operation • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package Pipeline 3-1-1-1 3.3 V 2.5 V Flow Through 2-1-1-1 3.3 V 2.5 V tKQ tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) -250 -225 -200 -166 -150 -133 Unit 2.5 2.7 3.0 3.4 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.7 7.5 ns 280 330 275 320 255 300 250 295 230 270 230 265 200 230 195 225 185 215 180 210 165 190 165 185 mA mA mA mA tKQ tCycle 5.5 5.5 6.0 6.0 6.5 6.5 7.0 7.0 7.5 7.5 8.5 8.5 ns ns Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) 175 200 175 200 165 190 165 190 160 180 160 180 150 170 150 170 145 165 145 165 135 150 135 150 mA mA mA mA Functional Description 250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS816018/32/36T operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible. Applications The GS816018/32/36T is an 18,874,368-bit (16,777,216-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst Rev: 2.12 3/2002 1/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 A6 A7 E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9 GS816018 100-Pin TQFP Pinout VDDQ LBO A5 A4 VSS NC NC DQB1 DQB2 VSS VDDQ DQB3 DQB4 FT VDD NC VSS DQB5 DQB6 VDDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 2.12 3/2002 A19 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC A3 A2 A1 A0 NC NC VSS VDD A18 A17 A10 A11 A12 A13 A14 A15 A16 NC NC NC 2/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9 GS816032 100-Pin TQFP Pinout VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 LBO A5 A4 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 2.12 3/2002 NC DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 NC A3 A2 A1 A0 NC NC VSS VDD A18 A17 A10 A11 A12 A13 A14 A15 A16 NC DQC8 DQC7 VDDQ 3/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9 GS816036 100-Pin TQFP Pinout VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 LBO A5 A4 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 DQD9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 2.12 3/2002 DQB9 DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 DQA9 A3 A2 A1 A0 NC NC VSS VDD A18 A17 A10 A11 A12 A13 A14 A15 A16 DQC9 DQC8 DQC7 VDDQ 4/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 TQFP Pin Description Pin Location Symbol Type Description 37, 36 A0, A1 I Address field LSBs and Address Counter preset Inputs 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43, 42 A2–A18 I Address Inputs 80 A19 I Address Inputs (x18 versions) 63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 13, 12, 9, 8, 7, 6, 3, 2 18, 19, 22, 23, 24, 25, 28, 29 DQA1–DQA8 DQB1–DQB8 DQC1–DQC8 DQD1–DQD8 I/O Data Input and Output pins (x32, x36 Version) 51, 80, 1, 30 DQA9, DQB9, DQC9, DQD9 I/O Data Input and Output pins (x36 Version) 51, 80, 1, 30 NC 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 DQA1–DQA9 DQB1–DQB9 I/O Data Input and Output pins (x18 Version) 51, 52, 53, 56, 57 75, 78, 79, 95, 96, 1, 2, 3, 6, 7, 25, 28, 29, 30 NC — No Connect (x18 Version) 87 BW I Byte Write—Writes all enabled bytes; active low 93, 94 BA, BB I Byte Write Enable for DQA, DQB Data I/Os; active low 95, 96 BC, BD I Byte Write Enable for DQC, DQD Data I/Os; active low (x32, x36 Version) 89 CK I Clock Input Signal; active high 88 GW I Global Write Enable—Writes all bytes; active low 98, 92 E1, E3 I Chip Enable; active low 97 E2 I Chip Enable; active high 86 G I Output Enable; active low 83 ADV I Burst address counter advance enable; active low 84, 85 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low 64 ZZ I Sleep Mode control; active high 14 FT I Flow Through or Pipeline mode; active low 31 LBO I Linear Burst Order mode; active low 15, 41, 65, 91 VDD I Core power supply 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS I I/O and Core Ground 4, 11, 20, 27, 54, 61, 70, 77 VDDQ I Output driver power supply 16, 38, 39, 66 NC — No Connect Rev: 2.12 3/2002 No Connect (x32 Version) 5/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 GS816018/32/36 Block Diagram Register A0–An D Q A0 A0 D0 Q0 A1 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q Register D 36 Q BB 36 4 Register D Q D Q Q D D Register Register Q Register BC BD Register D Q Register E1 E2 E3 D Q Register D Q FT G ZZ 1 Power Down DQx1–DQx9 Control Note: Only x36 version shown for simplicity. Rev: 2.12 3/2002 6/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ State Function L Linear Burst H Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB Note: There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Interleaved Burst Sequence Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 2.12 3/2002 7/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L H H H H 1 Write byte a H L L H H H 2, 3 Write byte b H L H L H H 2, 3 Write byte c H L H H L H 2, 3, 4 Write byte d H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 2.12 3/2002 8/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Synchronous Truth Table Operation Address Used State Diagram Key5 E1 E2 Deselect Cycle, Power Down None X H X X Deselect Cycle, Power Down None X L F Deselect Cycle, Power Down None X L Read Cycle, Begin Burst External R Read Cycle, Begin Burst External Write Cycle, Begin Burst ADV W3 DQ4 L X X High-Z L X X X High-Z F H L X X High-Z L T L X X X Q R L T H L X F Q External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend Burst Current H X X H H T D ADSP ADSC Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 2.12 3/2002 9/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write CW First Read CR CR W X R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 2.12 3/2002 10/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 2.12 3/2002 11/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to 4.6 V VCK Voltage on Clock Input Pin –0.5 to 6 V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V IIN Input Current on Any Pin +/–20 mA IOUT Output Current on Any I/O Pin +/–20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature –55 to 125 o C TBIAS Temperature Under Bias –55 to 125 o C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Rev: 2.12 3/2002 12/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Power Supply Voltage Ranges Parameter Symbol Min. Typ. Max. Unit 3.3 V Supply Voltage VDD3 3.0 3.3 3.6 V 2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V 3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. VDDQ3 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 2.0 — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.8 V 1 VDDQ I/O Input High Voltage VIHQ 2.0 — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ –0.3 — 0.8 V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. VDDQ2 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ –0.3 — 0.3*VDD V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Rev: 2.12 3/2002 13/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Recommended Operating Temperatures Parameter Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 2 Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C 2 Note: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS 50% 50% VDD VSS – 2.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. Package Thermal Characteristics Rating Layer Board Symbol Max Unit Notes Junction to Ambient (at 200 lfm) single RΘJA 40 °C/W 1,2 Junction to Ambient (at 200 lfm) four RΘJA 24 °C/W 1,2 RΘJC Junction to Case (TOP) — 9 °C/W 3 Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 2.12 3/2002 14/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 AC Test Conditions Parameter Conditions VDD – 0.2 V Input high level Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 30pF* 50Ω VDDQ/2 * Distributed Test Jig Capacitance DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IIN1 VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH –1 uA –1 uA 1 uA 100 uA FT Input Current IIN2 VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL –100 uA –1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V — Output High Voltage VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V — Output Low Voltage VOL IOL = 8 mA — 0.4 V Rev: 2.12 3/2002 15/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Rev: 2.12 3/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 16/28 — Device Deselected; All other inputs ≥ VIH or ≤ VIL Deselect Current 165 10 IDD IDD 60 85 IDD Pipeline Flow Through 20 ISB 20 ISB Pipeline Flow Through 165 10 260 15 180 20 IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD Flow Through Pipeline Flow Through Pipeline 290 30 260 20 IDD IDDQ Pipeline IDDQ 180 20 IDD IDDQ Flow Through Flow Through 290 40 0 to 70°C IDD IDDQ Symbol Pipeline Mode 65 90 30 30 175 10 270 15 190 20 300 30 175 10 270 20 190 20 300 40 –40 to 85°C -250 60 80 20 20 155 10 235 15 170 20 265 30 155 10 235 20 170 20 265 35 65 85 30 30 165 10 245 15 180 20 275 30 165 10 245 20 180 20 275 35 –40 to 85°C -225 0 to 70°C Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. — ZZ ≥ VDD – 0.2 V (x18) (x32/ x36) (x18) (x32/ x36) Standby Current 2.5 V Operating Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open Device Selected; All other inputs ≥VIH or ≤ VIL Output open Operating Current 3.3 V Test Conditions Parameter Operating Currents 50 75 20 20 150 10 215 15 165 15 240 25 150 10 215 15 165 15 240 30 0 to 70°C 55 80 30 30 160 10 225 15 175 15 250 25 160 10 225 15 175 15 250 30 –40 to 85°C -200 50 64 20 20 140 10 185 10 155 15 205 20 140 10 185 15 155 15 205 25 0 to 70°C 55 70 30 30 150 10 195 10 165 15 215 20 150 10 195 15 165 15 215 25 –40 to 85°C -166 50 60 20 20 135 10 170 10 150 15 190 20 135 10 170 15 150 15 190 25 0 to 70°C 55 65 30 30 145 10 180 10 160 15 200 20 145 10 180 15 160 15 200 25 –40 to 85°C -150 45 50 20 20 125 10 155 10 140 10 170 15 125 10 155 10 140 10 170 20 0 to 70°C 50 55 30 30 135 10 165 10 150 10 180 15 135 10 165 10 150 10 180 20 –40 to 85°C -133 mA mA mA mA mA mA mA mA mA mA mA mA Unit Preliminary GS816018/32/36T-250/225/200/166/150/133 © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 AC Electrical Characteristics Pipeline Flow Through Parameter Symbol Clock Cycle Time -250 -225 -200 -166 -150 -133 Unit Min Max Min Max Min Max Min Max Min Max Min Max tKC 4.0 — 4.4 — 5.0 — 6.0 — 6.7 — 7.5 — ns Clock to Output Valid tKQ — 2.5 — 2.7 — 3.0 — 3.4 — 3.8 — 4.0 ns Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns 1 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in Low-Z tLZ Setup time tS 1.2 — 1.3 — 1.4 — 1.5 — 1.5 — 1.5 — ns Hold time tH 0.2 — 0.3 — 0.4 — 0.5 — 0.5 — 0.5 — ns Clock Cycle Time tKC 5.5 — 6.0 — 6.5 — 7.0 — 7.5 — 8.5 — ns Clock to Output Valid tKQ — 5.5 — 6.0 — 6.5 — 7.0 — 7.5 — 8.5 ns Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Clock to Output in Low-Z tLZ1 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.5 — 1.7 — ns Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.7 — 2 — ns Clock to Output in High-Z tHZ1 1.5 2.3 1.5 2.5 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns G to Output Valid tOE — 2.3 — 2.5 — 3.2 — 3.5 — 3.8 — 4.0 ns G to output in Low-Z tOLZ1 0 — 0 — 0 — 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 2.3 — 2.5 — 3.0 — 3.0 — 3.0 — 3.0 ns ZZ setup time tZZS2 5 — 5 — 5 — 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — 1 — 1 — 1 — ns ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — 20 — ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 2.12 3/2002 17/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Write Cycle Timing Single Write Burst Write Deselected Write CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated write ADSC tS tH ADV tS tH A0–An ADV must be inactive for ADSP Write WR2 WR1 WR3 tS tH GW tS tH BW tS tH BA–BD WR1 WR1 WR2 tS tH WR3 WR3 E1 masks ADSP E1 tS tH Deselected with E2 E2 tS tH E2 and E3 only sampled with ADSP or ADSC E3 G tS tH DQA–DQD Rev: 2.12 3/2002 Hi-Z Write specified byte for 2A and all bytes for 2B, 2C& 2D D1A D2A D2B D2C D2D 18/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D3A © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Flow Through Read Cycle Timing Single Read Burst Read tKL CK tKH tS tH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst Suspend Burst ADV tS tH A0–An RD1 RD2 RD3 tS tH tS tH GW BW BA–BB tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP or ADSC Deselected with E2 E2 tS tH E3 tOE tOHZ G tKQX tOLZ DQA–DQD Q1A Hi-Z Q2A tKQX Q2B Q2c Q2D Q3A tLZ tHZ tKQ Rev: 2.12 3/2002 19/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Flow Through Read-Write Cycle Timing Single Write Single Read Burst Read CK tS tH tKC tKH tKL ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An RD2 WR1 RD1 tS tH GW tS tH tS BW tS BA–BD tH WR1 tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH Deselected with E3 E3 tOE tOHZ G tS tKQ DQA–DQD Hi-Z Q1A tH D1A Q2A Q2B Q2c Q2D Q2A Burst wrap around to it’s initial state Rev: 2.12 3/2002 20/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Pipelined SCD Read Cycle Timing Single Read Burst Read CK tKH tS tH tKL tKC ADSP ADSP is blocked by E inactive tS tH ADSC initiated read ADSC tS tH Suspend Burst ADV tS tH A0–An RD2 RD1 RD3 tS tH tS tH GW BW BWA–BWD tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP or ADSC Deselected with E2 E2 tS tH E3 tOE G DQA–DQD tOHZ Hi-Z tKQX tKQX tOLZ Q1A Q2A Q2B Q2c Q2D Q3A tLZ tHZ tKQ Rev: 2.12 3/2002 21/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Pipelined SCD Read-Write Cycle Timing Single Write Single Read Burst Read tKL CK tS tH tKH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An WR1 RD1 RD2 tS tH GW tS tH BW tS tH BWA–BWD WR1 tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH Deselected with E3 E3 tOE tOHZ G DQA–DQD Rev: 2.12 3/2002 Hi-Z tS tH tKQ Q1A D1A Q2A 22/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q2Bb Q2c Q2D © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. tKC tKH tKL ADSP ADSC tZZS ZZ ~ ~ ~ ~ tS tH ~ ~ CK tZZH ~ ~~ ~ ~ ~ ~ ~ ~ ~~ ~ ~ ~ ~ ~ Sleep Mode Timing Diagram tZZR Snooze Application Tips Single and Dual Cycle Deselect SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention. Rev: 2.12 3/2002 23/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 TQFP Package Drawing L Min. Nom. Max A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 — 0.20 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch — 0.65 — L Foot Length 0.45 0.60 0.75 L1 Lead Length — 1.00 — Y Coplanarity θ Lead Angle L1 e b A1 A2 0.10 — Y 0° c D D1 Description Pin 1 Symbol θ 7° E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 2.12 3/2002 24/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Package Speed2 (MHz/ns) TA3 1M x 18 GS816018T-250 Pipeline/Flow Through TQFP 250/5.5 C 1M x 18 GS816018T-225 Pipeline/Flow Through TQFP 225/6 C 1M x 18 GS816018T-200 Pipeline/Flow Through TQFP 200/6.5 C 1M x 18 GS816018T-166 Pipeline/Flow Through TQFP 166/7 C 1M x 18 GS816018T-150 Pipeline/Flow Through TQFP 150/7.5 C 1M x 18 GS816018T-133 Pipeline/Flow Through TQFP 133/8.5 C 512K x 32 GS816032T-250 Pipeline/Flow Through TQFP 250/5.5 C 512K x 32 GS816032T-225 Pipeline/Flow Through TQFP 225/6 C 512K x 32 GS816032T-200 Pipeline/Flow Through TQFP 200/6.5 C 512K x 32 GS816032T-166 Pipeline/Flow Through TQFP 166/7 C 512K x 32 GS816032T-150 Pipeline/Flow Through TQFP 150/7.5 C 512K x 32 GS816032T-133 Pipeline/Flow Through TQFP 133/8.5 C 512K x 36 GS816036T-250 Pipeline/Flow Through TQFP 250/5.5 C 512K x 36 GS816036T-225 Pipeline/Flow Through TQFP 225/6 C 512K x 36 GS816036T-200 Pipeline/Flow Through TQFP 200/6.5 C 512K x 36 GS816036T-166 Pipeline/Flow Through TQFP 166/7 C 512K x 36 GS816036T-150 Pipeline/Flow Through TQFP 150/7.5 C 512K x 36 GS816036T-133 Pipeline/Flow Through TQFP 133/8.5 C 1M x 18 GS816018T-250I Pipeline/Flow Through TQFP 250/5.5 I Not Available 1M x 18 GS816018T-225I Pipeline/Flow Through TQFP 225/6 I Not Available 1M x 18 GS816018T-200I Pipeline/Flow Through TQFP 200/6.5 I Not Available 1M x 18 GS816018T-166I Pipeline/Flow Through TQFP 166/7 I 1M x 18 GS816018T-150I Pipeline/Flow Through TQFP 150/7.5 I 1M x 18 GS816018T-133I Pipeline/Flow Through TQFP 133/8.5 I 512K x 32 GS816032T-250I Pipeline/Flow Through TQFP 250/5.5 I Not Available 512K x 32 GS816032T-225I Pipeline/Flow Through TQFP 225/6 I Not Available 512K x 32 GS816032T-200I Pipeline/Flow Through TQFP 200/6.5 I Not Available 512K x 32 GS816032T-166I Pipeline/Flow Through TQFP 166/7 I 512K x 32 GS816032T-150I Pipeline/Flow Through TQFP 150/7.5 I 512K x 32 GS816032T-133I Pipeline/Flow Through TQFP 133/8.5 I Status Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018T-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 2.12 3/2002 25/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 Org Part Number1 Type Package Speed2 (MHz/ns) TA3 Status 512K x 36 GS816036T-250I Pipeline/Flow Through TQFP 250/5.5 I Not Available 512K x 36 GS816036T-225I Pipeline/Flow Through TQFP 225/6 I Not Available 512K x 36 GS816036T-200I Pipeline/Flow Through TQFP 200/6.5 I Not Available 512K x 36 GS816036T-166I Pipeline/Flow Through TQFP 166/7 I 512K x 36 GS816036T-150I Pipeline/Flow Through TQFP 150/7.5 I 512K x 36 GS816036T-133I Pipeline/Flow Through TQFP 133/8.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018T-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 2.12 3/2002 26/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New GS816018T-150IT 1.00 9/ 1999A;GS816018T-150IT 2.00 1/1999B GS816018T- 2.00 11/ 1999B;GS816018T 2.01 1/ 2000C Types of Changes Format or Content Page;Revisions;Reason Content • Converted from 0.25u 3.3V process to 0.18u 2.5V process. Master File Rev B • Added x72 Pinout. • Added GSI Logo. Format • Changed Flow-Through Read-Write cycle Timing Diagram for accuracy • Changed pin description in TQFP to match order of pins in pinout. GS816018T 2.01 1/ 2000C;GS816018 T 2.02 1/ 2000D • Front page; Features - changed 2.5V I/O supply to 2.5V or3.3V I/O supply; Core and Interface voltages - Changed paragraph to include information for 3.3V;Completeness • Absolute Maximum Ratings; Changed VDDQ - Value: From: .05 to VDD : to : -.05 to 3.6; Completeness. • Recommended Operating Conditions;Changed: I/O Supply Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from VDD +0.3 to 3.6; Same page - took out Note 1;Completeness • Electrical Characteristics - Added second Output High Voltage line to table; completeness. • Note: There was not a Rev 2.02 for the 8160Z or the 8161Z. GS18/362.0 1/2000DGS18/ 362.03 2/2000E GS18/362.03 2/2000E; 816018_r2_04 Content • Input High Voltage (p. 11) changed to 0.7* VDD • Input Low Voltage (p.11) changed to 0.3* VDD 816018_r2_04; 816018_r2_05 Content • Changed the value of ZZ recovery in the AC Electrical Characteristics table on page 15 from 20 ns to 100 ns • Added 225 MHz speed bin • Updated Pg. 1 table, AC Characteristics table, and Operating Currents table to match 815xxx • Updated format to comply with Technical Publications standards 816018_r2_05; 816018_r2_06 Content/Format 816018_r2_06; 816018_r2_07 Content • Updated Capitance table—removed Input row and changed Output row to I/O 816018_r2_07; 816018_r2_08 Content • Updated Features list on page 1 • Completely reworked table on page 1 • Updated Mode Pin Functions tableon page 7 Content • Added 3.3 V references to entire document • Updated Operating Conditions table • Added Pin 56 to Pin Description table • Updated Operating Currents table and added note • Updated Application Tips paragraph • Updated table on page 1; added power numbers 816018_r2_08; 816018_r2_09 Rev: 2.12 3/2002 27/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New 816018_r2_09; 816018_r2_10 816018_r2_10; 816018_r2_11 816018_r2_11; 816018_r2_12 Rev: 2.12 3/2002 Types of Changes Format or Content Page;Revisions;Reason Content • Updated Operating Currents table • Updated table on page 1; updated power numbers • Updated Recommended Operating Conditions table (added VDDQ references) Content • Updated table on page 1 • Created recommended operating conditions tables on pages 12 and 13 • Updated AC Electrical Characteristics table • Added Sleep mode description on page 23 • Updated Ordering Information for 225 MHz part (changed from 7ns to 6.5 ns) • Added 250 MHz speed bin • Deleted 180 MHz speed bin Content • Updated AC Characteristics table • Updated FT power numbers • Updated Mb references from 16Mb to 18Mb • Updated AC Test Conditions table and removed Output Load 2 diagram 28/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc.