ISL8488E, ISL8489E, ISL8490E, ISL8491E ® Data Sheet July 26, 2007 ±15kV ESD Protected, 5V, Low Power, High Speed and Slew Rate Limited, Full Duplex, RS-485/RS-422 Transceivers FN6073.4 Features • RS-485 I/O Pin ESD Protection . . . . . . . . . . . . . ±15kV HBM - Class 3 ESD Level on all Other Pins . . . . . . >7kV HBM The ISL8488E, ISL8489E, ISL8490E, ISL8491E devices are ESD protected, BiCMOS, 5V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Each driver output and receiver input is protected against ±15kV ESD strikes, without latch-up. Unlike competitive versions, these Intersil devices are specified for 10% tolerance supplies (4.5V to 5.5V). • High Data Rates (ISL8490E, ISL8491E) . . up to 10Mbps • Slew Rate Limited for Error Free Data Transmission (ISL8488E, ISL8489E) • Single Unit Load Allows up to 32 Devices on the Bus (See ISL4489E, ISL4491E for 256 Devices on Bus) • Low Quiescent Current: - 120µA (ISL8488E) - 140µA (ISL8489E) - 370µA (ISL8490E, ISL8491E) These devices are configured for full duplex (separate Rx input and Tx output pins) applications, so they are ideal for RS-422 networks requiring high ESD tolerance on the bus pins. The ISL8488E, ISL8490E are 8 Ld versions without Rx and Tx output enables. The other two versions include Rx and Tx output enable pins in a standard 14 Ld pinout. • -7V to +12V Common Mode Input Voltage Range • Three-State Rx and Tx Outputs (Except ISL8488E, ISL8490E) The ISL8488E, ISL8489E utilize slew rate limited drivers which reduce EMI, and minimize reflections from improperly terminated transmission lines, or unterminated stubs in multidrop and multipoint applications. • Full Duplex Pinout • Operates from a Single +5V Supply (10% Tolerance) • Current Limiting and Thermal Shutdown for Driver Overload Protection Data rates up to 10Mbps are achievable by using the ISL8490E, ISL8491E, which feature higher slew rates. • Pb-Free Plus Anneal Available (RoHS Compliant) The devices present a “single unit load” to the RS-485 bus, which allows a total of 32 transmitters and receivers on the network. For “1/8 unit load” versions (256 devices on the bus), please refer to the ISL4489E, ISL4491E data sheet. Applications • Factory Automation Receiver (Rx) inputs feature a “fail-safe if open” design, which ensures a logic high Rx output if Rx inputs are floating. • Security Networks Driver (Tx) outputs are short circuit protected, even for voltages exceeding the power supply voltage. Additionally, on-chip thermal shutdown circuitry disables the Tx outputs to prevent damage if power dissipation becomes excessive. • Industrial/Process Control Networks • Building Environmental Control Systems • Level Translators (e.g., RS-232 to RS-422) • RS-232 “Extension Cords” TABLE 1. SUMMARY OF FEATURES PART NUMBER HALF/FULL DUPLEX HIGH ESD? NO. OF DEVICES ALLOWED ON BUS DATA RATE (Mbps) ISL8488E Full Yes 32 0.25 Yes No 120 8 ISL8489E Full Yes 32 0.25 Yes Yes 140 14 ISL8490E Full Yes 32 10 No No 370 8 ISL8491E Full Yes 32 10 No Yes 370 14 1 SLEW-RATE RECEIVER/ QUIESCENT PIN LIMITED? DRIVER ENABLE? ICC (μA) COUNT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL8488E, ISL8489E, ISL8490E, ISL8491E Pinouts Ordering Information ISL8488E, ISL8490E (8 LD SOIC) TOP VIEW VCC 1 R RO 2 DI 3 GND 4 D PART NUMBER (Note 1) 8 A ISL8488EIB 7 B 6 Z 5 Y ISL8489E, ISL8491E (14 LD SOIC) TOP VIEW 8 Ld SOIC M8.15 ISL8488EIBZA 8488 EIBZ (Note 2) -40 to +85 8 Ld SOIC (Pb-free) M8.15 ISL8489EIB ISL8489EIB -40 to +85 14 Ld SOIC M14.15 ISL8489EIBZ (Note 2) 8489EIBZ -40 to +85 14 Ld SOIC M14.15 (Pb-free) ISL8490EIBZ (Note 2) 8490E IBZ -40 to +85 8 Ld SOIC (Pb-free) ISL8491EIB ISL8491EIB -40 to +85 14 Ld SOIC M14.15 8491EIBZ -40 to +85 14 Ld SOIC M14.15 (Pb-free) 14 VCC RO 2 13 NC ISL8491EIBZ (Note 2) RE 3 12 A NOTES: DE 4 11 B DI 5 D 9 Y GND 7 8 NC 8488 EIB M8.15 1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 10 Z GND 6 TEMP. PKG. RANGE (°C) PACKAGE DWG. # -40 to +85 NC 1 R PART MARKING 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Truth Tables (For ISL8488E, ISL8490E, only the DE = 1 and RE = 0 entries are valid) TRANSMITTING RECEIVING INPUTS OUTPUTS INPUTS OUTPUT RE DE DI Z Y RE DE A-B RO X 1 1 0 1 0 X ≥ +0.2V 1 X 1 0 1 0 0 X ≤ -0.2V 0 X 0 X High-Z High-Z 0 X Inputs Open 1 1 X X High-Z Pin Descriptions PIN FUNCTION RO Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating). RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. DE Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low. DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. GND Ground connection. A ±15kV HBM ESD Protected, Non-inverting receiver input. B ±15kV HBM ESD Protected, Inverting receiver input. Y ±15kV HBM ESD Protected, Non-inverting driver output. Z ±15kV HBM ESD Protected, Inverting driver output. VCC NC System power supply input (4.5V to 5.5V). No Connection. 2 FN6073.4 July 26, 2007 ISL8488E, ISL8489E, ISL8490E, ISL8491E Typical Operating Circuit ISL8488E, ISL8490E +5V +5V + + 0.1µF 0.1µF 1 1 VCC 2 3 RO R VCC A 8 B 7 Z 6 Y 5 DI D RT RT 5 Y 6 Z 7 B 8 A GND D R DI 3 RO 2 GND 4 4 ISL8489E, ISL8491E +5V +5V + RO 3 RE 4 DE 5 0.1µF 14 VCC 2 + 0.1µF 14 R A 12 B 11 Z 10 Y 9 DI D GND RT RT 9 Y 10 Z 11 B 12 A VCC DI 5 DE 4 RE 3 RO 2 D R GND 6, 7 6, 7 3 FN6073.4 July 26, 2007 ISL8488E, ISL8489E, ISL8490E, ISL8491E Absolute Maximum Ratings Thermal Information VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltages DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC + 0.5V) Input/Output Voltages A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to + 12.5V RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC + 0.5V) Short Circuit Duration Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table Thermal Resistance (Typical) θJA (°C/W) 8 Ld SOIC Package (Note 3) . . . . . . . . . . . . . . . . . . 170 14 Ld SOIC Package (Note 3) . . . . . . . . . . . . . . . . . 128 Maximum Junction Temperature (Plastic Package) . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C, (Note 4). PARAMETER SYMBOL TEST CONDITIONS TEMP MIN (°C) (NOTE 9) TYP MAX (NOTE 9) UNITS DC CHARACTERISTICS Driver Differential VOUT (no load) VOD1 Driver Differential VOUT (with load) VOD2 Full - - VCC V R = 50Ω (RS-422) (Figure 1) Full 2 3 - V R = 27Ω (RS-485) (Figure 1) Full 1.5 2.3 5 V ΔVOD R = 27Ω or 50Ω (Figure 1) Full - 0.01 0.2 V VOC R = 27Ω or 50Ω (Figure 1) Full - - 3 V ΔVOC R = 27Ω or 50Ω (Figure 1) Full - 0.01 0.2 V VIH DE, DI, RE Full 2 - - V Logic Input Low Voltage VIL DE, DI, RE Full 0.8 - - V Logic Input Current IIN1 DI Full -2 - 2 μA DE, RE (Note 8) Full -40 - 40 μA VIN = 12V Full - - 1 mA VIN = -7V Change in Magnitude of Driver Differential VOUT for Complementary Output States Driver Common-Mode VOUT Change in Magnitude of Driver Common-Mode VOUT for Complementary Output States Logic Input High Voltage Input Current (A, B) (Note 7) IIN2 DE = 0V, VCC = 0V or 4.5V to 5.5V Full -0.8 - - mA Driver Three-State Output Current (Y, Z) IOZD DE = 0V, -7V ≤ VO ≤ 12V (Note 8) Full -100 - 100 μA Receiver Differential Threshold Voltage VTH -7V ≤ VCM ≤ 12V Full -0.2 - 0.2 V 70 - mV Receiver Input Hysteresis ΔVTH VCM = 0V 25 - Receiver Output High Voltage VOH IO = -4mA, VID = 200mV Full 3.5 - - V Receiver Output Low Voltage VOL IO = 4mA, VID = 200mV Full - - 0.4 V Receiver Three-State Output Current IOZR RE = VCC, 0.4V ≤ VO ≤ 2.4V (Note 8) Full - - ±1 μA Receiver Input Resistance RIN -7V ≤ VCM ≤ 12V Full 12 - - kΩ No-Load Supply Current (Note 5) ICC Driver Short-Circuit Current, VO = High or Low IOSD1 4 ISL8488E, DI = 0V or VCC Full - 120 140 μA ISL8489E, DE, DI, RE = 0V or VCC Full - 140 190 μA ISL8490E/ISL8491E, DE, DI, RE = 0V or VCC Full - 370 460 μA DE = VCC, -7V ≤ VY or VZ ≤ 12V (Note 6) Full 35 - 250 mA FN6073.4 July 26, 2007 ISL8488E, ISL8489E, ISL8490E, ISL8491E Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C, (Note 4). (Continued) PARAMETER SYMBOL Receiver Short-Circuit Current IOSR TEST CONDITIONS 0V ≤ VO ≤ VCC TEMP MIN (°C) (NOTE 9) TYP MAX (NOTE 9) UNITS Full 7 - 85 mA tPLH, tPHL RDIFF = 54Ω, CL = 100pF (Figure 2) Full 250 400 2000 ns tSKEW RDIFF = 54Ω, CL = 100pF (Figure 2) Full - 160 800 ns tR, tF SWITCHING CHARACTERISTICS (ISL8488E, ISL8489E) Driver Input to Output Delay Driver Output Skew RDIFF = 54Ω, CL = 100pF (Figure 2) Full 250 600 2000 ns Driver Enable to Output High tZH CL = 100pF, SW = GND (Figure 3, Note 8) Full 250 1000 2000 ns Driver Enable to Output Low tZL CL = 100pF, SW = VCC (Figure 3, Note 8) Full 250 860 2000 ns Driver Disable from Output High tHZ CL = 15pF, SW = GND (Figure 3, Note 8) Full 300 660 3000 ns tLZ CL = 15pF, SW = VCC (Figure 3, Note 8) Driver Differential Rise or Fall Time Driver Disable from Output Low Full 300 640 3000 ns Full 250 500 2000 ns (Figure 4) 25 - 60 - ns tZH CL = 15pF, SW = GND (Figure 5, Note 8) Full - 10 50 ns tPLH, tPHL (Figure 4) Receiver Input to Output Delay Receiver Skew | tPLH - tPHL | tSKD Receiver Enable to Output High Receiver Enable to Output Low tZL CL = 15pF, SW = VCC (Figure 5, Note 8) Full - 10 50 ns Receiver Disable from Output High tHZ CL = 15pF, SW = GND (Figure 5, Note 8) Full - 10 50 ns Receiver Disable from Output Low tLZ CL = 15pF, SW = VCC (Figure 5, Note 8) Full - 10 50 ns Full 250 - - kbps tPLH, tPHL RDIFF = 54Ω, CL = 100pF (Figure 2) Full 13 24 50 ns tSKEW RDIFF = 54Ω, CL = 100pF (Figure 2) Full - 3 10 ns tR, tF RDIFF = 54Ω, CL = 100pF (Figure 2) Full 5 12 25 ns Maximum Data Rate fMAX SWITCHING CHARACTERISTICS (ISL8490E, ISL8491E) Driver Input to Output Delay Driver Output Skew Driver Differential Rise or Fall Time Driver Enable to Output High tZH CL = 100pF, SW = GND (Figure 3, Note 8) Full - 14 70 ns Driver Enable to Output Low tZL CL = 100pF, SW = VCC (Figure 3, Note 8) Full - 14 70 ns Driver Disable from Output High tHZ CL = 15pF, SW = GND (Figure 3, Note 8) Full - 44 70 ns Driver Disable from Output Low tLZ CL = 15pF, SW = VCC (Figure 3, Note 8) Full - 21 70 ns tPLH, tPHL (Figure 4) Receiver Input to Output Delay Receiver Skew | tPLH - tPHL | tSKD Full 30 90 150 ns (Figure 4) 25 - 5 - ns Receiver Enable to Output High tZH CL = 15pF, SW = GND (Figure 5, Note 8) Full - 9 50 ns Receiver Enable to Output Low tZL CL = 15pF, SW = VCC (Figure 5, Note 8) Full - 9 50 ns Receiver Disable from Output High tHZ CL = 15pF, SW = GND (Figure 5, Note 8) Full - 9 50 ns Receiver Disable from Output Low tLZ CL = 15pF, SW = VCC (Figure 5, Note 8) Full - 9 50 ns Full 10 - - Mbps 25 - ±15 - kV 25 - >±7 - kV Maximum Data Rate fMAX ESD PERFORMANCE RS-485 Pins (A, B, Y, Z) Human Body Model All Other Pins NOTES: 4. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 5. Supply current specification is valid for loaded drivers when DE = 0V. 6. Applies to peak current. See “Typical Performance Curves” on page 9 for more information. 7. Devices meeting these limits are denoted as “single unit load (1 UL)” transceivers. The RS-485 standard allows up to 32 Unit Loads on the bus. 8. Not applicable to the ISL8488E, ISL8490E. 9. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. 5 FN6073.4 July 26, 2007 ISL8488E, ISL8489E, ISL8490E, ISL8491E Test Circuits and Waveforms R VCC DE Z DI VOD D Y R VOC FIGURE 1. DRIVER VOD AND VOC 3V DI 1.5V 1.5V 0V tPLH VCC tPHL CL = 100pF DE VOH 50% OUT (Y) 50% Z DI VOL RDIFF D Y tPLH tPHL CL = 100pF VOH SIGNAL GENERATOR OUT (Z) 50% 50% VOL 90% DIFF OUT (Y - Z) 10% tR +VOD 90% 10% -VOD tF SKEW = |tPLH (Y or Z) - tPHL (Z or Y)| FIGURE 2A. TEST CIRCUIT FIGURE 2B. MEASUREMENT POINTS FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES 6 FN6073.4 July 26, 2007 ISL8488E, ISL8489E, ISL8490E, ISL8491E Test Circuits and Waveforms (Continued) DE Z DI 500Ω VCC D SIGNAL GENERATOR SW Y 3V DE 1.5V 1.5V GND 0V CL tZH tHZ OUTPUT HIGH OUT (Y, Z) PARAMETER OUTPUT RE DI SW CL (pF) tHZ Y/Z X 1/0 GND 15 tLZ Y/Z X 0/1 VCC 15 2.3V 0V tZL tLZ VCC OUT (Y, Z) tZH Y/Z X 1/0 GND 100 tZL Y/Z X 0/1 VCC 100 VOH - 0.5V VOH 2.3V VOL + 0.5V V OL OUTPUT LOW FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS FIGURE 3. DRIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL8488E, ISL8490E) RE 3V 15pF B +1.5V R A A 1.5V 1.5V RO 0V tPHL tPLH VCC SIGNAL GENERATOR 50% RO 50% 0V FIGURE 4B. MEASUREMENT POINTS FIGURE 4A. TEST CIRCUIT FIGURE 4. RECEIVER PROPAGATION DELAY RE 3V B R SIGNAL GENERATOR 1kΩ RO VCC SW A RE 1.5V 1.5V 0V GND 15pF tZH OUTPUT HIGH RO PARAMETER DE A SW tHZ X +1.5V GND tLZ X -1.5V VCC tZH X +1.5V GND tZL X -1.5V VCC FIGURE 5A. TEST CIRCUIT tHZ VOH - 0.5V VOH 1.5V 0V tZL tLZ VCC RO 1.5V VOL + 0.5V V OUTPUT LOW OL FIGURE 5B. MEASUREMENT POINTS FIGURE 5. RECEIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL8488E, ISL8490E) 7 FN6073.4 July 26, 2007 ISL8488E, ISL8489E, ISL8490E, ISL8491E Application Information Data Rate, Cables, and Terminations RS-485 and RS-422 are differential (balanced) data transmission standards for use in long haul or noisy environments. RS-422 is a subset of RS-485, so RS-485 transceivers are also RS-422 compliant. RS-422 is a point-to-multipoint (multidrop) standard, which allows only one driver and up to 10 (assuming one unit load devices) receivers on each bus. RS-485 is a true multipoint standard, which allows up to 32 one unit load devices (any combination of drivers and receivers) on each bus. To allow for multipoint operation, the RS-485 specification requires that drivers must handle bus contention without sustaining any damage. Twisted pair is the cable of choice for RS-485/RS-422 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common mode signals, which are effectively rejected by the differential receivers in these ICs. Another important advantage of RS-485 is the extended common mode range (CMR), which specifies that the driver outputs and receiver inputs withstand signals that range from +12V to -7V. RS-422 and RS-485 are intended for runs as long as 4000’, so the wide CMR is necessary to handle ground potential differences, as well as voltages induced in the cable by external fields. Receiver Features These devices utilize a differential input receiver for maximum noise immunity and common mode rejection. Input sensitivity is ±200mV, as required by the RS-422 and RS-485 specifications. Receiver input resistance surpasses the RS-422 specification of 4kΩ, and meets the RS-485 “Unit Load” requirement of 12kΩ minimum. Receiver inputs function with common mode voltages as great as ±7V outside the power supplies (i.e., +12V and -7V), making them ideal for long networks where induced voltages are a realistic concern. All the receivers include a “fail-safe if open” function that guarantees a high level receiver output if the receiver inputs are unconnected (floating). Receivers easily meet the data rate supported by the corresponding driver. ISL8489E/ISL8491E receiver outputs are three-statable via the active low RE input. Driver Features The RS-485/RS-422 driver is a differential output device that delivers at least 1.5V across a 54Ω load (RS-485), and at least 2V across a 100Ω load (RS-422). The drivers feature low propagation delay skew to maximize bit width, and to minimize EMI. ISL8489E/ISL8491E driver outputs are threestatable via the active high DE input. The ISL8488E/ISL8489E driver outputs are slew rate limited to further reduce EMI, and to minimize reflections in unterminated or improperly terminated networks. Data rates on these slew rate limited versions are a maximum of 250kbps. Outputs of ISL8490E/ISL8491E drivers are not limited, so faster output transition times allow data rates of at least 10Mbps. 8 RS-485/RS-422 are intended for network lengths up to 4000’, but the maximum system data rate decreases as the transmission length increases. Devices operating at 10Mbps are limited to lengths of a few hundred feet, while the 250kbps versions can operate at full data rates with lengths in excess of 1000’. Proper termination is imperative, when using the 10Mbps devices, to minimize reflections. Short networks using the 250kbps versions need not be terminated, but, terminations are recommended unless power dissipation is an overriding concern. In point-to-point, or point-to-multipoint (single driver on bus) networks, the main cable should be terminated in its characteristic impedance (typically 120Ω) at the end farthest from the driver. In multi-receiver applications, stubs connecting receivers to the main cable should be kept as short as possible. Multipoint (multi-driver) systems require that the main cable be terminated in its characteristic impedance at both ends. Stubs connecting a transceiver to the main cable should be kept as short as possible. Built-In Driver Overload Protection As stated previously, the RS-485 specification requires that drivers survive worst case bus contentions undamaged. The ISL84xxE devices meet this requirement via driver output short circuit current limits, and on-chip thermal shutdown circuitry. The driver output stages incorporate short circuit current limiting circuitry which ensures that the output current never exceeds the RS-485 specification, even at the common mode voltage range extremes. Additionally, these devices utilize a foldback circuit which reduces the short circuit current, and thus the power dissipation, whenever the contending voltage exceeds either supply. In the event of a major short circuit condition, ISL84xxE devices also include a thermal shutdown feature that disables the drivers whenever the die temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. The drivers automatically reenable after the die temperature drops about 15°. If the contention persists, the thermal shutdown/reenable cycle repeats until the fault is cleared. Receivers stay operational during thermal shutdown. ESD Protection All pins on these devices include class 3 Human Body Model (HBM) ESD protection structures, but the RS-485 pins (driver outputs and receiver inputs) incorporate advanced structures allowing them to survive ESD events in excess of FN6073.4 July 26, 2007 ISL8488E, ISL8489E, ISL8490E, ISL8491E ±15kV HBM. The RS-485 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, Typical Performance Curves protect without allowing any latch-up mechanism to activate, and without degrading the RS-485 common mode range of -7V to +12V. This built-in ESD protection eliminates the need for board level protection structures (e.g., transient suppression diodes), and the associated, undesirable capacitive load they present. VCC = 5V, TA = +25°C; Unless Otherwise Specified. 3.6 DIFFERENTIAL OUTPUT VOLTAGE (V) 90 DRIVER OUTPUT CURRENT (mA) 80 70 60 50 40 30 20 10 0 0 1 2 3 4 3.4 3.2 RDIFF = 100Ω 3.0 2.8 2.6 2.4 RDIFF = 54Ω 2.2 2.0 -40 5 -25 DIFFERENTIAL OUTPUT VOLTAGE (V) 25 50 75 85 TEMPERATURE (°C) FIGURE 6. DRIVER OUTPUT CURRENT vs DIFFERENTIAL OUTPUT VOLTAGE FIGURE 7. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs TEMPERATURE 400 160 140 ISL8490E/ISL8491E 120 ISL8490E/ISL8491E, DE = X, RE = X 350 Y OR Z = LOW 100 80 300 ISL8488E/ISL8489E 60 40 ICC (µA) OUTPUT CURRENT (mA) 0 20 0 -20 Y OR Z = HIGH -40 250 200 ISL8489E, DE = X, RE = X 150 -60 ISL8490E/ISL8491E -80 ISL8488E/ISL8489E -100 -120 -7 -6 -4 -2 0 2 4 6 OUTPUT VOLTAGE (V) 100 8 10 12 FIGURE 8. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT VOLTAGE 9 50 ISL8488E -40 -25 0 25 TEMPERATURE (°C) 50 75 85 FIGURE 9. SUPPLY CURRENT vs TEMPERATURE FN6073.4 July 26, 2007 ISL8488E, ISL8489E, ISL8490E, ISL8491E Typical Performance Curves VCC = 5V, TA = +25°C; Unless Otherwise Specified. 250 750 200 tPLHY tPLHZ 650 |tPLHY - tPHLZ| SKEW (ns) PROPAGATION DELAY (ns) 700 600 tPHLY 150 |tPHLY - tPLHZ| 100 550 tPHLZ 50 500 |CROSS PT. OF Y↑ AND Z↓ TO CROSS PT. OF Y↓ AND Z↑| 450 -40 -25 0 25 TEMPERATURE (°C) 50 0 -40 85 75 FIGURE 10. DRIVER PROPAGATION DELAY vs TEMPERATURE (ISL8488E/ISL8489E) -25 0 25 TEMPERATURE (°C) 50 85 75 FIGURE 11. DRIVER SKEW vs TEMPERATURE (ISL8488E/ISL8489E) 30 5 4 |tPHLY - tPLHZ| 26 24 tPLHY 22 tPHLZ tPLHZ 3 SKEW (ns) |tPLHY - tPHLZ| 2 20 1 18 |CROSS PT. OF Y↑ AND Z↓ TO CROSS PT. OF Y↓ AND Z↑| tPHLY 16 -40 -25 0 25 50 0 -40 85 75 -25 TEMPERATURE (°C) DRIVER OUTPUT (V) 0 4 Z 3 2 RECEIVER OUTPUT (V) 0 DRIVER INPUT (V) RECEIVER OUTPUT (V) DRIVER OUTPUT (V) 5 RO Y 1 0 TIME (400ns/DIV) FIGURE 14. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL8488E/ISL8489E) 10 50 85 75 FIGURE 13. DRIVER SKEW vs TEMPERATURE (ISL8490E/ISL8491E) RDIFF = 54Ω, CL = 100pF 5 25 TEMPERATURE (°C) FIGURE 12. DRIVER PROPAGATION DELAY vs TEMPERATURE (ISL8490E/ISL8491E) DI 0 RDIFF = 54Ω, CL = 100pF 5 DI 0 5 RO DRIVER INPUT (V) PROPAGATION DELAY (ns) 28 0 4 3 2 Y Z 1 0 TIME (400ns/DIV) FIGURE 15. DRIVER AND RECEIVER WAVEFORMS, HIGH TO LOW (ISL8488E/ISL8489E) FN6073.4 July 26, 2007 ISL8488E, ISL8489E, ISL8490E, ISL8491E DI 0 5 RO 0 4 Z 3 2 Y 1 0 TIME (20ns/DIV) FIGURE 16. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL8490E/ISL8491E) RDIFF = 54Ω, CL = 100pF 5 DI 0 5 RO DRIVER INPUT (V) 5 RECEIVER OUTPUT (V) RDIFF = 54Ω, CL = 100pF DRIVER INPUT (V) VCC = 5V, TA = +25°C; Unless Otherwise Specified. DRIVER OUTPUT (V) DRIVER OUTPUT (V) RECEIVER OUTPUT (V) Typical Performance Curves 0 4 3 2 Y Z 1 0 TIME (20ns/DIV) FIGURE 17. DRIVER AND RECEIVER WAVEFORMS, HIGH TO LOW (ISL8490E/ISL8491E) Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 518 PROCESS: Si Gate BiCMOS 11 FN6073.4 July 26, 2007 ISL8488E, ISL8489E, ISL8490E, ISL8491E Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC - 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 α 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 1.27 BSC H N NOTES: MILLIMETERS 8 0° 8 8° 0° 7 8° Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 12 FN6073.4 July 26, 2007 ISL8488E, ISL8489E, ISL8490E, ISL8491E Small Outline Plastic Packages (SOIC) M14.15 (JEDEC MS-012-AB ISSUE C) N INDEX AREA 0.25(0.010) M H 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- µα e A1 B 0.25(0.010) M C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3367 0.3444 8.55 8.75 3 E 0.1497 0.1574 3.80 4.00 4 e C 0.10(0.004) B S 0.050 BSC 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 N NOTES: MILLIMETERS α 14 0o 1.27 14 8o 0o 6 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN6073.4 July 26, 2007