Samsung K6X0808C1D-F 32kx8 bit low power cmos static ram Datasheet

K6X0808C1D Family
CMOS SRAM
Document Title
32Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No.
History
Draft Data
Remark
0.0
Initial draft
October 09, 2002
Preliminary
1.0
Finalized
- Changed ICC from 10mA to 5mA
- Changed ICC1 from 8mA to 7mA
- Changed ICC2 from 35mA to 25mA
- Changed ISB from 3mA to 0.4mA
- Changed IDR for K6X0808C1D-F 15µA to 10µA
- Changed IDR for K6X0808C1D-Q 25µA to 20µA
- Errata correction
December 16, 2003
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
December 2003
K6X0808C1D Family
CMOS SRAM
32Kx8 bit Low Power full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Process Technology: Full CMOS
• Organization: 32K x 8
• Power Supply Voltage: 4.5~5.5V
• Low Data Retention Voltage: 2V(Min)
• Three state output and TTL Compatible
• Package Type: 28-DIP-600B, 28-SOP-450,
28-TSOP1-0813.4F/R
The K6X0808C1D families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
verious operating temperature ranges and have various package types for user flexibility of system design. The families
also support low data retention voltage for battery back-up
operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family Operating Temperature Vcc Range
K6X0808C1D-F
Speed
Industrial(-40~85°C)
PKG Type
Operating
(ICC2, Max)
28-DIP-600B, 28-SOP-450,
28-TSOP1-0813.4F/R
15µA
4.5~5.5V
K6X0808C1D-Q
Standby
(ISB1, Max)
25mA
551)/70ns
Automotive(-40~125°C)
25µA
28-SOP-450, 28-TSOP1-0813.4F
1. The parameters are tested with 50pF test load
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
A14
1
28
VCC
A12
2
27
WE
A7
3
26
A13
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE
A2
8
21
A10
A1
9
20
CS
A0
10
19
I/O8
I/O1
11
18
I/O7
I/O2
12
17
I/O6
I/O3
13
16
I/O5
VSS
28-DIP
28-SOP
14
15
I/O4
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
28
2
27
3
26
4
25
5
24
A3
A4
A5
A6
A7
A12
A14
VCC
WE
A13
A8
A9
A11
OE
Pin Name
Function
6
7
8
28-TSOP
Type1 - Forward
23
22
21
9
20
10
19
11
18
12
17
13
16
14
15
14
15
13
16
12
17
11
18
10
19
9
20
8
7
28-TSOP
Type1 - Reverse
21
22
6
23
5
24
4
25
3
26
2
27
1
28
Pin Name
Function
I/O1~I/O8
Data Inputs/Outputs
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
Clk gen.
Row
Addresses
A2
A1
A0
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS
A10
I/O1
I/O8
Row
select
Data
cont
Precharge circuit.
Memory array
I/O Circuit
Column select
Data
cont
Column Addresses
CS
CS
Chip Select Input
OE
Output Enable Input
Vcc
Power
WE
Write Enable Input
Vss
Ground
Address Inputs
NC
No connect
WE
A0~A14
Control
logic
OE
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.0
December 2003
K6X0808C1D Family
CMOS SRAM
PRODUCT LIST
Industrial Temp. Products(-40~85°C)
Part Name
Automotive Temp. Products(-40~125°C)
Function
Part Name
28-SOP, 55ns, L Pwr
28-SOP, 70ns, L Pwr
28-TSOP-F, 55ns, L Pwr
28-TSOP-F, 70ns, L Pwr
K6X0808C1D-GQ55
K6X0808C1D-GQ70
K6X0808C1D-TQ55
K6X0808C1D-TQ70
28-DIP, 55ns, LL Pwr
28-DIP, 70ns, LL Pwr
28-SOP, 55ns, LL Pwr
28-SOP, 70ns, LL Pwr
28-TSOP-F, 55ns, LL Pwr
28-TSOP-F, 70ns, LL Pwr
28-TSOP-R, 55ns, LL Pwr
28-TSOP-R, 70ns, LL Pwr
K6X0808C1D-DF55
K6X0808C1D-DF70
K6X0808C1D-GF55
K6X0808C1D-GF70
K6X0808C1D-TF55
K6X0808C1D-TF70
K6X0808C1D-RF55
K6X0808C1D-RF70
Function
FUNCTIONAL DESCRIPTION
CS
OE
WE
I/O
Mode
Power
H
X1)
X1)
High-Z
Deselected
Standby
L
H
H
High-Z
Output Disabled
Active
L
L
H
Dout
Read
Active
L
Din
Write
Active
L
1)
X
1. X means don′t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
Ratings
Unit
Remark
VIN,VOUT
-0.5 to VCC+0.5V(Max. 7.0V)
V
-
VCC
-0.3 to 7.0
V
-
PD
1.0
W
-
TSTG
-65 to 150
°C
-
-40 to 85
°C
K6X0808C1D-F
-40 to 125
°C
K6X0808C1D-Q
TA
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
December 2003
K6X0808C1D Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
Input high voltage
VIH
2.2
-
Input low voltage
VIL
-0.5
Vcc+0.5
-
3)
V
V
2)
0.8
V
Note:
1. Industrial Product: TA=-40 to 85°C, Otherwise specified
Automotive Product: TA=-40 to 125°C, Otherwise specified
2. Overshoot: Vcc+3.0V in case of pulse width≤30ns.
3. Undershoot: -3.0V in case of pulse width≤30ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Output capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Min
Typ
Max
Unit
Input leakage current
Item
ILI
VIN=Vss to Vcc
-1
-
1
µA
Output leakage current
ILO
CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc
-1
-
1
µA
Operating power supply current
ICC
IIO=0mA, CS=VIL, VIN=VIH or VIL, Read
-
-
5
mA
ICC1
Cycle time=1µs, 100% duty, IIO=0mA, CS≤0.2V,
VIN≤0.2VIN≥Vcc -0.2V
-
-
7
mA
Average operating current
Symbol
Test Conditions
ICC2
Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL
-
-
25
mA
Output low voltage
VOL
IOL=2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH=-1.0mA
2.4
-
-
V
Standby Current(TTL)
ISB
CS=VIH, Other inputs=VIH or VIL
-
-
0.4
mA
Standby Current (CMOS)
ISB1
CS≥Vcc-0.2V, Other inputs=0~Vcc
K6X0808C1D-F
-
-
15
µA
K6X0808C1D-Q
-
-
25
µA
4
Revision 1.0
December 2003
K6X0808C1D Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL=100pF+1TTL
CL=50pF+1TTL
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
55 ns
Min
Read
Write
Units
70ns
1)
Max
Min
Max
Read cycle time
tRC
55
-
70
-
ns
Address access time
tAA
-
55
-
70
ns
Chip select to output
tCO
-
55
-
70
ns
Output enable to valid output
tOE
-
25
-
35
ns
Chip select to low-Z output
tLZ
10
-
10
-
ns
Output enable to low-Z output
tOLZ
5
-
5
-
ns
Chip disable to high-Z output
tHZ
0
20
0
30
ns
Output disable to high-Z output
tOHZ
0
20
0
30
ns
Output hold from address change
tOH
10
-
10
-
ns
Write cycle time
tWC
55
-
70
-
ns
Chip select to end of write
tCW
45
-
60
-
ns
Address set-up time
tAS
0
-
0
-
ns
Address valid to end of write
tAW
45
-
60
-
ns
Write pulse width
tWP
40
-
50
-
ns
Write recovery time
tWR
0
-
0
-
ns
Write to output high-Z
tWHZ
0
20
0
25
ns
Data to write time overlap
tDW
25
-
30
-
ns
Data hold from write time
tDH
0
-
0
-
ns
End write to output low-Z
tOW
5
-
5
-
ns
Min
Typ
Max
Unit
2.0
-
5.5
V
K6X0808C1D-F
-
-
10
µA
K6X0808C1D-Q
-
-
20
0
-
-
5
-
-
1. The parameter is tested with 50pF test load.
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Vcc for data retention
VDR
CS≥Vcc-0.2V
Data retention current
IDR
Vcc=3.0V, CS≥Vcc-0.2V
Data retention set-up time
tSDR
Recovery time
tRDR
See data retention waveform
5
ms
Revision 1.0
December 2003
K6X0808C1D Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tOE
OE
Data out
High-Z
tOHZ
tOLZ
tLZ
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 1.0
December 2003
K6X0808C1D Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS
Controlled)
tWC
Address
tCW(2)
tAS(3)
tWR(4)
CS
tAW
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC
Data Retention Mode
tSDR
tRDR
4.5V
2.2V
VDR
CS≥VCC - 0.2V
CS
GND
7
Revision 1.0
December 2003
K6X0808C1D Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeter(inch)
28 PIN DUAL INLINE PACKAGE(600mil)
0.25
+0.10
-0.05
+0.004
0.010-0.002
#28
#15
#1
#14
15.24
0.600
13.60±0.20
0.535±0.008
0~15°
3.81±0.20
0.150±0.008
5.08
0.200 MAX
36.72 MAX
1.446
36.32±0.20
1.430±0.008
3.30±0.30
0.130±0.012
0.46±0.10
0.018±0.004
1.52±0.10
0.060±0.004
( 1.65 )
0.065
0.38
0.015 MIN
2.54
0.100
28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)
0~8°
#15
11.81±0.30
0.465±0.012
#1
8.38±0.20
0.330±0.008
#14
+0.10
-0.05
0.006+0.004
-0.002
0.15
2.59±0.20
0.102±0.008
18.69
0.736 MAX
11.43
0.450
#28
1.02±0.20
0.040±0.008
3.00
0.118MAX
18.29±0.20
0.720±0.008
0.10 MAX
0.004 MAX
(
0.89
)
0.035
0.41±0.10
0.016±0.004
1.27
0.050
8
0.05 MIN
0.002
Revision 1.0
December 2003
K6X0808C1D Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeter(inch)
0.10 MAX
0.004 MAX
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
+0.10
-0.05
0.008+0.004
-0.002
0.20
13.40±0.20
0.528±0.008
#1
#28
0.55
0.0217
#14
0.425
)
0.017
8.00
0.315
8.40
0.331 MAX
(
#15
1.00±0.10
0.039±0.004
0.05
0.002 MIN
1.20
0.047 MAX
0.10 MAX
0.004 MAX
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)
+0.10
-0.05
+0.004
0.008-0.002
0.20
13.40±0.20
0.528±0.008
#14
#15
0.55
0.0217
#1
0.25
0.010 TYP
0.425
)
0.017
8.00
0.315
8.40
0.331 MAX
(
#28
11.80±0.10
0.465±0.004
+0.10
-0.05
+0.004
0.006-0.002
0.15
1.00±0.10
0.039±0.004
0.05
0.002 MIN
1.20
0.047 MAX
0~8°
0.45 ~0.75
0.018 ~0.030
(
9
0.50
)
0.020
Revision 1.0
December 2003
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