INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4001B gates Quadruple 2-input NOR gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4001B gates Quadruple 2-input NOR gate DESCRIPTION The HEF4001B provides the positive quadruple 2-input NOR function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. Fig.2 Pinning diagram. HEF4001BP(N): 14-lead DIL; plastic (SOT27-1) HEF4001BD(F): 14-lead DIL; ceramic (cerdip) HEF4001BT(D): 14-lead SO; plastic (SOT73) (SOT108-1) ( ): Package Designator North America Fig.1 Functional diagram. Fig.3 Logic diagram (one gate). FAMILY DATA, IDD LIMITS category GATES See Family Specifications January 1995 2 Philips Semiconductors Product specification HEF4001B gates Quadruple 2-input NOR gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V TYPICAL EXTRAPOLATION FORMULA SYMBOL TYP MAX 60 120 ns 33 ns + (0,55 ns/pF) CL tPHL 25 50 ns 14 ns + (0,23 ns/pF) CL 20 40 ns 12 ns + (0,16 ns/pF) CL Propagation delays In → On HIGH to LOW 5 10 15 5 LOW to HIGH 10 tPLH 15 Output transition times HIGH to LOW 5 10 tTHL 15 5 LOW to HIGH 10 15 VDD V Dynamic power 5 tTLH 50 100 ns 23 ns + (0,55 ns/pF) CL 25 45 ns 14 ns + (0,23 ns/pF) CL 20 35 ns 12 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL TYPICAL FORMULA FOR P (µW) 1100 fi + ∑ (foCL) × VDD2 where fi = input freq. (MHz) dissipation per 10 5000 fi + ∑ (foCL) × package (P) 15 14 200 fi + ∑ (foCL) × VDD2 VDD2 fo = output freq. (MHz) CL = load capacitance (pF) ∑(foCL) = sum of outputs VDD = supply voltage (V) January 1995 3