Sharp LH28F160SGED-L10 16 m-bit (512 kb x 16 x 2-bank) smartvoltage dual work flash memory Datasheet

LH28F160SGED-L10
LH28F160SGED-L10
16 M-bit (512 kB x 16 x 2-Bank)
SmartVoltage Dual Work Flash Memory
DESCRIPTION
The LH28F160SGED-L10 Dual Work flash memory
with SmartVoltage technology is a high-density,
low-cost, nonvolatile, read/write storage solution for
a wide range of applications. The LH28F160SGEDL10 is the highest density, highest performance
non-volatile read/write solution for solid-state
storage applications. LH28F160SGED-L10 can
read/write/erase at VCC = 2.7 V and VPP = 2.7 V.
Its low voltage operation capability realizes longer
battery life and suits for cellular phone application.
Its symmetrically-blocked architecture, flexible
voltage and enhanced cycling capability provide for
highly flexible component suitable for resident flash
arrays, SIMMs and memory cards. Its enhanced
suspend capabilities provide for an ideal solution for
code + data storage applications. For secure code
storage applications, such as networking, where
code is either directly executed out of flash or
downloaded to DRAM, the LH28F160SGED-L10
offers three levels of protection : absolute protection
with VPP at GND, selective hardware block locking,
or flexible software block locking. These alternatives
give designers ultimate control of their code security
needs.
FEATURES
• SmartVoltage Dual Work technology
– 2.7 V, 3.3 V or 5 V VCC
– 2.7 V, 3.3 V, 5 V or 12 V VPP
– Capable of performing erase, write and read
for each bank independently (Impossible to
perform read from both banks at a time).
• High performance read access time
– 100 ns (5.0±0.5 V)/100 ns (3.3±0.3 V)/
120 ns (2.7 to 3.6 V)
• Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• Enhanced data protection features
– Absolute protection with VPP = GND
– Flexible block locking
– Block erase/word write lockout during power
transitions
• SRAM-compatible write interface
• High-density symmetrically-blocked architecture
– Thirty-two 32 k-word erasable blocks
• Enhanced cycling capability
– 100 000 block erase cycles
– 1.6 million block erase cycles/bank
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases Icc
in static mode
• Automated word write and block erase
– Command user interface
– Status register
• ETOXTM∗ V nonvolatile flash technology
• Package
– 48-pin TSOP Type I (TSOP048-P-1220)
Normal bend
∗ ETOX is a trademark of Intel Corporation.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
-1-
LH28F160SGED-L10
PIN CONNECTIONS
48-PIN TSOP (Type I)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
VPP
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
TOP VIEW
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
(TSOP048-P-1220)
-2-
A16
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
BE1#
BE0#
A0
LH28F160SGED-L10
BLOCK DIAGRAM
Bank1
DQ0-DQ15
Bank0
INPUT
BUFFER
OUTPUT
BUFFER
I/O
LOGIC
IDENTIFIER
REGISTER
DATA
REGISTER
OUTPUT
MULTIPLEXER
BE1#
STATUS
REGISTER
BE0#
WE#
COMMAND
USER
INTERFACE
OE#
WP#
RP#
DATA
COMPARATOR
A0-A18
INPUT
BUFFER
ADDRESS
LATCH
Y DECODER
X DECODER
VCC
WRITE
STATE
MACHINE
Y GATING
PROGRAM/ERASE
VOLTAGE SWITCH
VPP
VCC
16
32 k-WORD
BLOCKS
GND
ADDRESS
COUNTER
-3-
LH28F160SGED-L10
PIN DESCRIPTION
SYMBOL
TYPE
A0-A18
INPUT
NAME AND FUNCTION
ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
DQ0-DQ15
INPUT/
OUTPUT
data during memory array, status register, and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
BANK ENABLE : Activates the device’s control logic, input buffers, decoders, and
BE0#,
BE1#
INPUT
sense amplifiers. When BE0# are "low", bank0 is in active. When BE1# are "low", bank1
is in active. Both BE0# and BE1# must not be low at the same time. BE0#, BE1#-high
deselects the device and reduces power consumption to standby levels.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
RP#
INPUT
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
RP# at VHH allows to set permanent lock-bit. Block erase, word write, or lock-bit
configuration with VIH ≤ RP# ≤ VHH produce spurious results and should not be
attempted.
OE#
INPUT
WE#
INPUT
WP#
INPUT
OUTPUT ENABLE : Controls the device's outputs during a read cycle.
WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
WRITE PROTECT : Master control for block locking. When VIL, locked blocks cannot be
erased and programmed, and block lock-bits cannot be set and reset.
BLOCK ERASE, WORD WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY :
For erasing array blocks, writing words, or configuring lock-bits. With VPP ≤ VPPLK,
VPP
SUPPLY
memory contents cannot be altered. Block erase, word write, and lock-bit configuration
with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious
results and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configured the device for 2.7 V, 3.3 V or
5 V operation. To switch from one voltage to another, ramp VCC down to GND and then
VCC
SUPPLY
ramp VCC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write
attempts to the flash memory are inhibited. Device operations at invalid VCC voltage
(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
GND
NC
SUPPLY
not be attempted.
GROUND : Do not float any ground pins.
NO CONNECT : Lead is not internal connected; recommend to be floated.
-4-
LH28F160SGED-L10
1 INTRODUCTION
This datasheet contains LH28F160SGED-L10
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F160SGEDL10 flash memory documentation also includes
ordering information which is referenced in
Section 7.
1.1
New Features
Key enhancements of LH28F160SGED-L10
SmartVoltage Dual Work flash memory are :
• SmartVoltage Dual Work Technology
• Enhanced Suspend Capabilities
• In-System Block Locking
• Permanent Lock Capability
Note following important differences :
• VPPLK has been lowered to 1.5 V to support
3.3 V and 5 V block erase, word write, and lockbit configuration operations. Designs that switch
VPP off during read operations should make sure
that the VPP voltage transitions to GND.
• To take advantage of SmartVoltage technology,
allow VCC connection to 2.7 V, 3.3 V or 5 V.
• Once set the permanent lock bit, the blocks
which have been set block lock-bit can not be
erased, written forever.
1.2
select one of banks. BE0# is assigned to No. 26
pin which is CE# in LH28F800SGE-L10, BE1#
is assigned to No. 27 pin which is GND in
LH28F800SGE-L10. To select either bank (bank0)
BE0# must be "L", and to select another bank
(bank1) BE1# must be "L". Selecting both banks
(bank0 and bank1) at a time, except of read
operation (array read, status register read), turns
both BE0# and BE1# to "L".
Product Overview
The LH28F160SGED-L10 is a high-performance
16 M-bit SmartVoltage Dual Work flash memory
organized as 1 024 k-word of 16 bits. The 1 024 kword of data is arranged in thirty-two 32 k-word
blocks which are individually erasable, lockable,
and unlockable in-system. The memory map is
shown in Fig. 1.
All pins except of BE# are shared by both banks,
and BE# is divided to BE0# and BE1# in order to
-5-
Operation mode of bank0 and bank1 as follows :
1) Both bank0 and bank1 are in deep power-down
(RP# = "L").
2) Both bank0 and bank1 are in standby
(BE0# = BE1# = "H").
3) Bank0 is in standby and bank1 is in active state
of programming or erase, or bank0 is in active
state of programming or erase and bank1 is in
standby.
4) Both bank0 and bank1 are in active state
(impossible to perform simultaneous read from
both banks). In this case bank0 and bank1
perform independent operation, for example,
after input Erase command to bank0 erase or
program command to bank1 is succeeded,
bank0 and bank1 perform each operation
concurrently.
SmartVoltage technology provides a choice of VCC
and VPP combinations, as shown in Table 1, to
meet system performance and power expectations.
2.7 to 3.6 V VCC consumes approximately one-fifth
the power of 5 V VCC. But, 5 V VCC provides the
highest read performance. VPP at 3.3 V and 5 V
eliminates the need for a separate 12 V converter,
while VPP = 12 V maximizes block erase and word
write performance. In addition to flexible erase and
program voltages, the dedicated VPP pin gives
complete data protection when VPP ≤ VPPLK.
LH28F160SGED-L10
Table 1 VCC and VPP Voltage Combinations
Offered by SmartVoltage Technology
VCC VOLTAGE
VPP VOLTAGE
2.7 V
2.7 V, 3.3 V, 5 V, 12 V
3.3 V
5V
3.3 V, 5 V, 12 V
5 V, 12 V
In each bank0, 1 contains of Status Registers. The
status register indicates when the WSM’s block
erase, word write, or lock-bit configuration operation
is finished.
Internal VCC and VPP detection circuitry automatically configures the device for optimized read
and write operations.
A command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timing
necessary for block erase, word write, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
32 k-word blocks typically within 1.2 second (5 V
VCC, 12 V VPP) independent of other blocks. Each
block can be independently erased 100 000 times
(1.6 million block erases per device). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.
Writing memory data is performed in word
increments typically within 7.5 µs (5 V VCC, 12 V
VPP). Word write suspend mode enables the
system to read data from, or write data to any other
flash memory array location.
The selected block can be locked or unlocked
individually by the combination of thirty-two block
lock bits and the RP# or WP#. Block erase or word
write must not be carried out by setting block lock
bits and setting WP# to low and RP# to VIH. Even
if WP# is high state or RP# is set to VHH, block
erase and word write to locked blocks is prohibited
by setting permanent lock bit.
-6-
The LH28F160SGED-L10 also incorporates a dual
bank-enable function with two input pins, BE0# and
BE1#. For minimum chip designs, BE0# may be
tied to ground and use BE1# as the bank enable
input. The LH28F160SGED-L10 uses the logical
combination of these two signals to enable or
disable the entire chip. Both BE0# and BE1# must
be active low to enable the device and if either one
becomes inactive, the bank will be disabled. This
feature allows the system designer to reduce the
number of control pins used in a large array of
16 M-bit devices.
The access time is 100 ns (tAVQV) at the VCC
supply voltage range of 4.5 to 5.5 V over the
temperature range, –10 to +70˚C. At lower VCC
voltage, the access time is 100 ns (3.0 to 3.6 V)
and 120 ns (2.7 to 3.6 V).
The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 1 mA at
5 V VCC and 3 mA at 2.7 to 3.6 V VCC, both
bank0, 1 are in active state.
When BE# and RP# pins are at VCC, the ICC
CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (tPHQV) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.
LH28F160SGED-L10
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
32 k-Word Block
15
32 k-Word Block
14
32 k-Word Block
13
32 k-Word Block
12
32 k-Word Block
11
32 k-Word Block
10
32 k-Word Block
9
32 k-Word Block
8
32 k-Word Block
7
32 k-Word Block
6
32 k-Word Block
5
32 k-Word Block
4
32 k-Word Block
3
32 k-Word Block
2
32 k-Word Block
1
32 k-Word Block
0
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
32 k-Word Block
15
32 k-Word Block
14
32 k-Word Block
13
32 k-Word Block
12
32 k-Word Block
11
32 k-Word Block
10
32 k-Word Block
9
32 k-Word Block
8
32 k-Word Block
7
32 k-Word Block
6
32 k-Word Block
5
32 k-Word Block
4
32 k-Word Block
3
32 k-Word Block
2
32 k-Word Block
1
32 k-Word Block
0
Bank1
(BE1# = "L")
Bank0
(BE0# = "L")
Fig.1 Memory Map
2 PRINCIPLES OF OPERATION
The LH28F800SGE-L10 SmartVoltage Dual Work
flash memory includes an on-chip WSM to manage
block erase, word write, and lock-bit configuration
functions. It allows for 100% TTL-level : control
inputs, fixed power supplies during block erasure,
word write, and lock-bit configuration, and minimal
processor overhead with RAM-like interface timings.
After initial device power-up or return from deep
power-down mode (see Table 2 "Bus Operations"),
the device defaults to read array mode.
Manipulation of external memory control pins allow
array read, standby, and output disable operations.
Status register and identifier codes can be
accessed through the CUI independent of the VPP
voltage. High voltage on VPP enables successful
-7-
block erasure, word writing, and lock-bit
configuration. All functions associated with altering
memory contents—block erase, word write, lock-bit
configuration, status, and identifier codes—are
accessed via the CUI and verified through the
status register.
Commands are written using standard microprocessor write timings. The CUI contents serve as
input to the WSM, which controls the block erase,
word write, and lock-bit configuration. The internal
algorithms are regulated by the WSM, including
pulse repetition, internal verification, and margining
of data. Addresses and data are internally latched
during write cycles. Writing the appropriate
command outputs array data, accesses the
identifier codes, or outputs status register data.
LH28F160SGED-L10
Interface software that initiates and polls progress
of block erase, word write, and lock-bit configuration
can be stored in any block. This code is copied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system
software to suspend a block erase to read/write
data from/to blocks other than that which is
suspended. Word write suspend allows system
software to suspend a word write to read data from
any other flash memory array location.
2.1
Data Protection
Depending on the application, the system designer
may choose to make the VPP power supply
switchable (available only when memory block
erases, word writes, or lock-bit configurations are
required) or hardwired to VPPH1/2/3. The device
accommodates either design practice and
encourages optimization of the processor-memory
interface.
When VPP ≤ VPPLK, memory contents cannot be
altered. The CUI, with two-step block erase, word
write, or lock-bit configuration command sequences,
provides protection from unwanted operations even
when high voltage is applied to VPP. All write
functions are disabled when VCC is below the write
lockout voltage VLKO or when RP# is at VIL. The
device’s block locking capability provides additional
protection from inadvertent code or data alteration
by gating erase and word write operations.
3 BUS OPERATION
The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1
Read
Information can be read from any block, identifier
codes, or status register independent of the VPP
voltage. RP# can be at either VIH or VHH.
-8-
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep powerdown mode, the device automatically resets to read
array mode. Five control pins dictate the data flow
in and out of the component : BE#, OE#, WE#,
RP# and WP#. BE# and OE# must be driven
active to obtain data at the outputs. BE# is the
device selection control, and when active enables
the selected memory device. OE# is the data
output (DQ0-DQ15) control and when active drives
the selected memory data onto the I/O bus. WE#
must be at VIH and RP# must be at VIH or VHH.
Fig. 13 illustrates read cycle.
3.2
Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0-DQ15 are
placed in a high-impedance state.
3.3
Standby
BE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ0-DQ15 outputs are placed
in a high-impedance state independent of BE#. If
deselected during block erase, word write, or lockbit configuration, the device continues functioning,
and consuming active power until the operation
completes.
3.4
Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time tPHQV is required
after return from power-down until initial memory
access outputs are valid. After this wake-up interval,
normal operation is restored. The CUI is reset to
read array mode and status register is set to 80H.
LH28F160SGED-L10
During block erase, word write, or lock-bit
configuration modes, RP#-low will abort the operation.
Memory contents being altered are no longer valid;
the data may be partially erased or written. Time
tPHWL is required after RP# goes to logic-high (VIH)
before another command can be written.
memories allow proper CPU initialization following a
system reset through the use of the RP# input. In
this application, RP# is controlled by the same
RESET# signal that resets the system CPU.
3.5
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase,
word write, or lock-bit configuration modes. If a
CPU reset occurs with no flash memory reset,
proper CPU initialization may not occur because
the flash memory may be providing status
information instead of array data. SHARP’s flash
7FFFF
78004
7FFFF
Reserved for
Future Implementation
78004
78003
78002
78001
78000
Reserved for
Future Implementation
78003
Block 15 Lock Configuration Code
78002
Block 15 Lock Configuration Code
Reserved for
Future Implementation
78001
Reserved for
Future Implementation
Block 15
78000
Block 15
(Blocks 2 through 14)
(Blocks 2 through 14)
0FFFF
08004
Read Identifier Codes
The read identifier codes operation outputs the
manufacture code, device code, block lock
configuration codes for each block, and the
permanent lock configuration code (see Fig. 2).
Using the manufacture and device codes, the
system CPU can automatically match the device
with its proper algorithms. The block lock and
permanent lock configuration codes identify locked
and unlocked blocks and permanent bank lock-bit
setting.
0FFFF
Reserved for
Future Implementation
08004
08003
Reserved for
Future Implementation
08003
08002
Block 1 Lock Configuration Code
08002
Block 1 Lock Configuration Code
08001
Reserved for
Future Implementation
08001
Reserved for
Future Implementation
08000
Block 1
07FFF
08000
Block 1
07FFF
Reserved for
Future Implementation
Reserved for
Future Implementation
00004
00004
00003
Permanent Lock Configuration Code
00003
Permanent Lock Configuration Code
00002
Block 0 Lock Configuration Code
00002
Block 0 Lock Configuration Code
00001
Device Code
00001
Device Code
00000
Manufacture Code
00000
Manufacture Code
Block 0
Bank1
(BE1# = "L")
Bank0
(BE0# = "L")
Fig. 2 Device Identifier Code Memory Map
-9-
Block 0
LH28F160SGED-L10
3.6
Write
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
BE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 14 and
Fig. 15 illustrate WE# and BE# controlled write
operations.
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register.
The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word Write command requires the
command and address of the location to be written.
Set Permanent Bank and Block Lock-Bit
commands require the command and address
within the device (Permanent Bank Lock) or block
within the device (Block Lock) to be locked. The
Clear Block Lock-Bits command requires the
command and address within the device.
4 COMMAND DEFINITIONS
When the VPP ≤ VPPLK, read operations from the
status register, identifier codes, or blocks are
enabled. Placing VPPH1/2/3 on VPP enables
successful block erase, word write and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
The CUI does not occupy an addressable memory
location. It is written when WE# and BE# are
Table 2 Bus Operations
MODE
NOTE
Bank0
Read
Bank1
Disable
1, 2,
VIH or
7, 8
VHH
Output Disable
VIH or VHH
Bank0
Standby
VIH or
VHH
Bank1
Bank0, 1
Deep Power-Down
3
Bank0
Read Identifier Codes
Bank1
7, 8
Disable
Bank0
Write
RP#
Bank1
Bank0, 1
5, 6, 7
BE0#
BE1#
VIL
VIH
OE#
VIH
VIL
VIL
VIL
VIL
X
VIH
X
VIL
VIL
VIH
WE#
ADDRESS
VPP
DQ0-15
VIH
X
X
DOUT
VIH
VIH
X
X
High Z
VIH
VIH
X
X
X
X
High Z
X
X
High Z
X
(NOTE 4)
X
DIN
VIL
X
X
X
X
VIH or
VIL
VIH
VIH
VIL
VIL
VIH
VIL
VIL
VIL
VIH
VIH
VIL
VIH
VIL
VIL
VIL
VHH
VIH or
VHH
See
Fig. 2
X
NOTES :
1.
2.
3.
Refer to Section 6.2.3 "DC CHARACTERISTICS".
When VPP ≤ VPPLK, memory contents can be read, but
not altered.
X can be VIL or VIH for control pins and addresses, and
VPPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC
CHARACTERISTICS" for VPPLK and VPPH1/2/3 voltages.
RP# at GND±0.2 V ensures the lowest deep powerdown current.
4.
5.
6.
7.
8.
- 10 -
See Section 4.2 for read identifier code data.
VIH < RP# < VHH produce spurious results and should
not be attempted.
Refer to Table 3 for valid DIN during a write operation.
Don’t use the timing both OE# and WE# are VIL.
Impossible to perform simultaneous read from both
banks at a time. Both BE0# and BE1# must not be low
at the same time.
LH28F160SGED-L10
COMMAND
Read Array/Reset
Table 3 Command Definitions (NOTE 9)
FIRST BUS CYCLE
SECOND BUS CYCLE
BUS CYCLES
NOTE
REQ’D.
Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3)
1
Write
X
FFH
Read Identifier Codes
Read Status Register
≥2
2
Clear Status Register
Block Erase
1
2
Word Write
4
Write
Write
X
X
90H
70H
5
Write
Write
X
BA
50H
20H
2
5, 6
Write
WA
40H or 10H
Block Erase and
Word Write Suspend
1
5
Write
X
B0H
Block Erase and
Word Write Resume
1
5
Write
X
D0H
Set Block Lock-Bit
2
7
Write
BA
60H
Set Permanent Bank
Lock-Bit
2
7
Write
X
Clear Block Lock-Bits
2
8
Write
X
Read
Read
IA
X
ID
SRD
Write
BA
D0H
Write
WA
WD
Write
BA
01H
60H
Write
X
F1H
60H
Write
X
D0H
NOTES :
1.
2.
3.
4.
5.
BUS operations are defined in Table 2.
X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
SRD = Data read from status register. See Table 6 for a
description of the status register bits.
WD = Data to be written at location WA. Data is latched
on the rising edge of WE# or BE# (whichever
goes high first).
ID = Data read from identifier codes.
Following the Read Identifier Codes command, read
operations access manufacture, device, block lock, and
permanent lock codes. See Section 4.2 for read
identifier code data.
If the block is locked and the permanent lock-bit is not
set, WP# must be at VIH or RP# must be at VHH to
enable block erase or word write operations. Attempts to
issue a block erase or word write to a locked block while
WP# is VIH or RP# is VHH.
6.
Either 40H or 10H is recognized by the WSM as the
word write setup.
7. If the permanent bank lock-bit is set, WP# must be at
VIH or RP# must be at VHH to set a block lock-bit. RP#
must be at VHH to set the permanent lock-bit. If the
permanent lock-bit is set, a block lock-bit cannot be set.
Once the permanent lock-bit is set, permanent lock-bit
reset is unable.
8. If the permanent bank lock-bit is set, clear block lock-bits
operation is unable. The clear block lock-bits operation
simultaneously clears all block lock-bits. If the permanent
lock-bit is not set, the Clear Block Lock-Bits command
can be done while WP# is VIH or RP# is VHH.
9. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.
- 11 -
LH28F160SGED-L10
4.1
Read Array Command
4.3
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, word write or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend or Word
Write Suspend command. The Read Array
command functions independently of the VPP
voltage and RP# can be VIH or VHH.
4.2
The status register may be read to determine when
a block erase, word write, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
BE#, whichever occurs. OE# or BE# must toggle to
VIH before further reads to update the status
register latch. The Read Status Register command
functions independently of the VPP voltage. RP#
can be VIH or VHH.
Read Identifier Codes Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture, device, block
lock configuration and permanent lock configuration
codes (see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the VPP voltage and RP# can be
VIH or VHH. Following the Read Identifier Codes
command, the following information can be read :
Table 4 Identifier Codes
CODE
ADDRESS
Manufacture Code
00000H
Device Code
00001H
Block Lock Configuration
XX002H (NOTE 1)
• Unlocked
• Locked
• Reserved for future enhancement
Permanent Lock Configuration 00003H
• Unlocked
• Locked
• Reserved for future enhancement
4.4
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several words in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied VPP voltage. RP# can
be VIH or VHH. This command is not functional
during block erase or word write suspend modes.
DATA
00B0H
0050H
DQ0 = 0
DQ0 = 1
DQ1-15
4.5
DQ0 = 0
DQ0 = 1
DQ1-15
NOTES :
1.
Read Status Register Command
X selects the specific block lock configuration code to be
read. See Fig. 2 for the device identifier code memory
map.
Block Erase Command
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
- 12 -
LH28F160SGED-L10
After the two-cycle block erase sequence is written,
the device automatically outputs status register data
when read (see Fig. 3). The CPU can detect block
erase completion by analyzing the output data of
the status register bit SR.7.
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when VCC =
VCC1/2/3 and VPP = VPPH1/2/3. In the absence of this
high voltage, block contents are protected against
erasure. If block erase is attempted while VPP ≤
VPPLK, SR.3 and SR.5 will be set to "1". Successful
block erase requires that the corresponding block
lock-bit be cleared or, if set, that WP# = VIH or RP#
= VHH. If block erase is attempted when the
corresponding block lock-bit is set and WP# = VIL
and RP# = VIH, SR.1 and SR.5 will be set to "1".
Once permanent lock-bit is set, the blocks which
have been set block lock-bit are unable to erase
forever. Block erase operations with VIH < RP# <
VHH produce spurious results and should not be
attempted.
4.6
Word Write Command
Word write is executed by a two-cycle command
sequence. Word write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word write and write verify algorithms
internally. After the word write sequence is written,
the device automatically outputs status register data
when read (see Fig. 4). The CPU can detect the
completion of the word write event by analyzing the
status register bit SR.7.
When word write is complete, status register bit
SR.4 should be checked. If word write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for "1"s that
do not successfully write to "0"s. The CUI remains
in read status register mode until it receives another
command.
Reliable word writes can only occur when VCC =
VCC1/2/3 and VPP = VPPH1/2/3. In the absence of this
high voltage, memory contents are protected
against word writes. If word write is attempted while
VPP ≤ VPPLK, status register bits SR.3 and SR.4 will
be set to "1". Successful word write requires that
the corresponding block lock-bit be cleared or, if
set, that WP# = VIH or RP# = VHH. If word write is
attempted when the corresponding block lock-bit is
set and WP# = VIL and RP# = VIH, SR.1 and SR.4
will be set to "1". Once permanent lock-bit is set,
the blocks which have been set block lock-bit are
unable to write forever. Word write operations with
VIH < RP# < VHH produce spurious results and
should not be attempted.
4.7
Block Erase Suspend Command
The Block Erase Suspend command allows block
erase interruption to read or word write data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be
set to "1"). Specification tWHRH2 defines the block
erase suspend latency.
- 13 -
LH28F160SGED-L10
At this point, a Read Array command can be
written to read data from blocks other than that
which is suspended. A Word Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the Word
Write Suspend command (see Section 4.8), a
word write operation can also be suspended.
During a word write operation with block erase
suspended, status register bit SR.7 will return to
"0". However, SR.6 will remain "1" to indicate block
erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear.
After the Erase Resume command is written, the
device automatically outputs status register data
when read (see Fig. 5). VPP must remain at
VPPH1/2/3 (the same VPP level used for block erase)
while block erase is suspended. RP# must also
remain at VIH or VHH (the same RP# level used for
block erase). WP# must also remain at VIL or VIH
(the same WP# level used for block erase). Block
erase cannot resume until word write operations
initiated during block erase suspend have
completed.
4.8
Word Write Suspend Command
The Word Write Suspend command allows word
write interruption to read data in other flash memory
locations. Once the word write process starts,
writing the Word Write Suspend command requests
that the WSM suspend the word write sequence at
a predetermined point in the algorithm. The device
continues to output status register data when read
after the Word Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the word write operation has been
suspended (both will be set to "1"). Specification
tWHRH1 defines the word write suspend latency.
At this point, a Read Array command can be
written to read data from locations other than that
which is suspended. The only other valid
commands while word write is suspended are Read
Status Register and Word Write Resume. After
Word Write Resume command is written to the
flash memory, the WSM will continue the word
write process. Status register bits SR.2 and SR.7
will automatically clear. After the Word Write
Resume command is written, the device
automatically outputs status register data when
read (see Fig. 6). VPP must remain at VPPH1/2/3
(the same VPP level used for word write) while in
word write suspend mode. RP# must also remain
at VIH or VHH (the same RP# level used for word
write). WP# must also remain at VIL or VIH (the
same WP# level used for word write).
4.9
Set Block and Permanent Bank
Lock-Bit Commands
The combination of the software command
sequence and hardware WP#, RP# pin provides
most flexible block lock (write protection) capability.
The word write/block erase operation is restricted
by the status of block lock-bit, WP# pin, RP# pin
and permanent lock-bit. The status of WP# pin,
RP# pin and permanent lock-bit restricts the set
block bit. When the permanent lock-bit has not
been set, and when WP# = VIH or RP# = VHH, the
block lock bit can be set with the status of the RP#
pin. When RP# = VHH, the permanent lock-bit can
be set with the permanent lock-bit set command.
After the permanent lock-bit has been set, the
write/erase operation to the block lock-bit can never
be accepted. Refer to Table 5 for the hardware
and the software write protection.
Set block lock-bit and permanent lock-bit are
executed by a two-cycle command sequence. The
set block or permanent lock-bit setup along with
appropriate block or device address is written
followed by either the set block lock-bit confirm (and
an address within the block to be locked) or the set
- 14 -
LH28F160SGED-L10
permanent lock-bit confirm (and any device
address). The WSM then controls the set lock-bit
algorithm. After the sequence is written, the device
automatically outputs status register data when
read (see Fig. 7). The CPU can detect the
completion of the set lock-bit event by analyzing the
status register bit SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of set-up followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Permanent Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations
occur only when VCC = VCC1/2/3 and VPP =
VPPH1/2/3. In the absence of this high voltage, lockbit contents are protected against alteration.
A successful set block lock-bit operation requires
that the permanent lock-bit be cleared and WP# =
VIH or RP# = VHH. If it is attempted with the
permanent lock-bit set, SR.1 and SR.4 will be set
to "1" and the operation will fail. Set block lock-bit
operations while VIH < RP# < VHH produce
spurious results and should not be attempted. A
successful set permanent lock-bit operation requires
that RP# = VHH. If it is attempted with RP# = VIH,
SR.1 and SR.4 will be set to "1" and the operation
will fail. Set permanent lock-bit operations with VIH
< RP# < VHH produce spurious results and should
not be attempted.
4.10 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the
permanent lock-bit not set and WP# = VIH or RP#
= VHH, block lock-bits can be cleared using the
Clear Block Lock-Bits command. If the permanent
lock-bit is set, clear block lock-bits operation is
unable. See Table 5 for a summary of hardware
and software write protection options.
Clear block lock-bits option is executed by a twocycle command sequence. A clear block lock-bits
setup is first written. After the command is written,
the device automatically outputs status register data
when read (see Fig. 8). The CPU can detect
completion of the clear block lock-bits event by
analyzing the status register bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bits
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block LockBits command sequence will result in status register
bits SR.4 and SR.5 being set to "1". Also, a reliable
clear block lock-bits operation can only occur when
VCC = VCC1/2/3 and VPP = VPPH1/2/3. In a clear
block lock-bits operation is attempted while VPP ≤
VPPLK, SR.3 and SR.5 will be set to "1". In the
absence of this high voltage, the block lock-bit
contents are protected against alteration. A
successful clear block lock-bits operation requires
that the permanent lock-bit is not set and WP# =
VIH or RP# = VHH. If it is attempted with the
permanent lock-bit set or WP# = VIL and RP# =
VIH, SR.1 and SR.5 will be set to "1" and the
operation will fail. A clear block lock-bits operation
with VIH < RP# < VHH produce spurious results and
should not be attempted.
- 15 -
LH28F160SGED-L10
If a clear block lock-bits operation is aborted due to
VPP or VCC transition out of valid range or WP# or
RP# active transition, block lock-bit values are left
in an undetermined state. A repeat of clear block
lock-bits is required to initialize block lock-bit
contents to known values. Once the permanent
lock-bit is set, it cannot be cleared.
Table 5 Write Protection Alternatives (NOTE 1)
PERMANENT BLOCK
OPERATION
RP#
EFFECT
WP#
LOCK-BIT LOCK-BIT
X
0
X
VIH or VHH Block Erase and Word Write Enabled
VIH
Block Erase
or
Word Write
Set Block
0
VHH
1
VIL
VIH
1
X
0
VIH
VIL
X
Lock-Bit
1
Set Permanent
Bank Lock-Bit (NOTE 1)
X
VIL
X
X
X
VIH
Clear Block
VIH or VHH
0
X
Lock-Bits
1
X
Block Lock-Bit Override.
Block Erase and Word Write Enabled
Block Lock-Bit Override.
Block Erase and Word Write Enabled
Block is Locked.
Block Erase and Word Write Disabled
Permanent Lock-Bit is set.
Block Erase and Word Write Disabled
VIH or VHH Set Block Lock-Bit Enabled
VHH
VIH
X
VHH
VIH
Set Block Lock-Bit Enabled
Set Block Lock-Bit Disabled
Permanent Lock-Bit is set.
Set Block Lock-Bit Disabled
Set Permanent Lock-Bit Enabled
Set Permanent Lock-Bit Disabled
VIH or VHH Clear Block Lock-Bits Enabled
VIL
VIL
VHH
VIH
Clear Block Lock-Bits Enabled
Clear Block Lock-Bits Disabled
X
X
Permanent Lock-Bit is set.
Clear Block Lock-Bits Disabled
NOTE :
1.
There are two banks (bank0 and bank1). Each bank has it’s own permanent lock-bit.
- 16 -
LH28F160SGED-L10
Table 6 Status Register Definition
WSMS
7
ESS
6
ECLBS
5
WWSLBS
4
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
VPPS
3
WWSS
2
DPS
1
R
0
NOTES :
Check RY#/BY# or SR.7 to determine block erase, word
write, or lock-bit configuration completion. SR.6-0 are invalid
while SR.7 = "0".
SR.6 = ERASE SUSPEND STATUS (ESS)
If both SR.5 and SR.4 are "1"s after a block erase or lock-bit
configuration attempt, an improper command sequence was
entered.
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS (ECLBS)
SR.3 does not provide a continuous indication of VPP level.
1 = Error in Block Erase or Clear Lock-Bits
The WSM interrogates and indicates the VPP level only after
Block Erase, Word Write, Set Block/Permanent Lock-Bit, or
Clear Block Lock-Bits command sequences. SR.3 is not
guaranteed to reports accurate feedback only when VPP ≠
VPPH1/2/3.
0 = Successful Block Erase or Clear Lock-Bits
SR.4 = WORD WRITE AND SET LOCK-BIT STATUS
(WWSLBS)
1 = Error in Word Write or Set Permanent/Block
Lock-Bit
0 = Successful Word Write or Set Permanent/Block
Lock-Bit
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = WORD WRITE SUSPEND STATUS (WWSS)
1 = Word Write Suspended
0 = Word Write in Progress/Completed
SR.1 does not provide a continuous indication of permanent
and block lock-bit values. The WSM interrogates the
permanent lock-bit, block lock-bit, WP# and RP# only after
Block Erase, Word Write, or Lock-Bit configuration command
sequences. It informs the system, depending on the attempted
operation, if the block lock-bit is set, permanent lock-bit is set,
and/or WP# is not VIH, RP# is not VHH. Reading the block lock
and permanent lock configuration codes after writing the Read
Identifier Codes command indicates permanent and block
lock-bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Permanent Lock-Bit, Block Lock-Bit and/or
WP#/RP# Lock Detected, Operation Abort
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
- 17 -
LH28F160SGED-L10
BUS
OPERATION COMMAND
Start
Write 20H,
Block Address
Write D0H,
Block Address
Read
Status Register
No
0
Suspend Block
Erase Loop
Suspend
Block Erase
SR.7 =
Yes
1
COMMENTS
Write
Erase Setup
Data = 20H
Addr = Within Block to be Erased
Write
Erase
Confirm
Data = D0H
Addr = Within Block to be Erased
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures.
Full status check can be done after each block erase or after
a sequence of block erasures.
Write FFH after the last block erase operation to place device
in read array mode.
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
BUS
OPERATION COMMAND
SR.1 =
1
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
RP# = VIH, Block Lock-Bit is Set
Only required for systems
implementing lock-bit configuration
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.5
1 = Block Erase Error
VPP Range Error
0
Device Protect Error
0
SR.4, 5 =
1
Command Sequence
Error
0
SR.5 =
1
Block Erase
Error
COMMENTS
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple blocks
are erased before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
0
Block Erase
Successful
Fig. 3 Automated Block Erase Flowchart
- 18 -
LH28F160SGED-L10
BUS
OPERATION COMMAND
Start
Write 40H,
Address
Write Word
Data and Address
Read
Status Register
No
0
Suspend Word
Write Loop
Suspend
Word Write
SR.7 =
Yes
COMMENTS
Write
Setup
Word Write
Data = 40H
Addr = Location to be Written
Write
Word Write
Data = Data to be Written
Addr = Location to be Written
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent word writes.
SR full status check can be done after each word write or
after a sequence of word writes.
Write FFH after the last word write operation to place device
in read array mode.
1
Full Status
Check if Desired
Word Write
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
BUS
OPERATION COMMAND
SR.1 =
1
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
RP# = VIH, Block Lock-Bit is Set
Only required for systems
implementing lock-bit configuration
Standby
Check SR.4
1 = Data Write Error
VPP Range Error
0
Device Protect Error
0
SR.4 =
0
1
Word Write Error
COMMENTS
SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple locations are
written before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
Word Write
Successful
Fig. 4 Automated Word Write Flowchart
- 19 -
LH28F160SGED-L10
BUS
OPERATION
Start
Write
Write B0H
COMMENTS
COMMAND
Erase
Suspend
Data = B0H
Addr = X
Read
Status Register Data
Addr = X
Read
Status Register
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
0
Standby
Check SR.6
1 = Block Erase Suspended
0 = Block Erase Completed
SR.7 =
1
SR.6 =
Write
0
Erase
Resume
Data = D0H
Addr = X
Block Erase
Completed
1
Read
Read
or Word
Write?
Read Array Data
Word Write
Word Write Loop
No
Done?
Yes
Write D0H
Write FFH
Block Erase
Resumed
Read
Array Data
Fig. 5 Block Erase Suspend/Resume Flowchart
- 20 -
LH28F160SGED-L10
BUS
OPERATION
Start
Write
Write B0H
Read
Status Register
0
SR.7 =
1
SR.2 =
Word Write
Completed
1
Word Write
Suspend
Data = B0H
Addr = X
Read
Status Register Data
Addr = X
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.2
1 = Word Write Suspended
0 = Word Write Completed
Write
0
COMMENTS
COMMAND
Read Array
Read array locations other
than that being written.
Read
Write
Data = FFH
Addr = X
Word Write
Resume
Data = D0H
Addr = X
Write FFH
Read
Array Data
Done
Reading
No
Yes
Write D0H
Write FFH
Word Write Resumed
Read
Array Data
Fig. 6 Word Write Suspend/Resume Flowchart
- 21 -
LH28F160SGED-L10
BUS
OPERATION
Start
COMMAND
COMMENTS
Write 60H,
Block/Device Address
Write
Set
Data = 60H
Block/Permanent
Addr = Block Address (Block),
Lock-Bit
Device Address (Permanent)
Setup
Write 01H/F1H,
Block/Device Address
Write
Set
Data = 01H (Block),
Block or Permanent
F1H (Permanent)
Lock-Bit
Addr = Block Address (Block),
Confirm
Device Address (Permanent)
Read
Status Register
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
0
Repeat for subsequent lock-bit set operations.
SR.7 =
Full status check can be done after each lock-bit set
operation or after a sequence of lock-bit set operations.
1
Write FFH after the last lock-bit set operation to place device
in read array mode.
Full Status
Check if Desired
Set Lock-Bit
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
BUS
OPERATION COMMAND
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
RP# = VIH
(Set Permanent Lock-Bit Operation)
WP# = VIL and RP# = VIH or
Permanent Lock-Bit is Set
(Set Block Lock-Bit Operarion)
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.4
1 = Set Lock-Bit Error
1
SR.3 =
VPP Range Error
0
SR.1 =
1
Device Protect Error
0
1
SR.4, 5 =
Command Sequence
Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple lock-bits
are set before full status is checked.
0
SR.4 =
COMMENTS
1
Set Lock-Bit
Error
If error is detected, clear the status register before attempting
retry or other error recovery.
0
Set Lock-Bit
Successful
Fig. 7 Set Block and Permanent Lock-Bit Flowchart
- 22 -
LH28F160SGED-L10
BUS
OPERATION
Start
Write 60H
Write
Clear Block
Lock-Bits
Setup
Data = 60H
Addr = X
Write
Clear Block
Lock-Bits
Confirm
Data = D0H
Addr = X
Write D0H
Read
Status Register
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write FFH after the last clear block lock-bits operation to place
device in read array mode.
0
SR.7 =
COMMENTS
COMMAND
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
BUS
OPERATION COMMAND
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
WP# = VIL and RP# = VIH or
Permanent Lock-Bit is Set
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.5
1 = Clear Block Lock-Bits Error
1
SR.3 =
VPP Range Error
0
SR.1 =
1
Device Protect Error
0
1
SR.4, 5 =
Command Sequence
Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command.
If error is detected, clear the status register before attempting
retry or other error recovery.
0
SR.5 =
COMMENTS
1
Clear Block Lock-Bits
Error
0
Clear Block Lock-Bits
Successful
Fig. 8 Clear Block Lock-Bits Flowchart
- 23 -
LH28F160SGED-L10
5 DESIGN CONSIDERATIONS
5.3
5.1
Three-Line Output Control
The device will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections. Threeline control provides for :
a. Lowest possible memory power consumption.
b. Complete assurance that data bus contention
will not occur.
To use these control inputs efficiently, an address
decoder should enable BE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2
Power Supply Decoupling
Flash memory power switching characteristics
require careful device decoupling. System
designers are interested in three supply current
issues; standby current levels, active current levels
and transient peaks produced by falling and rising
edges of BE# and OE#. Transient current
magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device
should have a 0.1 µF ceramic capacitor connected
between its VCC and GND and between its VPP
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7 µF electrolytic capacitor should be placed at
the array’s power supply connection between VCC
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
VPP Trace on Printed Circuit Boards
Updating flash memories that reside in the target
system requires that the printed circuit board
designers pay attention to the VPP power supply
trace. The VPP pin supplies the memory cell current
for word writing and block erasing. Use similar trace
widths and layout considerations given to the VCC
power bus. Adequate VPP supply traces and
decoupling will decrease VPP voltage spikes and
overshoots.
5.4
VCC, VPP, RP# Transitions
Block erase, word write and lock-bit configuration
are not guaranteed if VPP falls outside of a valid
VPPH1/2/3 range, VCC falls outside of a valid VCC1/2/3
range, or RP# ≠ VIH or VHH. If VPP error is
detected, status register bit SR.3 is set to "1" along
with SR.4 or SR.5, depending on the attempted
operation. Then, the operation will abort and the
device will enter deep power-down. The aborted
operation may leave data partially altered.
Therefore, the command sequence must be
repeated after normal operation is restored. Device
power-off or RP# transitions to VIL clear the status
register.
The CUI latches commands issued by system
software and is not altered by VPP or BE#
transitions or WSM actions. Its state is read array
mode upon power-up, after exit from deep powerdown or after VCC transitions below VLKO.
After block erase, word write, or lock-bit
configuration, even after VPP transitions down to
VPPLK, the CUI must be placed in read array mode
via the Read Array command if subsequent access
to the memory array is desired.
5.5
Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure, word writing, or lock-bit
configuration during power transitions. Upon power-
- 24 -
LH28F160SGED-L10
up, the device is indifferent as to which power
supply (VPP or VCC) powers-up first. Internal
circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active. Since both WE# and BE# must be low for a
command write, driving either to VIH will inhibit
writes. The CUI’s two-step command sequence
architecture provides added level of protection
against data alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP# = VIL regardless of its control inputs
state.
5.6
Power Consumption
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is
retained when system power is removed.
In addition, deep power-down mode ensures
extremely low power consumption even when
system power is applied. For example, portable
computing products and other power sensitive
applications that use an array of devices for solidstate storage can consume negligible power by
lowering RP# to VIL standby or sleep modes. If
access is again needed, the devices can be read
following the tPHQV and tPHWL wake-up cycles
required after RP# is first raised to VIH. See Section
6.2.4 through 6.2.6 "AC CHARACTERISTICS READ-ONLY and WRITE OPERATIONS" and
Fig. 13, Fig. 14 and Fig. 15 for more information.
- 25 -
LH28F160SGED-L10
6 ELECTRICAL SPECIFICATIONS
NOTICE : The specifications are subject to
change without notice. Verify with your local
SHARP sales office that you have the latest
datasheet before finalizing a design.
Absolute Maximum Ratings∗
6.1
Operating Temperature
During Read, Block Erase, Word Write,
and Lock-Bit Configuration.... –10 to +70°C (NOTE 1)
Temperature under Bias ............. –10 to +80°C
Storage Temperature ........................ –65 to +125°C
Voltage On Any Pin
(except VCC, VPP, and RP#) .. –2.0 to 7.0 V (NOTE 2)
∗WARNING : Stressing the device beyond the
"Absolute
Maximum Ratings" may cause
permanent damage. These are stress ratings only.
Operation beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device reliability.
NOTES :
VCC
Supply Voltage ................. –2.0 to +7.0 V (NOTE 2)
VPP Update Voltage during
Block Erase, Word Write and
Lock-Bit Configuration.... –2.0 to +14.0 V (NOTE 2, 3)
RP# Voltage with Respect to
GND during Lock-Bit
Configuration Operations ... –2.0 to +14.0 V (NOTE 2, 3)
Output Short Circuit Current................100 mA (NOTE 4)
6.2
1.
2.
3.
4.
Operating temperature is for commercial product defined
by this specification.
All specified voltages are with respect to GND. Minimum
DC voltage is –0.5 V on input/output pins and –0.2 V on
VCC and VPP pins. During transitions, this level may
undershoot to –2.0 V for periods < 20 ns. Maximum DC
voltage on input/output pins and VCC is VCC+0.5 V
which, during transitions, may overshoot to VCC+2.0 V
for periods < 20 ns.
Maximum DC voltage on VPP and RP# may overshoot
to +14.0 V for periods < 20 ns.
Output shorted for no more than one second. No more
than one output shorted at a time.
Operating Conditions
SYMBOL
PARAMETER
TA
Operating Temperature
MIN.
–10
MAX.
+70
UNIT
˚C
VCC1
VCC Supply Voltage (2.7 to 3.6 V)
2.7
3.6
V
VCC2
VCC3
VCC Supply Voltage (3.3±0.3 V)
3.0
3.6
V
VCC Supply Voltage (5.0±0.5 V)
4.50
5.50
V
TEST CONDITION
Ambient Temperature
6.2.1 CAPACITANCE (NOTE 1)
TA = +25˚C, f = 1 MHz
SYMBOL
PARAMETER
CIN
Input Capacitance
COUT
Output Capacitance
NOTE
2
TYP.
14
MAX.
20
UNIT
pF
18
24
pF
NOTES :
1.
2.
Sampled, not 100% tested.
BE0# and BE1# have half the value of this.
- 26 -
CONDITION
VIN = 0.0 V
VOUT = 0.0 V
LH28F160SGED-L10
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
2.7
1.35
INPUT
TEST POINTS
1.35 OUTPUT
0.0
AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output
timing ends, at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns.
Fig. 9 Transient Input/Output Reference Waveform for VCC = 2.7 to 3.6 V
3.0
1.5
INPUT
TEST POINTS
1.5
OUTPUT
0.0
AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output
timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns.
Fig. 10 Transient Input/Output Reference Waveform for VCC = 3.3±0.3 V
2.4
2.0
INPUT
2.0
TEST POINTS
0.8
0.45
OUTPUT
0.8
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing
begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to
90 %) < 10 ns.
Fig. 11 Transient Input/Output Reference Waveform for VCC = 5.0±0.5 V
Test Configuration Capacitance Loading Value
TEST CONFIGURATION
VCC = 3.3±0.3 V, 2.7 to 3.6 V
1.3 V
1N914
VCC = 5.0±0.5 V
RL = 3.3 kΩ
DEVICE
UNDER
TEST
OUT
CL
CL Includes Jig
Capacitance
Fig. 12 Transient Equivalent Testing
Load Circuit
- 27 -
CL (pF)
50
100
LH28F160SGED-L10
6.2.3 DC CHARACTERISTICS
Following is the supply current of one bank. For the supply current of one device total, refer to the NOTE 8.
SYMBOL
PARAMETER
NOTE
VCC = 2.7 to 3.6 V VCC = 5.0±0.5 V
UNIT
TYP.
MAX.
TYP.
MAX.
TEST
CONDITIONS
VCC = VCC Max.
VIN = VCC or GND
VCC = VCC Max.
VOUT = VCC or GND
CMOS inputs
VCC = VCC Max.
BE# = RP# = VCC±0.2 V
TTL inputs
VCC = VCC Max.
BE# = RP# = VIH
RP# = GND±0.2 V
IOUT = 0 mA
CMOS inputs
VCC = VCC Max.
BE# = GND
f = 5 MHz (3.3 V, 2.7 V),
8 MHz (5 V)
IOUT = 0 mA
TTL inputs
VCC = VCC Max.
BE# = GND
f = 5 MHz (3.3 V, 2.7 V),
8 MHz (5 V)
IOUT = 0 mA
VPP = 2.7 to 3.6 V
VPP = 5.0±0.5 V
VPP = 12.0±0.6 V
VPP = 2.7 to 3.6 V
VPP = 5.0±0.5 V
VPP = 12.0±0.6 V
ILI
Input Load Current
1
±0.5
±1
µA
ILO
Output Leakage Current
1
±0.5
±10
µA
100
100
µA
2
2
mA
12
16
µA
25
50
mA
30
65
mA
—
35
30
—
30
25
mA
mA
mA
mA
mA
mA
6
10
mA BE# = VIH
±15
200
±15
200
µA
µA
VPP ≤ VCC
VPP > VCC
5
5
µA
RP# = GND±0.2 V
—
80
30
—
40
30
mA
mA
mA
mA
mA
mA
VPP
VPP
VPP
VPP
VPP
VPP
200
µA
VPP = VPPH1/2/3
ICCS
ICCD
ICCR
VCC Standby Current
VCC Deep Power-Down
Current
VCC Read Current
1, 5, 8
1
1, 4,
5, 8
ICCW
VCC Word Write or
Set Lock-Bit Current
1, 6, 8
ICCE
VCC Block Erase or Clear
Block Lock-Bits Current
1, 6, 8
ICCWS VCC Word Write or Block
1, 2, 8
ICCES Erase Suspend Current
IPPS
1, 8
VPP Standby or Read Current
IPPR
VPP Deep Power-Down
1
IPPD
Current
IPPW
VPP Word Write or
Set Lock-Bit Current
1, 6, 8
IPPE
VPP Block Erase or Clear
Block Lock-Bits Current
1, 6, 8
IPPWS VPP Word Write or Block
IPPES Erase Suspend Current
1, 8
17
17
12
17
17
12
80
80
30
40
40
30
200
- 28 -
—
—
—
—
=
=
=
=
=
=
2.7 to 3.6 V
5.0±0.5 V
12.0±0.6 V
2.7 to 3.6 V
5.0±0.5 V
12.0±0.6 V
LH28F160SGED-L10
6.2.3 DC CHARACTERISTICS (contd.)
SYMBOL
PARAMETER
NOTE
VCC = 2.7 to 3.6 V VCC = 5.0±0.5 V
UNIT
MIN.
MAX.
MIN.
MAX.
–0.5
0.8
–0.5
0.8
V
VCC
VCC
2.0
2.0
V
+0.5
+0.5
VIL
Input Low Voltage
6
VIH
Input High Voltage
6
VOL
Output Low Voltage
6
VOH1
Output High Voltage
(TTL)
6
2.4
2.4
VOH2
Output High Voltage
(CMOS)
6
0.85
VCC
VCC
–0.4
0.85
VCC
VCC
–0.4
VLKO
VPP Lockout Voltage during
Normal Operations
VPP Voltage during
Word Write, Block Erase
or Lock-Bit Operations
VPP Voltage during
Word Write, Block Erase
or Lock-Bit Operations
VPP Voltage during
Word Write, Block Erase
or Lock-Bit Operations
VCC Lockout Voltage
VHH
RP# Unlock Voltage
VPPLK
VPPH1
VPPH2
VPPH3
0.4
3, 6
0.45
1.5
V
V
V
1.5
V
2.7
3.6
—
—
V
4.5
5.5
4.5
5.5
V
11.4
12.6
11.4
12.6
V
2.0
7
V
2.0
11.4
12.6
11.4
TEST
CONDITIONS
VCC = VCC Min.
IOL = 5.8 mA (VCC = 5 V),
IOL = 2.0 mA (VCC = 3.3 V, 2.7 V)
VCC = VCC Min.
IOH = –2.5 mA (VCC = 5 V),
IOH = –2.0 mA (VCC = 3.3 V, 2.7 V)
VCC = VCC Min.
IOH = –2.5 µA
VCC = VCC Min.
IOH = –100 µA
V
12.6
V
Set permanent lock-bit
Override block lock-bit
NOTES :
1.
2.
3.
4.
5.
6.
All currents are in RMS unless otherwise noted. Typical
values at nominal VCC voltage and TA = +25°C.
ICCWS and ICCES are specified with the device deselected. If reading or word writing in erase suspend
mode, the device’s current draw is the sum of ICCWS or
ICCES and ICCR or ICCW, respectively.
Block erases, word writes, and lock-bit configurations are
inhibited when VPP ≤ VPPLK, and not guaranteed in the
range between VPPLK (max.) and VPPH1 (min.), between
VPPH1 (max.) and VPPH2 (min.), between VPPH2 (max.)
and VPPH3 (min.), and above VPPH3 (max.).
Automatic Power Saving (APS) reduces typical ICCR to
1 mA at 5 V VCC and 3 mA at 2.7 to 3.6 V VCC in static
operation.
CMOS inputs are either VCC±0.2 V or GND±0.2 V. TTL
inputs are either VIL or VIH.
Sampled, not 100% tested.
7.
8.
- 29 -
Permanent lock-bit set operations are inhibited when
RP# = VIH. Block lock-bit configuration operations are
inhibited when the permanent lock-bit is set or RP# =
VIH and WP# = VIL. Block erases and word writes are
inhibited when the corresponding block lock-bit is set
and RP# = VIH and WP# = VIL or the permanent lock-bit
is set. Block erase, word write, and lock-bit configuration
operations are not guaranteed with VIH < RP# < VHH
and should not be attempted.
These are the values of the current which is consumed
within one bank area. The value for the bank0 and
bank1 should added in order to calculate the value for
the whole chip. If the bank0 is in write state and bank1
is in read state, the ICC = ICCW + ICCR. If both banks are
in standby mode, the value for the device is 2 times the
value in the above table.
LH28F160SGED-L10
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = –10 to +70˚C
SYMBOL
tAVAV
tAVQV
tELQV
tPHQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
tOH
VERSION
PARAMETER
NOTE
Read Cycle Time
Address to Output Delay
BE# to Output Delay
RP# High to Output Delay
OE# to Output Delay
BE# to Output in Low Z
BE# High to Output in High Z
OE# to Output in Low Z
OE# High to Output in High Z
Output Hold from Address, BE# or OE# Change,
Whichever Occurs First
• VCC = 3.3±0.3 V, TA = –10 to +70˚C
VERSION
SYMBOL
PARAMETER
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
BE# to Output Delay
tPHQV
RP# High to Output Delay
tGLQV
OE# to Output Delay
tELQX
BE# to Output in Low Z
tEHQZ
BE# High to Output in High Z
tGLQX
OE# to Output in Low Z
tGHQZ
OE# High to Output in High Z
Output Hold from Address, BE# or OE# Change,
tOH
Whichever Occurs First
• VCC = 5.0±0.5 V, TA = –10 to +70˚C
VERSION
SYMBOL
PARAMETER
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
BE# to Output Delay
tPHQV
RP# High to Output Delay
tGLQV
OE# to Output Delay
tELQX
BE# to Output in Low Z
tEHQZ
BE# High to Output in High Z
tGLQX
OE# to Output in Low Z
tGHQZ
OE# High to Output in High Z
Output Hold from Address, BE# or OE# Change,
tOH
Whichever Occurs First
2
2
3
3
3
3
3
NOTE
2
2
3
3
3
3
3
NOTE
2
2
3
3
3
3
3
LH28F160SGED-L10
MIN.
MAX.
120
120
120
600
50
0
55
0
25
0
LH28F160SGED-L10
MIN.
MAX.
100
100
100
600
45
0
45
0
20
0
LH28F160SGED-L10
MIN.
MAX.
100
100
100
400
50
0
55
0
15
0
NOTES :
1.
2.
3.
See AC Input/Output Reference Waveform (Fig. 9 through Fig. 11) for maximum allowable input slew rate.
OE# may be delayed up to tELQV-tGLQV after the falling edge of BE# without impact on tELQV.
Sampled, not 100% tested.
- 30 -
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LH28F160SGED-L10
Standby
VIH
ADDRESSES (A)
Device
Address Selection
Data Valid
Address Stable
VIL
tAVAV
VIH
BEX# (E)
VIL
tEHQZ
VIH
OE# (G)
tGHQZ
VIL
tELQV
VIH
tGLQV
WE# (W)
VIL
tGLQX
tELQX
VOH
High Z
Valid Output
DATA (D/Q)
(DQ0-DQ15)
tAVQV
VOL
VCC
tPHQV
RP# (P)
tOH
High Z
VIH
VIL
Fig. 13 AC Waveform for Read Operations
- 31 -
LH28F160SGED-L10
6.2.5 AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = –10 to +70˚C
SYMBOL
tAVAV
tPHWL
tELWL
tWLWH
tPHHWH
tVPWH
tAVWH
tDVWH
tWHDX
tWHAX
tWHEH
tWHWL
tWHGL
tQVVL
tQVPH
VERSION
PARAMETER
NOTE
Write Cycle Time
RP# High Recovery to WE# Going Low
BE# Setup to WE# Going Low
WE# Pulse Width
RP# VHH Setup to WE# Going High
VPP Setup to WE# Going High
Address Setup to WE# Going High
Data Setup to WE# Going High
Data Hold from WE# High
Address Hold from WE# High
BE# Hold from WE# High
WE# Pulse Width High
Write Recovery before Read
VPP Hold from Valid SRD
RP# VHH Hold from Valid SRD
2
2
2
3
3
2, 4
2, 4
• VCC = 3.3±0.3 V, TA = –10 to +70˚C
VERSION
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
tPHWL
RP# High Recovery to WE# Going Low
tELWL
BE# Setup to WE# Going Low
tWLWH WE# Pulse Width
tPHHWH RP# VHH Setup to WE# Going High
tVPWH VPP Setup to WE# Going High
tAVWH Address Setup to WE# Going High
tDVWH Data Setup to WE# Going High
tWHDX Data Hold from WE# High
tWHAX Address Hold from WE# High
tWHEH BE# Hold from WE# High
tWHWL WE# Pulse Width High
tWHGL Write Recovery before Read
tQVVL
VPP Hold from Valid SRD
RP# VHH Hold from Valid SRD
tQVPH
NOTE
2
2
2
3
3
2, 4
2, 4
LH28F160SGED-L10
MIN.
MAX.
120
1
10
50
100
100
50
50
5
5
10
30
0
0
0
LH28F160SGED-L10
MIN.
MAX.
100
1
10
50
100
100
50
50
5
5
10
30
0
0
0
UNIT
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES :
1.
2.
3.
Read timing characteristics during block erase, word
write and lock-bit configuration operations are the same
as during read-only operations. Refer to Section 6.2.4
"AC CHARACTERISTICS" for read-only operations.
Sampled, not 100% tested.
Refer to Table 3 for valid AIN and DIN for block erase,
word write, or lock-bit configuration.
4.
- 32 -
VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block
erase, word write, or lock-bit configuration success
(SR.1/3/4/5 = 0).
LH28F160SGED-L10
6.2.5 AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS (contd.) (NOTE 1)
• VCC = 5.0±0.5 V, TA = –10 to +70˚C
VERSION
SYMBOL
LH28F160SGED-L10
PARAMETER
tAVAV
Write Cycle Time
tPHWL
tELWL
RP# High Recovery to WE# Going Low
BE# Setup to WE# Going Low
NOTE
2
MIN.
MAX.
UNIT
100
ns
1
10
µs
ns
ns
ns
tWLWH WE# Pulse Width
tPHHWH RP# VHH Setup to WE# Going High
2
40
100
tVPWH
VPP Setup to WE# Going High
2
100
ns
tAVWH
tDVWH
Address Setup to WE# Going High
Data Setup to WE# Going High
3
3
40
40
ns
ns
tWHDX
tWHAX
Data Hold from WE# High
Address Hold from WE# High
5
5
ns
ns
tWHEH
BE# Hold from WE# High
10
ns
tWHWL
tWHGL
WE# Pulse Width High
Write Recovery before Read
30
0
ns
ns
tQVVL
tQVPH
VPP Hold from Valid SRD
RP# VHH Hold from Valid SRD
0
0
ns
ns
2, 4
2, 4
NOTES :
1.
2.
3.
Read timing characteristics during block erase, word
write and lock-bit configuration operations are the same
as during read-only operations. Refer to Section 6.2.4
"AC CHARACTERISTICS" for read-only operations.
Sampled, not 100% tested.
Refer to Table 3 for valid AIN and DIN for block erase,
word write, or lock-bit configuration.
4.
- 33 -
VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block
erase, word write, or lock-bit configuration success
(SR.1/3/4/5 = 0).
LH28F160SGED-L10
(NOTE 1)
(NOTE 2)
(NOTE 3)
(NOTE 4)
(NOTE 5)
(NOTE 6)
VIH
ADDRESSES (A)
AIN
VIL
AIN
tAVAV
tAVWH
tWHAX
VIH
BEx# (E)
VIL
tWHEH
tELWL
tWHGL
VIH
OE# (G)
VIL
tWHQV1/2/3/4
tWHWL
VIH
WE# (W)
tWLWH
tDVWH
tWHDX
VIL
VIH
DATA (D/Q)
VIL
High Z
tPHWL
DIN
DIN
Valid
SRD
tQVSL
tSHWH
VIH
WP# (S)
VIL
VIH
RP# (P)
VIL
tVPWH
tQVVL
VPPH1/2/3
VPP (V)
VPPLK
VIL
NOTES :
1.
2.
3.
4.
5.
6.
VCC power-up and standby.
Write block erase or word write setup.
Write block erase confirm or valid address and data.
Automated erase or program delay.
Read status register data.
Write Read Array command.
Fig. 14 AC Waveform for WE#-Controlled Write Operations
- 34 -
DIN
LH28F160SGED-L10
6.2.6 AC CHARACTERISTICS FOR BE#-CONTROLLED WRITES OPERATIONS (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = –10 to +70˚C
VERSION
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
tPHEL
RP# High Recovery to BE# Going Low
tWLEL
WE# Setup to BE# Going Low
tELEH
BE# Pulse Width
tPHHEH RP# VHH Setup to BE# Going High
tVPEH
VPP Setup to BE# Going High
tAVEH
Address Setup to BE# Going High
tDVEH
Data Setup to BE# Going High
tEHDX
Data Hold from BE# High
tEHAX
Address Hold from BE# High
tEHWH WE# Hold from BE# High
tEHEL
BE# Pulse Width High
tEHGL
Write Recovery before Read
tQVVL
VPP Hold from Valid SRD
RP# VHH Hold from Valid SRD
tQVPH
NOTE
2
2
2
3
3
2, 4
2, 4
• VCC = 3.3±0.3 V, TA = –10 to +70˚C
VERSION
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
tPHEL
RP# High Recovery to BE# Going Low
tWLEL
WE# Setup to BE# Going Low
tELEH
BE# Pulse Width
tPHHEH RP# VHH Setup to BE# Going High
tVPEH
VPP Setup to BE# Going High
tAVEH
Address Setup to BE# Going High
tDVEH
Data Setup to BE# Going High
tEHDX
Data Hold from BE# High
tEHAX
Address Hold from BE# High
tEHWH WE# Hold from BE# High
tEHEL
BE# Pulse Width High
tEHGL
Write Recovery before Read
tQVVL
VPP Hold from Valid SRD
tQVPH
RP# VHH Hold from Valid SRD
NOTE
2
2
2
3
3
2, 4
2, 4
LH28F160SGED-L10
MIN.
MAX.
120
1
0
70
100
100
50
50
5
5
0
25
0
0
0
LH28F160SGED-L10
MIN.
MAX.
100
1
0
70
100
100
50
50
5
5
0
25
0
0
0
UNIT
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES :
1.
2.
3.
In systems where BE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold,
and inactive WE# times should be measured relative to
the BE# waveform.
Sampled, not 100% tested.
Refer to Table 3 for valid AIN and DIN for block erase,
word write, or lock-bit configuration.
4.
- 35 -
VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block
erase, word write, or lock-bit configuration success
(SR.1/3/4/5 = 0).
LH28F160SGED-L10
6.2.6 AC CHARACTERISTICS FOR BE#-CONTROLLED WRITES OPERATIONS (contd.) (NOTE 1)
• VCC = 5.0±0.5 V, TA = –10 to +70˚C
VERSION
SYMBOL
LH28F160SGED-L10
PARAMETER
tAVAV
Write Cycle Time
tPHEL
tWLEL
RP# High Recovery to BE# Going Low
WE# Setup to BE# Going Low
tELEH
tPHHEH
BE# Pulse Width
RP# VHH Setup to BE# Going High
tVPEH
tAVEH
tDVEH
tEHDX
tEHAX
NOTE
MIN.
MAX.
UNIT
100
ns
1
0
µs
ns
2
50
100
ns
ns
VPP Setup to BE# Going High
2
100
ns
Address Setup to BE# Going High
Data Setup to BE# Going High
3
3
40
40
ns
ns
Data Hold from BE# High
Address Hold from BE# High
5
5
ns
ns
tEHWH
WE# Hold from BE# High
0
ns
tEHEL
tEHGL
BE# Pulse Width High
Write Recovery before Read
25
0
ns
ns
tQVVL
tQVPH
VPP Hold from Valid SRD
RP# VHH Hold from Valid SRD
0
0
ns
ns
2
2, 4
2, 4
NOTES :
1.
2.
3.
In systems where BE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold,
and inactive WE# times should be measured relative to
the BE# waveform.
Sampled, not 100% tested.
Refer to Table 3 for valid AIN and DIN for block erase,
word write, or lock-bit configuration.
4.
- 36 -
VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block
erase, word write, or lock-bit configuration success
(SR.1/3/4/5 = 0).
LH28F160SGED-L10
(NOTE 1)
(NOTE 2)
(NOTE 3)
(NOTE 4)
(NOTE 5)
(NOTE 6)
VIH
ADDRESSES (A)
AIN
VIL
AIN
tAVAV
tAVEH
tEHAX
VIH
WE# (W)
VIL
tWLEL
tEHWH
tEHGL
VIH
OEX# (G)
VIL
tEHEL
tEHQV1/2/3/4
VIH
BEX# (E)
tELEH
tDVEH
tEHDX
VIL
VIH
DATA (D/Q)
VIL
High Z
tPHEL
DIN
DIN
tSHEH
Valid
SRD
tQVSL
VIH
WP# (S)
VIL
VIH
RP# (P)
VIL
tVPEH
tQVVL
VPPH1/2/3
VPP (V)
VPPLK
VIL
- 37 -
DIN
LH28F160SGED-L10
6.2.7 RESET OPERATIONS
VIH
RP# (P)
VIL
tPLPH
(A) Reset During Read Array Mode
VIH
RP# (P)
VIL
tPLPH
(B) Reset During Block Erase, Word Write, or Lock-Bit Configuration
2.7 V/3.3 V/5 V
VCC
VIL
t235VPH
VIH
RP# (P)
VIL
(C) VCC Rising Timing
Fig. 16 AC Waveform for Reset Operation
Reset AC Specifications
SYMBOL
tPLPH
PARAMETER
NOTE
RP# Pulse Low Time (If RP# is tied to VCC,
this specification is not applicable)
VCC 2.7 V to RP# High
t235VPH VCC 3.0 V to RP# High
VCC 4.5 V to RP# High
1
VCC = 2.7 to 3.6 V
MIN.
MAX.
VCC = 5.0±0.5 V
MIN.
MAX.
UNIT
100
100
ns
100
100
ns
NOTES :
1.
When the device power-up, holding RP#-low minimum 100 ns is required after VCC has been in predefined range and also
has been in stable there.
- 38 -
LH28F160SGED-L10
6.2.8 BLOCK ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE (NOTE 3)
• VCC = 2.7 to 3.6 V, TA = –10 to +70˚C
SYMBOL
tWHQV1
PARAMETER
NOTE
VPP = 2.7 to 3.6 V
VPP = 5.0±0.5 V
VPP = 12.0±0.6 V
MIN. TYP.(NOTE 1) MAX.
MIN. TYP.(NOTE 1) MAX.
MIN. TYP.(NOTE 1) MAX.
UNIT
Word Write Time
2
49
63
20
28
15.4
µs
Block Write Time
2
1.7
2.1
0.7
1.0
0.56
s
tWHQV2
Block Erase Time
tEHQV2
2
3.0
2.0
1.9
s
2
44
28
24.4
µs
2
3.8
2.6
2.3
s
12.6
10.5
10.5
µs
34.1
20.2
20.2
µs
tEHQV1
tWHQV3
Set Lock-Bit Time
tEHQV3
tWHQV4 Clear Block Lock-Bits
tEHQV4 Time
tWHRH1 Word Write Suspend
tEHRH1
Latency Time to Read
tWHRH2 Erase Suspend Latency
Time to Read
tEHRH2
• VCC = 3.3±0.3 V, TA = –10 to +70˚C
SYMBOL
PARAMETER
NOTE
VPP = 3.3±0.3 V
VPP = 5.0±0.5 V
VPP = 12.0±0.6 V
MIN. TYP.(NOTE 1) MAX.
MIN. TYP.(NOTE 1) MAX.
MIN. TYP.(NOTE 1) MAX.
UNIT
tWHQV1
Word Write Time
tEHQV1
2
35
45
14
20
11
µs
Block Write Time
2
1.2
1.5
0.5
0.7
0.4
s
Block Erase Time
2
2.1
1.4
1.3
s
tWHQV3
Set Lock-Bit Time
tEHQV3
2
31
20
17.4
µs
tWHQV4 Clear Block Lock-Bits
tEHQV4 Time
2
2.7
1.8
1.6
s
9
7.5
7.5
µs
24.3
14.4
14.4
µs
tWHQV2
tEHQV2
tWHRH1 Word Write Suspend
tEHRH1 Latency Time to Read
tWHRH2 Erase Suspend Latency
tEHRH2
Time to Read
NOTES :
1.
Typical values measured at TA = +25˚C and nominal
voltages. Assumes corresponding lock-bits are not set.
Subject to change based on device characterization.
2.
3.
- 39 -
Excludes system-level overhead.
Sampled, not 100% tested.
LH28F160SGED-L10
6.2.8 BLOCK ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE (contd.) (NOTE 3)
• VCC = 5.0±0.5 V, TA = –10 to +70˚C
SYMBOL
tWHQV1
PARAMETER
NOTE
VPP = 5.0±0.5 V
VPP = 12.0±0.6 V
MIN. TYP.(NOTE 1) MAX.
MIN. TYP.(NOTE 1) MAX.
UNIT
Word Write Time
2
10
14
7.5
µs
Block Write Time
2
0.4
0.5
0.25
s
tWHQV2
Block Erase Time
tEHQV2
2
1.3
1.2
s
Set Lock-Bit Time
2
18
15
µs
Clear Block Lock-Bits Time
2
1.6
1.5
s
Word Write Suspend Latency Time to Read
7.5
6
µs
Erase Suspend Latency Time to Read
14.4
14.4
µs
tEHQV1
tWHQV3
tEHQV3
tWHQV4
tEHQV4
tWHRH1
tEHRH1
tWHRH2
tEHRH2
NOTES :
1.
Typical values measured at TA = +25˚C and nominal
voltages. Assumes corresponding lock-bits are not set.
Subject to change based on device characterization.
2.
3.
- 40 -
Excludes system-level overhead.
Sampled, not 100% tested.
LH28F160SGED-L10
7 ORDERING INFORMATION
Product line designator for all SHARP Flash products
L H 2 8 F 1 6 0 S G E D - L 1 0
Access Speed (ns)
10 : 100 ns (5.0±0.5 V), 100 ns (3.3±0.3 V),
120 ns (2.7 to 3.6 V)
Device Density
160 = 16 M-bit
Architecture
S = Symmetrical Block
Dual Work technology
Power Supply Type
G = SmartVoltage Technology
Package
E = 48-pin TSOP (I) (TSOP-048-P-1220) Normal bend
Operating Temperature = –10 to +70°C
VALID OPERATIONAL COMBINATIONS
OPTION
1
ORDER CODE
LH28F160SGED-L10
VCC = 2.7 to 3.6 V
VCC = 3.3±0.3 V
VCC = 5.0±0.5 V
50 pF load,
1.35 V I/O Levels
120 ns
50 pF load,
1.5 V I/O Levels
100 ns
100 pF load,
TTL I/O Levels
100 ns
- 41 -
PACKAGING
48
24
0.1
12.0 ±0.2
0.10
0.5 TYP.
M
1
48 _ 0.2±0.08
48 TSOP (TSOP048-P-1220)
25
1.2MAX.
1.0 ±0.1
0.125
18.4 ±0.2
Package base plane
19.0 ±0.1
0.1±0.1
0.125 ±0.05
20.0±0.3