6-Bit Programmable 2-/3-/4-Phase Synchronous Buck Controller ADP3188 FEATURES VCC RAMPADJ RT 28 14 13 ADP3188 UVLO SHUTDOWN AND BIAS EN 11 OSCILLATOR GND 19 SET RESET CMP 26 PWM2 CMP RESET 2-/3-/4-PHASE DRIVER LOGIC RESET CMP RESET 24 PWM4 CMP CSREF CURRENT BALANCING CIRCUIT 25 PWM3 DAC-250mV DELAY PWRGD 10 CROWBAR CURRENT LIMIT 23 SW1 22 SW2 ILIMIT 15 21 SW3 EN 20 SW4 CURRENT LIMIT CIRCUIT DELAY 12 GENERAL DESCRIPTION The ADP3188 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. The part uses an internal 6-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.8375 V and 1.6 V. It uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing the construction of up to four complementary buck switching stages. 27 PWM1 DAC+150mV APPLICATIONS Desktop PC power supplies for Next-generation Intel® processors VRM modules EN SOFT START 17 CSSUM 16 CSREF 18 CSCOMP 8 FB COMP 9 PRECISION REFERENCE 7 FBRTN VID DAC 1 2 3 4 5 6 VID4 VID3 VID2 VID1 VID0 VID5 Figure 1. The ADP3188 also includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current, so it is always optimally positioned for a system transient. The ADP3188 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the-fly output voltage changes requested by the CPU. The ADP3188 is specified over the commercial temperature range of 0°C to 85°C and is available in 28-lead, TSSOP and QSOP packages. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. 04835-001 Selectable 2-, 3- or 4-phase operation at up to 1 MHz per phase ±9.5 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Active current balancing between all output phases Built-in power good/crowbar blanking supports on-the-fly VID code changes 6-bit digitally programmable 0.8375 V to 1.6 V output Programmable short-circuit protection with programmable latch-off delay FUNCTIONAL BLOCK DIAGRAM ADP3188 TABLE OF CONTENTS Specifications..................................................................................... 3 Inductor Selection ...................................................................... 15 Test Circuits....................................................................................... 5 Designing an Inductor............................................................... 16 Absolute Maximum Ratings............................................................ 6 Selecting a Standard Inductor .............................................. 16 ESD Caution.................................................................................. 6 Output Droop Resistance.......................................................... 16 Pin Configuration and Function DescriptionS ............................ 7 Inductor DCR Temperature Correction ................................. 17 Typical Performance Characteristics ............................................. 8 Output Offset .............................................................................. 17 Theory of Operation ........................................................................ 9 COUT Selection ............................................................................. 18 Start-Up Sequence........................................................................ 9 Power MOSFETs......................................................................... 18 Master Clock Frequency.............................................................. 9 Ramp Resistor Selection............................................................ 20 Output Voltage Differential Sensing .......................................... 9 COMP Pin Ramp ....................................................................... 20 Output Current Sensing .............................................................. 9 Current-Limit Setpoint.............................................................. 20 Active Impedance Control Mode............................................. 10 Feedback Loop Compensation Design.................................... 20 Current-Control Mode and Thermal Balance........................ 10 CIN Selection and Input Current di/dt Reduction.................. 22 Voltage Control Mode................................................................ 10 Tuning the ADP3188 ................................................................. 23 Soft Start ...................................................................................... 10 DC Loadline Setting .............................................................. 23 Current-Limit, Short-Circuit, and Latch-Off Protection...... 11 AC Loadline Setting............................................................... 24 Dynamic VID.............................................................................. 11 Layout and Component Placement.............................................. 26 Power Good Monitoring ........................................................... 12 General Recommendations....................................................... 26 Output Crowbar ......................................................................... 13 Power Circuitry Recommendations ........................................ 26 Output Enable and UVLO ........................................................ 13 Signal Circuitry Recommendations......................................... 26 Application Information................................................................ 15 Outline Dimensions ....................................................................... 27 Setting the Clock Frequency ..................................................... 15 Ordering Guide .......................................................................... 27 Soft Start and Current-Limit Latch-Off Delay Times ........... 15 REVISION HISTORY 4/05—Rev. 0 to Rev. A Changes to Figure 10.........................................................................14 Changes to Ordering Guide .............................................................27 4/04—Revision 0: Initial Version Rev. A | Page 2 of 28 ADP3188 SPECIFICATIONS VCC = 12 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1 Table 1. Parameter ERROR AMPLIFIER Output Voltage Range2 Accuracy Symbol VCOMP VFB ∆VFB IFB IFBRTN IO(ERR) GBW(ERR) Line Regulation Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate VID INPUTS Input Low Voltage Input High Voltage Input Current, Input Voltage Low Input Current, Input Voltage High Pull-Up Resistance Internal Pull-Up Voltage VID Transition Delay Time No CPU Detection Turn-Off Delay Time2 OSCILLATOR Frequency Range Frequency Variation VIL(VID) VIH(VID) IIL(VID) IIH(VID) RVID Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT-SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Positioning Accuracy Output Voltage Range Output Current CURRENT-BALANCE CIRCUIT Common-Mode Range Input Resistance Input Current Input Current Matching Relative to nominal DAC output, referenced to FBRTN, CSSUM = CSCOMP, Figure 2 VCC = 10 V to 14 V fOSC fPHASE VRT VRAMPADJ IRAMPADJ VOS(CSA) ∆ISW(X) 0.05 15.5 100 500 20 25 Max Unit 3.1 +9.5 V mV % 17 140 µA µA µA MHz V/µs 0.4 V V µA µA kΩ V ns ns 0.8 VID(X) = 0 V VID(X) = 1.25 V TA = 25°C, RT = 250 kΩ, 4-phase TA = 25°C, RT = 115 kΩ, 4-phase TA = 25°C, RT = 75 kΩ, 4-phase RT = 100 kΩ to GND RAMPADJ – FB CSSUM – CSREF, Figure 3 TA = 25°C to 85°C, CSSUM – CSREF, Figure 3 35 0.9 400 400 0.25 155 1.9 −50 0 −25 5 60 1.1 200 400 600 2.0 −1.75 −1.5 −50 CCSCOMP = 10 pF CSSUM and CSREF Figure 4 −35 15 85 4 245 2.1 +50 100 MHz kHz kHz kHz V mV µA +1.75 +1.5 mV mV +50 nA MHz V/µs V mV V µA 10 10 0 −77 0.05 ICSCOMP VSW(X)CM RSW(X) ISW(X) Typ 0.7 −9.5 FB forced to VOUT – 3% COMP = FB CCOMP = 10 pF IBIAS(CSSUM) GBW(CSA) ∆VFB Min 14 VID code change to FB change VID code change to 11111 to PWM going low 2 2 Conditions −80 2.7 −83 2.7 500 SW(X) = 0 V SW(X) = 0 V SW(X) = 0 V Rev. A | Page 3 of 28 −600 20 4 −5 30 7 +200 40 10 +5 mV kΩ µA % ADP3188 Parameter CURRENT-LIMIT COMPARATOR Output Voltage Normal Mode Shutdown Mode Output Current, Normal Mode Maximum Output Current Current-Limit Threshold Voltage Current-Limit Setting Ratio DELAY Normal Mode Voltage DELAY Overcurrent Threshold Latch-Off Delay Time Symbol Conditions Min Typ Max Unit VILIMIT(NM) VILIMIT(SD) EN > 0.8 V, RILIMIT = 250 kΩ EN < 0.4 V, IILIMIT = −100 µA 2.9 3 3.1 400 V mV IILIMIT(NM) EN > 0.8 V, RILIMIT = 250 kΩ 125 10.4 3 1.8 1.5 145 µA µA mV 20 1 25 µA ms 0.4 2 12 60 105 VCL VCSREF – VCSCOMP, RILIMIT = 250 kΩ VCL/IILIMIT VDELAY(NM) VDELAY(OC) tDELAY RDELAY = 250 kΩ RDELAY = 250 kΩ RDELAY = 250 kΩ, CDELAY = 12 nF 2.9 1.7 SOFT START Output Current, Soft-Start Mode Soft-Start Delay Time IDELAY(SS) tDELAY(SS) During startup, DELAY < 2.4 V 15 ENABLE INPUT Input Low Voltage Input High Voltage Input Current, Input Voltage Low Input Current, Input Voltage High VIL(EN) VIH(EN) IIL(EN) IIH(EN) EN = 0 V EN = 1.25 V VPWRGD(UV) VPWRGD(OV) VOL(PWRGD) Relative to nominal DAC output Relative to nominal DAC output IPWRGD(SINK) = 4 mA −180 90 RDELAY = 250 kΩ, CDELAY = 12 nF, VID code = 011111 1 POWER GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Low Voltage Power Good Delay Time During Soft Start2 VID Code Changing VID Code Static Crowbar Trip Point Crowbar Reset Point Crowbar Delay Time VID Code Changing VID Code Static PWM OUTPUTS Output Low Voltage Output High Voltage SUPPLY DC Supply Current UVLO Threshold Voltage UVLO Hysteresis 1 2 RDELAY = 250 kΩ, CDELAY = 12 nF, VID code= 011111 VCROWBAR tCROWBAR Relative to nominal DAC output Relative to FBRTN Overvoltage to PWM going low 90 450 100 VOL(PWM) VOH(PWM) IPWM(SINK) = −400 µA IPWM(SOURCE) = 400 µA VUVLO VCC rising All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization, not tested in production. Rev. A | Page 4 of 28 mV/µA V V ms 10 +1 25 V V µA µA −250 150 225 −300 200 400 mV mV mV 0.8 −1 100 3.1 1.9 ms 250 200 150 550 200 650 µs ns mV mV µs ns 250 400 160 5 500 4.0 mV V 6.5 0.7 5 6.9 0.9 10 7.3 1.1 mA V V ADP3188 TEST CIRCUITS ADP3188 ADP3188 VID4 VCC 28 2 VID3 PWM1 27 3 VID2 PWM2 26 4 VID1 PWM3 5 VID0 PWM4 24 1 + 12V 1 µF VCC 100n F 12V 28 CSCOMP 6-BIT CODE 18 25 100nF 39kΩ CSSUM 17 VID5 SW1 23 7 FBRTN SW2 22 8 FB SW3 21 9 COMP SW4 20 10 PWRGD GND 19 11 EN 1kΩ CSREF 16 1.0V GND VOS = 19 CSCOMP – 1V 40 1kΩ Figure 3. Current-Sense Amplifier VOS 1.25V CSCOMP 18 20kΩ 12 DELAY CSSUM 17 13 RT CSREF 16 14 RAMPADJ 250kΩ ADP3188 ILIMIT 15 VCC 250kΩ 12V 28 04835-002 FB 8 10kΩ Figure 2. Closed-Loop Output Voltage Accuracy COMP 9 CSCOMP 200kΩ 18 200kΩ 100nF CSSUM 17 ∆V CSREF 16 1.0V GND 19 ∆VFB = FB∆V = 80mV – FB∆V = 0mV Figure 4. Positioning Voltage Rev. A | Page 5 of 28 04835-004 12nF 100nF 04835-003 6 ADP3188 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC FBRTN VID0 to VID5, EN, DELAY, ILIMIT, CSCOMP, RT, PWM1 to PWM4, COMP SW1 – SW4 All Other Inputs and Outputs Storage Temperature Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (θJA) Lead Temperature Soldering (10 sec) Infrared (15 sec) Rating −0.3 V to +15 V −0.3 V to +0.3 V −0.3 V to +5.5 V −5 V to +25 V −0.3 V to VCC + 0.3 V −65°C to +150°C 0°C to 85°C 125°C 100°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND. 300°C 260°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 28 ADP3188 VID4 1 28 VCC VID3 2 27 PWM1 VID2 3 26 PWM2 VID1 4 25 PWM3 5 24 PWM4 ADP3188 23 SW1 TOP VIEW (Not to Scale) 22 SW2 VID0 VID5 6 FBRTN 7 FB 8 21 SW3 COMP 9 20 SW4 PWRGD 10 19 GND EN 11 18 CSCOMP DELAY 12 17 CSSUM RT 13 16 CSREF RAMPADJ 14 15 ILIMIT 04835-005 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 to 6 Mnemonic VID4 to VID0, VID5 7 8 FBRTN FB 9 10 COMP PWRGD 11 12 EN DELAY 13 RT 14 RAMPADJ 15 ILIMIT 16 CSREF 17 CSSUM 18 CSCOMP 19 20 to 23 GND SW4 to SW1 24 to 27 PWM4 to PMW1 28 VCC Description Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing a Logic 1 if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8375 V to 1.6 V (see Table 4). Leaving all the VID pins open results in the ADP3188 going into No CPU mode, shutting off its PWM outputs and pulling the PWRGD output low. Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no-load offset point. Error Amplifier Output and Compensation Point. Power Good Output. Open-drain output that signals when the output voltage is outside the proper operating range. Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Soft-Start Delay and Current-Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected between this pin and GND sets the soft-start ramp-up time and the overcurrent latch-off delay time. Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Current-Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current-limit threshold of the converter. This pin is actively pulled low when the ADP3188 EN input is low, or when VCC is below its UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low. Current-Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current-sense amplifier and the power good and crowbar functions. This pin should be connected to the common point of the output inductors. Current-Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. Current-Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determine the slope of the load line and the positioning loop response time. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Current-Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the ADP3188 to operate as a 2-, 3-, or 4-phase controller. Supply Voltage for the Device. Rev. A | Page 7 of 28 ADP3188 TYPICAL PERFORMANCE CHARACTERISTICS 4 5.3 5.2 SUPPLY CURRENT (mA) 3 2 1 5.1 5.0 4.9 4.8 0 0 50 100 150 200 RT VALUE (kΩ) 250 300 4.6 0 0.5 1 1.5 2 2.5 3 OSCILLATOR FREQUENCY (MHz) 3.5 Figure 7. Supply Current vs. Oscillator Frequency Figure 6. Master Clock Frequency vs. RT Rev. A | Page 8 of 28 4 04835-007 4.7 04835-006 MASTER CLOCK FREQUENCY (MHz) TA = 25°C 4-PHASE OPERATION ADP3188 THEORY OF OPERATION The ADP3188 combines a mulitmode, fixed frequency PWM control with mulitphase logic outputs for use in 2-, 3-, and 4 - phase synchronous buck CPU core supply power converters. The internal VID DAC is designed to interface with the Intel 6-bit VRD/VRM 10-and 10.1-compatible CPUs. Multiphase operation is important for producing the high currents and low voltages demanded by today’s microprocessors. Handling the high currents in a single-phase converter places high thermal demands on the components in the system, such as the inductors and MOSFETs. The multimode control of the ADP3188 ensures a stable, high performance topology for • Balancing currents and thermals between phases • High speed response at the lowest possible switching frequency and output decoupling • Minimizing thermal switching losses due to lower frequency operation • Tight load line regulation and accuracy • High current output for up to 4-phase operation • Reduced output ripple due to multiphase cancellation • PC board layout noise immunity • Ease of use and design due to independent component selection • Flexibility in operation for tailoring design to low cost or high performance The PWM outputs are logic-level devices intended for driving external gate drivers such as the ADP3418. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. Also, more than one output can be on at the same time for overlapping phases. MASTER CLOCK FREQUENCY The clock frequency of the ADP3188 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 6. To determine the frequency per phase, the clock is divided by the number of phases in use. If PWM4 is grounded, divide the master clock by 3 for the frequency of the remaining phases. If PWM3 and 4 are grounded, divide by 2. If all phases are in use, divide by 4. OUTPUT VOLTAGE DIFFERENTIAL SENSING The ADP3188 combines differential sensing with a high accuracy VID DAC and reference and a low offset error amplifier. This maintains a worst-case specification of ±9.5 mV differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB and FBRTN pins. FB should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. FBRTN should be connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 100 µA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage. START-UP SEQUENCE OUTPUT CURRENT SENSING During start-up, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3188 operates as a 4-phase PWM controller. Grounding the PWM4 pin programs 3-phase operation, and grounding the PWM3 and PWM4 pins programs 2-phase operation. The ADP3188 provides a dedicated current-sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current and for current-limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element, such as the low-side MOSFET. This amplifier can be configured several ways depending on the objectives of the system: When the ADP3188 is enabled, the controller outputs a voltage on PWM3 and PWM4, which is approximately 675 mV. An internal comparator checks each pin’s voltage vs. a threshold of 300 mV. If the pin is grounded, it is below the threshold, and the phase is disabled. The output resistance of the PWM pin is approximately 5 kΩ during this detection time. Any external pull-down resistance connected to the PWM pin should not be less than 25 kΩ to ensure proper operation. PWM1 and PWM2 are disabled during the phase detection interval, which occurs during the first two clock cycles of the internal oscillator. After this time, if the PWM output is not grounded, the 5 kΩ resistance is removed, and it switches between 0 V and 5 V. If the PWM output is grounded, it remains off. • Output inductor DCR sensing without a thermistor for lowest cost • Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature • Sense resistors for highest accuracy measurements Rev. A | Page 9 of 28 ADP3188 The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor to set the load line required by the microprocessor. The current information is then given as the difference of CSREF – CSCOMP. This difference signal is used internally to offset the VID DAC for voltage positioning and as a differential input for the current-limit comparator. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors, so that it can be made extremely accurate. ACTIVE IMPEDANCE CONTROL MODE For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the CSCOMP pin can be scaled to equal the droop impedance of the regulator multiplied by the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This differs from previous implementations and allows enhanced feed-forward response. CURRENT-CONTROL MODE AND THERMAL BALANCE The ADP3188 has individual inputs for each phase, which are used for monitoring the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system, which has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current-balance information is independent of the average output current information used for positioning described previously. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed-forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. Detailed information about programming the ramp is given in the Application Information section. External resistors can be placed in series with individual phases to create, if desired, an intentional current imbalance such as when one phase may have better cooling and can support higher currents. Resistors RSW1 through RSW4 (see the typical application circuit in Figure 10) can be used for adjusting thermal balance. It is best to have the ability to add these resistors during the initial design, so make sure that placeholders are provided in the layout. To increase the current in any given phase, make RSW for this phase larger (make RSW = 0 for the hottest phase, and do not change during balancing). Increasing RSW to only 500 Ω makes a substantial increase in phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase first. VOLTAGE CONTROL MODE A high gain bandwidth voltage mode error amplifier is used for the voltage-mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed in Table 4. This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with a resistor (RB) and is used for sensing and controlling the output voltage at this point. A current source from the FB pin flowing through RB is used for setting the no-load offset voltage from the VID voltage. The no-load voltage is negative with respect to the VID DAC. The main loop compensation is incorporated into the feedback network between FB and COMP. SOFT START The power-on ramp-up time of the output voltage is set with a capacitor and resistor in parallel from the DELAY pin to ground. The RC time constant also determines the current-limit latchoff time as explained in the following section. In UVLO, or when EN is a logic low, the DELAY pin is held at ground. After the UVLO threshold is reached and EN is a logic high, the DELAY capacitor is charged with an internal 20 µA current source. The output voltage follows the ramping voltage on the DELAY pin, limiting the inrush current. The soft-start time depends on the value of the VID DAC and CDLY, with a secondary effect from RDLY. Refer to the Application Information section for detailed information on setting CDLY. If either EN is taken low, or VCC drops below UVLO, the DELAY capacitor is reset to ground to be ready for another soft-start cycle. Figure 8 shows a typical soft-start sequence for the ADP3188. Rev. A | Page 10 of 28 ADP3188 DELAY to VCC. This prevents the DELAY capacitor from discharging, so the 1.8 V threshold is never reached. The resistor has an impact on the soft-start time because the current through it adds to the internal 20 µA current source. During start-up when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit controls the internal COMP voltage to the PWM comparators to 2 V. This limits the voltage drop across the low-side MOSFETs through the current balance circuitry. 04835-008 An inherent per phase current limit protects individual phases, if one or more phases stops functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage. Figure 8. Typical Start-Up Waveforms Channel 1: PWRGD, Channel 2: CSREF, Channel 3: DELAY, Channel 4: COMP CURRENT-LIMIT, SHORT-CIRCUIT, AND LATCH-OFF PROTECTION After the limit is reached, the 3 V pull-up on the DELAY pin is disconnected, and the external delay capacitor is discharged through the external resistor. A comparator monitors the DELAY voltage and shuts off the controller when the voltage drops below 1.8 V. The current-limit latch-off delay time is therefore set by the RC time constant discharging from 3 V to 1.8 V. The Application Information section discusses the selection of CDLY and RDLY. Because the controller continues to cycle the phases during the latch-off delay time, if the short is removed before the 1.8 V threshold is reached, the controller returns to normal operation. The recovery characteristic depends on the state of PWRGD. If the output voltage is within the PWRGD window, the controller resumes normal operation. However, if a short circuit has caused the output voltage to drop below the PWRGD threshold, a soft-start cycle is initiated. The latch-off function can be reset by either removing and reapplying VCC to the ADP3188, or by pulling the EN pin low for a short time. To disable the short-circuit latch-off function, the external resistor to ground should be left open, and a high value (>1 MΩ) resistor should be connected from 04835-0-009 The ADP3188 compares a programmable current-limit setpoint to the voltage from the output of the current-sense amplifier. The level of current limit is set with the resistor from the ILIMIT pin to ground. During normal operation, the voltage on ILIMIT is 3 V. The current through the external resistor is internally scaled to give a current-limit threshold of 10.4 mV/µA. If the difference in voltage between CSREF and CSCOMP rises above the current-limit threshold, the internal current-limit amplifier controls the internal COMP voltage to maintain the average output current at the limit. Figure 9. Overcurrent Latch-Off Waveforms Channel 1: CSREF, Channel 2: DELAY, Channel 3: COMP, Channel 4: Phase 1 Switch Node DYNAMIC VID The ADP3188 has the ability to dynamically change the VID input while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID onthe-fly (OTF). A VID OTF can occur under either light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. When a VID input changes state, the ADP3188 detects the change and ignores the DAC inputs for a minimum of 400 ns. This time prevents a false code due to logic skew while the six VID inputs are changing. Additionally, the first VID change initiates the PWRGD and crowbar blanking functions for a minimum of 100 µs to prevent a false PWRGD or crowbar event. Each VID change resets the internal timer. Rev. A | Page 11 of 28 ADP3188 Table 4. VID Codes for the ADP3188 VID4 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VID2 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 VID1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 VID0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 VID5 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output No CPU No CPU 0.8375 V 0.8500 V 0.8625 V 0.8750 V 0.8875 V 0.9000 V 0.9125 V 0.9250 V 0.9375 V 0.9500 V 0.9625 V 0.9750 V 0.9875 V 1.0000 V 1.0125 V 1.0250 V 1.0375 V 1.0500 V 1.0625 V 1.0750 V 1.0875 V 1.1000 V 1.1125 V 1.1250 V 1.1375 V 1.1500 V 1.1625 V 1.1750 V 1.1875 V 1.2000 V POWER GOOD MONITORING The power good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified in Table 4. These limits are based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if all of the VID DAC inputs are high, or whenever the EN pin is pulled low. PWRGD is blanked during a VID OTF event for a period of 250 µs to prevent false signals during the time the output is changing. VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output 1.2125 V 1.2250 V 1.2375 V 1.2500 V 1.2625 V 1.2750 V 1.2875 V 1.3000 V 1.3125 V 1.3250 V 1.3375 V 1.3500 V 1.3625 V 1.3750 V 1.3875 V 1.4000 V 1.4125 V 1.4250 V 1.4375 V 1.4500 V 1.4625 V 1.4750 V 1.4875 V 1.5000 V 1.5125 V 1.5250 V 1.5375 V 1.5500 V 1.5625 V 1.5750 V 1.5875 V 1.6000 V The PWRGD circuitry also incorporates an initial turn-on delay time based on the DELAY ramp. The PWRGD pin is held low until the DELAY pin reaches 2.6 V. The time between when the PWRGD undervoltage threshold is reached and when the DELAY pin reaches 2.6 V provides the turn-on delay time. This time is incorporated into the soft-start ramp. To ensure a 1 ms delay time on PWRGD, the soft-start ramp must also be >1 ms. Refer to the Application Information section for detailed information on setting CDLY. Rev. A | Page 12 of 28 ADP3188 OUTPUT CROWBAR OUTPUT ENABLE AND UVLO As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 550 mV. For the ADP3188 to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold, and the EN pin must be higher than its logic threshold. If UVLO is less than the threshold or the EN pin is a logic low, the ADP3188 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and holds the ILIMIT pin at ground. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high-side MOSFET, this action current-limits the input supply or blows its fuse, protecting the microprocessor from being destroyed. In the application circuit, the ILIMIT pin should be connected to the OD pins of the ADP3418 drivers. The ILIMIT being grounded disables the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs were not disabled, a negative voltage could be generated during output due to the high current discharge of the output capacitors through the inductors. Rev. A | Page 13 of 28 *FOR A DESCRIPTION OF OPTIONAL RSW RESISTORS, SEE THE THEORY OF OPERATION SECTION. Rev. A | Page 14 of 28 VIN 12V VIN RTN Figure 10. Typical VR 10.1 Application Circuit 04835-010 ENABLE POWER GOOD C22 1000pF FROM CPU CDLY 39nF RB 1.21k Ω CB 470pF C1 + C4 1µF RDLY 470k Ω RT 137k Ω 1% CA RA 470pF 12.1kΩ + C2 + CFB 22pF R1 10Ω D1 1N4148 2700µF/16V/3.3 A × 2 SANYO MV-WX SERIES C3 100µF L1 370nH 18A 14 RAMPADJ RT DELAY 12 13 EN 11 PWRGD ILIMIT CSREF CSSUM CSCOMP GND SW4 10 COMP SW2 FBRTN 7 9 SW1 VID5 6 SW3 PWM4 VID0 5 FB PWM3 VID1 8 PWM2 VID2 4 VID3 3 VCC PWM1 VID4 2 U1 ADP3188 1 R2 357k Ω 1% 15 16 17 18 19 20 21 22 23 24 25 26 27 28 RLIM 150kΩ 1% CCS1 560pF CCS2 1.5nF C23 0.01µF RCS2 84.5kΩ R PH4 158k Ω 1% RSW4 * RSW2 * RCS1 35.7k Ω RSW3 * RSW1 * C21 100pF RPH3 158k Ω 1% R7 10Ω RPH2 158kΩ 1% RPH1 158k Ω 1% C17 4.7µF D5 1N4148 C13 4.7µF D4 1N4148 C9 4.7µF D3 1N4148 C5 4.7µF D2 1N4148 DRVL VCC 4 6 5 PGND DRVL OD VCC 3 4 PGND DRVL OD VCC SW DRVH 4 IN BST 3 2 1 5 6 7 8 5 6 7 8 C18 10nF C20 15nF DRVL U5 ADP3418 R6 2.2Ω VCC PGND OD 3 4 SW DRVH IN BST C14 10nF 2 1 U4 ADP3418 C16 15nF 7 SW IN R5 2.2Ω 8 DRVH BST 2 C10 10nF 5 6 7 8 1 U3 ADP3418 C12 15nF PGND OD 3 R4 2.2Ω SW IN 2 DRVH BST 1 C6 10nF C8 15nF U2 ADP3418 R3 2.2Ω Q15 NTD110N02 Q13 NTD40N03 Q11 NTD110N02 Q9 NTD40N03 Q16 NTD110N02 L5 320nH/1.4m Ω C19 4.7µF Q14 NTD40N03 Q12 NTD110N02 L4 320nH/1.4m Ω Q10 NTD40N03 C15 4.7µF L3 320nH/1.4m Ω C11 4.7µF L2 320nH/1.4m Ω Q6 NTD40N03 Q4 NTD110N02 Q7 Q8 NTD110N02 NTD110N02 Q5 NTD40N03 Q3 NTD110N02 Q1 NTD40N03 C7 4.7µF Q2 NTD40N03 RTH1 100k Ω, 5% NTC C22 + 10µF × 18 MLCC IN SOCKET C31 + 560µF/4V × 8 SANYO SEPC SERIES 5mΩ EACH VCC(CORE) RTN 95A TDC, 119A PK 0.8375V – 1.6V VCC(CORE) ADP3188 ADP3188 APPLICATION INFORMATION The design parameters for a typical Intel VRD 10.1-compliant CPU application are as follows: • Input voltage (VIN) = 12 V • VID setting voltage (VVID) = 1.300 V • Duty cycle (D) = 0.108 • Nominal output voltage at no load (VONL) = 1.281 V • Nominal output voltage at 101 A load (VOFL) = 1.180 V • Static output voltage drop based on a 1.0 mΩ load line (RO) from no load to full load (VD) = VONL − VOFL = 1.281 V − 1.180 V = 101 mV • Maximum output current (IO) = 119 A • Maximum output current step (∆IO) = 95 A • Number of phases (n) = 4 • Switching frequency per phase (fSW) = 330 kHz ⎛ VVID C DLY = ⎜⎜ 20 µ A − RDLY 2 × ⎝ The ADP3188 uses a fixed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and/or the input and output capacitors. With n = 4 for four phases, a clock frequency of 1.32 MHz sets the switching frequency (fSW) of each phase to 330 kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Equation 1 shows that to achieve an 1.32 MHz oscillator frequency, the correct value for RT is 137 kΩ. Alternatively, the value for RT can be calculated using 1 − 27 kΩ n × f SW × 4.7 pF ⎞ t SS ⎟⎟ × ⎠ VVID (2) where tSS is the desired soft-start time. Assuming an RDLY of 390 kΩ and a desired soft-start time of 3 ms, CDLY is 36 nF. The closest standard value for CDLY is 39 nF. Once CDLY is chosen, RDLY can be calculated for the current-limit latch-off time using RDLY = 1.96 × t DELAY C DLY (3) If the result for RDLY is less than 200 kΩ, a smaller soft-start time should be considered by recalculating the equation for CDLY, or a longer latch-off time should be used. RDLY should never be less than 200 kΩ. In this example, a delay time of 9 ms results in RDLY = 452 kΩ. The closest standard 5% value is 470 kΩ. SETTING THE CLOCK FREQUENCY RT = However, as long as RDLY is kept greater than 200 kΩ, this effect is minor. The value for CDLY can be approximated using (1) INDUCTOR SELECTION The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs, but allows using smaller inductors and, for a specified peak-to-peak transient deviation, less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger inductors and more output capacitance for the same peak-topeak transient deviation. In any multiphase converter, a practical value for the peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current in the inductor. IR = where 4.7 pF and 27 kΩ are internal IC component values. For good initial accuracy and frequency stability, a 1% resistor is recommended. VVID × (1 − D ) f SW × L (4) Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage. SOFT START AND CURRENT-LIMIT LATCH-OFF DELAY TIMES Because the soft start and current-limit latch-off delay functions share the DELAY pin, these two parameters must be considered together. The first step is to set CDLY for the soft-start ramp. This ramp is generated with a 20 µA internal current source. The value of RDLY has a second-order impact on the soft-start time because it sinks part of the current source to ground. L≥ VVID × RO × (1 − (n × D )) f SW × VRIPPLE (5) Solving Equation 5 for a 10 mV p-p output ripple voltage yields L≥ 1.3 V × 1.0 mΩ × (1 − 0.432) = 224 nH 330 kHz × 10 mV If the resulting ripple voltage is less than it was designed for, make the inductor smaller until the ripple value is met. This allows optimal transient response and minimum output decoupling. Rev. A | Page 15 of 28 ADP3188 The smallest possible inductor should be used to minimize the number of output capacitors. For this example, choosing a 320 nH inductor is a good starting point and gives a calculated ripple current of 11 A. The inductor should not saturate at the peak current of 35.5 A and should be able to handle the sum of the power dissipation caused by the average current of 30 A in the winding and core loss. Another important factor in the inductor design is the DCR, which is used for measuring the phase currents. A large DCR can cause excessive power losses, while too small a value can lead to increased measurement error. A good rule is to have the DCR be about 1 to 1½ times the droop resistance (RO). For this design, an inductor with a DCR of 1.4 mΩ is used. DESIGNING AN INDUCTOR Once the inductance and DCR are known, the next step is to either design an inductor, or to find a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to control the accuracy of the system. 15% inductance and 8% DCR (at room temperature) are reasonable tolerances that most manufacturers can meet. The first decision in designing the inductor is to choose the core material. Several possibilities for providing low core loss at high frequencies include the powder cores (for example, KoolMµ® from Magnetics, Inc. or from Micrometals) and the gapped soft ferrite cores (for example, 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low, and the ripple current is high. • Coiltronics (561) 752-5000 www.coiltronics.com • Sumida Electric Company (847) 545-6700 www.sumida.com • Vishay Intertechnology (402) 563-6866 www.vishay.com OUTPUT DROOP RESISTANCE The design requires the regulator output voltage measured at the CPU pins to drop when the output current increases. The specified voltage drop corresponds to a dc output resistance (RO). The output current is measured by summing the voltage across each inductor and passing the signal through a low-pass filter. This summer filter is the CS amplifier configured with resistors RPH(X) (summers), and RCS and CCS (filter). The output resistance of the regulator is set by the following equations, where RL is the DCR of the output inductors: RO = CCS = • • (7) RPH ( x ) = RL × RCS RO RPH ( x ) = 1.4 mΩ × 100 kΩ = 140 kΩ 1.0 mΩ Next, use Equation 6 to solve for CCS. Magnetic Designer Software Intusoft (www.intusoft.com) CCS = Designing Magnetic Components for High-Frequency DCDC Converters, by William T. McLyman, K G Magnetics, Inc., ISBN 1883107008 Selecting a Standard Inductor The following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high power applications upon request: • L RL × RCS (6) The user has the flexibility of choosing either RCS or RPH(X). It is best to select RCS equal to 100 kΩ, and then solve for RPH(X) by rearranging Equation 6. The best choice for a core geometry is a closed-loop type such as a potentiometer core, PQ, U, or E core or toroid. A good compromise between price and performance is a core with a toroidal shape. Many useful magnetics design references are available for quickly designing a power inductor, such as RCS × RL RPH ( x ) 320 nH = 2.28 nF 1.4 mΩ × 100 kΩ It is best to have a dual location for CCS in the layout, so that standard values can be used in parallel to get as close to the value desired. For accuracy, CCS should be a 5% or 10% NPO capacitor. This example uses a 5% combination for CCS of 1.5 nF and 560 pF in parallel. Recalculating RCS and RPH(X) using this capacitor combination yields 110 kΩ and 154 kΩ. The closest standard 1% value for RPH(X) is 158 kΩ. Coilcraft (847) 639-6400 www.coilcraft.com Rev. A | Page 16 of 28 ADP3188 INDUCTOR DCR TEMPERATURE CORRECTION Compute the relative values for RCS1, RCS2, and RTH using 4. With the inductor’s DCR being used as the sense element and copper wire being the source of the DCR, compensation is needed for temperature changes of the inductor’s winding. Fortunately, copper has a well-known temperature coefficient (TC) of 0.39%/°C. rCS2 = rCS1 = If RCS is designed to have an opposite and equal percentage change in resistance to that of the wire, it cancels the temperature variation of the inductor’s DCR. Due to the nonlinear nature of NTC thermistors, resistors RCS1 and RCS2 are needed. See Figure 11 to linearize the NTC and produce the desired temperature tracking. rTH = 5. PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR OR LOW-SIDE MOSFET TO SWITCH NODES R TH R PH1 R PH2 TO V OUT SENSE k= R PH3 R CS1 R CS2 6. 18 C CS1 CSSUM 17 C CS2 (1 − A) 1 A − 1 − rCS2 r1 − rCS2 1 1 1 − 1 − rCS2 rCS1 (8) Calculate RTH = rTH × RCS, then select the closest value of thermistor available. Also compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: ADP3188 CSCOMP ( A − B ) × r1 × r2 − A × (1 − B ) × r2 + B × (1 − A) × r1 A × (1 − B ) × r1 − B × (1 − A) × r2 − ( A − B ) RTH ( ACTUAL ) RTH (CALCULATED ) (9) Calculate values for RCS1 and RCS2 using Equation 10: RCS1 = RCS × k × rCS1 KEEP THIS PATH AS SHORT AS POSSIBLE AND WELL AWAY FROM SWITCH NODE LINES RCS2 = RCS × ((1 − k ) + (k × rCS2 )) (10) 16 04835-011 CSREF Figure 11. Temperature Compensation Circuit Values The following procedure and expressions yield values to use for RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given RCS value. 1. For this example, RCS has been calculated to be 110 kΩ. Start with a thermistor value of 100 kΩ. Next, look through the available 0603-size thermistors, and find a Vishay NTHS0603N01N1003JR NTC thermistor with A = 0.3602 and B = 0.09174. From these, compute rCS1 = 0.3795, rCS2 = 0.7195, and rTH = 1.075. Solve for RTH, which yields118.28 kΩ. Then, choose 100 kΩ, which makes k = 0.8455. Finally, RCS1 and RCS2 are 35.3 kΩ and 83.9 kΩ. Choose the closest 1% resistor values, which yields a choice of 35.7 kΩ or 84.5 kΩ. Select an NTC based on type and value. Because there isn’t a value yet, start with a thermistor with a value close to RCS. The NTC should also have an initial tolerance of better than 5%. OUTPUT OFFSET 2. Based on the type of NTC, find its relative resistance value at two temperatures. The temperatures that work well are 50°C and 90°C. These resistance values are called A (RTH(50°C)/RTH(25°C)) and B (RTH(90°C)/RTH(25°C)). Note: the NTC’s relative value is always 1 at 25°C. The Intel specification requires that at no load the nominal output voltage of the regulator be offset to a value lower than the nominal voltage corresponding to the VID code. The offset is set by a constant current source flowing out of the FB pin (IFB) and flowing through RB. The value of RB can be found using Equation 11: 3. Find the relative values of RCS required for each of these temperatures. This is based on the percentage change needed, which in this example is initially 0.39%/°C. The relative values are called r1 (1/(1 + TC × (T1 − 25))) and r2 (1/(1 + TC × (T2 − 25))), where TC = 0.0039 for copper. T1 = 50°C and T2 = 90°C are chosen. From this, calculate that r1 = 0.9112 and r2 = 0.7978. RB = VVID − VONL I FB RB = 1.3 V − 1.281 V = 1.22 kΩ 15.5 µA The closest standard 1% resistor value is 1.21 kΩ. Rev. A | Page 17 of 28 (11) ADP3188 COUT SELECTION The required output decoupling for the regulator is typically recommended by Intel for various processors and platforms. Also, to determine what is required, use some simple design guidelines. These guidelines are based on having both bulk and ceramic capacitors in the system. This example uses 18, 10 µF 1206 MLC capacitors (CZ = 180 µF). The VID on-the-fly step change is 450 mV in 230 µs with a setting error of 2.5 mV. The maximum allowable load release overshoot for this example is 50 mV, so solving for the bulk capacitance yields ⎞ ⎛ ⎟ ⎜ ⎟ ⎜ 320 nH × 95 A C x (MIN ) ≤ ⎜ − 180 µF ⎟ = 3.65 mF ⎞ ⎛ 50 mV ⎟ ⎜ 4 × ⎜1.0 mΩ + ⎟ × 1. 3 V ⎜ ⎟ ⎜ 95 A ⎟⎠ ⎝ ⎠ ⎝ The first thing is to select the total amount of ceramic capacitance. This is based on the number and type of capacitor to be used. The best location for ceramic capacitors is inside the socket, with 12 to 18 of size 1206 being the physical limit. Others can be placed along the outer edge of the socket as well. C x (MAX ) ≤ Combined ceramic values of 200 µF to 300 µF are recommended, usually made up of multiple 10 µF or 22 µF capacitors. Select the number of ceramic capacitors and find the total ceramic capacitance (CZ). Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when considering the VID on-the-fly voltage stepping of the output (voltage step VV in time tV with error of VERR). A lower limit is based on meeting the capacitance for load release for a given maximum load step ∆IO and a maximum allowable overshoot. The total amount of load release voltage is given as ∆VO = ∆IO × RO + ∆Vrl, where ∆Vrl is the maximum allowable overshoot voltage. ⎞ ⎛ ⎟ ⎜ ⎟ ⎜ L × ∆ IO C x (MIN ) ≥ ⎜ − Cz ⎟ ⎟ ⎜ n × ⎛⎜ R + ∆Vrl ⎞⎟ × V ⎜ O ∆I ⎟ VID ⎟ ⎜ O ⎠ ⎝ ⎠ ⎝ (12) 320 nH × 450 mV 4 × 4.6 2 × (1.0 mΩ )2 × 1.3 V × ⎛ ⎞ 2 ⎜ ⎟ ⎛ 230 µs × 1.3 V × 4 × 4.6 × 1.0 mΩ ⎞ ⎟⎟ − 1⎟ − 180 µ F ⎜ 1 + ⎜⎜ 450 mV × 320 nH ⎝ ⎠ ⎜ ⎟ ⎝ ⎠ = 48.5 mF where K = 4.6. Using eight 560 µF Al-Poly capacitors with a typical ESR of 5 mΩ each yields CX = 4.48 mF with an RX = 0.63 mΩ. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using 2 Lx ≤ C z × R O ×Q 2 Lx ≤ 180 µF × (1 mΩ ) × 2 = 360 pH (14) 2 C x ( MAX ) ≤ ⎛ ⎞ 2 ⎜ ⎟ ⎛ VVID nKRO ⎞ VV ⎜ ⎟ × × ⎜ 1 + ⎜ tv × − 1⎟ − C z ⎟ 2 2 V V L nK RO VID ⎜ V ⎝ ⎠ ⎟ ⎝ ⎠ L ⎛V where K = 1n ⎜⎜ ERR ⎝ VV (13) ⎞ ⎟ ⎟ ⎠ To meet the conditions of these expressions and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance (RO). If the CX(MIN) is larger than CX(MAX), the system cannot meet the VID on-the-fly specification and may require the use of a smaller inductor or more phases (and may need the switching frequency to increase to keep the output ripple the same). where Q is limited to the square root of 2 to ensure a critically damped system. In this example, LX is approximately 350 pH for the eight A1-Polys capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased if there is excessive ringing. Note for this multimode control technique, all ceramic designs can be used as long as the conditions of Equations 11, 12, and 13 are satisfied. POWER MOSFETS For this example, the N-channel power MOSFETs have been selected for one high-side switch and two low-side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3418) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With VGATE ~10 V, logic-level threshold MOSFETs (VGS(TH)°< 2.5 V) are recommended. Rev. A | Page 18 of 28 ADP3188 The maximum output current (IO) determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With the ADP3188, currents are balanced between phases, thus the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, the following expression shows the total power being dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO): ⎡⎛ I PSF = (1 − D ) × ⎢⎜⎜ O ⎢⎝ nSF ⎣ 2 ⎞ ⎛nI ⎟ + 1 ×⎜ R ⎟ 12 ⎜ n ⎠ ⎝ SF ⎞ ⎟ ⎟ ⎠ 2 ⎤ ⎥ × RDS (SF ) ⎥ ⎦ Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input needs to be small (less than 10% is recommended) to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the nonoverlap dead time of the MOSFET driver (40 ns typical for the ADP3418). The output impedance of the driver is approximately 2 Ω, and the typical MOSFET input gate resistances are about 1 Ω to 2 Ω, so a total gate capacitance of less than 6000 pF should be adhered to. Because there are two MOSFETs in parallel, the input capacitance for each synchronous MOSFET should be limited to 3000 pF. The high-side (main) MOSFET has to be able to handle two main power dissipation components: conduction and switching losses. The switching loss is related to the amount of time it takes for the main MOSFET to turn on and off, and to the current and voltage that are being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET, where nMF is the total number of main MOSFETs: VCC × I O nMF × RG × nMF × C ISS n The conduction loss of the main MOSFET is given by the following, where RDS(MF) is the on resistance of the MOSFET: ⎡⎛ I PC ( MF ) = D × ⎢⎜⎜ O ⎢⎝ n MF ⎣ (15) Knowing the maximum output current being designed for and the maximum allowed power dissipation, it is possible to find the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an ambient temperature of 50°C, a safe limit for PSF is 1 W to 1.5 W at 120°C junction temperature. Thus, for this example (119 A maximum), RDS(SF) (per MOSFET) < 7.5 mΩ. This RDS(SF) is also at a junction temperature of about 120°C, so be certain to account for this temperature when making this selection. This example uses two lower-side MOSFETs at 4.8 mΩ each at 120°C. PS ( MF ) = 2 × f SW × Note that adding more main MOSFETs (nMF) does not really help the switching loss per MOSFET because the additional gate capacitance slows switching. The best way to reduce switching loss is to use lower gate capacitance devices. 2 ⎞ 1 ⎛ n × IR ⎟ + ×⎜ ⎟ 12 ⎜⎝ n MF ⎠ ⎞ ⎟ ⎟ ⎠ 2⎤ ⎥ × R DS ( MF ) ⎥ ⎦ (17) Typically, for main MOSFETs, the highest speed (low CISS) device is preferred, but these usually have higher on resistance. Select a device that meets the total power dissipation (about 1.5 W for a single D-PAK) when combining the switching and conduction losses. For this example, an NTD40N03L was selected as the main MOSFET (eight total; nMF = 8), with a CISS = 584 pF (max) and RDS(MF) = 19 mΩ (max at TJ = 120°C), and an NTD110N02L was selected as the synchronous MOSFET (eight total; nSF = 8), with CISS = 2710 pF (max) and RDS(SF) = 4.8 mΩ (max at TJ = 120°C). The synchronous MOSFET CISS is less than 3000 pF, satisfying that requirement. Solving for the power dissipation per MOSFET at IO = 119 A and IR = 11 A yields 958 mW for each synchronous MOSFET and 872 mW for each main MOSFET. These numbers comply with the guideline to limit the power dissipation to 1 W per MOSFET. One last thing to consider is the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by the following equation, where QGMF is the total gate charge for each main MOSFET, and QGSF is the total gate charge for each synchronous MOSFET: ⎡f ⎤ PDRV = ⎢ SW × (nMF × QGMF + nSF × QGSF ) + I CC ⎥ × VCC ⎢⎣ 2 × n ⎥⎦ (18) Also shown is the standby dissipation factor (ICC × VCC) for the driver. For the ADP3418, the maximum dissipation should be less than 400 mW. In this example, with ICC = 7 mA, QGMF = 5.8 nC, and QGSF = 48 nC, 297 mW is found in each driver, which is below the 400 mW dissipation limit. See the ADP3418 data sheet for more details. (16) where RG is the total gate resistance (2 Ω for the ADP3418 and about 1 Ω for typical high speed switching MOSFETs, making RG = 3 Ω), and CISS is the input capacitance of the main MOSFET. Rev. A | Page 19 of 28 ADP3188 RAMP RESISTOR SELECTION The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. The following expression is used for determining the optimum value: The limit of the per-phase current limit described earlier is determined by AR × L RR = 3 × AD × RDS × C R RR = For values of RLIM greater than 500 kΩ, the current limit may be lower than expected, so some adjustment of RLIM may be needed. Here, ILIM is the average current limit for the output of the supply. In this example, choosing a peak current limit of 200 A for ILIM, results in RLIM = 156 kΩ, for which 150 kΩ is chosen as the nearest 1% value. (19) I PHLIM ≅ 0.2 × 320 nH = 356 kΩ 3 × 5 × 2.4 mΩ × 5 pF where AR is the internal ramp amplifier gain, AD is the current balancing amplifier gain, RDS is the total low-side MOSFET on resistance, and CR is the internal ramp capacitor value. The closest standard 1% resistor value is 357 kΩ. The internal ramp voltage magnitude can be calculated by using VR = VR = AR × (1 − D ) × VVID R R × C R × f SW 0.2 × (1 − 0.108 ) × 1.3 V = 390 m V 357 kΩ × 5 pF × 330 kHz (20) COMP PIN RAMP A ramp signal on the COMP pin is due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input: VR ⎛ 2 × (1 − n × D ) ⎜1 − ⎜ n× f ×C × R X SW O ⎝ ⎞ ⎟ ⎟ ⎠ (21) CURRENT-LIMIT SETPOINT To select the current-limit setpoint, first find the resistor value for RLIM. The current-limit threshold for the ADP3188 is set with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/µA (ALIM). RLIM can be found using ALIM × VLIM I LIM × RO + IR 2 (23) For the ADP3188, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the current-balancing amplifier gain (AD) is 5. Using VR of 0.49 V and RDS(MAX) of 3 mΩ (low-side on resistance at 150°C), calculate a per-phase peak current limit of 100 A. Although this number may seem high, this current level can be reached only with an absolute short at the output, and the current-limit latch-off function shuts down the regulator before overheating can occur. This limit can be adjusted by changing the ramp voltage (VR), but make sure not to set the per-phase limit lower than the average per-phase current (ILIM/n). D MAX = D × VCOMP ( MAX ) − VBIAS VRT (24) In this example, the maximum duty cycle is 0.46. FEEDBACK LOOP COMPENSATION DESIGN Optimized compensation of the ADP3188 allows the best possible response of the regulator’s output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion to the load current at any load current-slew rate. This ensures the optimal positioning and allows the minimization of the output decoupling. With the multimode feedback structure of the ADP3188, the feedback compensation must be set to make the converter’s output impedance, working in parallel with the output decoupling, to meet this goal. Several poles and zeros created by the output inductor and decoupling capacitors (output filter) need to be compensated for. In this example, the overall ramp signal is 0.49 V. RLIM = AD × R DS (MAX ) The per-phase initial duty cycle limit is determined by The size of the internal ramp can be made larger or smaller. If it is made larger, stability and transient response improve, but thermal balance degrades. Likewise, if the ramp is made smaller, thermal balance improves at the sacrifice of transient response and stability. The factor of three in the denominator of Equation 19 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance. VRT = VCOMP (MAX ) − V R − V BIAS (22) Rev. A | Page 20 of 28 ADP3188 A type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. Equations 25 to 29 yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the section). The first step is to compute the time constants for all of the poles and zeros in the system RE = n × RO + AD × RDS + RL × VRT 2 × L × (1 − n × D ) × VRT + VVID n × C X × RO × VVID RE = 4 × 1 mΩ + 5 × 2.4 mΩ + T A = C X × (RO − R ′) + 1.4 mΩ × 0.49 V 2 × 320 nH × (1 − 0.432 ) × 0.49 V + = 24.2 mΩ 1.3 V 4 × 4.45 mF × 1 mΩ × 1.3 V L X RO − R ′ 350 pH 1 mΩ − 0.65 mΩ = 4.45 mF × (1 mΩ − 0.5 mΩ ) + × = 2.50 µs × 1 mΩ 10.63 mΩ RO RX TB = (RX + R′ − RO ) × C X = (0.63 mΩ + 0.5 mΩ − 1 mΩ) × 4.45 mF = 580 ns ⎛ A × R DS V RT × ⎜⎜ L − D 2 × f SW ⎝ TC = VVID × R E TD = CX CA = n × RO × T A RE × R B CB = TD 333 ns = = 24.3 p F R A 13.7 kΩ (29) (32) (33) These are the starting values, prior to tuning the design, to account for layout and other parasitic effects (see the section). The final values selected after tuning are C A = 470 pF 4 × 1 mΩ × 2.50 µs CA = = 342 pF 24.2 mΩ × 1.21 kΩ TC 4.7 µs = = 13.7 kΩ C A 342 pF TB 580 ns = = 479 nF RB 1.21 kΩ C FB = (30) RA = (28) C X × C Z × RO2 4.45 mF × 180 µF × (1 mΩ )2 = = 333 ns × (RO − R ') + C Z × RO 4.45 mF × (1 mΩ − 0.5 mΩ ) + 180 µF × 1 mΩ The compensation values can then be solved using the following: (26) (27) ⎞ ⎛ 5 × 2.4 mΩ ⎞ ⎟ 0.49 V × ⎜ 320 nH − ⎟ ⎟ ⎜ 2 × 330 kHz ⎟⎠ ⎠= ⎝ = 4.7 µs 1.3 V × 24.2 mΩ where, for the ADP3188, R' is the PCB resistance from the bulk capacitors to the ceramics and where RDS is the total lowside MOSFET on resistance per phase. In this example, AD is 5, VRT equals 0.49 V, R' is approximately 0.5 mΩ (assuming a 4-layer, 1 ounce motherboard), and LX is 350 pH for the eight Al-Poly capacitors. (25) R A = 12.1 kΩ C B = 470 pF C FB = 22 pF (31) Rev. A | Page 21 of 28 ADP3188 Figure 12 and Figure 13 show the typical transient response using these compensation values. CIN SELECTION AND INPUT CURRENT DI/DT REDUCTION In continuous inductor current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n × VOUT/VIN and an amplitude of one-nth the maximum output current. To prevent large voltage transients, a low ESR input capacitor, sized for the maximum rms current, must be used. The maximum rms capacitor current is given by I CRMS = D × I O × 1 −1 N×D 04835-0-012 (34) Figure 12. Typical Transient Response for Design Example Load Step I CRMS = 0.108 × 119 A × 1 − 1 = 14.7 A 4 × 0.108 Note that the capacitor manufacturer’s ripple current ratings are often based on only 2,000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be placed in parallel to meet size or height requirements in the design. In this example, the input capacitor bank is formed by two 2,700 µF, 16 V aluminum electrolytic capacitors and eight 4.7 µF ceramic capacitors. 04835-0-013 To reduce the input current di/dt to a level below the recommended maximum of 0.1 A/µs, an additional small inductor (L > 370 nH at 18 A) should be inserted between the converter and the supply bus. That inductor also acts as a filter between the converter and the primary power source. 100 Figure 13. Typical Transient Response for Design Example Load Release EFFICIENCY (%) 80 60 40 20 0 0 20 40 60 80 OUTPUT CURRENT (A) 100 120 Figure 14. Efficiency of the Circuit of Figure 10 vs. Output Current Rev. A | Page 22 of 28 04835-014 VOUT = 1.3 V TA = 25°C ADP3188 TUNING THE ADP3188 1. Build a circuit based on the compensation values computed from the design spreadsheet. 2. Hook up the dc load to circuit, turn it on, and verify its operation. Also, check for jitter at no load and full load. 6. Measure the output voltage from no-load to full-load using 5 A steps. Compute the loadline slope for each change, and then average to get the overall loadline slope (ROMEAS). 7. If ROMEAS is off from RO by more than 0.05 mΩ, use the following to adjust the RPH values: DC Loadline Setting 3. Measure the output voltage at no load (VNL). Verify that it is within tolerance. 4. Measure the output voltage at full load cold (VFLCOLD). Let the board sit for ~10 minutes at full load, and then measure the output (VFLHOT). If there is a change of more than a few millivolts, adjust RCS1 and RCS2 using Equations 35 and 36. RCS2 ( NEW ) = RCS2(OLD ) × 5. V NL − VFLCOLD V NL − VFLHOT RPH ( NEW ) = RPH (OLD ) × ROMEAS RO (36) 8. Repeat Steps 6 and 7 to check the loadline, and repeat adjustments if necessary. 9. Once dc loadline adjustment is complete, do not change RPH, RCS1, RCS2, or RTH for remainder of procedure. 10. Measure the output ripple at no load and full load with a scope, and make sure it is within specifications. (35) Repeat Step 4 until the cold and hot voltage measurements remain the same. RCS1( NEW ) = (37) 1 RCS1(OLD ) + RTH (25°C ) RCS1(OLD ) × RTH (25°C ) + (RCS1(OLD ) − RCS2 ( NEW ) ) × (RCS1(OLD ) − RTH (25° C ) ) Rev. A | Page 23 of 28 − 1 RTH (25° C ) ADP3188 Initial Transient Setting AC Loadline Setting 11. Remove the dc load from the circuit and hook up the dynamic load. 19. With the dynamic load still set at the maximum step size, expand the scope time scale to see 2 µs/div to 5 µs/div. The waveform may have two overshoots and one minor undershoot (see Figure 16). Here, VDROOP is the final desired value. 12. Hook up the scope to the output voltage and set it to dc coupling, with the time scale at 100 µs/div. 13. Set the dynamic load for a transient step of about 40 A at 1 kHz with a 50% duty cycle. 14. Measure the output waveform (if not visible, use dc offset on scope to view). Try to use a vertical scale of 100 mV/div or finer. This waveform should look similar to Figure 15. VDROOP VTRAN2 04835-0-016 VTRAN1 VACDRP Figure 16. Transient Setting Waveform VDCDRP 20. If both overshoots are larger than desired, try making these adjustments: 04835-015 Note that if these adjustments do not change the response, the output decoupling is the limiting factor. Check the output response every time a change is made, or nodes are switched, to make sure the response remains stable. Figure 15. AC Loadline Waveform 15. Use the horizontal cursors to measure VACDRP and VDCDRP as shown. Do not measure the undershoot or overshoot that happens immediately after this step. 16. If VACDRP and VDCDRP are different by more than a few millivolts, use Equation 38 to adjust CCS. It may be necessary to parallel different values to get the correct one as there are limited standard capacitor values available. It is a good idea to have locations for two capacitors in the layout for this. C CS ( NEW ) = C CS (OLD ) × V ACDRP V DCDRP (38) • Make the ramp resistor larger by 25% (RRAMP). • For VTRAN1, increase CB, or increase the switching frequency. • For VTRAN2, increase RA, and decrease CA by 25%. 21. For load release (see Figure 17), if VTRANREL is larger than VTRAN1 (see Figure 16), there is not enough output capacitance. Either more capacitance is needed, or the inductor values need to be smaller. (If inductors are changed, start the design again using the spreadsheet and this tuning procedure.) 17. Repeat Steps 11 to 13, and repeat the adjustments if necessary. Once complete, do not change CCS for the remainder of the procedure. VTRANREL VDROOP 04835-0-017 18. Set the dynamic load step to maximum step size (do not use a step size larger than needed) and verify that the output waveform is square, which means that VACDRP and VDCDRP are equal. Figure 17. Transient Setting Waveform Rev. A | Page 24 of 28 ADP3188 Because the ADP3188 turns off all of the phases (switches inductors to ground), there is no ripple voltage present during load release. Thus, headroom does not need to be added for ripple, allowing load release VTRANREL to be larger than VTRAN1 by the amount of ripple, and still meet specifications. If VTRAN1 and VTRANREL are less than the desired final droop, this implies that capacitors can be removed. When removing capacitors, also check the output ripple voltage to make sure it is still within specifications. Rev. A | Page 25 of 28 ADP3188 LAYOUT AND COMPONENT PLACEMENT POWER CIRCUITRY RECOMMENDATIONS The following guidelines are recommended for optimal performance of a switching regulator in a PC system. GENERAL RECOMMENDATIONS For good results, a PCB with at least four layers is recommended. This allows the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 mΩ at room temperature. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths. Then, the resistance and inductance introduced by these current paths is minimized, and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3188) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground noisier. An analog ground plane should be used around and under the ADP3188 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and not tied to any other power circuitry to prevent power currents from flowing in it. The components around the ADP3188 should be located close to the controller with short traces. The most important traces to keep short, and away from other traces, are the FB and CSSUM pins. The output capacitors should be connected as close as possible to the load (or connector), for example, a microprocessor core, that receives the power. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop, as described next. The switching power path should be routed on the PCB to encompass the shortest possible length in order to minimize radiated switching noise energy (EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. Whenever a power dissipating component, for example, a power MOSFET, is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. This improves current rating through the vias and also improves thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heat-sink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. SIGNAL CIRCUITRY RECOMMENDATIONS The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential-mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB and FBRTN traces should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller. Rev. A | Page 26 of 28 ADP3188 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8° 0° 0.20 0.09 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 18. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 0.390 BSC 28 15 0.154 BSC 1 14 0.236 BSC PIN 1 0.069 0.053 0.065 0.049 0.010 0.004 0.025 BSC 0.012 0.008 SEATING PLANE COPLANARITY 0.004 0.010 0.006 8° 0° 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137AF Figure 19. 28-Lead Shrink Small Outline Package [QSOP] (RQ-28) Dimensions shown in inches ORDERING GUIDE Model ADP3188JRUZ-REEL1 ADP3188JRQZ-REEL1 1 Temperature Range 0°C to 85°C 0°C to 85°C Package Description Thin Shrink Small Outline Package 13” Reel Shrink Small Outline Package 13” Reel Z = Pb-free part. Rev. A | Page 27 of 28 Package Option RU-28 RQ-28 Quantity per Reel 2500 2500 ADP3188 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04835–0–4/05(A) Rev. A | Page 28 of 28