LANSDALE MC13156FB Wideband fm if system Datasheet

ML13156
Wideband FM IF System
Legacy Device: Motorola MC13156
The ML13156 is a wideband FM IF subsystem targeted at high performance data and analog applications. The ML13156 has an onboard
grounded collector VCO transistor that may be used with a fundamental or overtone crystal in single channel operation or with a PLL in
multichannel operation. The mixer is useful to 500 MHz and may be
used in a balanced–differential, or single–ended configuration. The IF
amplifier is split to accommodate two low cost cascaded filters. RSSI
output is derived by summing the output of both IF sections. A precision data shaper has a hold function to preset the shaper for fast recovery of new data.
Applications for the ML13156 include CT–2, wideband data links
and other radio systems utilizing GMSK, FSK, or FM modulation.
• 2.0 to 6.0 Vdc Operation
• Typical Sensitivity at 200 MHz of 2.0 µV for 12 dB SINAD
• RSSI Dynamic Range Typically 80 dB
• High Performance Data Shaper for Enhanced CT–2 Operation
• Internal 330 Ω and 1.4 kΩ Terminations for 10.7 Mhz and 455 kHz
Filters
• Split IF for Improved Filtering and Extended RSSI Range
• 3rd Order Intercept (Input) of –25 dBm (Input Matched)
• Operating Temperature Range – TA = –40 to +85°C
Simplified Block Diagram
LO
In
LO
Emit
24
23
VEE1
22
CAR
Det
RSSI
21
20
VEE2
19
DS
Hold
Data
Out
DS
Gnd
DS
In
Demod
Quad
Coil
18
17
16
15
14
13
Mixer
Data
Slicer
Bias
5.0
pF
Bias
LIM Amp
IF Amp
1
2
3
4
5
RF
In 1
RF
In 2
Mix
Out
VCC1
IF
In
6
7
IF
IF
DEC 1 DEC 2
8
9
10
IF
Out
VCC2
LIM
In
11
12
SO 24W = -6P
PLASTIC PACKAGE
CASE 751E
(SO-24L)
24
1
QFP 32 = -8P
PLASTIC QFP PACKAGE
CASE 873
32
1
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
SO 24W
QFP 32
MC13156DW
MC13156FB
ML13156-6P
ML13156-8P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN CONNECTIONS
SO–24L
QFP
RF Input 1
RF Input 2
Mixer Output
VCC1
Function
1
2
3
4
31
32
1
2
IF Amp Input
IF Amp Decoupling 1
IF Amp Decoupling 2
VCC Connect (N/C Internal)
5
6
7
–
3
4
5
6
IF Amp Output
VCC2
Limiter IF Input
Limiter Decoupling 1
8
9
10
11
7
8
9
10
Limiter Decoupling 2
VCC Connect (N/C Internal)
Quad Coil
Demodulator Output
12
–
13
14
11
12, 13, 14
15
16
Data Slicer Input
VCC Connect (N/C Internal)
Data Slicer Ground
Data Slicer Output
15
–
16
17
17
18
19
20
Data Slicer Hold
VEE2
RSSI Output/Carrier Detect In
Carrier Detect Output
18
19
20
21
21
22
23
24
VEE1 and Substrate
LO Emitter
LO Base
VCC Connect (N/C Internal)
22
23
24
–
25
26
27
28, 29, 30
LIM
LIM
DEC 1 DEC 2
NOTE: Pin Numbers shown for SOIC package only. Refer to Pin Assignments Table.
This device contains 197 active transistors.
Page 1 of 21
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ML13156
MAXIMUM RATINGS
Pin
Symbol
Value
Unit
Power Supply Voltage
Rating
16, 19, 22
–6.5
Vdc
Junction Temperature
–
VEE(max)
TJ(max)
150
°C
Storage Temperature Range
–
Tstg
–65 to +150
°C
NOTES: 1. Devices should not be operated at or outside these values. The "Recommended Operating
Conditions" table provides for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Rating
Power Supply Voltage @ TA = 25°C
–40°C ≤ TA ≤ +85°C
Input Frequency
Ambient Temperature Range
Input Signal Level
Pin
Symbol
Value
Unit
4, 9
16, 19, 22
VCC
VEE
0 (Ground)
–2.0 to –6.0
Vdc
1, 2
500
MHz
–
fin
TA
–40 to +85
°C
1, 2
Vin
200
mVrms
DC ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC1 = VCC2 = 0, no input signal.)
Pin
Symbol
Total Drain Current (See Figure 2)
VEE = –2.0 Vdc
VEE = –3.0 Vdc
VEE = –5.0 Vdc
VEE = –6.0 Vdc
19, 22
ITotal
Drain Current, I22 (See Figure 3)
VEE = –2.0 Vdc
VEE = –3.0 Vdc
VEE = –5.0 Vdc
VEE = –6.0 Vdc
22
Drain Current, I19 (See Figure 3)
VEE = –2.0 Vdc
VEE = –3.0 Vdc
VEE = –5.0 Vdc
VEE = –6.0 Vdc
19
Characteristic
I22
I19
Min
Typ
Max
Unit
–
3.0
–
–
4.8
5.0
5.2
5.4
–
8.0
–
–
–
–
–
–
3.0
3.1
3.3
3.4
–
–
–
–
–
–
–
–
1.8
1.9
1.9
2.0
–
–
–
–
1.0
1.1
1.2
Vdc
–
1.7
–
mA
mA
mA
mA
DATA SLICER (Input Voltage Referenced to VEE = –3.0 Vdc, no input signal; See Figure 15.)
Input Threshold Voltage (High Vin)
15
Output Current (Low Vin)
Data Slicer Enabled (No Hold)
V15 > 1.1 Vdc
V18 = 0 Vdc
17
V15
I17
AC ELECTRICAL CHARACTERISTICS (TA = 25°C, VEE = –3.0 Vdc, fRF = 130 MHz, fLO = 140.7 MHz, Figure 1 test
circuit, unless otherwise specified.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
1, 14
–
–
–100
–
dBm
Conversion Gain
Pin = –37 dBm (Figure 4)
1, 3
–
–
22
–
dB
Mixer Input Impedance
Single–Ended (Table 1)
1, 2
Rp
Cp
–
–
1.0
4.0
–
–
kΩ
pF
Mixer Output Impedance
3
–
–
330
–
Ω
IF RSSI Slope (Figure 6)
20
–
0.2
0.4
0.6
µA/dB
IF Gain (Figure 5)
5, 8
–
–
39
–
dB
Input Impedance
5
–
–
1.4
–
kΩ
Output Impedance
8
–
–
290
–
Ω
12 dB SINAD Sensitivity (See Figures 17, 23)
fin = 144.45 MHz; fmod = 1.0 kHz; fdev = ±75 kHz
MIXER
IF AMPLIFIER SECTION
Page 2 of 21
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Issue A
LANSDALE Semiconductor, Inc.
ML13156
AC ELECTRICAL CHARACTERISTICS (continued) (TA = 25°C, VEE = –3.0 Vdc, fRF = 130 MHz, fLO = 140.7 MHz, Figure 1 test
circuit, unless otherwise specified.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Limiter RSSI Slope (Figure 7)
20
–
0.2
0.4
0.6
µA/dB
Limiter Gain
–
–
–
55
–
dB
Input Impedance
10
–
–
1.4
–
kΩ
Output Current – Carrier Detect (High Vin)
21
–
–
0
–
µA
Output Current – Carrier Detect (Low Vin)
21
–
–
3.0
–
mA
Input Threshold Voltage – Carrier Detect
Input Voltage Referenced to VEE = –3.0 Vdc
20
–
0.9
1.2
1.4
Vdc
LIMITING AMPLIFIER SECTION
CARRIER DETECT
Figure 1. Test Circuit
ML13156
1:4
(1) TR 1
RF Input
130MHz
50
Mixer
1
Local
Oscillator
Input
140.7MHz
200m Vrms
24
200
23
2
1.0 n
Mixer
Output
330
3
4
IF Input
VEE
VCC
20
50
+
1.0 n
IF Output
VEE
A
RSSI
Output
A
19
VEE
100 n
+
1.0 n
1.0 µ
Data Slicer
Hold
18
Data
Slicer
Data Output
A
17
Bias
8
Carrier
Detect
A
6
1.0 n
7
1.0 n
9
10
SMA
100 n
IF Amp
1.0 n
Limiter
Input
A
1.0 µ
21
Bias
5
330
22
VCC
VEE
16
1.0 n
V
LIM Amp
15
100 n
1.0 n
50
1.0 n
11
1.0 n
14
12
13
100 k
100 k
5.0 p
150 p
(3)
1.0 µH
NOTES: 1. TR 1 Coilcraft 1:4 impedance transformer.
2. VCC is DC Ground.
3. 1.5 µH variable shielded inductor:
Toko Part # 292SNS–T1373 or Equivalent.
Page 3 of 21
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ML13156
Figure 2. Total Drain Current versus Supply
Voltage and Temperature
Figure 3. Drain Currents versus Supply Voltage
4.0
TA = 25°C
I 19 , I 22 DRAIN CURRENTS (mA)
TA = 85°C
6.0
55°C
5.5
25°C
5.0
–10°C
4.5
–40°C
4.0
3.5
1.0
2.0
3.0
4.0
5.0
6.0
3.2
2.8
2.4
2.0
3.0
4.0
5.0
6.0
7.0
VEE, SUPPLY VOLTAGE (–Vdc)
Figure 4. Mixer Gain versus Input Signal Level
Figure 5. IF Amplifier Gain versus Input
Signal Level and Ambient Temperature
40
22.5
38
20.0
TA = 25°C
17.5
15.0
36
34
32
–80
–70
–60
–50
–40
–30
–20
VEE = –5.0 Vdc
f = 10.7 MHz
26
–65
–10
85°C
55°C
25°C
–10°C
–40°C
30
28
–60
–55
–50
–45
–40
–35
–30
Pin, IF INPUT SIGNAL LEVEL (dBm)
Figure 6. IF Amplifier RSSI Output Current versus
Input Signal Level and Ambient Temperature
Figure 7. Limiter Amplifier RSSI Output Current
versus Input Signal Level and Temperature
17.5
TA = 25° to 85°C
VEE = –5.0 Vdc
f = 10.7 MHz
–10°C
–40°C
15.0
12.5
10.0
7.5
5.0
2.5
0
–50
–40
–30
–20
–10
0
10
LIMITER AMPLIFIER RSSI OUTPUT CURRENT (µ A)
Pin, RF INPUT SIGNAL LEVEL (dBm)
20.0
30
25
TA = 25° to 85°C
VEE = – 5.0 Vdc
f = 10.7 MHz
–10°C
–40°C
20
15
10
5.0
0
–70
Pin, IF INPUT SIGNAL LEVEL (dBm)
Page 4 of 21
I19
2.0
25.0
10.0
–90
I22
VEE, SUPPLY VOLTAGE (–Vdc)
12.5
IF AMPLIFIER RSSI CURRENT (µ A)
3.6
1.6
1.0
7.0
IF AMPLIFIER GAIN (dB)
MIXER GAIN (dB)
TOTAL DRAIN CURRENT, I TOTAL (mA)
6.5
–60
–50
–40
–30
–20
–10
0
10
Pin, INPUT SIGNAL LEVEL (dBm)
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Issue A
Page 5 of 21
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19
10
12
11
9
22
23
24
4
Linear Amplifier
1
RFin1
1.0 k
2
RFin2
1.0 k
Mixer
7 1.4 k
Quadrature Detector
14
Demod
32 k
6
IFdec2
32 k
IFdec1
Mix IFin
5
3 Output
Quad coil
5.0 p
13
330
IF Amplifier
16 k
8
400 µ
290
DS in
15
RSSI
20 Out
Data Slicer
IFout
RSSI
64 k
64 k
Carrier
Detect
Output
21
64 k
28 µ
18
16
17
Carrier Detect
DSHold
DSGnd
DS
Output
Figure 8.
VEE2
LIM in
IMdec2
IMdec1
V CC2
VEE1
Oemitter
LO base
VCC1
Local Oscillator
Figure 8. ML13156-6P Internal Circuit Schematic
LANSDALE Semiconductor, Inc.
ML13156
Issue A
LANSDALE Semiconductor, Inc.
ML13156
CIRCUIT DESCRIPTION
GENERAL
The ML13156 is a low power single conversion wideband FM
receiver incorporating a split IF. This device can be used as a single
conversion receiver or as the backend in digital FM systems such as
CT–2 and wide band data links with data rates up to 500 kbaud. It
contains a mixer, oscillator, signal strength meter drive, IF amplifier, limiting IF, quadrature detector and a data slicer with a hold
function (refer to Figure 8, Simplified Internal Circuit Schematic).
CURRENT REGULATION
Temperature compensating voltage independent current regulators are used throughout.
MIXER
The mixer is a double–balanced four quadrant multiplier and is
designed to work up to 500 MHz. It can be used in differential
or in single–ended mode by connecting the other input to the
positive supply rail.
RSSI current output is derived by summing the currents for the
IF and limiting amplifier stages. An external resistor at Pin 20
sets the voltage range or swing of the RSSI output voltage.
Linearity of the RSSI is optimized by using external ceramic or
crystal bandpass filters which have and insertion loss of 8.0 dB.
The RSSI circuit is designed to provide 70+ dB of dynamic
range with temperature compensation (see Figures 6 and 7
which show RSSI responses of the IF and Limiter amplifiers).
Variation in the RSSI output current with supply voltage is 5 ma
total delta (see Figure 11).
CARRIER DETECT
When the meter current flowing through the meter load resistance reaches 1.2 Vdc above ground, the comparator flips, causing the carrier detect output to go high. Hysteresis can be
accomplished by adding a very large resistor for positive feedback between the output and the input of the comparator.
Figure 4 shows the mixer gain and saturated output response as
a function of input signal drive. The circuit used to measure this
is shown in Figure 1. The linear gain of the mixer is approximately 22 dB. Figure 9 shows the mixer gain versus the IF output frequency with the local oscillator of 150 MHz at 100
mVms LO drive level. The RF frequency is swept. The sensitivity of the IF output of the mixer is shown in Figure 10 for an RF
input drive of 10 mVrms at 140 MHz and IF at 10 MHz.
IF AMPLIFIER
The first IF amplifier section is composed of three differential
stages with the second and third stages contributing to the RSSI.
This section has internal dc feedback and external input decoupling for improved symmetry and stability. The total gain of the
IF amplifier block is approximately 39 dB at 10.7 MHz. Figure
5 shows the gain and saturated output response of the IF amplifier over temperature, while Figure 12 shows the IF amplifier
gain as a function of the IF frequency.
The single–ended parallel equivalent input impedance of the
mixer is Rp ~ 1.0 kΩ and Cp ~ 4.0 pF (see Table 1 for details).
The buffered output of the mixer is internally loaded resulting in
an output impedance of 330 Ω.
The fixed internal input impedance is 1.4kΩ. It is designed for
application where a 455 kHz ceramic filter is used and no external output matching is necessary since the filter requires a 1.4
kΩ source and load impedance.
LOCAL OSCILLATOR
The on–chip transistor operates with crystal and LC resonant
elements up to 220 MHz. Series resonant, overtone crystals are
used to achieve excellent local oscillator stability. 3rd overtone
crystals are used through about 65 to 70 MHz. Operation from
70 MHz up to 180 MHz is feasible using the on–chip transistor
with a 5th or 7th overtone crystal. To enhance operation using
an overtone crystal, the internal transistor’s bias is increased by
adding an external resistor from Pin 23 to VEE. –10 dBm of
local oscillator drive is needed to adequately drive the mixer
(Figure 10).
For 10.7 Mhz ceramic filter applications, an external 430 Ω
resistor must be added in parallel to provide the equivalent load
impedance of 330 Ω that is required by the filter; however, no
external matching is necessary at the input since the mixer output matches the 330 Ω source impedance of the filter. For 455
kHz applications, an external 1.1 kΩ resistor must be added in
series with the mixer output to obtain the required matching
impedance of 1.4 kΩ of the filter input resistance. Overall RSSI
linearity is dependent on having total midband attenuation of 12
dB (6.0 dB insertion loss plus 6.0 dB impedance matching loss)
for the filter. The output of the IF amplifier is buffered and the
impedance is 290 Ω.
The oscillator configurations specified above, and two others
using an external transistor, are described in the application section:
1) A 133 MHz oscillator multiplier using a 3rd overtone
crystal, and
2) A 307.8 to 309.3 MHz manually tuned, varactor
controlled local oscillator.
RSSI
The Received Signal Strength Indicator (RSSI) output is a current proportional to the log of the received signal amplitude. The
Page 6 of 21
LIMITER
The limiter section is similar to the IF amplifier section except
that four stages are used with the last three contributing to the
RSSI. The fixed internal input impedance is 1.4 kΩ. The total
gain of the limiting amplifier sections is approximately 55 dB.
This IF limiting amplifier section internally drives the quadrature detector section.
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ML13156
Figure 10. Mixer IF Output Level versus
Local Oscillator Input Level
Figure 9. Mixer Gain versus IF Frequency
–5.0
VEE = –3.0 Vdc
Vin = 1.0 mVrms (–47 dBm)
RO = 330 Ω
Rin = 50 Ω
BW(3.0 dB) = 21.7 MHz
fIF = fLO – fRF
fLO = 150 MHz
VLO = 100 mVrms
10
5.0
0
–5.0
0.1
I 20 , RSSI OUTPUT CURRENT ( µ A)
40
35
30
25
20
15
10
5.0
1.0
10
–15
–20
–25
–30
fRF = 140 MHz; fLO = 150 MHz
RF Input Level = –27 dBm
(10 mVrms)
Rin = 50 Ω; RO = 330 Ω
–35
–40
–40
–30
–20
–10
0
10
fIF, IF FREQUENCY (MHz)
LO DRIVE (dBm)
Figure 11. RSSI Output Current versus
Supply Voltage and RF Input Signal Level
Figure 12. IF Amplifier Gain versus IF Frequency
Vin =
60
TA = 25°C
50
–20 dBm
–40 dBm
–60 dBm
–80 dBm
–100 dBm
0
1.0
VEE = –3.0 Vdc
TA = 25°C
–10
–45
–50
100
IF AMPLIFIER GAIN (dB)
MIXER GAIN (dB)
15
MIXER IF OUTPUT LEVEL (dBm)
20
2.0
40
30
Vin = 100 µV
Rin = 50 Ω
RO = 330 Ω
BW(3.0 dB) = 26.8 MHz
TA = 25°C
20
10
3.0
4.0
5.0
6.0
0
0.1
7.0
1.0
VEE, SUPPLY VOLTAGE (–Vdc)
10
100
f, FREQUENCY (MHz)
V 14 , RECOVERED AUDIO OUTPUT (mVrms)
Figure 13. Recovered Audio Output Voltage
versus Supply Voltage
400
300
200
fmod = 1.0 kHz
fdev = ±75 kHz
fRF = 140 MHz
RF Input Level = 1.0 mVrms
TA = 25°C
100
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
VEE, SUPPLY VOLTAGE (–Vdc)
Page 7 of 21
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Issue A
LANSDALE Semiconductor, Inc.
ML13156
QUADRATURE DETECTOR
The quadrature detector is a doubly balanced four quadrant
multiplier with an internal 5.0 pF quadrature capacitor to couple the IF signal to the external parallel RLC resonant circuit
that provides the 90 degree phase shift and drives the quadrature detector. A single pin (Pin 13) provides for the external
LC parallel resonant network and the internal connection to
the quadrature detector.
The bandwidth of the detector allows for recovery of relatively high data rate modulation. The recovered signal is converted from differential to single ended through a push–pull
NPN/PNP output stage. Variation in recovered audio output
voltage with supply voltage is very small (see Figure 13). The
output drive capability is approximately ±9.0 µA for a frequency deviation of ±75 kHz and 1.0 kHz modulating frequency (see Application Circuit)
Q3 and Q2. When the data slicer input (Pin 15) is pulled up,
Q1 turns off; Q2 turns on, thereby clamping the input at 2.0
Vbe. On the other hand, when Pin 15 is pulled down, Q1
turns on; Q2 turns off, thereby clamping the input at 1.0 Vbe.
The recovered data signal from the quadrature detector is ac
coupled to the data slicer via an input coupling capacitor. The
size of the capacitor and the nature of the data signal determine how faithfully the data slicer shapes up the recovered
signal. The time constant is short for large peak to peak voltage swings or when there is a change in dc level at the detector output. For small signal or for continuous bits of the same
polarity which drift close to the threshold voltage, the time
constant is longer. When centered there is no input current
allowed, which is to say, that the input looks high in impedance.
DATA SLICER
The data slicer input (Pin 15) is self centering around 1.1 V
with clamping occurring at 1.1 ± 0.5 Vbe Vdc. It is designed
to square up the data signal. Figure 14 shows a detailed
schematic of the data slicer.
Another unique feature of the data slicer is that it responds to
various logic levels applied to the Data Slicer Hold Control
pin (Pin 18). Figure 15 illustrates how the input and output
currents under “no hold” condition relate to the input voltage.
Figure 16 shows how the input current and input voltage
relate to the both the “no hold” and “hold” condition.
The Voltage Regulator sets up to 1.1 Vdc on the base of Q12,
the Differential Input Amplifier. There is a potential of 1.0
Vbe on the base–collector of transistor diode Q11 and 2.0
Vbe on the base–collector of Q10. This sets up a 1.5 Vbe
(~1.1 Vdc) on the node between the 36 kΩ resistors which is
connected to the base of Q12. The differential output of the
data slicer Q12 and Q13 is converted to a single–ended output by the Driver Circuit. Additional circuitry, not shown in
Figure 14, tends to keep the data slicer input centered at 1.1
Vdc as input signal levels vary.
The Input Diode Clamp Circuit provides the clamping at 1.0
Vbe (0.75 Vdc) and 2.0 Vbe (1.45 Vdc). Transistor diodes Q7
and Q8 are on , thus, providing a 2.0 Vbe potential at the base
of Q1. Also, the voltage regulator circuit provides a potential
of 2.0 Vbe on the base of Q3 and 1.0 Vbe on the emitter of
The Hold control (Pin 18) does three separate tasks:
1) With Pin 18 at 1.0 Vbe or greater, the output is shut off
(sets high). Q19 turns on which shunts the base drive
from Q20, thereby turning the output off.
2) With Pin 18 at 2.0 Vbe or greater, internal clamping diodes
are open circuited and the comparator input is shut off and
effectively open circuited. This is accomplished by turning
off the current source to emitters of the input differential
amplifier, thus, the input differential amplifier is shut off.
3) When the input is shut off, it allows the input capacitor to
hold its charge during transmit to improve recovery at the
beginning of the next receive period. When it is turned on,
it allows for very fast charging of the input capacitor for
quick recovery of new tuning or data average. The above
features are very desirable in a TDD digital FM system.
Page 8 of 21
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LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
Figure 14. Data Slicer Circuit
9
15
VCC
DS In
8.0 k
8.0 k
Data Out
17
Q15
Q14
Q10
Q3
36 k
Q20
Q1
Q12
Q5
Q13
36 k
Q7
Q2
Q8
16
DS Gnd
32 k
Q4
Q6
Q11
Q9
16 k
16 k
Voltage
Regulator
(Q10, Q11)
0.5
2.5
0.3
1.5
Output Current
(I17)
0.1
0.5
–0.1
–0.5
–0.5
0.6
Input Current
(I15)
0.8
1.0
VEE = –3.0 Vdc
V18 = 0 Vdc
(No Hold)
1.2
1.4
1.6
–1.5
–2.5
1.8
Driver and
Output Circuit
(Q14, Q20)
18
DS Hold
Figure 16. Data Slicer Input Current
versus Input Voltage
150
100
VEE = –3.0 Vdc
Hold
V18 ≥1
No Hold
V18 = 0 Vdc
50
0
–50
–100
–1.0
V15, INPUT VOLTAGE (Vdc)
Page 9 of 21
64 k
Differential
Input Amplifier
(Q12, Q13)
I 15 , INPUT CURRENT ( µA)
I 15 , INPUT CURRENT (mA)
Figure 15. Data Slicer Input/Output Currents
versus Input Voltage
–0.3
64 k
64 k
19
Input Diode
Clamp Circuit
(Q1 to Q9)
Q19
Q17
Q16
I 17 , OUTPUT CURRENT (mA)
VEE
Q18
No Hold
Hold
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
V15, INPUT VOLTAGE (Vdc)
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
Figure 17. MC13156DW Application Circuit
+
1.0 µ
(6)
0.146 µ
MMBR5179
ML13156
7.5 p
144.455 MHz
RF Input
Mixer
1
(1)
0.1 µ
10 n
100 p
(5) 0.82 µ
68 p
50 p
SMA
15 k
24
5.6 k
470
43 p
133.755 MHz
Osc/Tripler
23
2
1.0 k
(4) 3rd O.T.
XTAL
10 n
3
(2) 10.7 MHz
Ceramic
Filter
4
22
VEE
VCC
21
Bias
5
6
VEE
430
7
9
10
10 n
Data Slicer
Hold
10 k
Bias
VCC
19
18
Data
Slicer
8
VCC
RSSI
Output
10 n
47 k
IF Amp
(2) 10.7 MHz
Ceramic
Filter
100 k
20
10 n
10 n
Carrier
Detect
17
VEE
LIM Amp
Data
Output
16
100 n
15
180 p
10 n
11
100 k
14
100 k
430
10 n
13
12
5.0 p
150 p
+
10 k
(3)
1.5 µ
VCC
1.0 µ
NOTES: 1. 0.1 µH Variable Shielded Inductor: Coilcraft part # M1283–A or equivalent.
2. 10.7 MHz Ceramic Filter: Toko part # SK107M5–A0–10X or Murata Erie part # SFE10.7MHY–A.
3. 1.5 µH Variable Shielded Inductor: Toko part # 292SNS–T1373.
4. 3rd Overtone, Series Resonant, 25 PPM Crystal at 44.585 MHz.
5. 0.814 µH Variable Shielded Inductor: Coilcraft part # 143–18J12S.
6. 0.146 µH Variable Inductor: Coilcraft part # 146–04J08.
Page 10 of 21
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Issue A
LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
Page 11 of 21
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Issue A
LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
COMPONENT SELECTION
The evaluation PC board is designed to accommodate specific
components, while also being versatile enough to use components
from various manufacturers and coil types. Figures 18 and 19 show
the placement for the components specified in the application circuit (Figure 17). The application circuit schematic specifies particular components that were used to achieve the results shown in the
typical curves and tables but equivalent components should give
similar results.
INPUT MATCHING NETWORKS.COMPONENTS
The input matching circuit shown in the application circuit
schematic is passive high pass network which offers effective image
rejection when the local oscillator is below the RF input frequency.
Silver mica capacitors are used for their high Q and tight tolerance.
The PC board is not dedicated to any particular input matching network topology; space is provided for the designer to breadboard as
desired.
Alternate matching networks using 4:1 surface mount transformers
or BALUNs provide satisfactory performance. The 12 dB SINAD
sensitivity using the above matching networks is typically –100
dBm for fmod = 1.0 kHz and fdev = ±75 kHz at fIN = 144.45
MHz and fOSC = 133.75 MHz (see Figure 23).
It is desirable to use a SAW filter before the mixer to provide additional selectivity and adjacent channel rejection and improved sensitivity. The SAW filter should be designed to interface with the
mixer input impedance of approximately 1.0 kΩ. Table 1 displays
the series equivalent single–ended mixer input impedance.
LOCAL OSCILLATORS
VHF APPLICATIONS – The local oscillator circuit shown in the
application schematic utilizes a third overtone crystal and an RF
transistor. Selecting a transistor having good phase noise performance is important; a mandatory criteria is for the device to have
good linearity of beta over several decades of collector current. In
other words, if the low current beta is suppressed, it will not offer
good 1/f noise performance. A third overtone series resonant crystal
having at least 25 ppm tolerance over the operating temperature is
recommended. The local oscillator is an impedance inversion third
overtone Colpitts network and harmonic generator. In this circuit a
560 to 1.0 kΩ resistor shunts the crystal to ensure that it operates in
its overtone mode; thus, a blocking capacitor is needed to eliminate
the dc path to ground. The resulting parallel LC network should
“free–run” near the crystal frequency if a short to ground is placed
across the crystal. To provide sufficient output loading at the collector, a high Q variable inductor is used that is tuned to self resonate
at the 3rd harmonic of the overtone crystal frequency.
The on–chip grounded collector transistor may be used for HF and
VHF local oscillator with higher order overtone crystals. Figure 18
shows a 5th overtone oscillator at 93.3 MHz and Figure 19 shows a
7th overtone oscillator at 148.3 MHz. Both circuits use a Butler
overtone oscillator configuration. The amplifier is an emitter follower. The crystal is driven from the emitter and is coupled to the
high impedance base through a capacitive tap network. Operation at
the desired overtone frequency is ensured by the parallel resonant
circuit formed by the variable inductor and the tap transistor and
PC board. The variable inductor specified in the schematic could be
replaced with a high tolerance, high Q ceramic or air wound surface mount component. if the other component have good tolerance. A variable inductor provides an adjustment for gain and frequency of the resonant tank ensuring lock up and start up of the
crystal oscillator. The overtone crystal is chosen with ESR of typically 80 Ω and 120 Ω maximum; if the resistive loss in the crystal
is too high, the performance of the oscillator may be impacted by
lower gain margins.
Table 1. Mixer Input Impedance Data
(Single–ended configuration, VCC = 3.0 Vdc, local oscillator drive = 100 mVrms)
Page 12 of 21
Frequency
(MHz)
Series Equivalent
Complex Impedance
(R + jX)
(Ω)
Parallel
Resistance
Rp
(Ω)
Parallel
Capacitance
Cp
(pF)
90
190 – j380
950
4.7
100
160 – j360
970
4.4
110
130 – j340
1020
4.2
120
110 – j320
1040
4.2
130
97 – j300
1030
4.0
140
82 – j280
1040
4.0
150
71 – j270
1100
4.0
160
59 – j260
1200
3.9
170
52 – j240
1160
3.9
180
44 – j230
1250
3.8
190
38 – j220
1300
3.8
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LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
Page 13 of 21
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Issue A
LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
A series LC network to ground (which is VCC) is comprised of the
inductance of the base lead of the on–chip transistor and PC board
traces and tap capacitors. Parasitic oscillations often occur in the
200 to 800 MHz range. A small resistor is placed in series with the
base (Pin 24) to cancel the negative resistance associated with this
undesired mode of oscillation. Since the base input impedance is so
large a small resistor in the range of 27 to 68 Ω has very little effect
on the desired Butler mode of oscillation.
The crystal parallel capacitance, Co, provides a feedback path that
is low enough in reactance at frequencies of 5th overtone or higher
to cause trouble. Co has little effect near resonance because of the
low impedance of the crystal motional arm (Rm–Lm–Cm). As the
tunable inductor which forms the resonant tank with the tap capacitors is tuned off the crystal resonant frequency, it may be difficult
to tell if the oscillation is under crystal control. Frequency jumps
may occur as the inductor is tuned. In order to eliminate this behavior an inductor (Lo) is placed in parallel with the crystal. Lo is chosen to resonant with the crystal parallel capacitance (Co) at the
desired operation frequency. The inductor provides a feedback path
at frequencies well below resonance; however, the parallel tank network of the tap capacitors and tunable inductor prevent oscillation
at these frequencies.
UHF APPLICATION
Figure 20 shows a 318.5 to 320 MHz receiver which drives the
mixer with an external varactor controlled (307.8 to 309.3 MHz)
LC oscillator using an MPS901 (RF low power transistor in a
TO–92 plastic package; also MMBR901 is available in a SOT–23
surface mount package). With the 50 kΩ 10 turn potentiomenter
this oscillator is tunable over a range of approximately 1.5 MHz.
The MMBV909L is a low voltage varactor suitable for UHF applications; it is a dual back–to–back varactor in a SOT–23 package.
The input matching network uses a 1:4 impedance matching transformer (Recommended sources are Mini–Circuits and Coilcraft).
Using the same IF ceramic filters and quadrature detector circuit as
specified in the applications circuit in Figure 17, the 12 dB SINAD
performance is –95 dBm for a fmod = 1.0 kHz sinusoidal waveform and fdev ±40 kHz.
This circuit is breadboarded using the evaluation PC bard shown in
Figures 32 and 33. The RF ground is VCC and path lengths are
minimized. High quality surface mount components were used
except where specified. The absolute values of the components
used will vary with layout placement and component parasitics.
RSSI RESPONSE
Figure 24 shows the full RSSI response in the application circuit.
The 10.7 MHz, 110 kHz wide bandpass ceramic filters (recommended sources are TOKO part # SK107M5–AO–10X or Murata
Erie SFE10.7MHY–A) provide the correct band pass insertion loss
to linearize the curve between the limiter and IF portions of RSSI.
Figure 23 shows that limiting occurs at an input of –100 dBm. As
shown in Figure 24, the RSSI output linear from –100 dBm to –30
dBm.
The RSSI rise and fall times for various RF input signal levels and
R20 values are measures at Pin 20 without 10 nF filter capacitor. A
10 kHz square wave pulses the RF input signal on and off. Figure
25 shows that the rise and fall times are short enough to recover
greater than 10 kHz ASK data; with a wider IF band pass filters
data rates up to 50 kHz may be achieved. The circuit used is the
application circuit in Figure 17 with no RSSI output filter capacitor.
Figure 18. MC13156DW Application Circuit
fRF = 104 MHz; fLO = 93.30 MHz
5th Overtone Crystal Oscillator
(4)
0.135 µH
33
(2)
10 p
104 MHz
RF Input
SMA
3.0 p
Mixer
120 p
(1)
0.1 µ
27 p
1
24
2
23
1.0 µH
(3)
10 n
4.7 k
3
+
1.0 µ
VEE
22
30 p
5th OT
XTAL
To Filter
10 n
VCC
NOTES: 1. 0.1 µH Variable Shielded Inductor: Coilcraft part # M1283–A or equivalent.
2. Capacitors are Silver Mica.
3. 5th Overtone, Series Resonant, 25 PPM Crystal at 93.300 MHz.
4. 0.135 µH Variable Shielded Inductor: Coilcraft part # 146–05J08S or equivalent.
Page 14 of 21
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Issue A
LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
Figure 19. MC13156DW Application Circuit
fRF = 159 MHz; fLO = 148.30 MHz
7th Overtone Crystal Oscillator
(4)
76 nH
+
1.0 µ
33
(2)
5.0 p
159 MHz
RF Input
(1)
0.08 µH
SMA
27 p
Mixer
50 p
1
24
2
23
3
22
0.22 µH
47 p
10 n
4.7 k
470
VEE
(3)
7th OT
XTAL
10 n
To IF Filter
VCC
NOTES: 1. 0.08 µH Variable Shielded Inductor: Toko part # 292SNS–T1365Z or equivalent.
2. Capacitors are Silver Mica.
3. 7th Overtone, Series Resonant, 25 PPM Crystal at 148.300 MHz.
4. 76 nH Variable Shielded Inductor: Coilcraft part # 150≠03J08S or equivalent.
Figure 20. MC13156DW Varactor Controlled LC Oscillator
4.7 k
MPS901
(1)
1:4 Transformer
6.8 p
47 k
VVCO
+
1.0 µ
(6)
318.5 to
320 MHz
RF Input
(2)
50 k
1.0 M
0.1 µ
Mixer
1
24
2
23
20 p
24 p
(4)
MMBV909L
SMA
1.8 k
3
VEE
12 k
24 p
(3)
18.5 nH
22
1.0 n
307.8–309.3 MHz
LC Varactor
Controlled Oscillator
VCC = 3.3 Vdc (Reg)
NOTES: 1. 1:4 Impedance Transformer: Mini±Circuits.
2. 50 k Potentiometer, 10 turns.
3. Spring Coil; Coilcraft A05T.
4. Dual Varactor in SOT–23 Package.
5. All other components are surface mount components.
6. Ferrite beads through loop of 24 AWG wire.
Page 15 of 21
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Issue A
LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
45 MHZ NARROWBAND RECEIVER
The above application examples utilize a 10.7 MHz IF. In this section a narrowband receiver with a 455 kHz IF will be described.
Figure 21 shows a full schematic of a 45 MHz reciever that uses a
3rd overtone crystal with the on–chip oscillator transistor. The
oscillator configuration is similar to the one used in Figure 17; it is
called an impedance inversion Colpitts. A 44.545 Mhz 3rd overtone, series resonant crystal is used to achieve an IF frequency at
455 kHz. The ceramic IF filters selected are Murata Erie part #
SFG455A3. 1.2 kΩ chip resistors are used in series with the filters
to achieve the terminating resistance of 1.4 kΩ to the filter. The IF
decoupling is very important; 0.1 µF chip capacitors are used at
Pins 6, 7, 11 and 12. The quadrature detector tank circuit uses a
455 kHz quadrature tank from Toko.
The 12 dB SINAD performance is –109 dBm for a fmod = 1.0 kHz
and a fdev = ±4.0 kHz. The RSSI dynamic range is approximately
80 db of linear range (see Figure 22).
RECEIVER DESIGN CONSIDERATIONS
The curves of signal levels at various portions of the application
receiver with respect to RF input level are shown in Figure 26. This
information helps determine the network topology and gain blocks
required ahead of the MC13156 to achieve the desired sensitivity
and dynamic range of the receiver system. In the application circuit
the input third order intercept (IP3) performance of the system is
approximately –25 dBm (see Figure 27).
Figure 21. MC13156DW Application Circuit at 45 MHz
1.8 µH
+
1.0 µ
(6)
33 p
45 Hz
RF Input
SMA
(1)
0.33 µH
10 n
Mixer
1
24
56 p
180 p
23
2
10 n
1.2 k
(2) 455 kHz
Ceramic
Filter
39 p
3
4
VCC
21
Bias
VEE
7
9
VCC
10 n
Data Slicer
Hold
10 k
17
Bias
8
19
18
Data
Slicer
Data
Output
VEE
16
100 n
15
10
LIM Amp
0.1 µ
Carrier
Detect
RSSI
Output
10 n
47 k
6
470 k
(4) 3rd OT
XTAL
44.545
MHz
100 k
IF Amp
0.1 µ
VCC
10 n
20
0.1 µ
(2) 455 kHz
Ceramic
Filter
10 k
22
VEE
5
1.2 k
(5) 0.416 µH
100 k
14
11
1.0 n
0.1 µ
Audio To
C–Message
Filter and
Amp.
100 k
13
12
5.0 p
27 k
NOTES: 1. 0.33 µH Variable Shielded Inductor: Coilcraft part # 7M3–331 or equivalent.
2. 455 kHz Ceramic Filter: Murata Erie part # SFG455A3.
3. 455 kHz Quadrature Tank: Toko part # 7MC8128Z.
4. 3rd Overtone, Series Resonant, 25 PPM Crystal at 44.540 MHz.
5. 0.416 µH Variable Shielded Inductor: Coilcraft part # 143–10J12S.
6. 1.8 µH Molded Inductor.
Page 16 of 21
+
www.lansdale.com
180 p
(3)
680 µH
VCC = 2.0 to 5.0 Vdc
1.0 µ
Issue A
LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
Figure 23. S + N/N versus RF Input Signal Level
1.8
10
1.6
0
1.4
fRF = 45.00 MHz
VCC = 2.0 Vdc
12 dB SINAD @ –109 dBm
(0.8 µVrms)
(See Figure 21)
1.2
1.0
S + N, N (dB)
RSSI OUTPUT VOLTAGE (Vdc)
Figure 22. RSSI Output Voltage
versus Input Signal Level
0.8
–20
–30
–40
0.4
–120
–50
–110 –100
N
–100
–80
–60
–40
–20
0
20
VCC = 5.0 Vdc
fc = 144.455 MHz
fLO = 133.755 MHz
Low Loss 10.7 MHz
Ceramic Filter
(See Figure 17)
0.6
0.4
–100
–80
–60
–40
–20
0
–50
–40
–30
–20
35
tr
tf
tr
tf
tr
tf
30
25
20
@ 22 k
@ 22 k
@ 47 k
@ 47 k
@ 100 k
@ 100 k
15
10
5.0
0
0
–20
–40
–60
–80
SIGNAL INPUT LEVEL (dBm)
RF INPUT SIGNAL LEVEL (dBm)
Figure 26. Signal Levels versus
RF Input Signal Level
Figure 27. 1.0 dB Compression Pt. and Input
Third Order Intercept Pt. versus Input Power
0
10
LO Level = –2.0 dBm
(See Figure 17)
MIXER IF OUTPUT LEVEL (dBm)
IF Output
Limiter Input
–20
–30
–40
–50
–60
–90
–80
–70
–60
–50
–40
–30
0
–10
–20
VCC = 5.0 Vdc
fRF1 = 144.4 MHz
fRF2 = 144.5 MHz
fLO = 133.75 MHz
PLO = –2.0 dBm
(See Figure 17)
1.0 dB Comp. Pt.
= –37 dBm
IP3 = –25 dBm
–30
–40
–50
–60
–70
–100
RF INPUT SIGNAL LEVEL (dBm)
Page 17 of 21
–60
Figure 25. RSSI Output Rise and Fall Times
versus RF Input Signal Level
0.8
–70
–100
–70
Figure 24. RSSI Output Voltage
versus Input Signal Level
1.0
–10
–80
RF INPUT SIGNAL (dBm)
1.2
0.2
–120
–90
SIGNAL INPUT LEVEL (dBm)
t r , t f , RSSI RISE AND FALL TIMES (µ s)
RSSI OUTPUT VOLTAGE (Vdc)
VCC = 5.0 Vdc
fdev = ±75 kHz
fmod = 1.0 kHz
fin = 144.45 MHz
(See Figure 17)
–10
0.6
1.4
POWER (dBm)
S+N
–80
–60
–40
–20
0
RF INPUT POWER (dBm)
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Issue A
LANSDALE Semiconductor, Inc.
ML13156
BER TESTING AND PERORMANCE
Bit error rate versus RF signal input level and IF filter bandwidth
are shown in Figure 28. The bit error rate data was taken under the
following test conditions:
•
•
•
•
•
Data rate = 100kbps
Filter cutoff frequency set to 39% of the data rate or 39 kHz.
Filter type is a 5 pole equal–ripple with 0.5° phase error.
VCC = 4.0 Vdc
Frequency deviation = ±32 kHz.
Page 18 of 21
10 –1
BER, BIT ERROR RATE
DESCRIPTION
The test setup shown in Figure 29 is configured so that the function
generator supplies a 100 kHz clock source to the bit error rate
tester. This device generates and receives a repeating data pattern
and drives a 5 pole baseband data filter. The filter effectively
reduces harmonic content of the base band data which is used to
modulate the RF generator which is running at 144.45 MHz.
Following processing of the signal by the receiver (ML13156), the
recovered baseband sinewave (data) is AC coupled to the data
slicer. The data slicer is essentially an auto–threshold comparator
which tracks the zero crossing of the incoming sinewave and provides logic level data at its output. Data errors associated with the
recovered data are collected by the bit error rate receiver and displayed.
10 –3
Figure 28. Bit Error Rate versus RF
Input Signal Level and IF Bandpass Filter
VCC = 4.0 Vdc
Data Pattern = 2E09 Prbs NRZ
Baseband Filter fc = 50 kHz
fdev = ±32 kHz
IF Filter BW
110 kHz
IF Filter BW
230 kHz
10 –5
10 –7
–90
–85
–80
–75
–70
RF INPUT SIGNAL LEVEL (dBm)
EVALUATION PC BOARD
The evaluation PCB is very versatile and is intended to be used
across the entire useful frequency range of this device. The center
section of the board provides an area for attaching all SMT components to the component ground side (see Figures 32 and 33).
Additionally, the peripheral area surrounding the RF core provides
pads to add supporting and interface circuitry as a particular application dictates
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Issue A
LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
Figure 29. Bit Error Rate Test Setup
Function Generator
Bit Error Rate Tester
RF Generator
Wavetek Model No. 164
HP3780A or Equivalent
HP8640B
Clock
Out
Gen
Clock
Input
Rcr
Clock
Input
Rcr
Data
Input
Generator
Output
Modulation
Input
RF
Output
5 Pole
Bandpass
Filter
Data Slicer
Output
Mixer
Input
MC13156
UUT
Page 19 of 21
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Issue A
LANSDALE Semiconductor, Inc.
ML13156
OUTLINE DIMENSIONS
PLASTIC QFP PACKAGE
(ML13156-8P)
CASE 873–01
ISSUE A
L
0.20 (0.008)
D
S
H A–B
V
M
B
0.20 (0.008)
L
0.05 (0.002) A–B
–B–
–A–
M
C A–B
S
D
S
16
S
17
24
25
B
32
P
B
DETAIL A
9
1
8
–A–, –B–, –D–
–D–
DETAIL A
A
0.20 (0.008)
M
C A–B
D
S
S
0.05 (0.002) A–B
S
0.20 (0.008)
M
H A–B
S
D
F
BASE
METAL
S
M
DETAIL C
N
J
C E
–C–
SEATING
PLANE
–H–
H
M
G
DATUM
PLANE
0.01 (0.004)
D
0.20 (0.008)
M
C A–B
S
D
S
SECTION B–B
VIEW ROTATED 90 CLOCKWISE
U
T
R
–H–
DATUM
PLANE
K
X
DETAIL C
Page 20 of 21
Q
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
www.lansdale.com
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
X
MILLIMETERS
MIN
MAX
7.10
6.95
6.95
7.10
1.40
1.60
0.273
0.373
1.30
1.50
0.273
–––
0.80 BSC
–––
0.20
0.119
0.197
0.33
0.57
5.6 REF
6°
8°
0.119
0.135
0.40 BSC
5°
10°
0.15
0.25
8.85
9.15
0.15
0.25
5°
11°
8.85
9.15
1.00 REF
INCHES
MIN
MAX
0.274
0.280
0.274
0.280
0.055
0.063
0.010
0.015
0.051
0.059
0.010
–––
0.031 BSC
–––
0.008
0.005
0.008
0.013
0.022
0.220 REF
6°
8°
0.005
0.005
0.016 BSC
5°
10°
0.006
0.010
0.348
0.360
0.006
0.010
5°
11°
0.348
0.360
0.039 REF
Issue A
LANSDALE Semiconductor, Inc.
ML13156
OUTLINE DIMENSIONS
PLASTIC PACKAGE
(ML13156-6P)
CASE 751E–04
(SO–24L)
ISSUE E
–A–
24
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
13
–B–
12X
P
0.010 (0.25)
1
M
B
M
12
24X
D
J
0.010 (0.25)
M
T A
S
B
S
F
R
C
–T–
SEATING
PLANE
22X
G
K
M
X 45°
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0°
8°
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0°
8°
0.395
0.415
0.010
0.029
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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