M28LV64 64K (8K x 8) LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION NOT FOR NEW DESIGN FAST ACCESS TIME: 200ns SINGLE LOW VOLTAGE OPERATION LOW POWER CONSUMPTION FAST WRITE CYCLE: – 64 Bytes Page Write Operation – Byte or Page Write Cycle: 3ms Max ENHANCED END OF WRITE DETECTION: – Ready/Busy Open Drain Output (only on the M28LV64) – Data Polling – Toggle Bit PAGE LOAD TIMER STATUS BIT HIGH RELIABILITY SINGLE POLYSILICON, CMOS TECHNOLOGY: – Endurance >100,000 Erase/Write Cycles – Data Retention >40 Years JEDEC APPROVED BYTEWIDE PIN OUT SOFTWARE DATA PROTECTION The M28LV64 is replaced by the M28C64-xxW 28 1 PDIP28 (P) PLCC32 (K) 28 1 SO28 (MS) 300 mils TSOP28 (N) 8 x13.4mm Figure 1. Logic Diagram DESCRIPTION The M28LV64 is an 8K x 8 low power Parallel EEPROM fabricated with SGS-THOMSON proprietary single polysilicon CMOS technology. The device offers fast access time with low power dissipation and requires a 2.7V to 3.6V power supply. VCC 13 8 A0-A12 Table 1. Signal Names A0 - A12 Address Input DQ0 - DQ7 Data Input / Output W Write Enable E Chip Enable G Output Enable RB Ready / Busy VCC Supply Voltage VSS Ground W DQ0-DQ7 M28LV64 E RB * G VSS AI01538B Note: * RB function is only available on the M28LV64. May 1997 This is information on a product still in production bu t not recommended for new de signs. 1/18 M28LV64 VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 RB DU VCC W NC 1 28 2 27 3 26 4 25 5 24 6 23 7 22 M28LV64 8 21 9 20 10 19 11 18 12 17 13 16 14 15 A7 A12 RB A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 2B. LCC Pin Connections 1 32 A6 A5 A4 A3 A2 A1 A0 NC DQ0 9 M28LV64 25 A8 A9 A11 NC G A10 E DQ7 DQ6 17 DQ1 DQ2 VSS DU DQ3 DQ4 DQ5 Figure 2A. DIP Pin Connections AI01539B AI01540B Warning: NC = Not Connected. Warning: NC = Not Connected, DU = Don’t Use. Figure 2C. SO Pin Connections Figure 2D. TSOP Pin Connections RB A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M28LV64 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 G A11 A9 A8 NC W VCC RB A12 A7 A6 A5 A4 A3 22 28 1 21 M28LV64 7 AI01541B Warning: NC = Not Connected. 2/18 15 14 8 AI01542B Warning: NC = Not Connected. A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 M28LV64 Table 2. Absolute Maximum Ratings Symbol (1) Parameter Value Unit Ambient Operating Temperature – 40 to 85 °C TSTG Storage Temperature Range – 65 to 150 °C VCC Supply Voltage – 0.3 to 6.5 V VIO Input/Output Voltage – 0.3 to VCC +0.6 V VI Input Voltage – 0.3 to 6.5 V 4000 V TA VESD Electrostatic Discharge Voltage (Human Body model) (2) Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. 100pF through 1500Ω; MIL-STD-883C, 3015.7 Figure 3. Block Diagram RB A6-A12 (Page Address) A0-A5 RESET ADDRESS LATCH X DECODE VPP GEN E G W CONTROL LOGIC 64K ARRAY ADDRESS LATCH Y DECODE SENSE AND DATA LATCH I/O BUFFERS PAGE LOAD TIMER STATUS TOGGLE BIT DATA POLLING DQ0-DQ7 AI01355 3/18 M28LV64 Table 3. Operating Modes (1) Mode E G W DQ0 - DQ7 Standby 1 X X Hi-Z Output Disable X 1 X Hi-Z Write Disable X X 1 Hi-Z Read 0 0 1 Data Out Write 0 1 0 Data In Note: 1. 0 = VIL; 1 = VIH; X = VIL or VIH. DESCRIPTION (cont’d) The M28LV64 outputs the Ready/Busy write status, the M28LV64-aaaX(aaa = access time) has no Ready/Busy status and the relevant RB pin is Not Connected (NC). The circuit has been designed to offer a flexible microcontroller interface featuring both hardware and software handshaking with Ready/Busy, Data Polling and Toggle Bit. The M28LV64 supports 64 byte page write operation. A Software Data Protection (SDP) is also possible using the standard JEDEC algorithm. PIN DESCRIPTION Addresses (A0-A12). The address inputs select an 8-bit memory location during a read or write operation. Chip Enable (E). The chip enable input must be low to enable all read/write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/ Out (DQ0 - DQ7). Data is written to or read from the M28LV64 through the I/O pins. Write Enable (W). The Write Enable input controls the writing of data to the M28LV64. Ready/Busy (RB). Ready/Busy is an open drain output that can be used to detect the end of the internal write cycle (this function applies only to the M28LV64). 4/18 OPERATION In order to prevent data corruption and inadvertent writeoperationsan internal VCC comparator inhibits Write operation if VCC is below VWI (see Table 6). Access to the memory in write mode is allowed after a power-up as specified in Table 6. Read The M28LV64 is accessed like a static RAM. When E and G are low with W high, the data addressed is presented on the I/O pins. The I/O pins are high impedance when either G or E is high. Write Write operations are initiated when both W and E are low and G is high.The M28LV64 supports both E and W controlled write cycles. The Address is latched by the falling edge of E or W which ever occurs last and the Data on the rising edge of E or W which ever occurs first. Once initiated the write operation is internally timed until completion. Page Write Page write allows up to 64 bytes to be consecutively latched into the memory prior to initiating a programming cycle. All bytes must be located in a single page address, that is A6-A12 must be the same for all bytes. The page write can be initiated during any byte write operation. Following the first byte write instruction the host may send another address and data with a minimum data transfer rate of tWHWH (see Figure 13). If a transition of E or W is not detected within tWHWH the internal programming cycle will start. M28LV64 Microcontroller Control Interface The M28LV64 provides two write operation status bits and one status pin that can be used to minimize the system write cycle. These signals are available on the I/O port bits DQ7 or DQ6 of the memory during programming cycle only, or as the RB signal on a separate pin. Figure 4. Status Bit Assignment DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DP = Data Polling TB = Toggle Bit PLTS = Page Load Timer Status Data Polling bit (DQ7). During the internal write cycle, any attempt to read the last byte written will produce on DQ7 the complementary value of the previously latched bit. Once the write cycle is finished the true logic value appears on DQ7 in the read cycle. Toggle bit (DQ6). The M28LV64 offers another way for determining when the internal write cycle is completed. During the internal Erase/Write cycle, DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the first read value is ”0”) on subsequent attempts to read the memory. When the internal cycle is completed the toggling will stop and the device will be accessible for a new Read or Write operation. Page Load Timer Status bit (DQ5). In the Page Write mode data may be latched by E or W up to 100µs after the previous byte. Up to 64 bytes may be input. The Data output (DQ5) indicates the status of the internal Page Load Timer. DQ5 may be read by asserting Output Enable Low (tPLTS). DQ5 Low indicates the timer is running, High indicates time-out after which the write cycle will start and no new data may be input. Re ady/ Busy p in (av ail ab le only on the M28LV64). The RB pin provides a signal at its open drain output which is low during the erase/write cycle, but which is released at the completionof the programming cycle. Software Data Protection The M28LV64 offers a software controlled write protection facility that allows the user to inhibit all write modes to the device including the Chip Erase instruction. This can be useful in protecting the memory from inadvertent write cycles that may occur due to uncontrolled bus conditions. The M28LV64is shipped as standard in the ”unprotected” state meaning that the memory contents can be changed as required by the user. After the Software Data Protection enable algorithm is issued, the device enters the ”Protect Mode” of operation where no further write commands have any effect on the memory contents. The device remains in this mode until a valid Software Data Protection (SDP) disable sequence is received whereby the device reverts to its ”unprotected” state. The Software Data Protection is fully nonvolatile and is not changed by power on/off sequences. To enable the Software Data Protection (SDP) the device requires the user to write (with a Page Write) three specific data bytes to three specific memory locations as per Figure 5. Similarly to disable the Software Data Protection the user has to write specific data bytes into six different locations as per Figure 6 (with a Page Write). This complex series ensures that the user will never enable or disable the Software Data Protection accidentally. 5/18 M28LV64 Figure 5. Software Data Protection Enable Algorithm and Memory Write WRITE AAh in Address 1555h Page Write Instruction (Note 1) WRITE 55h in Address 0AAAh WRITE AAh in Address 1555h Page Write Instruction (Note 1) WRITE 55h in Address 0AAAh WRITE A0h in Address 1555h WRITE A0h in Address 1555h WRITE is enabled SDP is set Write Page (1 up to 64 bytes) SDP ENABLE ALGORITHM WRITE IN MEMORY WHEN SDP IS SET AI01356B Note: 1. MSB Address bits (A6 to A12) differ during these specific Page Write operations. Figure 6. Software Data Protection Disable Algorithm WRITE AAh in Address 1555h WRITE 55h in Address 0AAAh Page Write Instruction WRITE 80h in Address 1555h WRITE AAh in Address 1555h WRITE 55h in Address 0AAAh WRITE 20h in Address 1555h Unprotected State AI01357 6/18 M28LV64 AC MEASUREMENT CONDITIONS Figure 8. AC Testing Equivalent Load Circuit Input Rise and Fall Times ≤ 20ns Input Pulse Voltages 0V to VCC -0.3V Input and Output Timing Ref. Voltages 1.5V VCC Note that Output Hi-Z is defined as the point where data is no longer driven. 1.8kΩ DEVICE UNDER TEST Figure 7. AC Testing Input Output Waveforms OUT 1.3kΩ CL = 100pF VCC –0.3V 0.5 VCC 0V CL includes JIG capacitance AI01274 AI01396 Table 4. Capacitance (1) (TA = 25 °C, f = 1 MHz ) Symbol C IN Parameter Test Condition Input Capacitance Output Capacitance C OUT Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: 1. Sampled only, not 100% tested. Table 5. Read Mode DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V) Symbol Parameter Test Condition Min Max Unit ILI Input Leakage Current 0V ≤ VIN ≤ VCC 1019 µA ILO Output Leakage Current 0V ≤ VIN ≤ VCC 10 µA E = VIL, G = VIL, f = 5 MHz, VCC = 3.3V 8 mA E = VIL, G = VIL, f = 5 MHz, VCC = 3.6V 10 mA E > VCC –0.3V 20 µA ICC (1) ICC2 (1) Supply Current (CMOS inputs) Supply Current (Standby) CMOS VIL Input Low Voltage – 0.3 0.6 V VIH Input High Voltage 2 VCC +0.5 V VOL Output Low Voltage IOL = 1 mA 0.2 VCC V VOH Output High Voltage IOH = 1 mA 0.8 VCC V Note: 1. All I/O’s open circuit. Table 6. Power Up Timing (1) (TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V) Symbol Parameter Min Max Unit tPUR Time Delay to Read Operation 1 µs tPUW Time Delay to Write Operation (once VCC ≥ 4.5V) 15 ms VWI Write Inhibit Threshold 1.5 2.5 V Note: 1. Sampled only, not 100% tested. 7/18 M28LV64 Table 7. Read Mode AC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V) M28LV64 Symbol Alt Parameter Test Condition -200 min tAVQV tACC Address Valid to Output Valid tELQV tCE tGLQV max -250 min -300 max min Unit max E = VIL, G = VIL 200 250 300 ns Chip Enable Low to Output Valid G = VIL 200 250 300 ns tOE Output Enable Low to Output Valid E = VIL 100 150 150 ns (1,2 ) tDF Chip Enable High to Output Hi-Z G = VIL 0 55 0 60 0 60 ns tGHQZ (1,2) tDF Output Enable High to Output Hi-Z E = VIL 0 55 0 60 0 60 ns tAXQX (2) tOH Address Transition to Output Transition E = VIL, G = VIL 0 tEHQZ 0 0 ns Notes: 1. Output Hi-Z is defined as the point at which data is no longer driven. 2. Guaranted, not 100% sampled. Figure 9. Read Mode AC Waveforms A0-A12 VALID tAVQV tAXQX E tGLQV tEHQZ G tELQV DQ0-DQ7 tGHQZ DATA OUT Hi-Z AI00749B Note: Wri te Enable (W) = High 8/18 M28LV64 Table 8. Write Mode AC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V) Symbol Alt tAVWL tAS tAVEL Parameter Test Condition Min Max Unit Address Valid to Write Enable Low E = VIL, G = VIH 0 ns tAS Address Valid to Chip Enable Low G = VIH , W = VIL 0 ns tELWL tCES Chip Enable Low to Write Enable Low G = VIH 0 ns tGHWL tOES Output Enable High to Write Enable Low E = VIL 0 ns tGHEL tOES Output Enable High to Chip Enable Low W = VIL 0 ns tWLEL tWES Write Enable Low to Chip Enable Low G = VIH 0 ns tWLAX tAH Write Enable Low to Address Transition 100 ns tELAX tAH Chip Enable Low to Address Transition 100 ns tWLDV tDV Write Enable Low to Input Valid E = VIL, G = VIH 1 µs tELDV tDV Chip Enable Low to Input Valid G = VIH , W = VIL 1 µs tELEH tWP Chip Enable Low to Chip Enable High 100 1000 ns tWHEH tCEH Write Enable High to Chip Enable High 0 ns tWHGL tOEH Write Enable High to Output Enable Low 0 ns tEHGL tOEH Chip Enable High to Output Enable Low 0 ns tEHWH tWEH Chip Enable High to Write Enable High 0 ns tWHDX tDH Write Enable High to Input Transition 0 ns tEHDX tDH Chip Enable High to Input Transition 0 ns tWHWL tWPH Write Enable High to Write Enable Low 50 ns tWLWH tWP Write Enable Low to Write Enable High 100 ns tWHWH tBLC Byte Load Repeat Cycle Time 0.2 tWHRH tWC Write Cycle Time tWHRL tDB Write Enable High to Ready/Busy Low tEHRL tDB Chip Enable High to Ready/Busy Low tDVWH tDS Data Valid before Write Enable High 50 ns tDVEH tDS Data Valid before Chip Enable High 50 ns 100 µs 3 ms Note 1 150 ns Note 1 150 ns Note: 1. With a 3.3 kΩ external pull-up resistor. 9/18 M28LV64 Figure 10. Write Mode AC Waveforms - Write Enable Controlled A0-A12 VALID tAVWL tWLAX E tWHEH tELWL G tGHWL tWLWH tWHGL W tWLDV tWHWL DATA IN DQ0-DQ7 tDVWH tWHDX RB tWHRL AI00750 Figure 11. Write Mode AC Waveforms - Chip Enable Controlled A0-A12 VALID tAVEL tELAX E tGHEL tELEH G tWLEL tEHGL W tELDV DQ0-DQ7 tEHWH DATA IN tDVEH tEHDX RB tEHRL AI00751 10/18 M28LV64 Figure 12. Page Write Mode AC Waveforms - Write Enable Controlled A0-A12 Addr 0 Addr 1 Addr 2 Addr n E tPLTS G tWHWL tWHRH W tWLWH tWHWH Byte 0 DQ0-DQ7 Byte 1 tWHWH Byte 2 Byte n DQ5 Byte n tWHRL RB AI00752C Figure 13. Software Protected Write Cycle Waveforms G E tWLWH tWHWL tWHWH W tWLAX tAVEL A0-A5 Byte Address tWHDX A6-A12 1555h 0AAAh 1555h Page Address tDVWH DQ0-DQ7 AAh 55h A0h Byte 0 Byte 62 Byte 63 AI01358 Note: A6 through A12 must specify the same page address during each high to low transition of W (or E) after the software code has been entered. G must be high only when W and E are both low. 11/18 M28LV64 Figure 14. Data Polling Waveform Sequence A0-A12 Address of the last byte of the Page Write instruction E G W DQ7 DQ7 DQ7 LAST WRITE DQ7 DQ7 INTERNAL WRITE SEQUENCE DQ7 READY AI00753C Figure 15. Toggle Bit Waveform Sequence A0-A12 E G W DQ6 (1) LAST WRITE TOGGLE INTERNAL WRITE SEQUENCE READY AI00754D Note: 1. First Toggle bit is forced to ’0’ 12/18 M28LV64 ORDERING INFORMATION SCHEME Example: Speed -200 200ns -250 250ns -300 300ns M28LV64 -200 X K 1 Write Monitoring blank RB function active X No RB function Package Temperature Range P PDIP28 1 0 to 70 °C K PLCC32 6 –40 to 85 °C MS N SO28 300 mils TSOP28 8 x 13.4mm The M2864 is replaced by the M28C64-xxW. Devices are shipped from the factory with the memory content set at all ”1’s” (FFh). For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you. 13/18 M28LV64 PDIP28 - 28 pin Plastic DIP, 600 mils width mm Symb Typ inches Min Max A 3.94 A1 Min Max 5.08 0.155 0.200 0.38 1.78 0.015 0.070 A2 3.56 4.06 0.140 0.160 B 0.38 0.56 0.015 0.021 B1 1.14 1.78 0.045 0.070 C 0.20 0.30 0.008 0.012 D 34.70 37.34 1.366 1.470 E 14.80 16.26 0.583 0.640 E1 12.50 13.97 0.492 0.550 – – – – eA 15.20 17.78 0.598 0.700 L 3.05 3.82 0.120 0.150 S 1.02 2.29 0.040 0.090 α 0° 15° 0° 15° N 28 e1 2.54 Typ 0.100 28 PDIP28 A2 A1 B1 B A L α e1 eA C D S N E1 E 1 PDIP Drawing is not to scale. 14/18 M28LV64 PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular mm Symb Typ inches Min Max A 2.54 A1 Typ Min Max 3.56 0.100 0.140 1.52 2.41 0.060 0.095 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430 E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530 e 1.27 – – 0.050 – – j 0.89 – – 0.035 – – N 32 32 Nd 7 7 Ne 9 9 CP 0.10 0.004 PLCC32 D D1 A1 j 1 N B1 E1 E Ne e D2/E2 B A Nd PLCC CP Drawing is not to scale. 15/18 M28LV64 SO28 - 28 lead Plastic Small Outline, 300 mils body width mm Symb Typ inches Min Max A 2.46 A1 Min Max 2.64 0.097 0.104 0.13 0.29 0.005 0.011 A2 2.29 2.39 0.090 0.094 B 0.35 0.48 0.014 0.019 C 0.23 0.32 0.009 0.013 D 17.81 18.06 0.701 0.711 E 7.42 7.59 0.292 0.299 – – – – H 10.16 10.41 0.400 0.410 L 0.61 1.02 0.024 0.040 α 0° 8° 0° 8° N 28 e 1.27 CP Typ 0.050 28 0.10 0.004 SO28 A2 A C B CP e D N E H 1 A1 SO-b Drawing is not to scale. 16/18 α L M28LV64 TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm mm Symb Typ inches Min Max Typ Min Max A 1.25 0.049 A1 0.20 0.008 A2 0.95 1.15 0.037 0.045 B 0.17 0.27 0.007 0.011 C 0.10 0.21 0.004 0.008 D 13.20 13.60 0.520 0.535 D1 11.70 11.90 0.461 0.469 E 7.90 8.10 0.311 0.319 – – – – L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N 28 e 0.55 0.022 28 CP 0.10 0.004 TSOP28 A2 22 21 e 28 1 E B 7 8 D1 A CP D DIE C TSOP-c A1 α L Drawing is not to scale. 17/18 M28LV64 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1997 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 18/18