AD AD565A High speed 12-bit monolithic d/a converter Datasheet

a
High Speed 12-Bit
Monolithic D/A Converters
AD565A
FEATURES
Single Chip Construction
Very High Speed Settling to 1/2 LSB
AD565A: 250 ns max
AD566A: 350 ns max
Full-Scale Switching Time: 30 ns
Guaranteed for Operation with ⴞ12 V (565A) Supplies,
with –12 V Supply (AD566A)
Linearity Guaranteed Overtemperature
1/2 LSB max (K, T Grades)
Monotonicity Guaranteed Overtemperature
Low Power: AD566A = 180 mW max;
AD565A = 225 mW max
Use with On-Board High Stability Reference (AD565A)
or with External Reference (AD566A)
Low Cost
MlL-STD-883-Compliant Versions Available
AD566A is obsolete
PRODUCT DESCRIPTION
The AD565A and AD566A are fast 12-bit digital-to-analog
converters that incorporate the latest advances in analog circuit
design to achieve high speeds at low cost.
The AD565A and AD566A use 12 precision, high speed bipolar
current-steering switches, a control amplifier, and a laser-trimmed
thin-film resistor network to produce a very fast, high accuracy
analog output current. The AD565A also includes a buried
Zener reference that features low noise, long-term stability, and
temperature drift characteristics comparable to the best discrete
reference diodes.
The combination of performance and flexibility in the AD565A and
AD566A has resulted from major innovations in circuit design,
an important new high speed bipolar process, and continuing
advances in laser-wafer-trimming techniques (LWT). The
AD565A and AD566A have a 10%–90% full-scale transition
time less than 35 ns and settle to within ±1/2 LSB in 250 ns max
(350 ns for AD566A). Both are laser-trimmed at the wafer level
to ± 1/8 LSB typical linearity and are specified to ± 1/4 LSB max
error (K and T grades) at +25°C. High speed and accuracy make
the AD565A and AD566A the ideal choice for high speed display
drivers as well as for fast analog-to-digital converters.
The laser trimming process that provides the excellent linearity
is also used to trim both the absolute value and the temperature
coefficient of the reference of the AD565A, resulting in a typical
full-scale gain TC of 10 ppm/°C. When tighter TC performance
is required or when a system reference is available, the AD566A
may be used with an external reference.
FUNCTIONAL BLOCK DIAGRAMS
VCC
REF OUT
BIPOLAR OFF
20V SPAN
AD565A
10V
REF
IN
REF
GND
19.95k⍀
5k⍀
9.95k⍀
0.5mA
IREF
DAC OUT
DAC
IOUT =
4 ⴛ IREF ⴛ CODE
20k⍀
10V SPAN
5k⍀
IO
8k⍀
CODE INPUT
–VEE
POWER MSB
GND
LSB
BIPOLAR OFF
20V SPAN
AD566A
5k⍀
9.95k⍀
REF
IN
REF
GND
19.95k⍀
10V SPAN
0.5mA
IREF
5k⍀
DAC OUT
DAC
IOUT =
4 ⴛ IREF ⴛ CODE
20k⍀
IO
8k⍀
CODE INPUT
–VEE
POWER MSB
GND
LSB
AD565A and AD566A are available in four performance
grades. The J and K grades are specified for use over the 0°C to
+70°C temperature range while the S and T grades are specified for the –55°C to +125°C range. The D grades are all packaged in a 24-lead, hermetically sealed, ceramic, dual-in-line
package. The JR grade is packaged in a 28-lead plastic SOIC.
PRODUCT HIGHLIGHTS
1. The wide output compliance range of the AD565A and
AD566A are ideally suited for fast, low noise, accurate voltage
output configurations without an output amplifier.
2. The devices incorporate a newly developed, fully differential,
nonsaturating precision current switching cell structure that
combines the dc accuracy and stability first developed in the
AD562/AD563 with very fast switching times and an optimally
damped settling characteristic.
3. The devices also contain SiCr thin-film application resistors
that can be used with an external op amp to provide a precision voltage output or as input resistors for a successiveapproximation A/D converter. The resistors are matched to
the internal ladder network to guarantee a low gain temperature
coefficient and are laser-trimmed for minimum full-scale and
bipolar offset errors.
REV. F
4. The AD565A and AD566A are available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military
Products Databook or current /883B data sheet for detailed
specifications.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/461-3113
© Analog Devices, Inc., 2015
TheAD566Aisnolongeravailable.
AD565A* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
DESIGN RESOURCES
View a parametric search of comparable parts.
• AD565A Material Declaration
• PCN-PDN Information
DOCUMENTATION
• Quality And Reliability
Data Sheet
• Symbols and Footprints
• AD565A: High Speed 12-Bit Monolithic D/A Converters
Data Sheet
DISCUSSIONS
SOFTWARE AND SYSTEMS REQUIREMENTS
• JAN to Generic Cross Reference
REFERENCE MATERIALS
View all AD565A EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
Solutions Bulletins & Brochures
TECHNICAL SUPPORT
• Digital to Analog Converters ICs Solutions Bulletin
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
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AD565A–SPECIFICATIONS (T = 25ⴗC, V
A
Parameter
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1”
Bit OFF Logic “0”
Logic Current (Each Bit)
Bit ON Logic “1”
Bit OFF Logic “0”
RESOLUTION
OUTPUT
Current
Unipolar (All Bits On)
Bipolar (All Bits On or Off)
Resistance (Exclusive of Span Resistors)
Offset
Unipolar
Bipolar (Figure 3, R2 = 50 Ω Fixed)
Capacitance
Compliance Voltage
TMIN to TMAX
ACCURACY (Error Relative to
Full Scale) 25°C
Min
2.0
–1.6
ⴞ0.8
6
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 2)
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 3)
Gain Adjustment Range (Figure 2)
Bipolar Zero Adjustment Range
REFERENCE INPUT
Input Impedance
REFERENCE OUTPUT
Voltage
Current (Available for External Loads)3
POWER DISSIPATION
= 15 V, VEE = 15 V, unless otherwise noted.)
Max
Min
5.5
0.8
2.0
120
35
300
100
12
–2.0
± 1.0
8
–2.4
ⴞ1.2
10
0.01
0.05
25
0.05
0.15
–1.5
+10
± 1/4
(0.006)
± 1/2
(0.012)
TMIN to TMAX
DIFFERENTIAL NONLINEARITY
25°C
TMIN to TMAX
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
TEMPERATURE RANGE
Operating
Storage
POWER REQUIREMENTS
VCC, +11.4 to +16.5 V dc
VEE, –11.4 to –16.5 V dc
POWER SUPPLY GAIN SENSITIVITY2
VCC = +11.4 to +16.5 V dc
VEE = –11.4 to –16.5 V dc
PROGRAMMABLE OUTPUT RANGES
(See Figures 2, 3, 4)
AD565AJ
Typ
CC
–1.6
ⴞ0.8
6
Unit
5.5
0.8
V
V
120
35
300
100
12
μA
μA
Bits
–2.0
± 1.0
8
–2.4
ⴞ1.2
10
mA
mA
kΩ
0.01
0.05
25
0.05
0.1
% of F.S. Range
% of F.S. Range
pF
+10
V
ⴞ0.35
(0.0084)
ⴞ1/2
(0.012)
LSB
% of F.S. Range
LSB
% of F.S. Range
± 1/8
(0.003)
± 1/4
(0.006)
± 1/4
ⴞ1/2
MONOTONICITY GUARANTEED
LSB
1
5
15
2
2
10
50
1
5
10
2
2
10
20
ppm/°C
ppm/°C
ppm/°C
ppm/°C
250
400
250
400
ns
15
30
30
50
15
30
30
50
ns
ns
+70
+150
°C
°C
0
–65
+70
+150
0
–65
3
–12
5
–18
3
–12
5
–18
mA
mA
3
15
10
25
3
15
10
25
ppm of F.S./%
ppm of F.S./%
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
± 0.1
ⴞ0.25
± 0.05
ⴞ0.15
15
20
25
9.90
1.5
10.00
2.5
225
10.10
± 0.25
± 0.15
Max
–1.5
ⴞ1/2
(0.012)
ⴞ3/4
(0.018)
± 1/2
ⴞ3/4
MONOTONICITY GUARANTEED
AD565AK
Typ
345
V
V
V
V
V
± 0.1
ⴞ0.25
% of F.S. Range
± 0.05
± 0.1
% of F.S. Range
% of F.S. Range
% of F.S. Range
15
20
25
kΩ
9.90
1.5
10.00
2.5
225
10.10
V
mA
mW
± 0.25
± 0.15
345
NOTES
1
The digital inputs are guaranteed but not tested over the operating temperature range.
2
The power supply gain sensitivity is tested in reference to a V CC, VEE of ± 15 V dc.
3
For operation at elevated temperatures, the reference cannot supply current for external loads. It, therefore, should be buffered if additional loads are to be supplied.
Specifications subject to change without notice.
–2–
REV. F
AD565A
Parameter
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1”
Bit OFF Logic “0”
Logic Current (Each Bit)
Bit ON Logic “1”
Bit OFF Logic “0”
RESOLUTION
OUTPUT
Current
Unipolar (All Bits On)
Bipolar (All Bits On or Off)
Resistance (Exclusive of Span Resistors)
Offset
Unipolar
Bipolar (Figure 3, R2 = 50 Ω Fixed)
Capacitance
Compliance Voltage
TMIN to TMAX
ACCURACY (Error Relative to
Full Scale) 25°C
Min
2.0
–1.6
ⴞ0.8
6
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 2)
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 3)
Gain Adjustment Range (Figure 2)
Bipolar Zero Adjustment Range
REFERENCE INPUT
Input Impedance
REFERENCE OUTPUT
Voltage
Current (Available for External Loads)3
POWER DISSIPATION
Max
Min
5.5
0.8
2.0
120
35
300
100
12
–2.0
± 1.0
8
–2.4
ⴞ1.2
10
0.01
0.05
25
0.05
0.15
–1.5
+10
± 1/4
(0.006)
± 1/2
(0.012)
TMIN to TMAX
DIFFERENTIAL NONLINEARITY
25°C
TMIN to TMAX
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
TEMPERATURE RANGE
Operating
Storage
POWER REQUIREMENTS
VCC, +11.4 to +16.5 V dc
VEE, –11.4 to –16.5 V dc
POWER SUPPLY GAIN SENSITIVITY2
VCC = +11.4 to +16.5 V dc
VEE = –11.4 to –16.5 V dc
PROGRAMMABLE OUTPUT RANGES
(See Figures 2, 3, 4)
AD565AS
Typ
–1.6
ⴞ0.8
6
Unit
5.5
0.8
V
V
120
35
300
100
12
μA
μA
Bits
–2.0
± 1.0
8
–2.4
ⴞ1.2
10
mA
mA
kΩ
0.01
0.05
25
0.05
0.1
% of F.S. Range
% of F.S. Range
pF
+10
V
ⴞ0.35
(0.0084)
ⴞ1/2
(0.012)
LSB
% of F.S. Range
LSB
% of F.S. Range
± 1/8
(0.003)
± 1/4
(0.006)
± 1/4
ⴞ1/2
MONOTONICITY GUARANTEED
LSB
1
5
15
2
2
10
30
1
5
10
2
2
10
15
ppm/°C
ppm/°C
ppm/°C
ppm/°C
250
400
250
400
ns
15
30
30
50
15
30
30
50
ns
ns
+125
+150
°C
°C
–55
–65
+125
+150
–55
–65
3
–12
5
–18
3
–12
5
–18
mA
mA
3
15
10
25
3
15
10
25
ppm of F.S./%
ppm of F.S./%
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
± 0.1
ⴞ0.25
± 0.05
ⴞ0.15
15
20
25
9.90
1.5
10.00
2.5
225
10.10
± 0.25
± 0.15
Max
–1.5
ⴞ1/2
(0.012)
ⴞ3/4
(0.018)
± 1/2
ⴞ3/4
MONOTONICITY GUARANTEED
AD565AT
Typ
345
V
V
V
V
V
± 0.1
ⴞ0.25
% of F.S. Range
± 0.05
ⴞ0.1
% of F.S. Range
% of F.S. Range
% of F.S. Range
15
20
25
kΩ
9.90
1.5
10.00
2.5
225
10.10
V
mA
mW
± 0.25
± 0.15
345
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specification subject to change without notice.
REV. F
–3–
AD566A–SPECIFICATIONS(T = 25ⴗC, V
A
EE
= –15 V, unless otherwise noted)
AD566AJ
Parameter
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1”
Bit OFF Logic “0”
Logic Current (Each Bit)
Bit ON Logic “1”
Bit OFF Logic “0”
RESOLUTION
OUTPUT
Current
Unipolar (All Bits On)
Bipolar (All Bits On or Off)
Resistance (Exclusive of Span Resistors)
Offset
Unipolar (Adjustable to Zero per Figure 3)
Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed)
Capacitance
Compliance Voltage
TMIN to TMAX
ACCURACY (Error Relative to
Full Scale) 25°C
Min
2.0
0
120
35
–1.6
ⴞ0.8
6
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 3)
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 4)
Gain Adjustment Range (Figure 3)
Bipolar Zero Adjustment Range
REFERENCE INPUT
Input Impedance
POWER DISSIPATION
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants
Reference Voltage
Accuracy
Reference Feedthrough (Unipolar Mode,
All Bits OFF, and 1 V to 10 V [p-p], Sine Wave
Frequency for 1/2 LSB [p-p] Feedthrough)
Output Slew Rate 10%–90%
90%–10%
Output Settling Time (All Bits ON and a 0 V–10 V
Step Change in Reference Voltage)
CONTROL AMPLIFIER
Full Power Bandwidth
Small-Signal Closed-Loop Bandwidth
AD566AK
Max
Min
5.5
0.8
2.0
0
300
100
12
–2.0
± 1.0
8
–2.4
ⴞ1.2
10
0.01
0.05
25
0.05
0.15
–1.5
+10
± 1/4
(0.006)
± 1/2
(0.012)
TMIN to TMAX
DIFFERENTIAL NONLINEARITY
25°C
TMIN to TMAX
TEMPERATURE COEFFICIENTS
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
POWER REQUIREMENTS
VEE, –11.4 to –16.5 V dc
POWER SUPPLY GAIN SENSITIVITY 2
VEE = –11.4 to –16.5 V dc
PROGRAMMABLE OUTPUT RANGES
(see Figures 3, 4, 5)
Typ
–1.6
ⴞ0.8
6
15
Unit
5.5
0.8
V
V
120
35
300
100
12
μA
μA
Bits
–2.0
± 1.0
8
–2.4
ⴞ1.2
10
mA
mA
kΩ
0.01
0.05
25
0.05
0.1
% of F.S. Range
% of F.S. Range
pF
+10
V
ⴞ0.35
(0.0084)
ⴞ1/2
(0.012)
LSB
% of F.S. Range
LSB
% of F.S. Range
± 1/8
(0.003)
± 1/4
(0.006)
± 1/4
ⴞ1/2
MONOTONICITY GUARANTEED
LSB
1
5
7
2
2
10
10
1
5
3
2
2
10
5
ppm/°C
ppm/°C
ppm/°C
ppm/°C
250
350
250
350
ns
15
30
30
50
15
30
30
50
ns
ns
–12
–18
–12
–18
mA
15
25
15
25
ppm of F.S./%
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
± 0.25
± 0.15
Max
–1.5
ⴞ1/2
(0.012)
ⴞ3/4
(0.018)
± 1/2
ⴞ3/4
MONOTONICITY GUARANTEED
Typ
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
± 0.1
ⴞ0.25
± 0.05
ⴞ0.15
20
180
25
300
± 0.25
± 0.15
15
V
V
V
V
V
± 0.1
ⴞ0.25
% of F.S. Range
± 0.05
ⴞ0.1
% of F.S. Range
% of F.S. Range
% of F.S. Range
20
180
25
300
kΩ
mW
Two (2): Bipolar Operation at Digital Input Only
1 V to 10 V, Unipolar
10 Bits (± 0.05% of Reduced F.S.) for 1 V dc Reference Voltage
40
5
1
kHz typ
mA/μs
mA/μs
1.5 μs to 0.01% F.S.
300
1.8
kHz
MHz
NOTES
1
The digital input levels are guaranteed but not tested over the temperature range.
2
The power supply gain sensitivity is tested in reference to a V EE of –1.5 V dc.
Specifications subject to change without notice.
–4–
REV. F
AD565A
AD566AS
Parameter
Min
Typ
AD566AT
Max
Min
5.5
0.8
2.0
0
Typ
Max
Unit
5.5
0.8
V
V
+120
+35
300
100
12
μA
μA
Bits
–2.0
± 1.0
8
–2.4
ⴞ1.2
10
mA
mA
kΩ
0.01
0.05
25
0.05
0.1
% of F.S. Range
% of F.S. Range
pF
+10
V
ⴞ0.35
(0.0084)
ⴞ1/2
(0.012)
LSB
% of F.S. Range
LSB
% of F.S. Range
1
DATA INPUTS (Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1”
Bit OFF Logic “0”
Logic Current (Each Bit)
Bit ON Logic “1”
Bit OFF Logic “0”
RESOLUTION
OUTPUT
Current
Unipolar (All Bits On)
Bipolar (All Bits On or Off)
Resistance (Exclusive of Span Resistors)
Offset
Unipolar (Adjustable to Zero per Figure 3)
Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed)
Capacitance
Compliance Voltage
TMIN to TMAX
ACCURACY (Error Relative to
Full Scale) 25°C
2.0
0
–1.6
ⴞ0.8
6
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 3)
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 4)
Gain Adjustment Range (Figure 3)
Bipolar Zero Adjustment Range
REFERENCE INPUT
Input Impedance
POWER DISSIPATION
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants
Reference Voltage
Accuracy
Reference Feedthrough (Unipolar Mode,
All Bits OFF, and 1 V to 10 V [p-p], Sine Wave
Frequency for l/2 LSB [p-p] Feedthrough)
Output Slew Rate 10%–90%
90%–10%
Output Settling Time (All Bits ON and a 0 V–10 V
Step Change in Reference Voltage)
CONTROL AMPLIFIER
Full Power Bandwidth
Small-Signal Closed-Loop Bandwidth
300
100
12
–2.0
± 1.0
8
–2.4
ⴞ1.2
10
0.01
0.05
25
0.05
0.15
–1.5
+10
± 1/4
(0.006)
± 1/2
(0.012)
TMIN to TMAX
DIFFERENTIAL NONLINEARITY
25°C
TMIN to TMAX
TEMPERATURE COEFFICIENTS
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
POWER REQUIREMENTS
VEE, –11.4 to –16.5 V dc
POWER SUPPLY GAIN SENSITIVITY 2
VEE = –11.4 to –16.5 V dc
PROGRAMMABLE OUTPUT RANGES
(see Figures 3, 4, 5)
120
35
–1.6
ⴞ0.8
6
–1.5
ⴞ1/2
(0.012)
ⴞ3/4
(0.018)
± 1/2
ⴞ3/4
MONOTONICITY GUARANTEED
± 1/8
(0.003)
± 1/4
(0.006)
± 1/4
ⴞ1/2
MONOTONICITY GUARANTEED
1
5
7
2
2
10
10
1
5
3
2
2
10
5
ppm/°C
ppm/°C
ppm/°C
ppm/°C
250
350
250
350
ns
15
30
30
50
15
30
30
50
ns
ns
–12
–18
–12
–18
mA
15
25
15
25
ppm of F.S./%
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
± 0.25
± 0.15
15
LSB
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
± 0.1
ⴞ0.25
± 0.05
ⴞ0.15
20
180
25
300
± 0.25
± 0.15
15
V
V
V
V
V
± 0.1
ⴞ0.25
% of F.S. Range
± 0.05
ⴞ0.1
% of F.S. Range
% of F.S. Range
% of F.S. Range
20
180
25
300
kΩ
mW
Two (2): Bipolar Operation at Digital Input Only
1 V to 10 V, Unipolar
10 Bits (± 0.05% of Reduced F.S.) for 1 V dc Reference Voltage
40
5
1
kHz typ
mA/μs
mA/μs
1.5 μs to 0.01% F.S.
300
1.8
kHz
MHz
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specification subject to change without notice.
REV. F
–5–
AD565A
ABSOLUTE MAXIMUM RATINGS
GROUNDING RULES
VCC to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
VEE to Power Ground (AD565A) . . . . . . . . . . . . 0 V to –18 V
Voltage on DAC Output (Pin 9) . . . . . . . . . . . . –3 V to +12 V
Digital Inputs (Pins 13 to 24) to
Power Ground . . . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V
REF IN to Reference Ground . . . . . . . . . . . . . . . . . . . . ± 12 V
Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . ± 12 V
10 V Span R to Reference Ground . . . . . . . . . . . . . . . . ± 12 V
20 V Span R to Reference Ground . . . . . . . . . . . . . . . . ± 24 V
REF OUT (AD565A) . . . . . Indefinite Short to Power Ground
Momentary Short to VCC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
The AD565A and AD566A use separate reference and power
grounds to allow optimum connections for low noise and high
speed performance. These grounds should be tied together at one
point, usually the device power ground. The separate ground
returns minimize current flow in low level signal paths. In this
way, logic return currents are not summed into the same return
path with analog signals.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD565A/AD566A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–6–
WARNING!
ESD SENSITIVE DEVICE
REV.F
AD565A
PIN CONFIGURATIONS
24-Lead DIP
24-Lead DIP
NC 1
24
BIT 1 IN (MSB)
NC 1
24
BIT 1 IN (MSB)
2
23
BIT 2 IN
NC 2
23
BIT 2 IN
VCC 3
22
BIT 3 IN
REF GND 3
22
BIT 3 IN
REF OUT (+10V ±1%) 4
21
BIT 4 IN
AMP SUMMING JUNCTION 4
21
BIT 4 IN
REF GND 5
20
BIT 5 IN
REF V HI IN 5
20
BIT 5 IN
NC
AD565A
–VEE –15V IN (20mA)
TOP VIEW 19 BIT 6 IN
–VEE 7 (Not to Scale) 18 BIT 7 IN
REF IN 6
BIPOLAR OFFSET IN 8
DAC OUT (–2mA F.S.)
9
BIPOLAR OFFSET IN
17
BIT 8 IN
NC
8
17
BIT 8 IN
16
BIT 9 IN
DAC OUT (–2mA F.S.)
9
16
BIT 9 IN
10V SPAN R 10
15
BIT 10 IN
10V SPAN R 10
15
BIT 10 IN
20V SPAN R 11
14
BIT 11 IN
20V SPAN R 11
14
BIT 11 IN
PWR GND 12
13
BIT 12 IN (LSB)
PWR GND 12
13
BIT 12 IN (LSB)
NC = NO CONNECT
NC = NO CONNECT
28-Lead SOIC
NC 1
28
NC
NC
2
27
BIT 1 (MSB)
NC
3
26
BIT 2
VCC 4
25
BIT 3
REF OUT (10V)
5
24
BIT 4
REF GND
6
23
BIT 5
REF IN
7
NC
AD565A
TOP VIEW 22 BIT 6
8 (Not to Scale) 21 BIT 7
9
20
BIT 8
BIPOLAR OFFSET IN 10
19
BIT 9
DAC OUT 11
18
BIT 10
NC 12
17
BIT 11
10V SPAN R 13
16
BIT 12 (LSB)
20V SPAN R 14
15
PWR GND
–VEE
NC = NO CONNECT
REV. F
AD566A
TOP VIEW 19 BIT 6 IN
7 (Not to Scale) 18 BIT 7 IN
6
–7–
AD565A
CONNECTING THE AD565A FOR BUFFERED VOLTAGE
OUTPUT
REF
OUT
The standard current-to-voltage conversion connections using an
operational amplifier are shown in Figures 1, 2, and 3 with the
preferred trimming techniques. If a low offset operational amplifier
(OP77, AD741L, OP07) is used, excellent performance can be
obtained in many situations without trimming (an op amp with
less than 0.5 mV max offset voltage should be used to keep offset
errors below 1/2 LSB). If a 50 Ω fixed resistor is substituted for
the 100 Ω trimmer, unipolar zero is typically within ± 1/2 LSB
(plus op amp offset) and full-scale accuracy is within 0.1%
(0.25% max). Substituting a 50 Ω resistor for the 100 Ω bipolar offset trimmer gives a bipolar zero error typically within
± 2 LSB (0.05%).
REF
GND
9.95k⍀
19.95k⍀
REF
IN
REF
GND
IREF
Please note that it is not necessary to trim the op amp to obtain
full accuracy at room temperature. In most bipolar situations,
an op amp trim is unnecessary unless the untrimmed offset drift
of the op amp is excessive.
FIGURE 3. OTHER VOLTAGE RANGES
–VEE
DAC
OUT
OUTPUT
0V TO
+10V
AD509
2.4k⍀
CODE
INPUT
POWER
GND
MSB
LSB
Turn ON all bits. Adjust 100 Ω gain trimmer R2 to give a
reading of +4.9976 V.
10V SPAN
DAC
MSB
STEP II . . . GAIN ADJUST
–15V
IOUT =
4 ⴛ IREF
ⴛ CODE
20k⍀
CODE
INPUT
Turn OFF all bits. Adjust 100 Ω trimmer R1 to give –5.000 V
output.
R1
50k⍀
10pF
IO 8k⍀
2.4k⍀
STEP I . . . OFFSET ADJUST
5k⍀
0.5mA
AD509
DAC
IOUT =
4 ⴛ IREF
ⴛ CODE
20k⍀
OUTPUT
–5V TO
+5V
DAC
OUT
Figure 2. ± 5 V Bipolar Voltage Output
10V
AD565A
10pF
IO 8k⍀
IREF
–VEE
20V SPAN
R2
100⍀
10V SPAN
5k⍀
0.5mA
POWER
GND
BIPOLAR OFF
5k⍀
AD565A
REF
IN
+15V
VCC
5k⍀
10V
19.95k⍀
This configuration provides a unipolar 0 V to 10 V output
range. In this mode, the bipolar terminal, Pin 8, should be
grounded if not used for trimming.
REF
OUT
BIPOLAR OFF
9.95k⍀
R2
100⍀
FIGURE 1. UNIPOLAR CONFIGURATION
100⍀
R1
100⍀
20V SPAN
The AD509 is recommended for buffered voltage-output
applications that require a settling time to ± 1/2 LSB of
1 μs. The feedback capacitor is shown with the optimum value
for each application; this capacitor is required to compensate for the 25 pF DAC output capacitance.
100k⍀
VCC
LSB
The AD565A can also be easily configured for a unipolar 0 V to
+5 V range or ± 2.5 V and ± 10 V bipolar ranges by using the
additional 5 kΩ application resistor provided at the 20 V span R
terminal, Pin 11. For a 5 V span (0 V to +5 V, or ± 2.5 V), the
two 5 kΩ resistors are used in parallel by shorting Pin 11 to Pin 9
and connecting Pin 10 to the op amp output and the bipolar
offset either to ground for unipolar or to REF OUT for the
bipolar offset either to ground for unipolar or to REF OUT for
the bipolar range. For the ± 10 V range (20 V span) use the 5 kΩ
resistors in series by connecting only Pin 11 to the op amp output
and the bipolar offset connected as shown. The ± 10 V option is
shown in Figure 3.
Figure 1. 0 V to 10 V Unipolar Voltage Output
STEP I . . . ZERO ADJUST
REF
OUT
Turn all bits OFF and adjust zero trimmer R1 until the output
reads 0.000 V (1 LSB = 2.44 mV). In most cases, this trim is not
needed, but Pin 8 should then be connected to Pin 12.
VCC
R1
100⍀
BIPOLAR OFF
20V SPAN
9.95k⍀
R2
100⍀
STEP II . . . GAIN ADJUST
AD565A
REF
IN
REF
GND
0.5mA
IREF
–VEE
10pF
IO 8k⍀
DAC
OUT
OUTPUT
–10V TO
+10V
AD509
DAC
20k⍀
FIGURE 2. BIPOLAR CONFIGURATION
5k⍀
IOUT =
4 ⴛ IREF
ⴛ CODE
3.0k⍀
CODE
INPUT
POWER
GND
This configuration provides a bipolar output voltage from
–5.000 V to +4.9976 V, with positive full scale occurring with
all bits ON (all 1s).
10V SPAN
10V
19.95k⍀
Turn all bits ON and adjust 100 Ω gain trimmer R2 until the
output is 9.9976 V. (Full scale is adjusted to 1 LSB less than
nominal full scale of 10.000 V.) If a 10.2375 V full scale is desired
(exactly 2.5 mV/bit), insert a 120 Ω resistor in series with the gain
resistor at Pin 10 to the op amp output.
5k⍀
MSB
LSB
Figure 3. ± 10 V Voltage Output
–8–
REV.F
AD565A
CONNECTING THE AD566A FOR BUFFERED VOLTAGE
OUTPUT
The standard current-to-voltage conversion connections using an
operational amplifier are shown in Figures 4, 5, and 6 with the
preferred trimming techniques. If a low offset operational amplifier
(OP77, AD741L, OP07) is used, excellent performance can be
obtained in many situations without trimming (an op amp with
less than 0.5 mV max offset voltage should be used to keep offset
errors below 1/2 LSB). If a 50 Ω fixed resistor is substituted for the
100 Ω trimmer, unipolar zero typically is within ±1/2 LSB (plus op
amp offset), and full-scale accuracy is within 0.1% (0.25% max).
Substituting a 50 Ω resistor for the 100 Ω bipolar offset trimmer
gives a bipolar zero error typically within ± 2 LSB (0.05%).
STEP II . . . GAIN ADJUST
Turn all bits ON and adjust 100 Ω gain trimmer, R2, until the
output is 9.9976 V. (Full scale is adjusted to 1 LSB less than
nominal full scale of 10.000 V.) If a 10.2375 V full scale is desired
(exactly 2.5 mV/bit), insert a 120 Ω resistor in series with the
gain resistor at Pin 10 to the op amp output.
FIGURE 5. BIPOLAR CONFIGURATION
This configuration provides a bipolar output voltage from
–5.000 V to +4.9976 V, with positive full scale occurring with
all bits ON (all 1s).
R1
100⍀
The AD509 is recommended for buffered voltage-output
applications that require a settling time to ± 1/2 LSB of 1 μs. The
feedback capacitor is shown with the optimum value for each
application; this capacitor is required to compensate for the
25 pF DAC output capacitance.
9.95k⍀
R2
100⍀
This configuration provides a unipolar 0 V to 10 V output range.
In this mode, the bipolar terminal, Pin 7, should be grounded if not
used for trimming.
+V
BIPOLAR OFF
9.95k⍀
+V
10V
EREF
AD561
IREF
IO 8k⍀
DAC
OUT
DAC
IOUT =
4 ⴛ IREF
ⴛ CODE
20k⍀
–VEE
–15V
5k⍀
AD509
2.4k⍀
CODE
INPUT
MSB
LSB
Figure 5. ± 5 V Bipolar Voltage Output
10V SPAN
STEP I . . . OFFSET ADJUST
10pF
0.5mA
IREF
DAC
DAC
OUT
AD509
2.4k⍀
CODE
INPUT
POWER
GND
–VEE
IO 8k⍀
IOUT =
4 ⴛ IREF
ⴛ CODE
20k⍀
REF
GND
MSB
LSB
Figure 4. 0 V to 10 V Unipolar Voltage Output
Turn OFF all bits. Adjust 100 Ω trimmer R1 to give –5.000
output V.
STEP II . . . GAIN ADJUST
Turn ON all bits. Adjust 100 Ω gain trimmer R2 to give a reading of +4.9976 V.
Please note that it is not necessary to trim the op amp to obtain
full accuracy at room temperature. In most bipolar situations,
an op amp trim is unnecessary unless the untrimmed offset drift
of the op amp is excessive.
STEP I . . . ZERO ADJUST
Turn all bits OFF and adjust zero trimmer, R1, until the output
reads 0.000 V (1 LSB = 2.44 mV). In most cases, this trim is
not needed, but Pin 7 should then be connected to Pin 12.
REV. F
10pF
0.5mA
POWER
GND
R1
50k⍀
5k⍀
REF
IN 19.95k⍀
EREF
AD561
10V SPAN
20V SPAN
AD566A
R2
100⍀
10V
5k⍀
5k⍀
REF
IN 19.95k⍀
REF
GND
+15V
100k⍀
20V SPAN
AD566A
FIGURE 4. UNIPOLAR CONFIGURATION
100⍀
BIPOLAR OFF
–9–
AD565A
FIGURE 6. OTHER VOLTAGE RANGES
The AD566A can also be easily configured for a unipolar 0 V to
+5 V range or ± 2.5 V and ± 10 V bipolar ranges by using the
additional 5 kΩ application resistor provided at the 20 V span R
terminal, Pin 11. For a 5 V span (0 V to +5 V or ± 2.5 V), the two
5 kΩ resistors are used in parallel by shorting Pin 11 to Pin 9 and
connecting Pin 10 to the op amp output and the bipolar offset
resistor either to ground for unipolar or to VREF for the bipolar
range. For the ±10 V range (20 V span), use the 5 kΩ resistors in
series by connecting only Pin 11 to the op amp output and the
bipolar offset connected as shown. The ± 10 V option is shown
in Figure 6.
R1
5k⍀
BIPOLAR OFF
20V SPAN
AD566A
9.95k⍀
14k⍀
R2
5k⍀
–V
7.5V
5k⍀
10V SPAN
10pF
5k⍀
REF
IN 19.95k⍀
0.5mA
IO 8k⍀
IREF
EREF
AD561
IOUT =
4 ⴛ IREF
ⴛ CODE
20k⍀
REF
GND
CODE
INPUT
POWER
GND
–VEE
DAC
OUT
DAC
MSB
AD509
2.4k⍀
R3
26k⍀*
LSB
* THE PARALLEL COMBINATION OF THE BIPOLAR OFFSET RESISTOR
AND R3 ESTABLISHES A CURRENT TO BALANCE THE MSB CURRENT.
THE EFFECT OF TEMPERATURE COEFFICIENT MISMATCH BETWEEN
THE BIPOLAR RESISTOR COMBINATION AND DAC RESISTORS IS
EXPANDED ON PREVIOUS PAGE.
Figure 6. ± 10 V Voltage Output
Table I. Digital Input Codes
DIGITAL INPUT
MSB
LSB
Straight Binary
ANALOG OUTPUT
Offset Binary
Twos Complement*
000000000000
011111111111
100000000000
111111111111
Zero
Mid Scale – 1 LSB
+1/2 FS
+FS – l LSB
–FS
Zero – 1 LSB
Zero
+FS – 1 LSB
Zero
+FS – 1 LSB
–FS
Zero – 1 LSB
*Inverts the MSB of the offset binary code with an external inverter to obtain twos complement.
–10–
REV.F
AD565A
OUTLINE DIMENSIONS
0.098 (2.49) MAX
0.005 (0.13) MIN
24
13
0.610 (15.49)
0.500 (12.70)
PIN 1
1
2
1.290 (32.77) MAX
0.225 (5.72)
MAX
0.200 (5.08)
0.120 (3.05)
0.075 (1.91)
0.015 (0.38)
0.620 (15.75)
0.590 (14.99)
0.150
(3.81)
MIN
0.023 (0.58) 0.100 (2.54) 0.070 (1.78) SEATING
PLANE
BSC
0.014 (0.36)
0.030 (0.76)
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 7. 24-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-24-2)
Dimensions shown in inches and (millimeters)
18.10 (0.7126)
17.70 (0.6969)
15
28
7.60 (0.2992)
7.40 (0.2913)
14
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
1.27 (0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
0.75 (0.0295)
45°
0.25 (0.0098)
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 8. 28-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)
Rev. F | Page 11
1.27 (0.0500)
0.40 (0.0157)
06-07-2006-A
1
AD565A
ORDERING GUIDE
Model1, 2
AD565AJD
AD565AJR
AD565AJRZ
AD565AJRZ-REEL
AD565AKD
AD565ASD
AD565ATD
1
2
Max Gain T.C.
(ppm of F.S./°C)
50
50
50
50
20
30
15
Temperature Range
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–55°C to +125°C
–55°C to +125°C
Linearity Error Max @
+25°C
±1/2 LSB
±1/2 LSB
±1/2 LSB
±1/2 LSB
±1/4 LSB
±1/2 LSB
±1/4 LSB
Package Description
24-Lead SBDIP
28-Lead SOIC_W
28-Lead SOIC_W
28-Lead SOIC_W
24-Lead SBDIP
24-Lead SBDIP
24-Lead SBDIP
Package Options
D-24-2
RW-28
RW-28
RW-28
D-24-2
D-24-2
D-24-2
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current/883B data
sheet.
Z = RoHS Copliant Part.
REVISION HISTORY
3/15—Rev. E to Rev. F
Added AD566A Obsolete Note ...................................................... 1
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 12
10/02—Rev. D to Rev. E
Edits to Specifications ...................................................................... 2
Outline Dimensions Updated ....................................................... 11
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00516-0-3/15(F)
Rev. F | Page 12